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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
1b136de1 42#include <net/vxlan.h>
c27a02cd
YP		 43
44#include <linux/mlx4/driver.h>
45#include <linux/mlx4/device.h>
46#include <linux/mlx4/cmd.h>
47#include <linux/mlx4/cq.h>
48
49#include "mlx4_en.h"
50#include "en_port.h"
51
d317966b 52int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 53{
bc6a4744
AV		 54 struct mlx4_en_priv *priv = netdev_priv(dev);
55 int i;
d317966b 56 unsigned int offset = 0;
bc6a4744
AV		 57
58 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 59 return -EINVAL;
60
bc6a4744
AV		 61 netdev_set_num_tc(dev, up);
62
63 /* Partition Tx queues evenly amongst UP's */
bc6a4744 64 for (i = 0; i < up; i++) {
d317966b
AV		 65 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
66 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 67 }
68
897d7846
AV		 69 return 0;
70}
71
e0d1095a 72#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV		 73/* must be called with local_bh_disable()d */
74static int mlx4_en_low_latency_recv(struct napi_struct *napi)
75{
76 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
77 struct net_device *dev = cq->dev;
78 struct mlx4_en_priv *priv = netdev_priv(dev);
41d942d5 79 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
9e77a2b8
AV		 80 int done;
81
82 if (!priv->port_up)
83 return LL_FLUSH_FAILED;
84
85 if (!mlx4_en_cq_lock_poll(cq))
86 return LL_FLUSH_BUSY;
87
88 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV		 89 if (likely(done))
90 rx_ring->cleaned += done;
91 else
92 rx_ring->misses++;
9e77a2b8
AV		 93
94 mlx4_en_cq_unlock_poll(cq);
95
96 return done;
97}
e0d1095a 98#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 99
1eb8c695
AV		 100#ifdef CONFIG_RFS_ACCEL
101
102struct mlx4_en_filter {
103 struct list_head next;
104 struct work_struct work;
105
75a353d4 106 u8 ip_proto;
1eb8c695
AV		 107 __be32 src_ip;
108 __be32 dst_ip;
109 __be16 src_port;
110 __be16 dst_port;
111
112 int rxq_index;
113 struct mlx4_en_priv *priv;
114 u32 flow_id; /* RFS infrastructure id */
115 int id; /* mlx4_en driver id */
116 u64 reg_id; /* Flow steering API id */
117 u8 activated; /* Used to prevent expiry before filter
118 * is attached
119 */
120 struct hlist_node filter_chain;
121};
122
123static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
124
75a353d4
EP		 125static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
126{
127 switch (ip_proto) {
128 case IPPROTO_UDP:
129 return MLX4_NET_TRANS_RULE_ID_UDP;
130 case IPPROTO_TCP:
131 return MLX4_NET_TRANS_RULE_ID_TCP;
132 default:
c3ca5205 133 return MLX4_NET_TRANS_RULE_NUM;
75a353d4
EP		 134 }
135};
136
1eb8c695
AV		 137static void mlx4_en_filter_work(struct work_struct *work)
138{
139 struct mlx4_en_filter *filter = container_of(work,
140 struct mlx4_en_filter,
141 work);
142 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 143 struct mlx4_spec_list spec_tcp_udp = {
144 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 145 {
146 .tcp_udp = {
147 .dst_port = filter->dst_port,
148 .dst_port_msk = (__force __be16)-1,
149 .src_port = filter->src_port,
150 .src_port_msk = (__force __be16)-1,
151 },
152 },
153 };
154 struct mlx4_spec_list spec_ip = {
155 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
156 {
157 .ipv4 = {
158 .dst_ip = filter->dst_ip,
159 .dst_ip_msk = (__force __be32)-1,
160 .src_ip = filter->src_ip,
161 .src_ip_msk = (__force __be32)-1,
162 },
163 },
164 };
165 struct mlx4_spec_list spec_eth = {
166 .id = MLX4_NET_TRANS_RULE_ID_ETH,
167 };
168 struct mlx4_net_trans_rule rule = {
169 .list = LIST_HEAD_INIT(rule.list),
170 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
171 .exclusive = 1,
172 .allow_loopback = 1,
f9162539 173 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 174 .port = priv->port,
175 .priority = MLX4_DOMAIN_RFS,
176 };
177 int rc;
1eb8c695
AV		 178 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
179
c3ca5205 180 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
75a353d4
EP		 181 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
182 filter->ip_proto);
183 goto ignore;
184 }
1eb8c695
AV		 185 list_add_tail(&spec_eth.list, &rule.list);
186 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 187 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 188
1eb8c695 189 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 190 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 191 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
192
193 filter->activated = 0;
194
195 if (filter->reg_id) {
196 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
197 if (rc && rc != -ENOENT)
198 en_err(priv, "Error detaching flow. rc = %d\n", rc);
199 }
200
201 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
202 if (rc)
203 en_err(priv, "Error attaching flow. err = %d\n", rc);
204
75a353d4 205ignore:
1eb8c695
AV		 206 mlx4_en_filter_rfs_expire(priv);
207
208 filter->activated = 1;
209}
210
211static inline struct hlist_head *
212filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
213 __be16 src_port, __be16 dst_port)
214{
215 unsigned long l;
216 int bucket_idx;
217
218 l = (__force unsigned long)src_port |
219 ((__force unsigned long)dst_port << 2);
220 l ^= (__force unsigned long)(src_ip ^ dst_ip);
221
222 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
223
224 return &priv->filter_hash[bucket_idx];
225}
226
227static struct mlx4_en_filter *
228mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 229 __be32 dst_ip, u8 ip_proto, __be16 src_port,
230 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 231{
232 struct mlx4_en_filter *filter = NULL;
233
234 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
235 if (!filter)
236 return NULL;
237
238 filter->priv = priv;
239 filter->rxq_index = rxq_index;
240 INIT_WORK(&filter->work, mlx4_en_filter_work);
241
242 filter->src_ip = src_ip;
243 filter->dst_ip = dst_ip;
75a353d4 244 filter->ip_proto = ip_proto;
1eb8c695
AV		 245 filter->src_port = src_port;
246 filter->dst_port = dst_port;
247
248 filter->flow_id = flow_id;
249
ee64c0ee 250 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 251
252 list_add_tail(&filter->next, &priv->filters);
253 hlist_add_head(&filter->filter_chain,
254 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
255 dst_port));
256
257 return filter;
258}
259
260static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
261{
262 struct mlx4_en_priv *priv = filter->priv;
263 int rc;
264
265 list_del(&filter->next);
266
267 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
268 if (rc && rc != -ENOENT)
269 en_err(priv, "Error detaching flow. rc = %d\n", rc);
270
271 kfree(filter);
272}
273
274static inline struct mlx4_en_filter *
275mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 276 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 277{
1eb8c695
AV		 278 struct mlx4_en_filter *filter;
279 struct mlx4_en_filter *ret = NULL;
280
b67bfe0d 281 hlist_for_each_entry(filter,
1eb8c695
AV		 282 filter_hash_bucket(priv, src_ip, dst_ip,
283 src_port, dst_port),
284 filter_chain) {
285 if (filter->src_ip == src_ip &&
286 filter->dst_ip == dst_ip &&
75a353d4 287 filter->ip_proto == ip_proto &&
1eb8c695
AV		 288 filter->src_port == src_port &&
289 filter->dst_port == dst_port) {
290 ret = filter;
291 break;
292 }
293 }
294
295 return ret;
296}
297
298static int
299mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
300 u16 rxq_index, u32 flow_id)
301{
302 struct mlx4_en_priv *priv = netdev_priv(net_dev);
303 struct mlx4_en_filter *filter;
304 const struct iphdr *ip;
305 const __be16 *ports;
75a353d4 306 u8 ip_proto;
1eb8c695
AV		 307 __be32 src_ip;
308 __be32 dst_ip;
309 __be16 src_port;
310 __be16 dst_port;
311 int nhoff = skb_network_offset(skb);
312 int ret = 0;
313
314 if (skb->protocol != htons(ETH_P_IP))
315 return -EPROTONOSUPPORT;
316
317 ip = (const struct iphdr *)(skb->data + nhoff);
318 if (ip_is_fragment(ip))
319 return -EPROTONOSUPPORT;
320
75a353d4
EP		 321 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
322 return -EPROTONOSUPPORT;
1eb8c695
AV		 323 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
324
75a353d4 325 ip_proto = ip->protocol;
1eb8c695
AV		 326 src_ip = ip->saddr;
327 dst_ip = ip->daddr;
328 src_port = ports[0];
329 dst_port = ports[1];
330
1eb8c695 331 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 332 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
333 src_port, dst_port);
1eb8c695
AV		 334 if (filter) {
335 if (filter->rxq_index == rxq_index)
336 goto out;
337
338 filter->rxq_index = rxq_index;
339 } else {
340 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 341 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 342 src_port, dst_port, flow_id);
343 if (!filter) {
344 ret = -ENOMEM;
345 goto err;
346 }
347 }
348
349 queue_work(priv->mdev->workqueue, &filter->work);
350
351out:
352 ret = filter->id;
353err:
354 spin_unlock_bh(&priv->filters_lock);
355
356 return ret;
357}
358
41d942d5 359void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 360{
361 struct mlx4_en_filter *filter, *tmp;
362 LIST_HEAD(del_list);
363
364 spin_lock_bh(&priv->filters_lock);
365 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
366 list_move(&filter->next, &del_list);
367 hlist_del(&filter->filter_chain);
368 }
369 spin_unlock_bh(&priv->filters_lock);
370
371 list_for_each_entry_safe(filter, tmp, &del_list, next) {
372 cancel_work_sync(&filter->work);
373 mlx4_en_filter_free(filter);
374 }
375}
376
377static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
378{
379 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
380 LIST_HEAD(del_list);
381 int i = 0;
382
383 spin_lock_bh(&priv->filters_lock);
384 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
385 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
386 break;
387
388 if (filter->activated &&
389 !work_pending(&filter->work) &&
390 rps_may_expire_flow(priv->dev,
391 filter->rxq_index, filter->flow_id,
392 filter->id)) {
393 list_move(&filter->next, &del_list);
394 hlist_del(&filter->filter_chain);
395 } else
396 last_filter = filter;
397
398 i++;
399 }
400
401 if (last_filter && (&last_filter->next != priv->filters.next))
402 list_move(&priv->filters, &last_filter->next);
403
404 spin_unlock_bh(&priv->filters_lock);
405
406 list_for_each_entry_safe(filter, tmp, &del_list, next)
407 mlx4_en_filter_free(filter);
408}
409#endif
410
80d5c368
PM		 411static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
412 __be16 proto, u16 vid)
c27a02cd
YP		 413{
414 struct mlx4_en_priv *priv = netdev_priv(dev);
415 struct mlx4_en_dev *mdev = priv->mdev;
416 int err;
4c3eb3ca 417 int idx;
c27a02cd 418
f1b553fb 419 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 420
f1b553fb 421 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 422
423 /* Add VID to port VLAN filter */
424 mutex_lock(&mdev->state_lock);
425 if (mdev->device_up && priv->port_up) {
f1b553fb 426 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 427 if (err)
453a6082 428 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 429 }
4c3eb3ca 430 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 431 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 432 mutex_unlock(&mdev->state_lock);
4c3eb3ca 433
8e586137 434 return 0;
c27a02cd
YP		 435}
436
80d5c368
PM		 437static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
438 __be16 proto, u16 vid)
c27a02cd
YP		 439{
440 struct mlx4_en_priv *priv = netdev_priv(dev);
441 struct mlx4_en_dev *mdev = priv->mdev;
442 int err;
443
f1b553fb 444 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 445
f1b553fb 446 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 447
448 /* Remove VID from port VLAN filter */
449 mutex_lock(&mdev->state_lock);
2009d005 450 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 451
c27a02cd 452 if (mdev->device_up && priv->port_up) {
f1b553fb 453 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 454 if (err)
453a6082 455 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 456 }
457 mutex_unlock(&mdev->state_lock);
8e586137
JP		 458
459 return 0;
c27a02cd
YP		 460}
461
6bbb6d99
YB		 462static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
463{
bab6a9ea
YB		 464 int i;
465 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 466 dst_mac[i] = src_mac & 0xff;
467 src_mac >>= 8;
468 }
469 memset(&dst_mac[ETH_ALEN], 0, 2);
470}
471
837052d0
OG		 472
473static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
474 int qpn, u64 *reg_id)
475{
476 int err;
837052d0 477
5eff6dad
OG		 478 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
479 priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
837052d0
OG		 480 return 0; /* do nothing */
481
b95089d0
OG		 482 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
483 MLX4_DOMAIN_NIC, reg_id);
837052d0
OG		 484 if (err) {
485 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
486 return err;
487 }
488 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
489 return 0;
490}
491
492
16a10ffd
YB		 493static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
494 unsigned char *mac, int *qpn, u64 *reg_id)
495{
496 struct mlx4_en_dev *mdev = priv->mdev;
497 struct mlx4_dev *dev = mdev->dev;
498 int err;
499
500 switch (dev->caps.steering_mode) {
501 case MLX4_STEERING_MODE_B0: {
502 struct mlx4_qp qp;
503 u8 gid[16] = {0};
504
505 qp.qpn = *qpn;
506 memcpy(&gid[10], mac, ETH_ALEN);
507 gid[5] = priv->port;
508
509 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
510 break;
511 }
512 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
513 struct mlx4_spec_list spec_eth = { {NULL} };
514 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
515
516 struct mlx4_net_trans_rule rule = {
517 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
518 .exclusive = 0,
519 .allow_loopback = 1,
f9162539 520 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 521 .priority = MLX4_DOMAIN_NIC,
522 };
523
524 rule.port = priv->port;
525 rule.qpn = *qpn;
526 INIT_LIST_HEAD(&rule.list);
527
528 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
529 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
530 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
531 list_add_tail(&spec_eth.list, &rule.list);
532
533 err = mlx4_flow_attach(dev, &rule, reg_id);
534 break;
535 }
536 default:
537 return -EINVAL;
538 }
539 if (err)
540 en_warn(priv, "Failed Attaching Unicast\n");
541
542 return err;
543}
544
545static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
546 unsigned char *mac, int qpn, u64 reg_id)
547{
548 struct mlx4_en_dev *mdev = priv->mdev;
549 struct mlx4_dev *dev = mdev->dev;
550
551 switch (dev->caps.steering_mode) {
552 case MLX4_STEERING_MODE_B0: {
553 struct mlx4_qp qp;
554 u8 gid[16] = {0};
555
556 qp.qpn = qpn;
557 memcpy(&gid[10], mac, ETH_ALEN);
558 gid[5] = priv->port;
559
560 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
561 break;
562 }
563 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
564 mlx4_flow_detach(dev, reg_id);
565 break;
566 }
567 default:
568 en_err(priv, "Invalid steering mode.\n");
569 }
570}
571
572static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
573{
574 struct mlx4_en_dev *mdev = priv->mdev;
575 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB		 576 int index = 0;
577 int err = 0;
16a10ffd 578 int *qpn = &priv->base_qpn;
9813337a 579 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 580
581 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
582 priv->dev->dev_addr);
583 index = mlx4_register_mac(dev, priv->port, mac);
584 if (index < 0) {
585 err = index;
586 en_err(priv, "Failed adding MAC: %pM\n",
587 priv->dev->dev_addr);
588 return err;
589 }
590
591 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
592 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
593 *qpn = base_qpn + index;
594 return 0;
595 }
596
d57febe1 597 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP);
16a10ffd
YB		 598 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
599 if (err) {
600 en_err(priv, "Failed to reserve qp for mac registration\n");
ba4b87ae
IS		 601 mlx4_unregister_mac(dev, priv->port, mac);
602 return err;
16a10ffd 603 }
16a10ffd 604
c07cb4b0 605 return 0;
16a10ffd
YB		 606}
607
608static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
609{
610 struct mlx4_en_dev *mdev = priv->mdev;
611 struct mlx4_dev *dev = mdev->dev;
16a10ffd 612 int qpn = priv->base_qpn;
16a10ffd 613
83a5a6ce 614 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
ba4b87ae 615 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 616 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
617 priv->dev->dev_addr);
618 mlx4_unregister_mac(dev, priv->port, mac);
619 } else {
83a5a6ce
YB		 620 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
621 priv->port, qpn);
622 mlx4_qp_release_range(dev, qpn, 1);
623 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 624 }
625}
626
627static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 628 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 629{
630 struct mlx4_en_dev *mdev = priv->mdev;
631 struct mlx4_dev *dev = mdev->dev;
16a10ffd 632 int err = 0;
9813337a 633 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 634
635 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 636 struct hlist_head *bucket;
637 unsigned int mac_hash;
638 struct mlx4_mac_entry *entry;
b67bfe0d 639 struct hlist_node *tmp;
9813337a 640 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 641
642 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 643 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 644 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
645 mlx4_en_uc_steer_release(priv, entry->mac,
646 qpn, entry->reg_id);
647 mlx4_unregister_mac(dev, priv->port,
648 prev_mac_u64);
649 hlist_del_rcu(&entry->hlist);
650 synchronize_rcu();
651 memcpy(entry->mac, new_mac, ETH_ALEN);
652 entry->reg_id = 0;
653 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
654 hlist_add_head_rcu(&entry->hlist,
655 &priv->mac_hash[mac_hash]);
656 mlx4_register_mac(dev, priv->port, new_mac_u64);
657 err = mlx4_en_uc_steer_add(priv, new_mac,
658 &qpn,
659 &entry->reg_id);
2a2083f7
OG		 660 if (err)
661 return err;
662 if (priv->tunnel_reg_id) {
663 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
664 priv->tunnel_reg_id = 0;
665 }
666 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
667 &priv->tunnel_reg_id);
c07cb4b0
YB		 668 return err;
669 }
670 }
671 return -EINVAL;
16a10ffd
YB		 672 }
673
674 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
675}
676
2695bab2
NO		 677static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
678 unsigned char new_mac[ETH_ALEN + 2])
c27a02cd 679{
c27a02cd
YP		 680 int err = 0;
681
c27a02cd
YP		 682 if (priv->port_up) {
683 /* Remove old MAC and insert the new one */
16a10ffd 684 err = mlx4_en_replace_mac(priv, priv->base_qpn,
2695bab2 685 new_mac, priv->current_mac);
c27a02cd 686 if (err)
453a6082 687 en_err(priv, "Failed changing HW MAC address\n");
c27a02cd 688 } else
48e551ff 689 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 690
2695bab2
NO		 691 if (!err)
692 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
ee755324 693
bfa8ab47
YB		 694 return err;
695}
696
697static int mlx4_en_set_mac(struct net_device *dev, void *addr)
698{
699 struct mlx4_en_priv *priv = netdev_priv(dev);
700 struct mlx4_en_dev *mdev = priv->mdev;
701 struct sockaddr *saddr = addr;
2695bab2 702 unsigned char new_mac[ETH_ALEN + 2];
bfa8ab47
YB		 703 int err;
704
705 if (!is_valid_ether_addr(saddr->sa_data))
706 return -EADDRNOTAVAIL;
707
bfa8ab47 708 mutex_lock(&mdev->state_lock);
2695bab2
NO		 709 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
710 err = mlx4_en_do_set_mac(priv, new_mac);
711 if (!err)
712 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
c27a02cd 713 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 714
715 return err;
c27a02cd
YP		 716}
717
718static void mlx4_en_clear_list(struct net_device *dev)
719{
720 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 721 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 722
6d199937
YP		 723 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
724 list_del(&mc_to_del->list);
725 kfree(mc_to_del);
726 }
c27a02cd
YP		 727}
728
729static void mlx4_en_cache_mclist(struct net_device *dev)
730{
731 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 732 struct netdev_hw_addr *ha;
6d199937 733 struct mlx4_en_mc_list *tmp;
ff6e2163 734
0e03567a 735 mlx4_en_clear_list(dev);
6d199937
YP		 736 netdev_for_each_mc_addr(ha, dev) {
737 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
738 if (!tmp) {
6d199937
YP		 739 mlx4_en_clear_list(dev);
740 return;
741 }
742 memcpy(tmp->addr, ha->addr, ETH_ALEN);
743 list_add_tail(&tmp->list, &priv->mc_list);
744 }
c27a02cd
YP		 745}
746
6d199937
YP		 747static void update_mclist_flags(struct mlx4_en_priv *priv,
748 struct list_head *dst,
749 struct list_head *src)
750{
751 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
752 bool found;
753
754 /* Find all the entries that should be removed from dst,
755 * These are the entries that are not found in src
756 */
757 list_for_each_entry(dst_tmp, dst, list) {
758 found = false;
759 list_for_each_entry(src_tmp, src, list) {
c0623e58 760 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 761 found = true;
762 break;
763 }
764 }
765 if (!found)
766 dst_tmp->action = MCLIST_REM;
767 }
768
769 /* Add entries that exist in src but not in dst
770 * mark them as need to add
771 */
772 list_for_each_entry(src_tmp, src, list) {
773 found = false;
774 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 775 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 776 dst_tmp->action = MCLIST_NONE;
777 found = true;
778 break;
779 }
780 }
781 if (!found) {
14f8dc49
JP		 782 new_mc = kmemdup(src_tmp,
783 sizeof(struct mlx4_en_mc_list),
6d199937 784 GFP_KERNEL);
14f8dc49 785 if (!new_mc)
6d199937 786 return;
14f8dc49 787
6d199937
YP		 788 new_mc->action = MCLIST_ADD;
789 list_add_tail(&new_mc->list, dst);
790 }
791 }
792}
c27a02cd 793
0eb74fdd 794static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 795{
796 struct mlx4_en_priv *priv = netdev_priv(dev);
797
798 if (!priv->port_up)
799 return;
800
0eb74fdd 801 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 802}
803
0eb74fdd
YB		 804static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
805 struct mlx4_en_dev *mdev)
c27a02cd 806{
c96d97f4 807 int err = 0;
c27a02cd 808
0eb74fdd 809 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 810 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 811 en_warn(priv, "Entering promiscuous mode\n");
812 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 813
0eb74fdd 814 /* Enable promiscouos mode */
c96d97f4 815 switch (mdev->dev->caps.steering_mode) {
592e49dd 816 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 817 err = mlx4_flow_steer_promisc_add(mdev->dev,
818 priv->port,
819 priv->base_qpn,
f9162539 820 MLX4_FS_ALL_DEFAULT);
592e49dd 821 if (err)
0eb74fdd
YB		 822 en_err(priv, "Failed enabling promiscuous mode\n");
823 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 824 break;
825
c96d97f4 826 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 827 err = mlx4_unicast_promisc_add(mdev->dev,
828 priv->base_qpn,
829 priv->port);
c96d97f4 830 if (err)
0eb74fdd
YB		 831 en_err(priv, "Failed enabling unicast promiscuous mode\n");
832
833 /* Add the default qp number as multicast
834 * promisc
835 */
836 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
837 err = mlx4_multicast_promisc_add(mdev->dev,
838 priv->base_qpn,
839 priv->port);
c96d97f4 840 if (err)
0eb74fdd
YB		 841 en_err(priv, "Failed enabling multicast promiscuous mode\n");
842 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 843 }
844 break;
c27a02cd 845
c96d97f4
HHZ		 846 case MLX4_STEERING_MODE_A0:
847 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
848 priv->port,
0eb74fdd
YB		 849 priv->base_qpn,
850 1);
1679200f 851 if (err)
0eb74fdd 852 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 853 break;
1679200f
YP		 854 }
855
0eb74fdd
YB		 856 /* Disable port multicast filter (unconditionally) */
857 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
858 0, MLX4_MCAST_DISABLE);
859 if (err)
860 en_err(priv, "Failed disabling multicast filter\n");
0eb74fdd
YB		 861 }
862}
863
864static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
865 struct mlx4_en_dev *mdev)
866{
867 int err = 0;
868
869 if (netif_msg_rx_status(priv))
870 en_warn(priv, "Leaving promiscuous mode\n");
871 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
872
873 /* Disable promiscouos mode */
874 switch (mdev->dev->caps.steering_mode) {
875 case MLX4_STEERING_MODE_DEVICE_MANAGED:
876 err = mlx4_flow_steer_promisc_remove(mdev->dev,
877 priv->port,
f9162539 878 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 879 if (err)
880 en_err(priv, "Failed disabling promiscuous mode\n");
881 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
882 break;
883
884 case MLX4_STEERING_MODE_B0:
885 err = mlx4_unicast_promisc_remove(mdev->dev,
886 priv->base_qpn,
887 priv->port);
888 if (err)
889 en_err(priv, "Failed disabling unicast promiscuous mode\n");
890 /* Disable Multicast promisc */
891 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
892 err = mlx4_multicast_promisc_remove(mdev->dev,
893 priv->base_qpn,
894 priv->port);
895 if (err)
896 en_err(priv, "Failed disabling multicast promiscuous mode\n");
897 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
898 }
899 break;
900
901 case MLX4_STEERING_MODE_A0:
902 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
903 priv->port,
904 priv->base_qpn, 0);
905 if (err)
906 en_err(priv, "Failed disabling promiscuous mode\n");
907 break;
c27a02cd 908 }
0eb74fdd
YB		 909}
910
911static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
912 struct net_device *dev,
913 struct mlx4_en_dev *mdev)
914{
915 struct mlx4_en_mc_list *mclist, *tmp;
916 u64 mcast_addr = 0;
917 u8 mc_list[16] = {0};
918 int err = 0;
919
c27a02cd
YP		 920 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
921 if (dev->flags & IFF_ALLMULTI) {
922 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
923 0, MLX4_MCAST_DISABLE);
924 if (err)
453a6082 925 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 926
927 /* Add the default qp number as multicast promisc */
928 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 929 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 930 case MLX4_STEERING_MODE_DEVICE_MANAGED:
931 err = mlx4_flow_steer_promisc_add(mdev->dev,
932 priv->port,
933 priv->base_qpn,
f9162539 934 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 935 break;
936
c96d97f4
HHZ		 937 case MLX4_STEERING_MODE_B0:
938 err = mlx4_multicast_promisc_add(mdev->dev,
939 priv->base_qpn,
940 priv->port);
941 break;
942
943 case MLX4_STEERING_MODE_A0:
944 break;
945 }
1679200f
YP		 946 if (err)
947 en_err(priv, "Failed entering multicast promisc mode\n");
948 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
949 }
c27a02cd 950 } else {
1679200f
YP		 951 /* Disable Multicast promisc */
952 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 953 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 954 case MLX4_STEERING_MODE_DEVICE_MANAGED:
955 err = mlx4_flow_steer_promisc_remove(mdev->dev,
956 priv->port,
f9162539 957 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 958 break;
959
c96d97f4
HHZ		 960 case MLX4_STEERING_MODE_B0:
961 err = mlx4_multicast_promisc_remove(mdev->dev,
962 priv->base_qpn,
963 priv->port);
964 break;
965
966 case MLX4_STEERING_MODE_A0:
967 break;
968 }
1679200f 969 if (err)
25985edc 970 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 971 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
972 }
ff6e2163 973
c27a02cd
YP		 974 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
975 0, MLX4_MCAST_DISABLE);
976 if (err)
453a6082 977 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 978
979 /* Flush mcast filter and init it with broadcast address */
980 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
981 1, MLX4_MCAST_CONFIG);
982
983 /* Update multicast list - we cache all addresses so they won't
984 * change while HW is updated holding the command semaphor */
dbd501a8 985 netif_addr_lock_bh(dev);
c27a02cd 986 mlx4_en_cache_mclist(dev);
dbd501a8 987 netif_addr_unlock_bh(dev);
6d199937 988 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 989 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 990 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
991 mcast_addr, 0, MLX4_MCAST_CONFIG);
992 }
993 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
994 0, MLX4_MCAST_ENABLE);
995 if (err)
453a6082 996 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 997
998 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
999 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1000 if (mclist->action == MCLIST_REM) {
1001 /* detach this address and delete from list */
1002 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1003 mc_list[5] = priv->port;
1004 err = mlx4_multicast_detach(mdev->dev,
1005 &priv->rss_map.indir_qp,
1006 mc_list,
0ff1fb65
HHZ		 1007 MLX4_PROT_ETH,
1008 mclist->reg_id);
6d199937
YP		 1009 if (err)
1010 en_err(priv, "Fail to detach multicast address\n");
1011
837052d0
OG		 1012 if (mclist->tunnel_reg_id) {
1013 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1014 if (err)
1015 en_err(priv, "Failed to detach multicast address\n");
1016 }
1017
6d199937
YP		 1018 /* remove from list */
1019 list_del(&mclist->list);
1020 kfree(mclist);
9c64508a 1021 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1022 /* attach the address */
1023 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1024 /* needed for B0 steering support */
6d199937
YP		 1025 mc_list[5] = priv->port;
1026 err = mlx4_multicast_attach(mdev->dev,
1027 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1028 mc_list,
1029 priv->port, 0,
1030 MLX4_PROT_ETH,
1031 &mclist->reg_id);
6d199937
YP		 1032 if (err)
1033 en_err(priv, "Fail to attach multicast address\n");
1034
837052d0
OG		 1035 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1036 &mclist->tunnel_reg_id);
1037 if (err)
1038 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1039 }
1040 }
c27a02cd 1041 }
0eb74fdd
YB		 1042}
1043
cc5387f7
YB		 1044static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1045 struct net_device *dev,
1046 struct mlx4_en_dev *mdev)
1047{
1048 struct netdev_hw_addr *ha;
1049 struct mlx4_mac_entry *entry;
b67bfe0d 1050 struct hlist_node *tmp;
cc5387f7
YB		 1051 bool found;
1052 u64 mac;
1053 int err = 0;
1054 struct hlist_head *bucket;
1055 unsigned int i;
1056 int removed = 0;
1057 u32 prev_flags;
1058
1059 /* Note that we do not need to protect our mac_hash traversal with rcu,
1060 * since all modification code is protected by mdev->state_lock
1061 */
1062
1063 /* find what to remove */
1064 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1065 bucket = &priv->mac_hash[i];
b67bfe0d 1066 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1067 found = false;
1068 netdev_for_each_uc_addr(ha, dev) {
1069 if (ether_addr_equal_64bits(entry->mac,
1070 ha->addr)) {
1071 found = true;
1072 break;
1073 }
1074 }
1075
1076 /* MAC address of the port is not in uc list */
2695bab2
NO		 1077 if (ether_addr_equal_64bits(entry->mac,
1078 priv->current_mac))
cc5387f7
YB		 1079 found = true;
1080
1081 if (!found) {
9813337a 1082 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1083 mlx4_en_uc_steer_release(priv, entry->mac,
1084 priv->base_qpn,
1085 entry->reg_id);
1086 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1087
1088 hlist_del_rcu(&entry->hlist);
1089 kfree_rcu(entry, rcu);
1090 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1091 entry->mac, priv->port);
1092 ++removed;
1093 }
1094 }
1095 }
1096
1097 /* if we didn't remove anything, there is no use in trying to add
1098 * again once we are in a forced promisc mode state
1099 */
1100 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1101 return;
1102
1103 prev_flags = priv->flags;
1104 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1105
1106 /* find what to add */
1107 netdev_for_each_uc_addr(ha, dev) {
1108 found = false;
1109 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1110 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1111 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1112 found = true;
1113 break;
1114 }
1115 }
1116
1117 if (!found) {
1118 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1119 if (!entry) {
1120 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1121 ha->addr, priv->port);
1122 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1123 break;
1124 }
9813337a 1125 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1126 memcpy(entry->mac, ha->addr, ETH_ALEN);
1127 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1128 if (err < 0) {
1129 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1130 ha->addr, priv->port, err);
1131 kfree(entry);
1132 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1133 break;
1134 }
1135 err = mlx4_en_uc_steer_add(priv, ha->addr,
1136 &priv->base_qpn,
1137 &entry->reg_id);
1138 if (err) {
1139 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1140 ha->addr, priv->port, err);
1141 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1142 kfree(entry);
1143 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1144 break;
1145 } else {
1146 unsigned int mac_hash;
1147 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1148 ha->addr, priv->port);
1149 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1150 bucket = &priv->mac_hash[mac_hash];
1151 hlist_add_head_rcu(&entry->hlist, bucket);
1152 }
1153 }
1154 }
1155
1156 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1157 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1158 priv->port);
1159 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1160 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1161 priv->port);
1162 }
1163}
1164
0eb74fdd
YB		 1165static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1166{
1167 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1168 rx_mode_task);
1169 struct mlx4_en_dev *mdev = priv->mdev;
1170 struct net_device *dev = priv->dev;
1171
1172 mutex_lock(&mdev->state_lock);
1173 if (!mdev->device_up) {
1174 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1175 goto out;
1176 }
1177 if (!priv->port_up) {
1178 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1179 goto out;
1180 }
1181
1182 if (!netif_carrier_ok(dev)) {
1183 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1184 if (priv->port_state.link_state) {
1185 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1186 netif_carrier_on(dev);
1187 en_dbg(LINK, priv, "Link Up\n");
1188 }
1189 }
1190 }
1191
cc5387f7
YB		 1192 if (dev->priv_flags & IFF_UNICAST_FLT)
1193 mlx4_en_do_uc_filter(priv, dev, mdev);
1194
0eb74fdd 1195 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1196 if ((dev->flags & IFF_PROMISC) ||
1197 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1198 mlx4_en_set_promisc_mode(priv, mdev);
1199 goto out;
1200 }
1201
1202 /* Not in promiscuous mode */
1203 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1204 mlx4_en_clear_promisc_mode(priv, mdev);
1205
1206 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1207out:
1208 mutex_unlock(&mdev->state_lock);
1209}
1210
1211#ifdef CONFIG_NET_POLL_CONTROLLER
1212static void mlx4_en_netpoll(struct net_device *dev)
1213{
1214 struct mlx4_en_priv *priv = netdev_priv(dev);
1215 struct mlx4_en_cq *cq;
c27a02cd
YP		 1216 int i;
1217
1218 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1219 cq = priv->rx_cq[i];
c98235cb 1220 napi_schedule(&cq->napi);
c27a02cd
YP		 1221 }
1222}
1223#endif
1224
ba4b87ae
IS		 1225static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv)
1226{
1227 u64 reg_id;
1228 int err = 0;
1229 int *qpn = &priv->base_qpn;
1230 struct mlx4_mac_entry *entry;
1231
1232 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
1233 if (err)
1234 return err;
1235
1236 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
1237 &priv->tunnel_reg_id);
1238 if (err)
1239 goto tunnel_err;
1240
1241 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1242 if (!entry) {
1243 err = -ENOMEM;
1244 goto alloc_err;
1245 }
1246
1247 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
1248 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
1249 entry->reg_id = reg_id;
1250 hlist_add_head_rcu(&entry->hlist,
1251 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
1252
1253 return 0;
1254
1255alloc_err:
1256 if (priv->tunnel_reg_id)
1257 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1258
1259tunnel_err:
1260 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
1261 return err;
1262}
1263
1264static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv)
1265{
1266 u64 mac;
1267 unsigned int i;
1268 int qpn = priv->base_qpn;
1269 struct hlist_head *bucket;
1270 struct hlist_node *tmp;
1271 struct mlx4_mac_entry *entry;
1272
1273 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1274 bucket = &priv->mac_hash[i];
1275 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1276 mac = mlx4_mac_to_u64(entry->mac);
1277 en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n",
1278 entry->mac);
1279 mlx4_en_uc_steer_release(priv, entry->mac,
1280 qpn, entry->reg_id);
1281
1282 mlx4_unregister_mac(priv->mdev->dev, priv->port, mac);
1283 hlist_del_rcu(&entry->hlist);
1284 kfree_rcu(entry, rcu);
1285 }
1286 }
1287
1288 if (priv->tunnel_reg_id) {
1289 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1290 priv->tunnel_reg_id = 0;
1291 }
1292}
1293
c27a02cd
YP		 1294static void mlx4_en_tx_timeout(struct net_device *dev)
1295{
1296 struct mlx4_en_priv *priv = netdev_priv(dev);
1297 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1298 int i;
c27a02cd
YP		 1299
1300 if (netif_msg_timer(priv))
453a6082 1301 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1302
b944ebec
YP		 1303 for (i = 0; i < priv->tx_ring_num; i++) {
1304 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1305 continue;
1306 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1307 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1308 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1309 }
1310
1e338db5 1311 priv->port_stats.tx_timeout++;
453a6082 1312 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1313 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1314}
1315
1316
1317static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1318{
1319 struct mlx4_en_priv *priv = netdev_priv(dev);
1320
1321 spin_lock_bh(&priv->stats_lock);
1322 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1323 spin_unlock_bh(&priv->stats_lock);
1324
1325 return &priv->ret_stats;
1326}
1327
1328static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1329{
c27a02cd
YP		 1330 struct mlx4_en_cq *cq;
1331 int i;
1332
1333 /* If we haven't received a specific coalescing setting
98a1708d 1334 * (module param), we set the moderation parameters as follows:
c27a02cd 1335 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1336 * satisfy our coalescing target.
c27a02cd
YP		 1337 * - moder_time is set to a fixed value.
1338 */
3db36fb2 1339 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1340 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1341 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1342 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1343 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1344 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1345
1346 /* Setup cq moderation params */
1347 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1348 cq = priv->rx_cq[i];
c27a02cd
YP		 1349 cq->moder_cnt = priv->rx_frames;
1350 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1351 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1352 priv->last_moder_packets[i] = 0;
1353 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1354 }
1355
1356 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1357 cq = priv->tx_cq[i];
a19a848a
YP		 1358 cq->moder_cnt = priv->tx_frames;
1359 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1360 }
1361
1362 /* Reset auto-moderation params */
1363 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1364 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1365 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1366 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1367 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1368 priv->adaptive_rx_coal = 1;
c27a02cd 1369 priv->last_moder_jiffies = 0;
c27a02cd 1370 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1371}
1372
1373static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1374{
1375 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1376 struct mlx4_en_cq *cq;
1377 unsigned long packets;
1378 unsigned long rate;
1379 unsigned long avg_pkt_size;
1380 unsigned long rx_packets;
1381 unsigned long rx_bytes;
c27a02cd
YP		 1382 unsigned long rx_pkt_diff;
1383 int moder_time;
6b4d8d9f 1384 int ring, err;
c27a02cd
YP		 1385
1386 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1387 return;
1388
6b4d8d9f
AG		 1389 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1390 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1391 rx_packets = priv->rx_ring[ring]->packets;
1392 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1393 spin_unlock_bh(&priv->stats_lock);
1394
1395 rx_pkt_diff = ((unsigned long) (rx_packets -
1396 priv->last_moder_packets[ring]));
1397 packets = rx_pkt_diff;
1398 rate = packets * HZ / period;
1399 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1400 priv->last_moder_bytes[ring])) / packets : 0;
1401
1402 /* Apply auto-moderation only when packet rate
1403 * exceeds a rate that it matters */
1404 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1405 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1406 if (rate < priv->pkt_rate_low)
1407 moder_time = priv->rx_usecs_low;
1408 else if (rate > priv->pkt_rate_high)
1409 moder_time = priv->rx_usecs_high;
1410 else
1411 moder_time = (rate - priv->pkt_rate_low) *
1412 (priv->rx_usecs_high - priv->rx_usecs_low) /
1413 (priv->pkt_rate_high - priv->pkt_rate_low) +
1414 priv->rx_usecs_low;
6b4d8d9f
AG		 1415 } else {
1416 moder_time = priv->rx_usecs_low;
c27a02cd 1417 }
c27a02cd 1418
6b4d8d9f
AG		 1419 if (moder_time != priv->last_moder_time[ring]) {
1420 priv->last_moder_time[ring] = moder_time;
41d942d5 1421 cq = priv->rx_cq[ring];
c27a02cd 1422 cq->moder_time = moder_time;
a1c6693a 1423 cq->moder_cnt = priv->rx_frames;
c27a02cd 1424 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1425 if (err)
48e551ff
YB		 1426 en_err(priv, "Failed modifying moderation for cq:%d\n",
1427 ring);
c27a02cd 1428 }
6b4d8d9f
AG		 1429 priv->last_moder_packets[ring] = rx_packets;
1430 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1431 }
1432
c27a02cd
YP		 1433 priv->last_moder_jiffies = jiffies;
1434}
1435
1436static void mlx4_en_do_get_stats(struct work_struct *work)
1437{
bf6aede7 1438 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1439 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1440 stats_task);
1441 struct mlx4_en_dev *mdev = priv->mdev;
1442 int err;
1443
c27a02cd
YP		 1444 mutex_lock(&mdev->state_lock);
1445 if (mdev->device_up) {
6123db2e
JM		 1446 if (priv->port_up) {
1447 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1448 if (err)
1449 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1450
c27a02cd 1451 mlx4_en_auto_moderation(priv);
6123db2e 1452 }
c27a02cd
YP		 1453
1454 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1455 }
d7e1a487 1456 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
2695bab2 1457 mlx4_en_do_set_mac(priv, priv->current_mac);
d7e1a487
YP		 1458 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1459 }
c27a02cd
YP		 1460 mutex_unlock(&mdev->state_lock);
1461}
1462
b6c39bfc
AV		 1463/* mlx4_en_service_task - Run service task for tasks that needed to be done
1464 * periodically
1465 */
1466static void mlx4_en_service_task(struct work_struct *work)
1467{
1468 struct delayed_work *delay = to_delayed_work(work);
1469 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1470 service_task);
1471 struct mlx4_en_dev *mdev = priv->mdev;
1472
1473 mutex_lock(&mdev->state_lock);
1474 if (mdev->device_up) {
dc8142ea
AV		 1475 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1476 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc 1477
07841f9d 1478 mlx4_en_recover_from_oom(priv);
b6c39bfc
AV		 1479 queue_delayed_work(mdev->workqueue, &priv->service_task,
1480 SERVICE_TASK_DELAY);
1481 }
1482 mutex_unlock(&mdev->state_lock);
1483}
1484
c27a02cd
YP		 1485static void mlx4_en_linkstate(struct work_struct *work)
1486{
1487 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1488 linkstate_task);
1489 struct mlx4_en_dev *mdev = priv->mdev;
1490 int linkstate = priv->link_state;
1491
1492 mutex_lock(&mdev->state_lock);
1493 /* If observable port state changed set carrier state and
1494 * report to system log */
1495 if (priv->last_link_state != linkstate) {
1496 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1497 en_info(priv, "Link Down\n");
c27a02cd
YP		 1498 netif_carrier_off(priv->dev);
1499 } else {
e5cc44b2 1500 en_info(priv, "Link Up\n");
c27a02cd
YP		 1501 netif_carrier_on(priv->dev);
1502 }
1503 }
1504 priv->last_link_state = linkstate;
1505 mutex_unlock(&mdev->state_lock);
1506}
1507
9e311e77
YA		 1508static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1509{
1510 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1511 int numa_node = priv->mdev->dev->numa_node;
9e311e77
YA		 1512
1513 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1514 return -ENOMEM;
1515
f36963c9
RR		 1516 cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node),
1517 ring->affinity_mask);
1518 return 0;
9e311e77
YA		 1519}
1520
1521static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1522{
1523 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1524}
c27a02cd 1525
18cc42a3 1526int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1527{
1528 struct mlx4_en_priv *priv = netdev_priv(dev);
1529 struct mlx4_en_dev *mdev = priv->mdev;
1530 struct mlx4_en_cq *cq;
1531 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1532 int rx_index = 0;
1533 int tx_index = 0;
c27a02cd
YP		 1534 int err = 0;
1535 int i;
1536 int j;
1679200f 1537 u8 mc_list[16] = {0};
c27a02cd
YP		 1538
1539 if (priv->port_up) {
453a6082 1540 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1541 return 0;
1542 }
1543
6d199937
YP		 1544 INIT_LIST_HEAD(&priv->mc_list);
1545 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1546 INIT_LIST_HEAD(&priv->ethtool_list);
1547 memset(&priv->ethtool_rules[0], 0,
1548 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1549
c27a02cd
YP		 1550 /* Calculate Rx buf size */
1551 dev->mtu = min(dev->mtu, priv->max_mtu);
1552 mlx4_en_calc_rx_buf(dev);
453a6082 1553 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1554
c27a02cd 1555 /* Configure rx cq's and rings */
38aab07c
YP		 1556 err = mlx4_en_activate_rx_rings(priv);
1557 if (err) {
453a6082 1558 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1559 return err;
1560 }
c27a02cd 1561 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1562 cq = priv->rx_cq[i];
c27a02cd 1563
9e77a2b8
AV		 1564 mlx4_en_cq_init_lock(cq);
1565
9e311e77
YA		 1566 err = mlx4_en_init_affinity_hint(priv, i);
1567 if (err) {
1568 en_err(priv, "Failed preparing IRQ affinity hint\n");
1569 goto cq_err;
1570 }
1571
76532d0c 1572 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1573 if (err) {
453a6082 1574 en_err(priv, "Failed activating Rx CQ\n");
9e311e77 1575 mlx4_en_free_affinity_hint(priv, i);
a4233304 1576 goto cq_err;
c27a02cd 1577 }
c3f2511f
IS		 1578
1579 for (j = 0; j < cq->size; j++) {
1580 struct mlx4_cqe *cqe = NULL;
1581
1582 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1583 priv->cqe_factor;
1584 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1585 }
1586
c27a02cd
YP		 1587 err = mlx4_en_set_cq_moder(priv, cq);
1588 if (err) {
1a91de28 1589 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd 1590 mlx4_en_deactivate_cq(priv, cq);
9e311e77 1591 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1592 goto cq_err;
1593 }
1594 mlx4_en_arm_cq(priv, cq);
41d942d5 1595 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1596 ++rx_index;
1597 }
1598
ffe455ad
EE		 1599 /* Set qp number */
1600 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1601 err = mlx4_en_get_qp(priv);
1679200f 1602 if (err) {
ffe455ad 1603 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1604 goto cq_err;
1605 }
1606 mdev->mac_removed[priv->port] = 0;
1607
6de5f7f6
EBE		 1608 priv->counter_index =
1609 mlx4_get_default_counter_index(mdev->dev, priv->port);
1610
c27a02cd
YP		 1611 err = mlx4_en_config_rss_steer(priv);
1612 if (err) {
453a6082 1613 en_err(priv, "Failed configuring rss steering\n");
1679200f 1614 goto mac_err;
c27a02cd
YP		 1615 }
1616
cabdc8ee
HHZ		 1617 err = mlx4_en_create_drop_qp(priv);
1618 if (err)
1619 goto rss_err;
1620
c27a02cd
YP		 1621 /* Configure tx cq's and rings */
1622 for (i = 0; i < priv->tx_ring_num; i++) {
1623 /* Configure cq */
41d942d5 1624 cq = priv->tx_cq[i];
76532d0c 1625 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1626 if (err) {
453a6082 1627 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1628 goto tx_err;
1629 }
1630 err = mlx4_en_set_cq_moder(priv, cq);
1631 if (err) {
1a91de28 1632 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd
YP		 1633 mlx4_en_deactivate_cq(priv, cq);
1634 goto tx_err;
1635 }
453a6082 1636 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1637 cq->buf->wqe_index = cpu_to_be16(0xffff);
1638
1639 /* Configure ring */
41d942d5 1640 tx_ring = priv->tx_ring[i];
0e98b523 1641 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1642 i / priv->num_tx_rings_p_up);
c27a02cd 1643 if (err) {
453a6082 1644 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1645 mlx4_en_deactivate_cq(priv, cq);
1646 goto tx_err;
1647 }
5b263f53 1648 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1649
1650 /* Arm CQ for TX completions */
1651 mlx4_en_arm_cq(priv, cq);
1652
c27a02cd
YP		 1653 /* Set initial ownership of all Tx TXBBs to SW (1) */
1654 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1655 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1656 ++tx_index;
1657 }
1658
1659 /* Configure port */
1660 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1661 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1662 priv->prof->tx_pause,
1663 priv->prof->tx_ppp,
1664 priv->prof->rx_pause,
1665 priv->prof->rx_ppp);
c27a02cd 1666 if (err) {
48e551ff
YB		 1667 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1668 priv->port, err);
c27a02cd
YP		 1669 goto tx_err;
1670 }
1671 /* Set default qp number */
1672 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1673 if (err) {
453a6082 1674 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1675 goto tx_err;
1676 }
c27a02cd 1677
837052d0 1678 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 1679 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 1680 if (err) {
1681 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1682 err);
1683 goto tx_err;
1684 }
1685 }
1686
c27a02cd 1687 /* Init port */
453a6082 1688 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1689 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1690 if (err) {
453a6082 1691 en_err(priv, "Failed Initializing port\n");
1679200f 1692 goto tx_err;
c27a02cd
YP		 1693 }
1694
ba4b87ae
IS		 1695 /* Set Unicast and VXLAN steering rules */
1696 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 &&
1697 mlx4_en_set_rss_steer_rules(priv))
1698 mlx4_warn(mdev, "Failed setting steering rules\n");
1699
1679200f 1700 /* Attach rx QP to bradcast address */
c7bf7169 1701 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1702 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1703 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1704 priv->port, 0, MLX4_PROT_ETH,
1705 &priv->broadcast_id))
1679200f
YP		 1706 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1707
b5845f98
HX		 1708 /* Must redo promiscuous mode setup. */
1709 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1710
c27a02cd 1711 /* Schedule multicast task to populate multicast list */
0eb74fdd 1712 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1713
a66132f3 1714#ifdef CONFIG_MLX4_EN_VXLAN
9737c6ab 1715 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1 1716 vxlan_get_rx_port(dev);
a66132f3 1717#endif
c27a02cd 1718 priv->port_up = true;
a11faac7 1719 netif_tx_start_all_queues(dev);
3484aac1
AV		 1720 netif_device_attach(dev);
1721
c27a02cd
YP		 1722 return 0;
1723
c27a02cd
YP		 1724tx_err:
1725 while (tx_index--) {
41d942d5
EE		 1726 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1727 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1728 }
cabdc8ee
HHZ		 1729 mlx4_en_destroy_drop_qp(priv);
1730rss_err:
c27a02cd 1731 mlx4_en_release_rss_steer(priv);
1679200f 1732mac_err:
16a10ffd 1733 mlx4_en_put_qp(priv);
c27a02cd 1734cq_err:
9e311e77 1735 while (rx_index--) {
41d942d5 1736 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
f94813f3 1737 mlx4_en_free_affinity_hint(priv, rx_index);
9e311e77 1738 }
38aab07c 1739 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1740 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1741
1742 return err; /* need to close devices */
1743}
1744
1745
3484aac1 1746void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1747{
1748 struct mlx4_en_priv *priv = netdev_priv(dev);
1749 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1750 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1751 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1752 int i;
1679200f 1753 u8 mc_list[16] = {0};
c27a02cd
YP		 1754
1755 if (!priv->port_up) {
453a6082 1756 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1757 return;
1758 }
c27a02cd 1759
0cc5c8bf
EE		 1760 /* close port*/
1761 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1762
c27a02cd
YP		 1763 /* Synchronize with tx routine */
1764 netif_tx_lock_bh(dev);
3484aac1
AV		 1765 if (detach)
1766 netif_device_detach(dev);
3c05f5ef 1767 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1768 netif_tx_unlock_bh(dev);
1769
3484aac1
AV		 1770 netif_tx_disable(dev);
1771
7c287380 1772 /* Set port as not active */
3c05f5ef 1773 priv->port_up = false;
6de5f7f6 1774 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
c27a02cd 1775
db0e7cba
AY		 1776 /* Promsicuous mode */
1777 if (mdev->dev->caps.steering_mode ==
1778 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1779 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1780 MLX4_EN_FLAG_MC_PROMISC);
1781 mlx4_flow_steer_promisc_remove(mdev->dev,
1782 priv->port,
f9162539 1783 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1784 mlx4_flow_steer_promisc_remove(mdev->dev,
1785 priv->port,
f9162539 1786 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1787 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1788 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1789
1790 /* Disable promiscouos mode */
1791 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1792 priv->port);
1793
1794 /* Disable Multicast promisc */
1795 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1796 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1797 priv->port);
1798 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1799 }
1800 }
1801
1679200f 1802 /* Detach All multicasts */
c7bf7169 1803 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1804 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1805 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1806 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1807 list_for_each_entry(mclist, &priv->curr_list, list) {
1808 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1809 mc_list[5] = priv->port;
1810 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1811 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1812 if (mclist->tunnel_reg_id)
1813 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1814 }
1815 mlx4_en_clear_list(dev);
6d199937
YP		 1816 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1817 list_del(&mclist->list);
1818 kfree(mclist);
1819 }
1820
1679200f
YP		 1821 /* Flush multicast filter */
1822 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1823
6efb5fac
HHZ		 1824 /* Remove flow steering rules for the port*/
1825 if (mdev->dev->caps.steering_mode ==
1826 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1827 ASSERT_RTNL();
1828 list_for_each_entry_safe(flow, tmp_flow,
1829 &priv->ethtool_list, list) {
1830 mlx4_flow_detach(mdev->dev, flow->id);
1831 list_del(&flow->list);
1832 }
1833 }
1834
cabdc8ee
HHZ		 1835 mlx4_en_destroy_drop_qp(priv);
1836
c27a02cd
YP		 1837 /* Free TX Rings */
1838 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1839 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1840 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1841 }
1842 msleep(10);
1843
1844 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1845 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd 1846
ba4b87ae
IS		 1847 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
1848 mlx4_en_delete_rss_steer_rules(priv);
1849
c27a02cd
YP		 1850 /* Free RSS qps */
1851 mlx4_en_release_rss_steer(priv);
1852
ffe455ad 1853 /* Unregister Mac address for the port */
16a10ffd 1854 mlx4_en_put_qp(priv);
5930e8d0 1855 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1856 mdev->mac_removed[priv->port] = 1;
ffe455ad 1857
c27a02cd
YP		 1858 /* Free RX Rings */
1859 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1860 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8
AV		 1861
1862 local_bh_disable();
1863 while (!mlx4_en_cq_lock_napi(cq)) {
1864 pr_info("CQ %d locked\n", i);
1865 mdelay(1);
1866 }
1867 local_bh_enable();
1868
f4a36751 1869 napi_synchronize(&cq->napi);
41d942d5 1870 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1871 mlx4_en_deactivate_cq(priv, cq);
9e311e77
YA		 1872
1873 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1874 }
1875}
1876
1877static void mlx4_en_restart(struct work_struct *work)
1878{
1879 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1880 watchdog_task);
1881 struct mlx4_en_dev *mdev = priv->mdev;
1882 struct net_device *dev = priv->dev;
1883
453a6082 1884 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1885
1886 mutex_lock(&mdev->state_lock);
1887 if (priv->port_up) {
3484aac1 1888 mlx4_en_stop_port(dev, 1);
1e338db5 1889 if (mlx4_en_start_port(dev))
453a6082 1890 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1891 }
1892 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1893}
1894
b477ba62 1895static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1896{
1897 struct mlx4_en_priv *priv = netdev_priv(dev);
1898 struct mlx4_en_dev *mdev = priv->mdev;
1899 int i;
c27a02cd 1900
c27a02cd 1901 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1902 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1903
1904 memset(&priv->stats, 0, sizeof(priv->stats));
1905 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1906 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1907 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
0b131561
MB		 1908 memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
1909 memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
1910 memset(&priv->rx_priority_flowstats, 0,
1911 sizeof(priv->rx_priority_flowstats));
1912 memset(&priv->tx_priority_flowstats, 0,
1913 sizeof(priv->tx_priority_flowstats));
b42de4d0 1914 memset(&priv->pf_stats, 0, sizeof(priv->pf_stats));
c27a02cd
YP		 1915
1916 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1917 priv->tx_ring[i]->bytes = 0;
1918 priv->tx_ring[i]->packets = 0;
1919 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1920 }
1921 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1922 priv->rx_ring[i]->bytes = 0;
1923 priv->rx_ring[i]->packets = 0;
1924 priv->rx_ring[i]->csum_ok = 0;
1925 priv->rx_ring[i]->csum_none = 0;
f8c6455b 1926 priv->rx_ring[i]->csum_complete = 0;
c27a02cd 1927 }
b477ba62
EE		 1928}
1929
1930static int mlx4_en_open(struct net_device *dev)
1931{
1932 struct mlx4_en_priv *priv = netdev_priv(dev);
1933 struct mlx4_en_dev *mdev = priv->mdev;
1934 int err = 0;
1935
1936 mutex_lock(&mdev->state_lock);
1937
1938 if (!mdev->device_up) {
1939 en_err(priv, "Cannot open - device down/disabled\n");
1940 err = -EBUSY;
1941 goto out;
1942 }
1943
1944 /* Reset HW statistics and SW counters */
1945 mlx4_en_clear_stats(dev);
c27a02cd 1946
c27a02cd
YP		 1947 err = mlx4_en_start_port(dev);
1948 if (err)
453a6082 1949 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1950
1951out:
1952 mutex_unlock(&mdev->state_lock);
1953 return err;
1954}
1955
1956
1957static int mlx4_en_close(struct net_device *dev)
1958{
1959 struct mlx4_en_priv *priv = netdev_priv(dev);
1960 struct mlx4_en_dev *mdev = priv->mdev;
1961
453a6082 1962 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1963
1964 mutex_lock(&mdev->state_lock);
1965
3484aac1 1966 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1967 netif_carrier_off(dev);
1968
1969 mutex_unlock(&mdev->state_lock);
1970 return 0;
1971}
1972
fe0af03c 1973void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1974{
1975 int i;
1976
1eb8c695 1977#ifdef CONFIG_RFS_ACCEL
1eb8c695
AV		 1978 priv->dev->rx_cpu_rmap = NULL;
1979#endif
1980
c27a02cd 1981 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1982 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1983 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1984 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1985 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1986 }
1987
1988 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1989 if (priv->rx_ring[i])
68355f71
TLSC		 1990 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1991 priv->prof->rx_ring_size, priv->stride);
41d942d5 1992 if (priv->rx_cq[i])
fe0af03c 1993 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1994 }
044ca2a5 1995
c27a02cd
YP		 1996}
1997
18cc42a3 1998int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1999{
c27a02cd
YP		 2000 struct mlx4_en_port_profile *prof = priv->prof;
2001 int i;
163561a4 2002 int node;
87a5c389 2003
c27a02cd
YP		 2004 /* Create tx Rings */
2005 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 2006 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2007 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 2008 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 2009 goto err;
2010
d03a68f8 2011 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
d03a68f8
IS		 2012 prof->tx_ring_size, TXBB_SIZE,
2013 node, i))
c27a02cd
YP		 2014 goto err;
2015 }
2016
2017 /* Create rx Rings */
2018 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2019 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2020 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2021 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2022 goto err;
2023
2024 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2025 prof->rx_ring_size, priv->stride,
2026 node))
c27a02cd
YP		 2027 goto err;
2028 }
2029
1eb8c695 2030#ifdef CONFIG_RFS_ACCEL
c66fa19c 2031 priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port);
1eb8c695
AV		 2032#endif
2033
c27a02cd
YP		 2034 return 0;
2035
2036err:
453a6082 2037 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2038 for (i = 0; i < priv->rx_ring_num; i++) {
2039 if (priv->rx_ring[i])
2040 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2041 prof->rx_ring_size,
2042 priv->stride);
2043 if (priv->rx_cq[i])
2044 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2045 }
2046 for (i = 0; i < priv->tx_ring_num; i++) {
2047 if (priv->tx_ring[i])
2048 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2049 if (priv->tx_cq[i])
2050 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2051 }
c27a02cd
YP		 2052 return -ENOMEM;
2053}
2054
2055
2056void mlx4_en_destroy_netdev(struct net_device *dev)
2057{
2058 struct mlx4_en_priv *priv = netdev_priv(dev);
2059 struct mlx4_en_dev *mdev = priv->mdev;
2060
453a6082 2061 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2062
2063 /* Unregister device - this will close the port if it was up */
2064 if (priv->registered)
2065 unregister_netdev(dev);
2066
2067 if (priv->allocated)
2068 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2069
2070 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2071 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2072 /* flush any pending task for this netdev */
2073 flush_workqueue(mdev->workqueue);
2074
2075 /* Detach the netdev so tasks would not attempt to access it */
2076 mutex_lock(&mdev->state_lock);
2077 mdev->pndev[priv->port] = NULL;
5da03547 2078 mdev->upper[priv->port] = NULL;
c27a02cd
YP		 2079 mutex_unlock(&mdev->state_lock);
2080
fe0af03c 2081 mlx4_en_free_resources(priv);
564c274c 2082
bc6a4744
AV		 2083 kfree(priv->tx_ring);
2084 kfree(priv->tx_cq);
2085
c27a02cd
YP		 2086 free_netdev(dev);
2087}
2088
2089static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2090{
2091 struct mlx4_en_priv *priv = netdev_priv(dev);
2092 struct mlx4_en_dev *mdev = priv->mdev;
2093 int err = 0;
2094
453a6082 2095 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2096 dev->mtu, new_mtu);
2097
2098 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2099 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2100 return -EPERM;
2101 }
2102 dev->mtu = new_mtu;
2103
2104 if (netif_running(dev)) {
2105 mutex_lock(&mdev->state_lock);
2106 if (!mdev->device_up) {
2107 /* NIC is probably restarting - let watchdog task reset
2108 * the port */
453a6082 2109 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2110 } else {
3484aac1 2111 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2112 err = mlx4_en_start_port(dev);
2113 if (err) {
453a6082 2114 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2115 priv->port);
2116 queue_work(mdev->workqueue, &priv->watchdog_task);
2117 }
2118 }
2119 mutex_unlock(&mdev->state_lock);
2120 }
2121 return 0;
2122}
2123
100dbda8 2124static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2125{
2126 struct mlx4_en_priv *priv = netdev_priv(dev);
2127 struct mlx4_en_dev *mdev = priv->mdev;
2128 struct hwtstamp_config config;
2129
2130 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2131 return -EFAULT;
2132
2133 /* reserved for future extensions */
2134 if (config.flags)
2135 return -EINVAL;
2136
2137 /* device doesn't support time stamping */
2138 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2139 return -EINVAL;
2140
2141 /* TX HW timestamp */
2142 switch (config.tx_type) {
2143 case HWTSTAMP_TX_OFF:
2144 case HWTSTAMP_TX_ON:
2145 break;
2146 default:
2147 return -ERANGE;
2148 }
2149
2150 /* RX HW timestamp */
2151 switch (config.rx_filter) {
2152 case HWTSTAMP_FILTER_NONE:
2153 break;
2154 case HWTSTAMP_FILTER_ALL:
2155 case HWTSTAMP_FILTER_SOME:
2156 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2157 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2158 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2159 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2160 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2161 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2162 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2163 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2164 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2165 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2166 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2167 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2168 config.rx_filter = HWTSTAMP_FILTER_ALL;
2169 break;
2170 default:
2171 return -ERANGE;
2172 }
2173
7787fa66 2174 if (mlx4_en_reset_config(dev, config, dev->features)) {
ec693d47
AV		 2175 config.tx_type = HWTSTAMP_TX_OFF;
2176 config.rx_filter = HWTSTAMP_FILTER_NONE;
2177 }
2178
2179 return copy_to_user(ifr->ifr_data, &config,
2180 sizeof(config)) ? -EFAULT : 0;
2181}
2182
100dbda8
BH		 2183static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2184{
2185 struct mlx4_en_priv *priv = netdev_priv(dev);
2186
2187 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2188 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2189}
2190
ec693d47
AV		 2191static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2192{
2193 switch (cmd) {
2194 case SIOCSHWTSTAMP:
100dbda8
BH		 2195 return mlx4_en_hwtstamp_set(dev, ifr);
2196 case SIOCGHWTSTAMP:
2197 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2198 default:
2199 return -EOPNOTSUPP;
2200 }
2201}
2202
e38af4fa
HHZ		 2203static netdev_features_t mlx4_en_fix_features(struct net_device *netdev,
2204 netdev_features_t features)
2205{
2206 struct mlx4_en_priv *en_priv = netdev_priv(netdev);
2207 struct mlx4_en_dev *mdev = en_priv->mdev;
2208
2209 /* Since there is no support for separate RX C-TAG/S-TAG vlan accel
2210 * enable/disable make sure S-TAG flag is always in same state as
2211 * C-TAG.
2212 */
2213 if (features & NETIF_F_HW_VLAN_CTAG_RX &&
2214 !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2215 features |= NETIF_F_HW_VLAN_STAG_RX;
2216 else
2217 features &= ~NETIF_F_HW_VLAN_STAG_RX;
2218
2219 return features;
2220}
2221
60d6fe99
AV		 2222static int mlx4_en_set_features(struct net_device *netdev,
2223 netdev_features_t features)
2224{
2225 struct mlx4_en_priv *priv = netdev_priv(netdev);
f0df3503 2226 bool reset = false;
537f6f95
SM		 2227 int ret = 0;
2228
f0df3503
MM		 2229 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) {
2230 en_info(priv, "Turn %s RX-FCS\n",
2231 (features & NETIF_F_RXFCS) ? "ON" : "OFF");
2232 reset = true;
2233 }
2234
78500b8c
MM		 2235 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) {
2236 u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0;
2237
2238 en_info(priv, "Turn %s RX-ALL\n",
2239 ignore_fcs_value ? "ON" : "OFF");
2240 ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev,
2241 priv->port, ignore_fcs_value);
2242 if (ret)
2243 return ret;
2244 }
2245
537f6f95
SM		 2246 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2247 en_info(priv, "Turn %s RX vlan strip offload\n",
2248 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
f0df3503 2249 reset = true;
537f6f95 2250 }
60d6fe99 2251
cfb53f36
IS		 2252 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2253 en_info(priv, "Turn %s TX vlan strip offload\n",
2254 (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2255
e38af4fa
HHZ		 2256 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX))
2257 en_info(priv, "Turn %s TX S-VLAN strip offload\n",
2258 (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF");
2259
241a08c3
IS		 2260 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2261 en_info(priv, "Turn %s loopback\n",
2262 (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2263 mlx4_en_update_loopback_state(netdev, features);
2264 }
79aeaccd 2265
f0df3503
MM		 2266 if (reset) {
2267 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2268 features);
2269 if (ret)
2270 return ret;
2271 }
60d6fe99 2272
f0df3503 2273 return 0;
60d6fe99
AV		 2274}
2275
8f7ba3ca
RE		 2276static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2277{
2278 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2279 struct mlx4_en_dev *mdev = en_priv->mdev;
9813337a 2280 u64 mac_u64 = mlx4_mac_to_u64(mac);
8f7ba3ca
RE		 2281
2282 if (!is_valid_ether_addr(mac))
2283 return -EINVAL;
2284
2285 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2286}
2287
3f7fb021
RE		 2288static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2289{
2290 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2291 struct mlx4_en_dev *mdev = en_priv->mdev;
2292
2293 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2294}
2295
cda373f4
IS		 2296static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2297 int max_tx_rate)
2298{
2299 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2300 struct mlx4_en_dev *mdev = en_priv->mdev;
2301
2302 return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2303 max_tx_rate);
2304}
2305
e6b6a231
RE		 2306static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2307{
2308 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2309 struct mlx4_en_dev *mdev = en_priv->mdev;
2310
2311 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2312}
2313
2cccb9e4
RE		 2314static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2315{
2316 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2317 struct mlx4_en_dev *mdev = en_priv->mdev;
2318
2319 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2320}
8f7ba3ca 2321
948e306d
RE		 2322static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2323{
2324 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2325 struct mlx4_en_dev *mdev = en_priv->mdev;
2326
2327 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2328}
84c86403 2329
62a89055
EBE		 2330static int mlx4_en_get_vf_stats(struct net_device *dev, int vf,
2331 struct ifla_vf_stats *vf_stats)
2332{
2333 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2334 struct mlx4_en_dev *mdev = en_priv->mdev;
2335
2336 return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats);
2337}
2338
84c86403
HHZ		 2339#define PORT_ID_BYTE_LEN 8
2340static int mlx4_en_get_phys_port_id(struct net_device *dev,
02637fce 2341 struct netdev_phys_item_id *ppid)
84c86403
HHZ		 2342{
2343 struct mlx4_en_priv *priv = netdev_priv(dev);
2344 struct mlx4_dev *mdev = priv->mdev->dev;
2345 int i;
2346 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2347
2348 if (!phys_port_id)
2349 return -EOPNOTSUPP;
2350
2351 ppid->id_len = sizeof(phys_port_id);
2352 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2353 ppid->id[i] = phys_port_id & 0xff;
2354 phys_port_id >>= 8;
2355 }
2356 return 0;
2357}
2358
a66132f3 2359#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2360static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2361{
2362 int ret;
2363 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2364 vxlan_add_task);
2365
2366 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2367 if (ret)
2368 goto out;
2369
2370 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2371 VXLAN_STEER_BY_OUTER_MAC, 1);
2372out:
f4a1edd5 2373 if (ret) {
1b136de1 2374 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
f4a1edd5
OG		 2375 return;
2376 }
2377
2378 /* set offloads */
2379 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2380 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2381 priv->dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2382 priv->dev->features |= NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2383}
2384
2385static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2386{
2387 int ret;
2388 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2389 vxlan_del_task);
f4a1edd5
OG		 2390 /* unset offloads */
2391 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2392 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL);
2393 priv->dev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL;
2394 priv->dev->features &= ~NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2395
2396 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2397 VXLAN_STEER_BY_OUTER_MAC, 0);
2398 if (ret)
2399 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2400
2401 priv->vxlan_port = 0;
2402}
2403
2404static void mlx4_en_add_vxlan_port(struct net_device *dev,
2405 sa_family_t sa_family, __be16 port)
2406{
2407 struct mlx4_en_priv *priv = netdev_priv(dev);
2408 __be16 current_port;
2409
e326f2f1 2410 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2411 return;
2412
2413 if (sa_family == AF_INET6)
2414 return;
2415
2416 current_port = priv->vxlan_port;
2417 if (current_port && current_port != port) {
2418 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2419 ntohs(current_port), ntohs(port));
2420 return;
2421 }
2422
2423 priv->vxlan_port = port;
2424 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2425}
2426
2427static void mlx4_en_del_vxlan_port(struct net_device *dev,
2428 sa_family_t sa_family, __be16 port)
2429{
2430 struct mlx4_en_priv *priv = netdev_priv(dev);
2431 __be16 current_port;
2432
2433 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
2434 return;
2435
2436 if (sa_family == AF_INET6)
2437 return;
2438
2439 current_port = priv->vxlan_port;
2440 if (current_port != port) {
2441 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2442 return;
2443 }
2444
2445 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2446}
956bdab2 2447
5f35227e
JG		 2448static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2449 struct net_device *dev,
2450 netdev_features_t features)
956bdab2 2451{
8cb65d00 2452 features = vlan_features_check(skb, features);
5f35227e 2453 return vxlan_features_check(skb, features);
956bdab2 2454}
a66132f3 2455#endif
1b136de1 2456
de1cf8a7 2457static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
c10e4fc6
OG		 2458{
2459 struct mlx4_en_priv *priv = netdev_priv(dev);
2460 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[queue_index];
2461 struct mlx4_update_qp_params params;
2462 int err;
2463
2464 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2465 return -EOPNOTSUPP;
2466
2467 /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */
2468 if (maxrate >> 12) {
2469 params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2470 params.rate_val = maxrate / 1000;
2471 } else if (maxrate) {
2472 params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2473 params.rate_val = maxrate;
2474 } else { /* zero serves to revoke the QP rate-limitation */
2475 params.rate_unit = 0;
2476 params.rate_val = 0;
2477 }
2478
2479 err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2480 &params);
2481 return err;
2482}
2483
3addc568
SH		 2484static const struct net_device_ops mlx4_netdev_ops = {
2485 .ndo_open = mlx4_en_open,
2486 .ndo_stop = mlx4_en_close,
2487 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2488 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2489 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2490 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2491 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2492 .ndo_validate_addr = eth_validate_addr,
3addc568 2493 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2494 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2495 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2496 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2497 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2498#ifdef CONFIG_NET_POLL_CONTROLLER
2499 .ndo_poll_controller = mlx4_en_netpoll,
2500#endif
60d6fe99 2501 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2502 .ndo_fix_features = mlx4_en_fix_features,
897d7846 2503 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2504#ifdef CONFIG_RFS_ACCEL
2505 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2506#endif
e0d1095a 2507#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2508 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2509#endif
84c86403 2510 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a66132f3 2511#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2512 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2513 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
5f35227e 2514 .ndo_features_check = mlx4_en_features_check,
a66132f3 2515#endif
c10e4fc6 2516 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
3addc568
SH		 2517};
2518
8f7ba3ca
RE		 2519static const struct net_device_ops mlx4_netdev_ops_master = {
2520 .ndo_open = mlx4_en_open,
2521 .ndo_stop = mlx4_en_close,
2522 .ndo_start_xmit = mlx4_en_xmit,
2523 .ndo_select_queue = mlx4_en_select_queue,
2524 .ndo_get_stats = mlx4_en_get_stats,
2525 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2526 .ndo_set_mac_address = mlx4_en_set_mac,
2527 .ndo_validate_addr = eth_validate_addr,
2528 .ndo_change_mtu = mlx4_en_change_mtu,
2529 .ndo_tx_timeout = mlx4_en_tx_timeout,
2530 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2531 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2532 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2533 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
cda373f4 2534 .ndo_set_vf_rate = mlx4_en_set_vf_rate,
e6b6a231 2535 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2536 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
62a89055 2537 .ndo_get_vf_stats = mlx4_en_get_vf_stats,
2cccb9e4 2538 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2539#ifdef CONFIG_NET_POLL_CONTROLLER
2540 .ndo_poll_controller = mlx4_en_netpoll,
2541#endif
2542 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2543 .ndo_fix_features = mlx4_en_fix_features,
8f7ba3ca
RE		 2544 .ndo_setup_tc = mlx4_en_setup_tc,
2545#ifdef CONFIG_RFS_ACCEL
2546 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2547#endif
84c86403 2548 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
9737c6ab
OG		 2549#ifdef CONFIG_MLX4_EN_VXLAN
2550 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2551 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
5f35227e 2552 .ndo_features_check = mlx4_en_features_check,
9737c6ab 2553#endif
c10e4fc6 2554 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
8f7ba3ca
RE		 2555};
2556
5da03547
MS		 2557struct mlx4_en_bond {
2558 struct work_struct work;
2559 struct mlx4_en_priv *priv;
2560 int is_bonded;
2561 struct mlx4_port_map port_map;
2562};
2563
2564static void mlx4_en_bond_work(struct work_struct *work)
2565{
2566 struct mlx4_en_bond *bond = container_of(work,
2567 struct mlx4_en_bond,
2568 work);
2569 int err = 0;
2570 struct mlx4_dev *dev = bond->priv->mdev->dev;
2571
2572 if (bond->is_bonded) {
2573 if (!mlx4_is_bonded(dev)) {
2574 err = mlx4_bond(dev);
2575 if (err)
2576 en_err(bond->priv, "Fail to bond device\n");
2577 }
2578 if (!err) {
2579 err = mlx4_port_map_set(dev, &bond->port_map);
2580 if (err)
2581 en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
2582 bond->port_map.port1,
2583 bond->port_map.port2,
2584 err);
2585 }
2586 } else if (mlx4_is_bonded(dev)) {
2587 err = mlx4_unbond(dev);
2588 if (err)
2589 en_err(bond->priv, "Fail to unbond device\n");
2590 }
2591 dev_put(bond->priv->dev);
2592 kfree(bond);
2593}
2594
2595static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
2596 u8 v2p_p1, u8 v2p_p2)
2597{
2598 struct mlx4_en_bond *bond = NULL;
2599
2600 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
2601 if (!bond)
2602 return -ENOMEM;
2603
2604 INIT_WORK(&bond->work, mlx4_en_bond_work);
2605 bond->priv = priv;
2606 bond->is_bonded = is_bonded;
2607 bond->port_map.port1 = v2p_p1;
2608 bond->port_map.port2 = v2p_p2;
2609 dev_hold(priv->dev);
2610 queue_work(priv->mdev->workqueue, &bond->work);
2611 return 0;
2612}
2613
2614int mlx4_en_netdev_event(struct notifier_block *this,
2615 unsigned long event, void *ptr)
2616{
2617 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2618 u8 port = 0;
2619 struct mlx4_en_dev *mdev;
2620 struct mlx4_dev *dev;
2621 int i, num_eth_ports = 0;
2622 bool do_bond = true;
2623 struct mlx4_en_priv *priv;
2624 u8 v2p_port1 = 0;
2625 u8 v2p_port2 = 0;
2626
2627 if (!net_eq(dev_net(ndev), &init_net))
2628 return NOTIFY_DONE;
2629
2630 mdev = container_of(this, struct mlx4_en_dev, nb);
2631 dev = mdev->dev;
2632
2633 /* Go into this mode only when two network devices set on two ports
2634 * of the same mlx4 device are slaves of the same bonding master
2635 */
2636 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
2637 ++num_eth_ports;
2638 if (!port && (mdev->pndev[i] == ndev))
2639 port = i;
2640 mdev->upper[i] = mdev->pndev[i] ?
2641 netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
2642 /* condition not met: network device is a slave */
2643 if (!mdev->upper[i])
2644 do_bond = false;
2645 if (num_eth_ports < 2)
2646 continue;
2647 /* condition not met: same master */
2648 if (mdev->upper[i] != mdev->upper[i-1])
2649 do_bond = false;
2650 }
2651 /* condition not met: 2 salves */
2652 do_bond = (num_eth_ports == 2) ? do_bond : false;
2653
2654 /* handle only events that come with enough info */
2655 if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
2656 return NOTIFY_DONE;
2657
2658 priv = netdev_priv(ndev);
2659 if (do_bond) {
2660 struct netdev_notifier_bonding_info *notifier_info = ptr;
2661 struct netdev_bonding_info *bonding_info =
2662 &notifier_info->bonding_info;
2663
2664 /* required mode 1, 2 or 4 */
2665 if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
2666 (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
2667 (bonding_info->master.bond_mode != BOND_MODE_8023AD))
2668 do_bond = false;
2669
2670 /* require exactly 2 slaves */
2671 if (bonding_info->master.num_slaves != 2)
2672 do_bond = false;
2673
2674 /* calc v2p */
2675 if (do_bond) {
2676 if (bonding_info->master.bond_mode ==
2677 BOND_MODE_ACTIVEBACKUP) {
2678 /* in active-backup mode virtual ports are
2679 * mapped to the physical port of the active
2680 * slave */
2681 if (bonding_info->slave.state ==
2682 BOND_STATE_BACKUP) {
2683 if (port == 1) {
2684 v2p_port1 = 2;
2685 v2p_port2 = 2;
2686 } else {
2687 v2p_port1 = 1;
2688 v2p_port2 = 1;
2689 }
2690 } else { /* BOND_STATE_ACTIVE */
2691 if (port == 1) {
2692 v2p_port1 = 1;
2693 v2p_port2 = 1;
2694 } else {
2695 v2p_port1 = 2;
2696 v2p_port2 = 2;
2697 }
2698 }
2699 } else { /* Active-Active */
2700 /* in active-active mode a virtual port is
2701 * mapped to the native physical port if and only
2702 * if the physical port is up */
2703 __s8 link = bonding_info->slave.link;
2704
2705 if (port == 1)
2706 v2p_port2 = 2;
2707 else
2708 v2p_port1 = 1;
2709 if ((link == BOND_LINK_UP) ||
2710 (link == BOND_LINK_FAIL)) {
2711 if (port == 1)
2712 v2p_port1 = 1;
2713 else
2714 v2p_port2 = 2;
2715 } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */
2716 if (port == 1)
2717 v2p_port1 = 2;
2718 else
2719 v2p_port2 = 1;
2720 }
2721 }
2722 }
2723 }
2724
2725 mlx4_en_queue_bond_work(priv, do_bond,
2726 v2p_port1, v2p_port2);
2727
2728 return NOTIFY_DONE;
2729}
2730
0b131561
MB		 2731void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
2732 struct mlx4_en_stats_bitmap *stats_bitmap,
2733 u8 rx_ppp, u8 rx_pause,
2734 u8 tx_ppp, u8 tx_pause)
2735{
b42de4d0 2736 int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS;
0b131561
MB		 2737
2738 if (!mlx4_is_slave(dev) &&
2739 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
2740 mutex_lock(&stats_bitmap->mutex);
2741 bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
2742
2743 if (rx_ppp)
2744 bitmap_set(stats_bitmap->bitmap, last_i,
2745 NUM_FLOW_PRIORITY_STATS_RX);
2746 last_i += NUM_FLOW_PRIORITY_STATS_RX;
2747
2748 if (rx_pause && !(rx_ppp))
2749 bitmap_set(stats_bitmap->bitmap, last_i,
2750 NUM_FLOW_STATS_RX);
2751 last_i += NUM_FLOW_STATS_RX;
2752
2753 if (tx_ppp)
2754 bitmap_set(stats_bitmap->bitmap, last_i,
2755 NUM_FLOW_PRIORITY_STATS_TX);
2756 last_i += NUM_FLOW_PRIORITY_STATS_TX;
2757
2758 if (tx_pause && !(tx_ppp))
2759 bitmap_set(stats_bitmap->bitmap, last_i,
2760 NUM_FLOW_STATS_TX);
2761 last_i += NUM_FLOW_STATS_TX;
2762
2763 mutex_unlock(&stats_bitmap->mutex);
2764 }
2765}
2766
6fcd2735 2767void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
0b131561
MB		 2768 struct mlx4_en_stats_bitmap *stats_bitmap,
2769 u8 rx_ppp, u8 rx_pause,
2770 u8 tx_ppp, u8 tx_pause)
ffa88f37 2771{
6fcd2735
EBE		 2772 int last_i = 0;
2773
3da8a36c
EBE		 2774 mutex_init(&stats_bitmap->mutex);
2775 bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
6fcd2735
EBE		 2776
2777 if (mlx4_is_slave(dev)) {
3da8a36c 2778 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2779 MLX4_FIND_NETDEV_STAT(rx_packets), 1);
3da8a36c 2780 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2781 MLX4_FIND_NETDEV_STAT(tx_packets), 1);
3da8a36c 2782 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2783 MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
3da8a36c 2784 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2785 MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
3da8a36c 2786 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2787 MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
3da8a36c 2788 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735
EBE		 2789 MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
2790 } else {
3da8a36c 2791 bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
ffa88f37 2792 }
6fcd2735 2793 last_i += NUM_MAIN_STATS;
ffa88f37 2794
3da8a36c 2795 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
6fcd2735 2796 last_i += NUM_PORT_STATS;
ffa88f37 2797
b42de4d0
EBE		 2798 if (mlx4_is_master(dev))
2799 bitmap_set(stats_bitmap->bitmap, last_i,
2800 NUM_PF_STATS);
2801 last_i += NUM_PF_STATS;
2802
0b131561
MB		 2803 mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
2804 rx_ppp, rx_pause,
2805 tx_ppp, tx_pause);
2806 last_i += NUM_FLOW_STATS;
2807
6fcd2735 2808 if (!mlx4_is_slave(dev))
3da8a36c 2809 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
ffa88f37
EBE		 2810}
2811
c27a02cd
YP		 2812int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2813 struct mlx4_en_port_profile *prof)
2814{
2815 struct net_device *dev;
2816 struct mlx4_en_priv *priv;
c07cb4b0 2817 int i;
c27a02cd
YP		 2818 int err;
2819
f1593d22 2820 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2821 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2822 if (dev == NULL)
c27a02cd 2823 return -ENOMEM;
c27a02cd 2824
d317966b
AV		 2825 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2826 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2827
872bf2fb 2828 SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
76a066f2 2829 dev->dev_port = port - 1;
c27a02cd
YP		 2830
2831 /*
2832 * Initialize driver private data
2833 */
2834
2835 priv = netdev_priv(dev);
2836 memset(priv, 0, sizeof(struct mlx4_en_priv));
6de5f7f6 2837 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
207af6c5
EE		 2838 spin_lock_init(&priv->stats_lock);
2839 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
2840 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2841 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2842 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
2843 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
2844#ifdef CONFIG_MLX4_EN_VXLAN
2845 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
2846 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
2847#endif
2848#ifdef CONFIG_RFS_ACCEL
2849 INIT_LIST_HEAD(&priv->filters);
2850 spin_lock_init(&priv->filters_lock);
2851#endif
2852
c27a02cd
YP		 2853 priv->dev = dev;
2854 priv->mdev = mdev;
ebf8c9aa 2855 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2856 priv->prof = prof;
2857 priv->port = port;
2858 priv->port_up = false;
c27a02cd 2859 priv->flags = prof->flags;
0fef9d03 2860 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
60d6fe99
AV		 2861 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2862 MLX4_WQE_CTRL_SOLICITED);
d317966b 2863 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2864 priv->tx_ring_num = prof->tx_ring_num;
fbc6daf1 2865 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
bd635c35 2866 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
d317966b 2867
41d942d5 2868 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2869 GFP_KERNEL);
bc6a4744
AV		 2870 if (!priv->tx_ring) {
2871 err = -ENOMEM;
2872 goto out;
2873 }
41d942d5 2874 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2875 GFP_KERNEL);
bc6a4744
AV		 2876 if (!priv->tx_cq) {
2877 err = -ENOMEM;
2878 goto out;
2879 }
c27a02cd 2880 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2881 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
b1b6b4da 2882 priv->cqe_size = mdev->dev->caps.cqe_size;
c27a02cd
YP		 2883 priv->mac_index = -1;
2884 priv->msg_enable = MLX4_EN_MSG_LEVEL;
564c274c 2885#ifdef CONFIG_MLX4_EN_DCB
540b3a39 2886 if (!mlx4_is_slave(priv->mdev->dev)) {
3742cc65 2887 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
540b3a39
OG		 2888 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2889 } else {
2890 en_info(priv, "enabling only PFC DCB ops\n");
2891 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2892 }
2893 }
564c274c 2894#endif
c27a02cd 2895
c07cb4b0
YB		 2896 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2897 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2898
c27a02cd
YP		 2899 /* Query for default mac and max mtu */
2900 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99 2901
f8c6455b
SM		 2902 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
2903 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
2904 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
2905
6bbb6d99
YB		 2906 /* Set default MAC */
2907 dev->addr_len = ETH_ALEN;
2908 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2909 if (!is_valid_ether_addr(dev->dev_addr)) {
2b3ddf27
JM		 2910 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2911 priv->port, dev->dev_addr);
2912 err = -EINVAL;
2913 goto out;
2914 } else if (mlx4_is_slave(priv->mdev->dev) &&
2915 (priv->mdev->dev->port_random_macs & 1 << priv->port)) {
2916 /* Random MAC was assigned in mlx4_slave_cap
2917 * in mlx4_core module
2918 */
2919 dev->addr_assign_type |= NET_ADDR_RANDOM;
2920 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
c27a02cd
YP		 2921 }
2922
2695bab2 2923 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
6bbb6d99 2924
c27a02cd
YP		 2925 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2926 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2927 err = mlx4_en_alloc_resources(priv);
2928 if (err)
2929 goto out;
2930
ec693d47
AV		 2931 /* Initialize time stamping config */
2932 priv->hwtstamp_config.flags = 0;
2933 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2934 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2935
c27a02cd
YP		 2936 /* Allocate page for receive rings */
2937 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2938 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2939 if (err) {
453a6082 2940 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2941 goto out;
2942 }
2943 priv->allocated = 1;
2944
c27a02cd
YP		 2945 /*
2946 * Initialize netdev entry points
2947 */
8f7ba3ca
RE		 2948 if (mlx4_is_master(priv->mdev->dev))
2949 dev->netdev_ops = &mlx4_netdev_ops_master;
2950 else
2951 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2952 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2953 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2954 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2955
7ad24ea4 2956 dev->ethtool_ops = &mlx4_en_ethtool_ops;
c27a02cd 2957
c27a02cd
YP		 2958 /*
2959 * Set driver features
2960 */
c8c64cff
MM		 2961 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2962 if (mdev->LSO_support)
2963 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2964
2965 dev->vlan_features = dev->hw_features;
2966
ad86107f 2967 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2968 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2969 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2970 NETIF_F_HW_VLAN_CTAG_FILTER;
537f6f95
SM		 2971 dev->hw_features |= NETIF_F_LOOPBACK |
2972 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c27a02cd 2973
e38af4fa
HHZ		 2974 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
2975 dev->features |= NETIF_F_HW_VLAN_STAG_RX |
2976 NETIF_F_HW_VLAN_STAG_FILTER;
2977 dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX;
2978 }
2979
2980 if (mlx4_is_slave(mdev->dev)) {
2981 int phv;
2982
2983 err = get_phv_bit(mdev->dev, port, &phv);
2984 if (!err && phv) {
2985 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
2986 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
2987 }
2988 } else {
2989 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
2990 !(mdev->dev->caps.flags2 &
2991 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2992 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
2993 }
2994
f0df3503
MM		 2995 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
2996 dev->hw_features |= NETIF_F_RXFCS;
2997
78500b8c
MM		 2998 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)
2999 dev->hw_features |= NETIF_F_RXALL;
3000
1eb8c695 3001 if (mdev->dev->caps.steering_mode ==
7d077cd3
MB		 3002 MLX4_STEERING_MODE_DEVICE_MANAGED &&
3003 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1eb8c695
AV		 3004 dev->hw_features |= NETIF_F_NTUPLE;
3005
cc5387f7
YB		 3006 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
3007 dev->priv_flags |= IFF_UNICAST_FLT;
3008
947cbb0a
EP		 3009 /* Setting a default hash function value */
3010 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
3011 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3012 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
3013 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
3014 } else {
3015 en_warn(priv,
3016 "No RSS hash capabilities exposed, using Toeplitz\n");
3017 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3018 }
3019
c27a02cd 3020 mdev->pndev[port] = dev;
5da03547 3021 mdev->upper[port] = NULL;
c27a02cd
YP		 3022
3023 netif_carrier_off(dev);
4801ae70
EE		 3024 mlx4_en_set_default_moderation(priv);
3025
453a6082
YP		 3026 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
3027 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
3028
79aeaccd
YB		 3029 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
3030
90822265 3031 /* Configure port */
5c8e9046 3032 mlx4_en_calc_rx_buf(dev);
90822265 3033 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 3034 priv->rx_skb_size + ETH_FCS_LEN,
3035 prof->tx_pause, prof->tx_ppp,
3036 prof->rx_pause, prof->rx_ppp);
90822265 3037 if (err) {
1a91de28
JP		 3038 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
3039 priv->port, err);
90822265
YP		 3040 goto out;
3041 }
3042
837052d0 3043 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 3044 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 3045 if (err) {
3046 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
3047 err);
3048 goto out;
3049 }
3050 }
3051
90822265
YP		 3052 /* Init port */
3053 en_warn(priv, "Initializing port\n");
3054 err = mlx4_INIT_PORT(mdev->dev, priv->port);
3055 if (err) {
3056 en_err(priv, "Failed Initializing port\n");
3057 goto out;
3058 }
c27a02cd 3059 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV		 3060
3061 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
3062 queue_delayed_work(mdev->workqueue, &priv->service_task,
3063 SERVICE_TASK_DELAY);
3064
0b131561
MB		 3065 mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
3066 mdev->profile.prof[priv->port].rx_ppp,
3067 mdev->profile.prof[priv->port].rx_pause,
3068 mdev->profile.prof[priv->port].tx_ppp,
3069 mdev->profile.prof[priv->port].tx_pause);
39de961a 3070
e5eda89d
IS		 3071 err = register_netdev(dev);
3072 if (err) {
3073 en_err(priv, "Netdev registration failed for port %d\n", port);
3074 goto out;
3075 }
3076
3077 priv->registered = 1;
3078
c27a02cd
YP		 3079 return 0;
3080
3081out:
3082 mlx4_en_destroy_netdev(dev);
3083 return err;
3084}
3085
537f6f95
SM		 3086int mlx4_en_reset_config(struct net_device *dev,
3087 struct hwtstamp_config ts_config,
3088 netdev_features_t features)
3089{
3090 struct mlx4_en_priv *priv = netdev_priv(dev);
3091 struct mlx4_en_dev *mdev = priv->mdev;
3092 int port_up = 0;
3093 int err = 0;
3094
3095 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
3096 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
f0df3503
MM		 3097 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3098 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS))
537f6f95
SM		 3099 return 0; /* Nothing to change */
3100
3101 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3102 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3103 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3104 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3105 return -EINVAL;
3106 }
3107
3108 mutex_lock(&mdev->state_lock);
3109 if (priv->port_up) {
3110 port_up = 1;
3111 mlx4_en_stop_port(dev, 1);
3112 }
3113
3114 mlx4_en_free_resources(priv);
3115
3116 en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n",
3117 ts_config.rx_filter, !!(features & NETIF_F_HW_VLAN_CTAG_RX));
3118
3119 priv->hwtstamp_config.tx_type = ts_config.tx_type;
3120 priv->hwtstamp_config.rx_filter = ts_config.rx_filter;
3121
3122 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3123 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3124 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3125 else
3126 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3127 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3128 /* RX time-stamping is OFF, update the RX vlan offload
3129 * to the latest wanted state
3130 */
3131 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3132 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3133 else
3134 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3135 }
3136
f0df3503
MM		 3137 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) {
3138 if (features & NETIF_F_RXFCS)
3139 dev->features |= NETIF_F_RXFCS;
3140 else
3141 dev->features &= ~NETIF_F_RXFCS;
3142 }
3143
537f6f95
SM		 3144 /* RX vlan offload and RX time-stamping can't co-exist !
3145 * Regardless of the caller's choice,
3146 * Turn Off RX vlan offload in case of time-stamping is ON
3147 */
3148 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3149 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3150 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3151 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3152 }
3153
3154 err = mlx4_en_alloc_resources(priv);
3155 if (err) {
3156 en_err(priv, "Failed reallocating port resources\n");
3157 goto out;
3158 }
3159 if (port_up) {
3160 err = mlx4_en_start_port(dev);
3161 if (err)
3162 en_err(priv, "Failed starting port\n");
3163 }
3164
3165out:
3166 mutex_unlock(&mdev->state_lock);
3167 netdev_features_change(dev);
3168 return err;
3169}
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