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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
47a38e15 | 35 | #include <linux/bpf.h> |
c27a02cd | 36 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c27a02cd YP |
38 | #include <linux/mlx4/qp.h> |
39 | #include <linux/skbuff.h> | |
b67bfe0d | 40 | #include <linux/rculist.h> |
c27a02cd YP |
41 | #include <linux/if_ether.h> |
42 | #include <linux/if_vlan.h> | |
43 | #include <linux/vmalloc.h> | |
35f6f453 | 44 | #include <linux/irq.h> |
c27a02cd | 45 | |
f8c6455b SM |
46 | #if IS_ENABLED(CONFIG_IPV6) |
47 | #include <net/ip6_checksum.h> | |
48 | #endif | |
49 | ||
c27a02cd YP |
50 | #include "mlx4_en.h" |
51 | ||
51151a16 ED |
52 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
53 | struct mlx4_en_rx_alloc *page_alloc, | |
54 | const struct mlx4_en_frag_info *frag_info, | |
55 | gfp_t _gfp) | |
56 | { | |
57 | int order; | |
58 | struct page *page; | |
59 | dma_addr_t dma; | |
60 | ||
d576acf0 | 61 | for (order = frag_info->order; ;) { |
51151a16 ED |
62 | gfp_t gfp = _gfp; |
63 | ||
64 | if (order) | |
04aeb56a | 65 | gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC; |
51151a16 ED |
66 | page = alloc_pages(gfp, order); |
67 | if (likely(page)) | |
68 | break; | |
69 | if (--order < 0 || | |
70 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
71 | return -ENOMEM; | |
72 | } | |
73 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
d576acf0 | 74 | frag_info->dma_dir); |
de3d6fa8 | 75 | if (unlikely(dma_mapping_error(priv->ddev, dma))) { |
51151a16 ED |
76 | put_page(page); |
77 | return -ENOMEM; | |
78 | } | |
70fbe079 | 79 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
80 | page_alloc->page = page; |
81 | page_alloc->dma = dma; | |
5f6e9800 | 82 | page_alloc->page_offset = 0; |
51151a16 | 83 | /* Not doing get_page() for each frag is a big win |
98226208 | 84 | * on asymetric workloads. Note we can not use atomic_set(). |
51151a16 | 85 | */ |
fe896d18 | 86 | page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1); |
51151a16 ED |
87 | return 0; |
88 | } | |
89 | ||
4cce66cd TLSC |
90 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
91 | struct mlx4_en_rx_desc *rx_desc, | |
92 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
93 | struct mlx4_en_rx_alloc *ring_alloc, |
94 | gfp_t gfp) | |
c27a02cd | 95 | { |
4cce66cd | 96 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 97 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd YP |
98 | struct page *page; |
99 | dma_addr_t dma; | |
4cce66cd | 100 | int i; |
c27a02cd | 101 | |
4cce66cd TLSC |
102 | for (i = 0; i < priv->num_frags; i++) { |
103 | frag_info = &priv->frag_info[i]; | |
51151a16 | 104 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
105 | page_alloc[i].page_offset += frag_info->frag_stride; |
106 | ||
107 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
108 | ring_alloc[i].page_size) | |
51151a16 | 109 | continue; |
70fbe079 | 110 | |
de3d6fa8 TT |
111 | if (unlikely(mlx4_alloc_pages(priv, &page_alloc[i], |
112 | frag_info, gfp))) | |
51151a16 | 113 | goto out; |
4cce66cd | 114 | } |
c27a02cd | 115 | |
4cce66cd TLSC |
116 | for (i = 0; i < priv->num_frags; i++) { |
117 | frags[i] = ring_alloc[i]; | |
70fbe079 | 118 | dma = ring_alloc[i].dma + ring_alloc[i].page_offset; |
4cce66cd TLSC |
119 | ring_alloc[i] = page_alloc[i]; |
120 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 121 | } |
4cce66cd | 122 | |
c27a02cd | 123 | return 0; |
4cce66cd | 124 | |
4cce66cd TLSC |
125 | out: |
126 | while (i--) { | |
51151a16 | 127 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 128 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
d576acf0 BB |
129 | page_alloc[i].page_size, |
130 | priv->frag_info[i].dma_dir); | |
51151a16 | 131 | page = page_alloc[i].page; |
851b10d6 KK |
132 | /* Revert changes done by mlx4_alloc_pages */ |
133 | page_ref_sub(page, page_alloc[i].page_size / | |
134 | priv->frag_info[i].frag_stride - 1); | |
51151a16 ED |
135 | put_page(page); |
136 | } | |
4cce66cd TLSC |
137 | } |
138 | return -ENOMEM; | |
139 | } | |
140 | ||
141 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
142 | struct mlx4_en_rx_alloc *frags, | |
143 | int i) | |
144 | { | |
51151a16 | 145 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
021f1107 | 146 | u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; |
4cce66cd | 147 | |
021f1107 AV |
148 | |
149 | if (next_frag_end > frags[i].page_size) | |
70fbe079 | 150 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, |
d576acf0 | 151 | frag_info->dma_dir); |
51151a16 | 152 | |
4cce66cd TLSC |
153 | if (frags[i].page) |
154 | put_page(frags[i].page); | |
c27a02cd YP |
155 | } |
156 | ||
157 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
158 | struct mlx4_en_rx_ring *ring) | |
159 | { | |
c27a02cd | 160 | int i; |
51151a16 | 161 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
162 | |
163 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 164 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 165 | |
51151a16 | 166 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
1ab25f86 | 167 | frag_info, GFP_KERNEL | __GFP_COLD)) |
4cce66cd | 168 | goto out; |
b110d2ce IS |
169 | |
170 | en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n", | |
171 | i, ring->page_alloc[i].page_size, | |
fe896d18 | 172 | page_ref_count(ring->page_alloc[i].page)); |
c27a02cd YP |
173 | } |
174 | return 0; | |
175 | ||
176 | out: | |
177 | while (i--) { | |
51151a16 ED |
178 | struct page *page; |
179 | ||
c27a02cd | 180 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 181 | dma_unmap_page(priv->ddev, page_alloc->dma, |
d576acf0 BB |
182 | page_alloc->page_size, |
183 | priv->frag_info[i].dma_dir); | |
51151a16 | 184 | page = page_alloc->page; |
851b10d6 KK |
185 | /* Revert changes done by mlx4_alloc_pages */ |
186 | page_ref_sub(page, page_alloc->page_size / | |
187 | priv->frag_info[i].frag_stride - 1); | |
51151a16 | 188 | put_page(page); |
c27a02cd YP |
189 | page_alloc->page = NULL; |
190 | } | |
191 | return -ENOMEM; | |
192 | } | |
193 | ||
194 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
195 | struct mlx4_en_rx_ring *ring) | |
196 | { | |
197 | struct mlx4_en_rx_alloc *page_alloc; | |
198 | int i; | |
199 | ||
200 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
201 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
202 | ||
c27a02cd | 203 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
204 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
205 | i, page_count(page_alloc->page)); | |
c27a02cd | 206 | |
4cce66cd | 207 | dma_unmap_page(priv->ddev, page_alloc->dma, |
d576acf0 | 208 | page_alloc->page_size, frag_info->dma_dir); |
70fbe079 AV |
209 | while (page_alloc->page_offset + frag_info->frag_stride < |
210 | page_alloc->page_size) { | |
51151a16 | 211 | put_page(page_alloc->page); |
70fbe079 | 212 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 213 | } |
c27a02cd YP |
214 | page_alloc->page = NULL; |
215 | } | |
216 | } | |
217 | ||
c27a02cd YP |
218 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
219 | struct mlx4_en_rx_ring *ring, int index) | |
220 | { | |
221 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
222 | int possible_frags; |
223 | int i; | |
224 | ||
c27a02cd YP |
225 | /* Set size and memtype fields */ |
226 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
227 | rx_desc->data[i].byte_count = |
228 | cpu_to_be32(priv->frag_info[i].frag_size); | |
229 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
230 | } | |
231 | ||
232 | /* If the number of used fragments does not fill up the ring stride, | |
233 | * remaining (unused) fragments must be padded with null address/size | |
234 | * and a special memory key */ | |
235 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
236 | for (i = priv->num_frags; i < possible_frags; i++) { | |
237 | rx_desc->data[i].byte_count = 0; | |
238 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
239 | rx_desc->data[i].addr = 0; | |
240 | } | |
241 | } | |
242 | ||
c27a02cd | 243 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
244 | struct mlx4_en_rx_ring *ring, int index, |
245 | gfp_t gfp) | |
c27a02cd YP |
246 | { |
247 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
248 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
249 | (index << priv->log_rx_info); | |
c27a02cd | 250 | |
d576acf0 BB |
251 | if (ring->page_cache.index > 0) { |
252 | frags[0] = ring->page_cache.buf[--ring->page_cache.index]; | |
253 | rx_desc->data[0].addr = cpu_to_be64(frags[0].dma); | |
254 | return 0; | |
255 | } | |
256 | ||
51151a16 | 257 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
258 | } |
259 | ||
07841f9d IS |
260 | static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring) |
261 | { | |
07841f9d IS |
262 | return ring->prod == ring->cons; |
263 | } | |
264 | ||
c27a02cd YP |
265 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) |
266 | { | |
267 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
268 | } | |
269 | ||
38aab07c YP |
270 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
271 | struct mlx4_en_rx_ring *ring, | |
272 | int index) | |
273 | { | |
4cce66cd | 274 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
275 | int nr; |
276 | ||
4cce66cd | 277 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 278 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 279 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 280 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
281 | } |
282 | } | |
283 | ||
c27a02cd YP |
284 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
285 | { | |
c27a02cd YP |
286 | struct mlx4_en_rx_ring *ring; |
287 | int ring_ind; | |
288 | int buf_ind; | |
38aab07c | 289 | int new_size; |
c27a02cd YP |
290 | |
291 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
292 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 293 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
294 | |
295 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 | 296 | ring->actual_size, |
1ab25f86 | 297 | GFP_KERNEL | __GFP_COLD)) { |
c27a02cd | 298 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
1a91de28 | 299 | en_err(priv, "Failed to allocate enough rx buffers\n"); |
c27a02cd YP |
300 | return -ENOMEM; |
301 | } else { | |
38aab07c | 302 | new_size = rounddown_pow_of_two(ring->actual_size); |
1a91de28 | 303 | en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", |
453a6082 | 304 | ring->actual_size, new_size); |
38aab07c | 305 | goto reduce_rings; |
c27a02cd YP |
306 | } |
307 | } | |
308 | ring->actual_size++; | |
309 | ring->prod++; | |
310 | } | |
311 | } | |
38aab07c YP |
312 | return 0; |
313 | ||
314 | reduce_rings: | |
315 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 316 | ring = priv->rx_ring[ring_ind]; |
38aab07c YP |
317 | while (ring->actual_size > new_size) { |
318 | ring->actual_size--; | |
319 | ring->prod--; | |
320 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
321 | } | |
38aab07c YP |
322 | } |
323 | ||
c27a02cd YP |
324 | return 0; |
325 | } | |
326 | ||
c27a02cd YP |
327 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
328 | struct mlx4_en_rx_ring *ring) | |
329 | { | |
c27a02cd | 330 | int index; |
c27a02cd | 331 | |
453a6082 YP |
332 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
333 | ring->cons, ring->prod); | |
c27a02cd YP |
334 | |
335 | /* Unmap and free Rx buffers */ | |
07841f9d | 336 | while (!mlx4_en_is_ring_empty(ring)) { |
c27a02cd | 337 | index = ring->cons & ring->size_mask; |
453a6082 | 338 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 339 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
340 | ++ring->cons; |
341 | } | |
342 | } | |
343 | ||
02512482 IS |
344 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) |
345 | { | |
346 | int i; | |
347 | int num_of_eqs; | |
bb2146bc | 348 | int num_rx_rings; |
02512482 IS |
349 | struct mlx4_dev *dev = mdev->dev; |
350 | ||
351 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
c66fa19c MB |
352 | num_of_eqs = max_t(int, MIN_RX_RINGS, |
353 | min_t(int, | |
354 | mlx4_get_eqs_per_port(mdev->dev, i), | |
355 | DEF_RX_RINGS)); | |
02512482 | 356 | |
ea1c1af1 AV |
357 | num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : |
358 | min_t(int, num_of_eqs, | |
359 | netif_get_num_default_rss_queues()); | |
02512482 | 360 | mdev->profile.prof[i].rx_ring_num = |
bb2146bc | 361 | rounddown_pow_of_two(num_rx_rings); |
02512482 IS |
362 | } |
363 | } | |
364 | ||
c27a02cd | 365 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 366 | struct mlx4_en_rx_ring **pring, |
163561a4 | 367 | u32 size, u16 stride, int node) |
c27a02cd YP |
368 | { |
369 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 370 | struct mlx4_en_rx_ring *ring; |
4cce66cd | 371 | int err = -ENOMEM; |
c27a02cd YP |
372 | int tmp; |
373 | ||
163561a4 | 374 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 375 | if (!ring) { |
163561a4 EE |
376 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
377 | if (!ring) { | |
378 | en_err(priv, "Failed to allocate RX ring structure\n"); | |
379 | return -ENOMEM; | |
380 | } | |
41d942d5 EE |
381 | } |
382 | ||
c27a02cd YP |
383 | ring->prod = 0; |
384 | ring->cons = 0; | |
385 | ring->size = size; | |
386 | ring->size_mask = size - 1; | |
387 | ring->stride = stride; | |
388 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 389 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
390 | |
391 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 392 | sizeof(struct mlx4_en_rx_alloc)); |
163561a4 | 393 | ring->rx_info = vmalloc_node(tmp, node); |
41d942d5 | 394 | if (!ring->rx_info) { |
163561a4 EE |
395 | ring->rx_info = vmalloc(tmp); |
396 | if (!ring->rx_info) { | |
397 | err = -ENOMEM; | |
398 | goto err_ring; | |
399 | } | |
41d942d5 | 400 | } |
e404decb | 401 | |
453a6082 | 402 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
403 | ring->rx_info, tmp); |
404 | ||
163561a4 | 405 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 406 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
73898db0 | 407 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); |
872bf2fb | 408 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 409 | if (err) |
41d942d5 | 410 | goto err_info; |
c27a02cd | 411 | |
c27a02cd YP |
412 | ring->buf = ring->wqres.buf.direct.buf; |
413 | ||
ec693d47 AV |
414 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
415 | ||
41d942d5 | 416 | *pring = ring; |
c27a02cd YP |
417 | return 0; |
418 | ||
41d942d5 | 419 | err_info: |
c27a02cd YP |
420 | vfree(ring->rx_info); |
421 | ring->rx_info = NULL; | |
41d942d5 EE |
422 | err_ring: |
423 | kfree(ring); | |
424 | *pring = NULL; | |
425 | ||
c27a02cd YP |
426 | return err; |
427 | } | |
428 | ||
429 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
430 | { | |
c27a02cd YP |
431 | struct mlx4_en_rx_ring *ring; |
432 | int i; | |
433 | int ring_ind; | |
434 | int err; | |
435 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
436 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
437 | |
438 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 439 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
440 | |
441 | ring->prod = 0; | |
442 | ring->cons = 0; | |
443 | ring->actual_size = 0; | |
41d942d5 | 444 | ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
c27a02cd YP |
445 | |
446 | ring->stride = stride; | |
9f519f68 YP |
447 | if (ring->stride <= TXBB_SIZE) |
448 | ring->buf += TXBB_SIZE; | |
449 | ||
c27a02cd YP |
450 | ring->log_stride = ffs(ring->stride) - 1; |
451 | ring->buf_size = ring->size * ring->stride; | |
452 | ||
453 | memset(ring->buf, 0, ring->buf_size); | |
454 | mlx4_en_update_rx_prod_db(ring); | |
455 | ||
4cce66cd | 456 | /* Initialize all descriptors */ |
c27a02cd YP |
457 | for (i = 0; i < ring->size; i++) |
458 | mlx4_en_init_rx_desc(priv, ring, i); | |
459 | ||
460 | /* Initialize page allocators */ | |
461 | err = mlx4_en_init_allocator(priv, ring); | |
462 | if (err) { | |
453a6082 | 463 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
464 | if (ring->stride <= TXBB_SIZE) |
465 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
466 | ring_ind--; |
467 | goto err_allocator; | |
c27a02cd | 468 | } |
c27a02cd | 469 | } |
b58515be IM |
470 | err = mlx4_en_fill_rx_buffers(priv); |
471 | if (err) | |
c27a02cd YP |
472 | goto err_buffers; |
473 | ||
474 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 475 | ring = priv->rx_ring[ring_ind]; |
c27a02cd | 476 | |
00d7d7bc | 477 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 478 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
479 | } |
480 | ||
481 | return 0; | |
482 | ||
c27a02cd YP |
483 | err_buffers: |
484 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
41d942d5 | 485 | mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); |
c27a02cd YP |
486 | |
487 | ring_ind = priv->rx_ring_num - 1; | |
488 | err_allocator: | |
489 | while (ring_ind >= 0) { | |
41d942d5 EE |
490 | if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) |
491 | priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; | |
492 | mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); | |
c27a02cd YP |
493 | ring_ind--; |
494 | } | |
495 | return err; | |
496 | } | |
497 | ||
07841f9d IS |
498 | /* We recover from out of memory by scheduling our napi poll |
499 | * function (mlx4_en_process_cq), which tries to allocate | |
500 | * all missing RX buffers (call to mlx4_en_refill_rx_buffers). | |
501 | */ | |
502 | void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) | |
503 | { | |
504 | int ring; | |
505 | ||
506 | if (!priv->port_up) | |
507 | return; | |
508 | ||
509 | for (ring = 0; ring < priv->rx_ring_num; ring++) { | |
510 | if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) | |
511 | napi_reschedule(&priv->rx_cq[ring]->napi); | |
512 | } | |
513 | } | |
514 | ||
d576acf0 BB |
515 | /* When the rx ring is running in page-per-packet mode, a released frame can go |
516 | * directly into a small cache, to avoid unmapping or touching the page | |
517 | * allocator. In bpf prog performance scenarios, buffers are either forwarded | |
518 | * or dropped, never converted to skbs, so every page can come directly from | |
519 | * this cache when it is sized to be a multiple of the napi budget. | |
520 | */ | |
521 | bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, | |
522 | struct mlx4_en_rx_alloc *frame) | |
523 | { | |
524 | struct mlx4_en_page_cache *cache = &ring->page_cache; | |
525 | ||
526 | if (cache->index >= MLX4_EN_CACHE_SIZE) | |
527 | return false; | |
528 | ||
529 | cache->buf[cache->index++] = *frame; | |
530 | return true; | |
531 | } | |
532 | ||
c27a02cd | 533 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 EE |
534 | struct mlx4_en_rx_ring **pring, |
535 | u32 size, u16 stride) | |
c27a02cd YP |
536 | { |
537 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 538 | struct mlx4_en_rx_ring *ring = *pring; |
cb7386d3 | 539 | struct bpf_prog *old_prog; |
c27a02cd | 540 | |
326fe02d BB |
541 | old_prog = rcu_dereference_protected( |
542 | ring->xdp_prog, | |
543 | lockdep_is_held(&mdev->state_lock)); | |
cb7386d3 BB |
544 | if (old_prog) |
545 | bpf_prog_put(old_prog); | |
68355f71 | 546 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
547 | vfree(ring->rx_info); |
548 | ring->rx_info = NULL; | |
41d942d5 EE |
549 | kfree(ring); |
550 | *pring = NULL; | |
c27a02cd YP |
551 | } |
552 | ||
553 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
554 | struct mlx4_en_rx_ring *ring) | |
555 | { | |
d576acf0 BB |
556 | int i; |
557 | ||
558 | for (i = 0; i < ring->page_cache.index; i++) { | |
559 | struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i]; | |
560 | ||
561 | dma_unmap_page(priv->ddev, frame->dma, frame->page_size, | |
562 | priv->frag_info[0].dma_dir); | |
563 | put_page(frame->page); | |
564 | } | |
565 | ring->page_cache.index = 0; | |
c27a02cd | 566 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
567 | if (ring->stride <= TXBB_SIZE) |
568 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
569 | mlx4_en_destroy_allocator(priv, ring); |
570 | } | |
571 | ||
572 | ||
c27a02cd YP |
573 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
574 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 575 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 576 | struct sk_buff *skb, |
c27a02cd YP |
577 | int length) |
578 | { | |
90278c9f | 579 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
580 | struct mlx4_en_frag_info *frag_info; |
581 | int nr; | |
582 | dma_addr_t dma; | |
583 | ||
4cce66cd | 584 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
585 | for (nr = 0; nr < priv->num_frags; nr++) { |
586 | frag_info = &priv->frag_info[nr]; | |
587 | if (length <= frag_info->frag_prefix_size) | |
588 | break; | |
de3d6fa8 | 589 | if (unlikely(!frags[nr].page)) |
4cce66cd | 590 | goto fail; |
c27a02cd | 591 | |
c27a02cd | 592 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
593 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
594 | DMA_FROM_DEVICE); | |
c27a02cd | 595 | |
4cce66cd | 596 | /* Save page reference in skb */ |
4cce66cd TLSC |
597 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
598 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 599 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 600 | skb->truesize += frag_info->frag_stride; |
51151a16 | 601 | frags[nr].page = NULL; |
c27a02cd YP |
602 | } |
603 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 604 | if (nr > 0) |
9e903e08 ED |
605 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
606 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
607 | return nr; |
608 | ||
609 | fail: | |
c27a02cd YP |
610 | while (nr > 0) { |
611 | nr--; | |
311761c8 | 612 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
613 | } |
614 | return 0; | |
615 | } | |
616 | ||
617 | ||
618 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
619 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 620 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
621 | unsigned int length) |
622 | { | |
c27a02cd YP |
623 | struct sk_buff *skb; |
624 | void *va; | |
625 | int used_frags; | |
626 | dma_addr_t dma; | |
627 | ||
c056b734 | 628 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
de3d6fa8 | 629 | if (unlikely(!skb)) { |
453a6082 | 630 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
631 | return NULL; |
632 | } | |
c27a02cd YP |
633 | skb_reserve(skb, NET_IP_ALIGN); |
634 | skb->len = length; | |
c27a02cd YP |
635 | |
636 | /* Get pointer to first fragment so we could copy the headers into the | |
637 | * (linear part of the) skb */ | |
70fbe079 | 638 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
639 | |
640 | if (length <= SMALL_PACKET_SIZE) { | |
641 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 642 | * sync buffers for the copy */ |
c27a02cd | 643 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 644 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 645 | DMA_FROM_DEVICE); |
c27a02cd | 646 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
647 | skb->tail += length; |
648 | } else { | |
cfecec56 ED |
649 | unsigned int pull_len; |
650 | ||
c27a02cd | 651 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
652 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
653 | skb, length); | |
785a0982 YP |
654 | if (unlikely(!used_frags)) { |
655 | kfree_skb(skb); | |
656 | return NULL; | |
657 | } | |
c27a02cd YP |
658 | skb_shinfo(skb)->nr_frags = used_frags; |
659 | ||
cfecec56 | 660 | pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); |
c27a02cd | 661 | /* Copy headers into the skb linear buffer */ |
cfecec56 ED |
662 | memcpy(skb->data, va, pull_len); |
663 | skb->tail += pull_len; | |
c27a02cd YP |
664 | |
665 | /* Skip headers in first fragment */ | |
cfecec56 | 666 | skb_shinfo(skb)->frags[0].page_offset += pull_len; |
c27a02cd YP |
667 | |
668 | /* Adjust size of first fragment */ | |
cfecec56 ED |
669 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); |
670 | skb->data_len = length - pull_len; | |
c27a02cd YP |
671 | } |
672 | return skb; | |
673 | } | |
674 | ||
e7c1c2c4 YP |
675 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
676 | { | |
677 | int i; | |
678 | int offset = ETH_HLEN; | |
679 | ||
680 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
681 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
682 | goto out_loopback; | |
683 | } | |
684 | /* Loopback found */ | |
685 | priv->loopback_ok = 1; | |
686 | ||
687 | out_loopback: | |
688 | dev_kfree_skb_any(skb); | |
689 | } | |
c27a02cd | 690 | |
4cce66cd TLSC |
691 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
692 | struct mlx4_en_rx_ring *ring) | |
693 | { | |
694 | int index = ring->prod & ring->size_mask; | |
695 | ||
696 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
1ab25f86 IS |
697 | if (mlx4_en_prepare_rx_desc(priv, ring, index, |
698 | GFP_ATOMIC | __GFP_COLD)) | |
4cce66cd TLSC |
699 | break; |
700 | ring->prod++; | |
701 | index = ring->prod & ring->size_mask; | |
702 | } | |
703 | } | |
704 | ||
f8c6455b SM |
705 | /* When hardware doesn't strip the vlan, we need to calculate the checksum |
706 | * over it and add it to the hardware's checksum calculation | |
707 | */ | |
708 | static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, | |
709 | struct vlan_hdr *vlanh) | |
710 | { | |
711 | return csum_add(hw_checksum, *(__wsum *)vlanh); | |
712 | } | |
713 | ||
714 | /* Although the stack expects checksum which doesn't include the pseudo | |
715 | * header, the HW adds it. To address that, we are subtracting the pseudo | |
716 | * header checksum from the checksum value provided by the HW. | |
717 | */ | |
718 | static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, | |
719 | struct iphdr *iph) | |
720 | { | |
721 | __u16 length_for_csum = 0; | |
722 | __wsum csum_pseudo_header = 0; | |
723 | ||
724 | length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); | |
725 | csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, | |
726 | length_for_csum, iph->protocol, 0); | |
727 | skb->csum = csum_sub(hw_checksum, csum_pseudo_header); | |
728 | } | |
729 | ||
730 | #if IS_ENABLED(CONFIG_IPV6) | |
731 | /* In IPv6 packets, besides subtracting the pseudo header checksum, | |
732 | * we also compute/add the IP header checksum which | |
733 | * is not added by the HW. | |
734 | */ | |
735 | static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, | |
736 | struct ipv6hdr *ipv6h) | |
737 | { | |
738 | __wsum csum_pseudo_hdr = 0; | |
739 | ||
de3d6fa8 TT |
740 | if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT || |
741 | ipv6h->nexthdr == IPPROTO_HOPOPTS)) | |
f8c6455b | 742 | return -1; |
82d69203 | 743 | hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr)); |
f8c6455b SM |
744 | |
745 | csum_pseudo_hdr = csum_partial(&ipv6h->saddr, | |
746 | sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); | |
747 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); | |
748 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); | |
749 | ||
750 | skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); | |
751 | skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); | |
752 | return 0; | |
753 | } | |
754 | #endif | |
755 | static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, | |
79a25852 | 756 | netdev_features_t dev_features) |
f8c6455b SM |
757 | { |
758 | __wsum hw_checksum = 0; | |
759 | ||
760 | void *hdr = (u8 *)va + sizeof(struct ethhdr); | |
761 | ||
762 | hw_checksum = csum_unfold((__force __sum16)cqe->checksum); | |
763 | ||
e802f8e4 | 764 | if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) && |
79a25852 | 765 | !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { |
f8c6455b SM |
766 | hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); |
767 | hdr += sizeof(struct vlan_hdr); | |
768 | } | |
769 | ||
770 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) | |
771 | get_fixed_ipv4_csum(hw_checksum, skb, hdr); | |
772 | #if IS_ENABLED(CONFIG_IPV6) | |
773 | else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) | |
de3d6fa8 | 774 | if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr))) |
f8c6455b SM |
775 | return -1; |
776 | #endif | |
777 | return 0; | |
778 | } | |
779 | ||
c27a02cd YP |
780 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
781 | { | |
782 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 783 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd | 784 | struct mlx4_cqe *cqe; |
41d942d5 | 785 | struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; |
4cce66cd | 786 | struct mlx4_en_rx_alloc *frags; |
c27a02cd | 787 | struct mlx4_en_rx_desc *rx_desc; |
47a38e15 | 788 | struct bpf_prog *xdp_prog; |
9ecc2d86 | 789 | int doorbell_pending; |
c27a02cd YP |
790 | struct sk_buff *skb; |
791 | int index; | |
792 | int nr; | |
793 | unsigned int length; | |
794 | int polled = 0; | |
795 | int ip_summed; | |
08ff3235 | 796 | int factor = priv->cqe_factor; |
ec693d47 | 797 | u64 timestamp; |
837052d0 | 798 | bool l2_tunnel; |
c27a02cd | 799 | |
de3d6fa8 | 800 | if (unlikely(!priv->port_up)) |
c27a02cd YP |
801 | return 0; |
802 | ||
de3d6fa8 | 803 | if (unlikely(budget <= 0)) |
38be0a34 EB |
804 | return polled; |
805 | ||
326fe02d BB |
806 | /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */ |
807 | rcu_read_lock(); | |
808 | xdp_prog = rcu_dereference(ring->xdp_prog); | |
9ecc2d86 | 809 | doorbell_pending = 0; |
47a38e15 | 810 | |
c27a02cd YP |
811 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx |
812 | * descriptor offset can be deduced from the CQE index instead of | |
813 | * reading 'cqe->index' */ | |
814 | index = cq->mcq.cons_index & ring->size_mask; | |
b1b6b4da | 815 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
c27a02cd YP |
816 | |
817 | /* Process all completed CQEs */ | |
818 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
819 | cq->mcq.cons_index & cq->size)) { | |
820 | ||
4cce66cd | 821 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
822 | rx_desc = ring->buf + (index << ring->log_stride); |
823 | ||
824 | /* | |
825 | * make sure we read the CQE after we read the ownership bit | |
826 | */ | |
12b3375f | 827 | dma_rmb(); |
c27a02cd YP |
828 | |
829 | /* Drop packet on bad receive or bad checksum */ | |
830 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
831 | MLX4_CQE_OPCODE_ERROR)) { | |
1a91de28 JP |
832 | en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", |
833 | ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, | |
834 | ((struct mlx4_err_cqe *)cqe)->syndrome); | |
c27a02cd YP |
835 | goto next; |
836 | } | |
837 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 838 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
839 | goto next; |
840 | } | |
841 | ||
79aeaccd YB |
842 | /* Check if we need to drop the packet if SRIOV is not enabled |
843 | * and not performing the selftest or flb disabled | |
844 | */ | |
845 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
846 | struct ethhdr *ethh; | |
847 | dma_addr_t dma; | |
79aeaccd YB |
848 | /* Get pointer to first fragment since we haven't |
849 | * skb yet and cast it to ethhdr struct | |
850 | */ | |
851 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
852 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
853 | DMA_FROM_DEVICE); | |
854 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 855 | frags[0].page_offset); |
79aeaccd | 856 | |
c07cb4b0 YB |
857 | if (is_multicast_ether_addr(ethh->h_dest)) { |
858 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
859 | struct hlist_head *bucket; |
860 | unsigned int mac_hash; | |
861 | ||
862 | /* Drop the packet, since HW loopback-ed it */ | |
863 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
864 | bucket = &priv->mac_hash[mac_hash]; | |
b67bfe0d | 865 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 | 866 | if (ether_addr_equal_64bits(entry->mac, |
326fe02d | 867 | ethh->h_source)) |
c07cb4b0 | 868 | goto next; |
c07cb4b0 | 869 | } |
c07cb4b0 | 870 | } |
79aeaccd | 871 | } |
5b4c4d36 | 872 | |
c27a02cd YP |
873 | /* |
874 | * Packet is OK - process it. | |
875 | */ | |
876 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 877 | length -= ring->fcs_del; |
837052d0 OG |
878 | l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && |
879 | (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); | |
c27a02cd | 880 | |
47a38e15 BB |
881 | /* A bpf program gets first chance to drop the packet. It may |
882 | * read bytes but not past the end of the frag. | |
883 | */ | |
884 | if (xdp_prog) { | |
885 | struct xdp_buff xdp; | |
886 | dma_addr_t dma; | |
887 | u32 act; | |
888 | ||
889 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
890 | dma_sync_single_for_cpu(priv->ddev, dma, | |
891 | priv->frag_info[0].frag_size, | |
892 | DMA_FROM_DEVICE); | |
893 | ||
894 | xdp.data = page_address(frags[0].page) + | |
895 | frags[0].page_offset; | |
896 | xdp.data_end = xdp.data + length; | |
897 | ||
898 | act = bpf_prog_run_xdp(xdp_prog, &xdp); | |
899 | switch (act) { | |
900 | case XDP_PASS: | |
901 | break; | |
9ecc2d86 | 902 | case XDP_TX: |
15fca2c8 | 903 | if (likely(!mlx4_en_xmit_frame(ring, frags, dev, |
67f8b1dc | 904 | length, cq->ring, |
de3d6fa8 | 905 | &doorbell_pending))) |
9ecc2d86 | 906 | goto consumed; |
15fca2c8 | 907 | goto xdp_drop_no_cnt; /* Drop on xmit failure */ |
47a38e15 BB |
908 | default: |
909 | bpf_warn_invalid_xdp_action(act); | |
910 | case XDP_ABORTED: | |
911 | case XDP_DROP: | |
15fca2c8 TT |
912 | ring->xdp_drop++; |
913 | xdp_drop_no_cnt: | |
de3d6fa8 | 914 | if (likely(mlx4_en_rx_recycle(ring, frags))) |
d576acf0 | 915 | goto consumed; |
47a38e15 BB |
916 | goto next; |
917 | } | |
918 | } | |
919 | ||
15fca2c8 TT |
920 | ring->bytes += length; |
921 | ring->packets++; | |
922 | ||
c8c64cff | 923 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
f8c6455b SM |
924 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | |
925 | MLX4_CQE_STATUS_UDP)) { | |
926 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && | |
927 | cqe->checksum == cpu_to_be16(0xffff)) { | |
928 | ip_summed = CHECKSUM_UNNECESSARY; | |
929 | ring->csum_ok++; | |
930 | } else { | |
931 | ip_summed = CHECKSUM_NONE; | |
932 | ring->csum_none++; | |
933 | } | |
c27a02cd | 934 | } else { |
f8c6455b SM |
935 | if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && |
936 | (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | | |
937 | MLX4_CQE_STATUS_IPV6))) { | |
938 | ip_summed = CHECKSUM_COMPLETE; | |
939 | ring->csum_complete++; | |
940 | } else { | |
941 | ip_summed = CHECKSUM_NONE; | |
942 | ring->csum_none++; | |
943 | } | |
c27a02cd YP |
944 | } |
945 | } else { | |
946 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 947 | ring->csum_none++; |
c27a02cd YP |
948 | } |
949 | ||
dd65beac SM |
950 | /* This packet is eligible for GRO if it is: |
951 | * - DIX Ethernet (type interpretation) | |
952 | * - TCP/IP (v4) | |
953 | * - without IP options | |
954 | * - not an IP fragment | |
dd65beac | 955 | */ |
868fdb06 | 956 | if (dev->features & NETIF_F_GRO) { |
dd65beac SM |
957 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); |
958 | if (!gro_skb) | |
959 | goto next; | |
960 | ||
961 | nr = mlx4_en_complete_rx_desc(priv, | |
962 | rx_desc, frags, gro_skb, | |
963 | length); | |
964 | if (!nr) | |
965 | goto next; | |
966 | ||
f8c6455b SM |
967 | if (ip_summed == CHECKSUM_COMPLETE) { |
968 | void *va = skb_frag_address(skb_shinfo(gro_skb)->frags); | |
79a25852 IS |
969 | if (check_csum(cqe, gro_skb, va, |
970 | dev->features)) { | |
f8c6455b SM |
971 | ip_summed = CHECKSUM_NONE; |
972 | ring->csum_none++; | |
973 | ring->csum_complete--; | |
974 | } | |
975 | } | |
976 | ||
dd65beac SM |
977 | skb_shinfo(gro_skb)->nr_frags = nr; |
978 | gro_skb->len = length; | |
979 | gro_skb->data_len = length; | |
980 | gro_skb->ip_summed = ip_summed; | |
981 | ||
982 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) | |
c58942f2 OG |
983 | gro_skb->csum_level = 1; |
984 | ||
dd65beac | 985 | if ((cqe->vlan_my_qpn & |
e802f8e4 | 986 | cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) && |
dd65beac SM |
987 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { |
988 | u16 vid = be16_to_cpu(cqe->sl_vid); | |
989 | ||
990 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); | |
e38af4fa HHZ |
991 | } else if ((be32_to_cpu(cqe->vlan_my_qpn) & |
992 | MLX4_CQE_SVLAN_PRESENT_MASK) && | |
993 | (dev->features & NETIF_F_HW_VLAN_STAG_RX)) { | |
994 | __vlan_hwaccel_put_tag(gro_skb, | |
995 | htons(ETH_P_8021AD), | |
996 | be16_to_cpu(cqe->sl_vid)); | |
dd65beac SM |
997 | } |
998 | ||
999 | if (dev->features & NETIF_F_RXHASH) | |
1000 | skb_set_hash(gro_skb, | |
1001 | be32_to_cpu(cqe->immed_rss_invalid), | |
0a6d4245 ED |
1002 | (ip_summed == CHECKSUM_UNNECESSARY) ? |
1003 | PKT_HASH_TYPE_L4 : | |
1004 | PKT_HASH_TYPE_L3); | |
dd65beac SM |
1005 | |
1006 | skb_record_rx_queue(gro_skb, cq->ring); | |
dd65beac SM |
1007 | |
1008 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { | |
1009 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
1010 | mlx4_en_fill_hwtstamps(mdev, | |
1011 | skb_hwtstamps(gro_skb), | |
1012 | timestamp); | |
1013 | } | |
1014 | ||
1015 | napi_gro_frags(&cq->napi); | |
1016 | goto next; | |
1017 | } | |
1018 | ||
1019 | /* GRO not possible, complete processing here */ | |
4cce66cd | 1020 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
de3d6fa8 | 1021 | if (unlikely(!skb)) { |
d21ed3a3 | 1022 | ring->dropped++; |
c27a02cd YP |
1023 | goto next; |
1024 | } | |
1025 | ||
57c970c2 | 1026 | if (unlikely(priv->validate_loopback)) { |
e7c1c2c4 YP |
1027 | validate_loopback(priv, skb); |
1028 | goto next; | |
1029 | } | |
1030 | ||
f8c6455b | 1031 | if (ip_summed == CHECKSUM_COMPLETE) { |
79a25852 | 1032 | if (check_csum(cqe, skb, skb->data, dev->features)) { |
f8c6455b SM |
1033 | ip_summed = CHECKSUM_NONE; |
1034 | ring->csum_complete--; | |
1035 | ring->csum_none++; | |
1036 | } | |
1037 | } | |
1038 | ||
c27a02cd YP |
1039 | skb->ip_summed = ip_summed; |
1040 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 1041 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 1042 | |
9ca8600e TH |
1043 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) |
1044 | skb->csum_level = 1; | |
837052d0 | 1045 | |
ad86107f | 1046 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
1047 | skb_set_hash(skb, |
1048 | be32_to_cpu(cqe->immed_rss_invalid), | |
0a6d4245 ED |
1049 | (ip_summed == CHECKSUM_UNNECESSARY) ? |
1050 | PKT_HASH_TYPE_L4 : | |
1051 | PKT_HASH_TYPE_L3); | |
ad86107f | 1052 | |
ec693d47 | 1053 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
e802f8e4 | 1054 | MLX4_CQE_CVLAN_PRESENT_MASK) && |
ec693d47 | 1055 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) |
86a9bad3 | 1056 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
e38af4fa HHZ |
1057 | else if ((be32_to_cpu(cqe->vlan_my_qpn) & |
1058 | MLX4_CQE_SVLAN_PRESENT_MASK) && | |
1059 | (dev->features & NETIF_F_HW_VLAN_STAG_RX)) | |
1060 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), | |
1061 | be16_to_cpu(cqe->sl_vid)); | |
f1b553fb | 1062 | |
ec693d47 AV |
1063 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
1064 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
1065 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
1066 | timestamp); | |
1067 | } | |
1068 | ||
868fdb06 | 1069 | napi_gro_receive(&cq->napi, skb); |
c27a02cd | 1070 | next: |
4cce66cd TLSC |
1071 | for (nr = 0; nr < priv->num_frags; nr++) |
1072 | mlx4_en_free_frag(priv, frags, nr); | |
1073 | ||
d576acf0 | 1074 | consumed: |
c27a02cd YP |
1075 | ++cq->mcq.cons_index; |
1076 | index = (cq->mcq.cons_index) & ring->size_mask; | |
b1b6b4da | 1077 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
f1d29a3f | 1078 | if (++polled == budget) |
c27a02cd | 1079 | goto out; |
c27a02cd YP |
1080 | } |
1081 | ||
c27a02cd | 1082 | out: |
326fe02d | 1083 | rcu_read_unlock(); |
9ecc2d86 | 1084 | if (doorbell_pending) |
67f8b1dc | 1085 | mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]); |
9ecc2d86 | 1086 | |
c27a02cd YP |
1087 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); |
1088 | mlx4_cq_set_ci(&cq->mcq); | |
1089 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
1090 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 1091 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
1092 | mlx4_en_update_rx_prod_db(ring); |
1093 | return polled; | |
1094 | } | |
1095 | ||
1096 | ||
1097 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
1098 | { | |
1099 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
1100 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
1101 | ||
477b35b4 ED |
1102 | if (likely(priv->port_up)) |
1103 | napi_schedule_irqoff(&cq->napi); | |
c27a02cd YP |
1104 | else |
1105 | mlx4_en_arm_cq(priv, cq); | |
1106 | } | |
1107 | ||
1108 | /* Rx CQ polling - called by NAPI */ | |
1109 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
1110 | { | |
1111 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
1112 | struct net_device *dev = cq->dev; | |
1113 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1114 | int done; | |
1115 | ||
1116 | done = mlx4_en_process_rx_cq(dev, cq, budget); | |
1117 | ||
1118 | /* If we used up all the quota - we're probably not done yet... */ | |
2eacc23c | 1119 | if (done == budget) { |
35f6f453 | 1120 | const struct cpumask *aff; |
dc2ec62f TG |
1121 | struct irq_data *idata; |
1122 | int cpu_curr; | |
35f6f453 | 1123 | |
c27a02cd | 1124 | INC_PERF_COUNTER(priv->pstats.napi_quota); |
35f6f453 AV |
1125 | |
1126 | cpu_curr = smp_processor_id(); | |
dc2ec62f TG |
1127 | idata = irq_desc_get_irq_data(cq->irq_desc); |
1128 | aff = irq_data_get_affinity_mask(idata); | |
35f6f453 | 1129 | |
2e1af7d7 ED |
1130 | if (likely(cpumask_test_cpu(cpu_curr, aff))) |
1131 | return budget; | |
1132 | ||
1133 | /* Current cpu is not according to smp_irq_affinity - | |
1134 | * probably affinity changed. need to stop this NAPI | |
1135 | * poll, and restart it on the right CPU | |
1136 | */ | |
1137 | done = 0; | |
c27a02cd | 1138 | } |
1a288172 ED |
1139 | /* Done for now */ |
1140 | napi_complete_done(napi, done); | |
1141 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
1142 | return done; |
1143 | } | |
1144 | ||
51151a16 | 1145 | static const int frag_sizes[] = { |
c27a02cd YP |
1146 | FRAG_SZ0, |
1147 | FRAG_SZ1, | |
1148 | FRAG_SZ2, | |
1149 | FRAG_SZ3 | |
1150 | }; | |
1151 | ||
1152 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
1153 | { | |
d576acf0 | 1154 | enum dma_data_direction dma_dir = PCI_DMA_FROMDEVICE; |
c27a02cd | 1155 | struct mlx4_en_priv *priv = netdev_priv(dev); |
47a38e15 | 1156 | int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu); |
d576acf0 BB |
1157 | int order = MLX4_EN_ALLOC_PREFER_ORDER; |
1158 | u32 align = SMP_CACHE_BYTES; | |
c27a02cd YP |
1159 | int buf_size = 0; |
1160 | int i = 0; | |
1161 | ||
d576acf0 BB |
1162 | /* bpf requires buffers to be set up as 1 packet per page. |
1163 | * This only works when num_frags == 1. | |
1164 | */ | |
67f8b1dc | 1165 | if (priv->tx_ring_num[TX_XDP]) { |
9ecc2d86 | 1166 | dma_dir = PCI_DMA_BIDIRECTIONAL; |
d576acf0 BB |
1167 | /* This will gain efficient xdp frame recycling at the expense |
1168 | * of more costly truesize accounting | |
1169 | */ | |
1170 | align = PAGE_SIZE; | |
1171 | order = 0; | |
1172 | } | |
1173 | ||
c27a02cd | 1174 | while (buf_size < eff_mtu) { |
d576acf0 | 1175 | priv->frag_info[i].order = order; |
c27a02cd YP |
1176 | priv->frag_info[i].frag_size = |
1177 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
1178 | frag_sizes[i] : eff_mtu - buf_size; | |
1179 | priv->frag_info[i].frag_prefix_size = buf_size; | |
e8e7f018 | 1180 | priv->frag_info[i].frag_stride = |
d576acf0 BB |
1181 | ALIGN(priv->frag_info[i].frag_size, align); |
1182 | priv->frag_info[i].dma_dir = dma_dir; | |
c27a02cd YP |
1183 | buf_size += priv->frag_info[i].frag_size; |
1184 | i++; | |
1185 | } | |
1186 | ||
1187 | priv->num_frags = i; | |
1188 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 1189 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 1190 | |
1a91de28 JP |
1191 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", |
1192 | eff_mtu, priv->num_frags); | |
c27a02cd | 1193 | for (i = 0; i < priv->num_frags; i++) { |
51151a16 | 1194 | en_err(priv, |
5f6e9800 | 1195 | " frag:%d - size:%d prefix:%d stride:%d\n", |
51151a16 ED |
1196 | i, |
1197 | priv->frag_info[i].frag_size, | |
1198 | priv->frag_info[i].frag_prefix_size, | |
51151a16 | 1199 | priv->frag_info[i].frag_stride); |
c27a02cd YP |
1200 | } |
1201 | } | |
1202 | ||
1203 | /* RSS related functions */ | |
1204 | ||
9f519f68 YP |
1205 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
1206 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
1207 | enum mlx4_qp_state *state, |
1208 | struct mlx4_qp *qp) | |
1209 | { | |
1210 | struct mlx4_en_dev *mdev = priv->mdev; | |
1211 | struct mlx4_qp_context *context; | |
1212 | int err = 0; | |
1213 | ||
14f8dc49 JP |
1214 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
1215 | if (!context) | |
c27a02cd | 1216 | return -ENOMEM; |
c27a02cd | 1217 | |
40f2287b | 1218 | err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); |
c27a02cd | 1219 | if (err) { |
453a6082 | 1220 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 1221 | goto out; |
c27a02cd YP |
1222 | } |
1223 | qp->event = mlx4_en_sqp_event; | |
1224 | ||
1225 | memset(context, 0, sizeof *context); | |
00d7d7bc | 1226 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 1227 | qpn, ring->cqn, -1, context); |
9f519f68 | 1228 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 1229 | |
f3a9d1f2 | 1230 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 1231 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 1232 | context->param3 |= cpu_to_be32(1 << 29); |
f0df3503 MM |
1233 | if (priv->dev->features & NETIF_F_RXFCS) |
1234 | ring->fcs_del = 0; | |
1235 | else | |
1236 | ring->fcs_del = ETH_FCS_LEN; | |
4a5f4dd8 YP |
1237 | } else |
1238 | ring->fcs_del = 0; | |
f3a9d1f2 | 1239 | |
9f519f68 | 1240 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
1241 | if (err) { |
1242 | mlx4_qp_remove(mdev->dev, qp); | |
1243 | mlx4_qp_free(mdev->dev, qp); | |
1244 | } | |
9f519f68 | 1245 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
1246 | out: |
1247 | kfree(context); | |
1248 | return err; | |
1249 | } | |
1250 | ||
cabdc8ee HHZ |
1251 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
1252 | { | |
1253 | int err; | |
1254 | u32 qpn; | |
1255 | ||
d57febe1 MB |
1256 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, |
1257 | MLX4_RESERVE_A0_QP); | |
cabdc8ee HHZ |
1258 | if (err) { |
1259 | en_err(priv, "Failed reserving drop qpn\n"); | |
1260 | return err; | |
1261 | } | |
40f2287b | 1262 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); |
cabdc8ee HHZ |
1263 | if (err) { |
1264 | en_err(priv, "Failed allocating drop qp\n"); | |
1265 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1266 | return err; | |
1267 | } | |
1268 | ||
1269 | return 0; | |
1270 | } | |
1271 | ||
1272 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
1273 | { | |
1274 | u32 qpn; | |
1275 | ||
1276 | qpn = priv->drop_qp.qpn; | |
1277 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
1278 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
1279 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1280 | } | |
1281 | ||
c27a02cd YP |
1282 | /* Allocate rx qp's and configure them according to rss map */ |
1283 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
1284 | { | |
1285 | struct mlx4_en_dev *mdev = priv->mdev; | |
1286 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1287 | struct mlx4_qp_context context; | |
876f6e67 | 1288 | struct mlx4_rss_context *rss_context; |
93d3e367 | 1289 | int rss_rings; |
c27a02cd | 1290 | void *ptr; |
876f6e67 | 1291 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 1292 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 1293 | int i, qpn; |
c27a02cd YP |
1294 | int err = 0; |
1295 | int good_qps = 0; | |
1296 | ||
453a6082 | 1297 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
1298 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
1299 | priv->rx_ring_num, | |
ddae0349 | 1300 | &rss_map->base_qpn, 0); |
c27a02cd | 1301 | if (err) { |
b6b912e0 | 1302 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
1303 | return err; |
1304 | } | |
1305 | ||
b6b912e0 | 1306 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 1307 | qpn = rss_map->base_qpn + i; |
41d942d5 | 1308 | err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], |
c27a02cd YP |
1309 | &rss_map->state[i], |
1310 | &rss_map->qps[i]); | |
1311 | if (err) | |
1312 | goto rss_err; | |
1313 | ||
1314 | ++good_qps; | |
1315 | } | |
1316 | ||
1317 | /* Configure RSS indirection qp */ | |
40f2287b | 1318 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); |
c27a02cd | 1319 | if (err) { |
453a6082 | 1320 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1321 | goto rss_err; |
c27a02cd YP |
1322 | } |
1323 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1324 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
41d942d5 | 1325 | priv->rx_ring[0]->cqn, -1, &context); |
c27a02cd | 1326 | |
93d3e367 YP |
1327 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1328 | rss_rings = priv->rx_ring_num; | |
1329 | else | |
1330 | rss_rings = priv->prof->rss_rings; | |
1331 | ||
876f6e67 OG |
1332 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1333 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1334 | rss_context = ptr; |
93d3e367 | 1335 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1336 | (rss_map->base_qpn)); |
89efea25 | 1337 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1338 | if (priv->mdev->profile.udp_rss) { |
1339 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1340 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1341 | } | |
837052d0 OG |
1342 | |
1343 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { | |
1344 | en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); | |
1345 | rss_mask |= MLX4_RSS_BY_INNER_HEADERS; | |
1346 | } | |
1347 | ||
0533943c | 1348 | rss_context->flags = rss_mask; |
876f6e67 | 1349 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
947cbb0a EP |
1350 | if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { |
1351 | rss_context->hash_fn = MLX4_RSS_HASH_XOR; | |
1352 | } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { | |
1353 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; | |
1354 | memcpy(rss_context->rss_key, priv->rss_key, | |
1355 | MLX4_EN_RSS_KEY_SIZE); | |
947cbb0a EP |
1356 | } else { |
1357 | en_err(priv, "Unknown RSS hash function requested\n"); | |
1358 | err = -EINVAL; | |
1359 | goto indir_err; | |
1360 | } | |
c27a02cd YP |
1361 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, |
1362 | &rss_map->indir_qp, &rss_map->indir_state); | |
1363 | if (err) | |
1364 | goto indir_err; | |
1365 | ||
1366 | return 0; | |
1367 | ||
1368 | indir_err: | |
1369 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1370 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1371 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1372 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1373 | rss_err: |
1374 | for (i = 0; i < good_qps; i++) { | |
1375 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1376 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1377 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1378 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1379 | } | |
b6b912e0 | 1380 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1381 | return err; |
1382 | } | |
1383 | ||
1384 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1385 | { | |
1386 | struct mlx4_en_dev *mdev = priv->mdev; | |
1387 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1388 | int i; | |
1389 | ||
1390 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1391 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1392 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1393 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1394 | |
b6b912e0 | 1395 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1396 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1397 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1398 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1399 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1400 | } | |
b6b912e0 | 1401 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1402 | } |