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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
c27a02cd | 35 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
b67bfe0d | 39 | #include <linux/rculist.h> |
c27a02cd YP |
40 | #include <linux/if_ether.h> |
41 | #include <linux/if_vlan.h> | |
42 | #include <linux/vmalloc.h> | |
35f6f453 | 43 | #include <linux/irq.h> |
c27a02cd | 44 | |
f8c6455b SM |
45 | #if IS_ENABLED(CONFIG_IPV6) |
46 | #include <net/ip6_checksum.h> | |
47 | #endif | |
48 | ||
c27a02cd YP |
49 | #include "mlx4_en.h" |
50 | ||
51151a16 ED |
51 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
52 | struct mlx4_en_rx_alloc *page_alloc, | |
53 | const struct mlx4_en_frag_info *frag_info, | |
54 | gfp_t _gfp) | |
55 | { | |
56 | int order; | |
57 | struct page *page; | |
58 | dma_addr_t dma; | |
59 | ||
60 | for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { | |
61 | gfp_t gfp = _gfp; | |
62 | ||
63 | if (order) | |
64 | gfp |= __GFP_COMP | __GFP_NOWARN; | |
65 | page = alloc_pages(gfp, order); | |
66 | if (likely(page)) | |
67 | break; | |
68 | if (--order < 0 || | |
69 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
70 | return -ENOMEM; | |
71 | } | |
72 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
73 | PCI_DMA_FROMDEVICE); | |
74 | if (dma_mapping_error(priv->ddev, dma)) { | |
75 | put_page(page); | |
76 | return -ENOMEM; | |
77 | } | |
70fbe079 | 78 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
79 | page_alloc->page = page; |
80 | page_alloc->dma = dma; | |
5f6e9800 | 81 | page_alloc->page_offset = 0; |
51151a16 | 82 | /* Not doing get_page() for each frag is a big win |
98226208 | 83 | * on asymetric workloads. Note we can not use atomic_set(). |
51151a16 | 84 | */ |
98226208 ED |
85 | atomic_add(page_alloc->page_size / frag_info->frag_stride - 1, |
86 | &page->_count); | |
51151a16 ED |
87 | return 0; |
88 | } | |
89 | ||
4cce66cd TLSC |
90 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
91 | struct mlx4_en_rx_desc *rx_desc, | |
92 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
93 | struct mlx4_en_rx_alloc *ring_alloc, |
94 | gfp_t gfp) | |
c27a02cd | 95 | { |
4cce66cd | 96 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 97 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd YP |
98 | struct page *page; |
99 | dma_addr_t dma; | |
4cce66cd | 100 | int i; |
c27a02cd | 101 | |
4cce66cd TLSC |
102 | for (i = 0; i < priv->num_frags; i++) { |
103 | frag_info = &priv->frag_info[i]; | |
51151a16 | 104 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
105 | page_alloc[i].page_offset += frag_info->frag_stride; |
106 | ||
107 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
108 | ring_alloc[i].page_size) | |
51151a16 | 109 | continue; |
70fbe079 | 110 | |
51151a16 ED |
111 | if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) |
112 | goto out; | |
4cce66cd | 113 | } |
c27a02cd | 114 | |
4cce66cd TLSC |
115 | for (i = 0; i < priv->num_frags; i++) { |
116 | frags[i] = ring_alloc[i]; | |
70fbe079 | 117 | dma = ring_alloc[i].dma + ring_alloc[i].page_offset; |
4cce66cd TLSC |
118 | ring_alloc[i] = page_alloc[i]; |
119 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 120 | } |
4cce66cd | 121 | |
c27a02cd | 122 | return 0; |
4cce66cd | 123 | |
4cce66cd TLSC |
124 | out: |
125 | while (i--) { | |
51151a16 | 126 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 127 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
70fbe079 | 128 | page_alloc[i].page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
129 | page = page_alloc[i].page; |
130 | atomic_set(&page->_count, 1); | |
131 | put_page(page); | |
132 | } | |
4cce66cd TLSC |
133 | } |
134 | return -ENOMEM; | |
135 | } | |
136 | ||
137 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
138 | struct mlx4_en_rx_alloc *frags, | |
139 | int i) | |
140 | { | |
51151a16 | 141 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
021f1107 | 142 | u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; |
4cce66cd | 143 | |
021f1107 AV |
144 | |
145 | if (next_frag_end > frags[i].page_size) | |
70fbe079 AV |
146 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, |
147 | PCI_DMA_FROMDEVICE); | |
51151a16 | 148 | |
4cce66cd TLSC |
149 | if (frags[i].page) |
150 | put_page(frags[i].page); | |
c27a02cd YP |
151 | } |
152 | ||
153 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
154 | struct mlx4_en_rx_ring *ring) | |
155 | { | |
c27a02cd | 156 | int i; |
51151a16 | 157 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
158 | |
159 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 160 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 161 | |
51151a16 | 162 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
1ab25f86 | 163 | frag_info, GFP_KERNEL | __GFP_COLD)) |
4cce66cd | 164 | goto out; |
b110d2ce IS |
165 | |
166 | en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n", | |
167 | i, ring->page_alloc[i].page_size, | |
168 | atomic_read(&ring->page_alloc[i].page->_count)); | |
c27a02cd YP |
169 | } |
170 | return 0; | |
171 | ||
172 | out: | |
173 | while (i--) { | |
51151a16 ED |
174 | struct page *page; |
175 | ||
c27a02cd | 176 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 177 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 | 178 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
179 | page = page_alloc->page; |
180 | atomic_set(&page->_count, 1); | |
181 | put_page(page); | |
c27a02cd YP |
182 | page_alloc->page = NULL; |
183 | } | |
184 | return -ENOMEM; | |
185 | } | |
186 | ||
187 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
188 | struct mlx4_en_rx_ring *ring) | |
189 | { | |
190 | struct mlx4_en_rx_alloc *page_alloc; | |
191 | int i; | |
192 | ||
193 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
194 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
195 | ||
c27a02cd | 196 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
197 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
198 | i, page_count(page_alloc->page)); | |
c27a02cd | 199 | |
4cce66cd | 200 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 AV |
201 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
202 | while (page_alloc->page_offset + frag_info->frag_stride < | |
203 | page_alloc->page_size) { | |
51151a16 | 204 | put_page(page_alloc->page); |
70fbe079 | 205 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 206 | } |
c27a02cd YP |
207 | page_alloc->page = NULL; |
208 | } | |
209 | } | |
210 | ||
c27a02cd YP |
211 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
212 | struct mlx4_en_rx_ring *ring, int index) | |
213 | { | |
214 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
215 | int possible_frags; |
216 | int i; | |
217 | ||
c27a02cd YP |
218 | /* Set size and memtype fields */ |
219 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
220 | rx_desc->data[i].byte_count = |
221 | cpu_to_be32(priv->frag_info[i].frag_size); | |
222 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
223 | } | |
224 | ||
225 | /* If the number of used fragments does not fill up the ring stride, | |
226 | * remaining (unused) fragments must be padded with null address/size | |
227 | * and a special memory key */ | |
228 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
229 | for (i = priv->num_frags; i < possible_frags; i++) { | |
230 | rx_desc->data[i].byte_count = 0; | |
231 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
232 | rx_desc->data[i].addr = 0; | |
233 | } | |
234 | } | |
235 | ||
c27a02cd | 236 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
237 | struct mlx4_en_rx_ring *ring, int index, |
238 | gfp_t gfp) | |
c27a02cd YP |
239 | { |
240 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
241 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
242 | (index << priv->log_rx_info); | |
c27a02cd | 243 | |
51151a16 | 244 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
245 | } |
246 | ||
07841f9d IS |
247 | static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring) |
248 | { | |
249 | BUG_ON((u32)(ring->prod - ring->cons) > ring->actual_size); | |
250 | return ring->prod == ring->cons; | |
251 | } | |
252 | ||
c27a02cd YP |
253 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) |
254 | { | |
255 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
256 | } | |
257 | ||
38aab07c YP |
258 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
259 | struct mlx4_en_rx_ring *ring, | |
260 | int index) | |
261 | { | |
4cce66cd | 262 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
263 | int nr; |
264 | ||
4cce66cd | 265 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 266 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 267 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 268 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
269 | } |
270 | } | |
271 | ||
c27a02cd YP |
272 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
273 | { | |
c27a02cd YP |
274 | struct mlx4_en_rx_ring *ring; |
275 | int ring_ind; | |
276 | int buf_ind; | |
38aab07c | 277 | int new_size; |
c27a02cd YP |
278 | |
279 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
280 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 281 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
282 | |
283 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 | 284 | ring->actual_size, |
1ab25f86 | 285 | GFP_KERNEL | __GFP_COLD)) { |
c27a02cd | 286 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
1a91de28 | 287 | en_err(priv, "Failed to allocate enough rx buffers\n"); |
c27a02cd YP |
288 | return -ENOMEM; |
289 | } else { | |
38aab07c | 290 | new_size = rounddown_pow_of_two(ring->actual_size); |
1a91de28 | 291 | en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", |
453a6082 | 292 | ring->actual_size, new_size); |
38aab07c | 293 | goto reduce_rings; |
c27a02cd YP |
294 | } |
295 | } | |
296 | ring->actual_size++; | |
297 | ring->prod++; | |
298 | } | |
299 | } | |
38aab07c YP |
300 | return 0; |
301 | ||
302 | reduce_rings: | |
303 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 304 | ring = priv->rx_ring[ring_ind]; |
38aab07c YP |
305 | while (ring->actual_size > new_size) { |
306 | ring->actual_size--; | |
307 | ring->prod--; | |
308 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
309 | } | |
38aab07c YP |
310 | } |
311 | ||
c27a02cd YP |
312 | return 0; |
313 | } | |
314 | ||
c27a02cd YP |
315 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
316 | struct mlx4_en_rx_ring *ring) | |
317 | { | |
c27a02cd | 318 | int index; |
c27a02cd | 319 | |
453a6082 YP |
320 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
321 | ring->cons, ring->prod); | |
c27a02cd YP |
322 | |
323 | /* Unmap and free Rx buffers */ | |
07841f9d | 324 | while (!mlx4_en_is_ring_empty(ring)) { |
c27a02cd | 325 | index = ring->cons & ring->size_mask; |
453a6082 | 326 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 327 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
328 | ++ring->cons; |
329 | } | |
330 | } | |
331 | ||
02512482 IS |
332 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) |
333 | { | |
334 | int i; | |
335 | int num_of_eqs; | |
bb2146bc | 336 | int num_rx_rings; |
02512482 IS |
337 | struct mlx4_dev *dev = mdev->dev; |
338 | ||
339 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
c66fa19c MB |
340 | num_of_eqs = max_t(int, MIN_RX_RINGS, |
341 | min_t(int, | |
342 | mlx4_get_eqs_per_port(mdev->dev, i), | |
343 | DEF_RX_RINGS)); | |
02512482 | 344 | |
ea1c1af1 AV |
345 | num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : |
346 | min_t(int, num_of_eqs, | |
347 | netif_get_num_default_rss_queues()); | |
02512482 | 348 | mdev->profile.prof[i].rx_ring_num = |
bb2146bc | 349 | rounddown_pow_of_two(num_rx_rings); |
02512482 IS |
350 | } |
351 | } | |
352 | ||
c27a02cd | 353 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 354 | struct mlx4_en_rx_ring **pring, |
163561a4 | 355 | u32 size, u16 stride, int node) |
c27a02cd YP |
356 | { |
357 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 358 | struct mlx4_en_rx_ring *ring; |
4cce66cd | 359 | int err = -ENOMEM; |
c27a02cd YP |
360 | int tmp; |
361 | ||
163561a4 | 362 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 363 | if (!ring) { |
163561a4 EE |
364 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
365 | if (!ring) { | |
366 | en_err(priv, "Failed to allocate RX ring structure\n"); | |
367 | return -ENOMEM; | |
368 | } | |
41d942d5 EE |
369 | } |
370 | ||
c27a02cd YP |
371 | ring->prod = 0; |
372 | ring->cons = 0; | |
373 | ring->size = size; | |
374 | ring->size_mask = size - 1; | |
375 | ring->stride = stride; | |
376 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 377 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
378 | |
379 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 380 | sizeof(struct mlx4_en_rx_alloc)); |
163561a4 | 381 | ring->rx_info = vmalloc_node(tmp, node); |
41d942d5 | 382 | if (!ring->rx_info) { |
163561a4 EE |
383 | ring->rx_info = vmalloc(tmp); |
384 | if (!ring->rx_info) { | |
385 | err = -ENOMEM; | |
386 | goto err_ring; | |
387 | } | |
41d942d5 | 388 | } |
e404decb | 389 | |
453a6082 | 390 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
391 | ring->rx_info, tmp); |
392 | ||
163561a4 | 393 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 394 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
c27a02cd YP |
395 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, |
396 | ring->buf_size, 2 * PAGE_SIZE); | |
872bf2fb | 397 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 398 | if (err) |
41d942d5 | 399 | goto err_info; |
c27a02cd YP |
400 | |
401 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
402 | if (err) { | |
453a6082 | 403 | en_err(priv, "Failed to map RX buffer\n"); |
c27a02cd YP |
404 | goto err_hwq; |
405 | } | |
406 | ring->buf = ring->wqres.buf.direct.buf; | |
407 | ||
ec693d47 AV |
408 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
409 | ||
41d942d5 | 410 | *pring = ring; |
c27a02cd YP |
411 | return 0; |
412 | ||
c27a02cd YP |
413 | err_hwq: |
414 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
41d942d5 | 415 | err_info: |
c27a02cd YP |
416 | vfree(ring->rx_info); |
417 | ring->rx_info = NULL; | |
41d942d5 EE |
418 | err_ring: |
419 | kfree(ring); | |
420 | *pring = NULL; | |
421 | ||
c27a02cd YP |
422 | return err; |
423 | } | |
424 | ||
425 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
426 | { | |
c27a02cd YP |
427 | struct mlx4_en_rx_ring *ring; |
428 | int i; | |
429 | int ring_ind; | |
430 | int err; | |
431 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
432 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
433 | |
434 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 435 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
436 | |
437 | ring->prod = 0; | |
438 | ring->cons = 0; | |
439 | ring->actual_size = 0; | |
41d942d5 | 440 | ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
c27a02cd YP |
441 | |
442 | ring->stride = stride; | |
9f519f68 YP |
443 | if (ring->stride <= TXBB_SIZE) |
444 | ring->buf += TXBB_SIZE; | |
445 | ||
c27a02cd YP |
446 | ring->log_stride = ffs(ring->stride) - 1; |
447 | ring->buf_size = ring->size * ring->stride; | |
448 | ||
449 | memset(ring->buf, 0, ring->buf_size); | |
450 | mlx4_en_update_rx_prod_db(ring); | |
451 | ||
4cce66cd | 452 | /* Initialize all descriptors */ |
c27a02cd YP |
453 | for (i = 0; i < ring->size; i++) |
454 | mlx4_en_init_rx_desc(priv, ring, i); | |
455 | ||
456 | /* Initialize page allocators */ | |
457 | err = mlx4_en_init_allocator(priv, ring); | |
458 | if (err) { | |
453a6082 | 459 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
460 | if (ring->stride <= TXBB_SIZE) |
461 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
462 | ring_ind--; |
463 | goto err_allocator; | |
c27a02cd | 464 | } |
c27a02cd | 465 | } |
b58515be IM |
466 | err = mlx4_en_fill_rx_buffers(priv); |
467 | if (err) | |
c27a02cd YP |
468 | goto err_buffers; |
469 | ||
470 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 471 | ring = priv->rx_ring[ring_ind]; |
c27a02cd | 472 | |
00d7d7bc | 473 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 474 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
475 | } |
476 | ||
477 | return 0; | |
478 | ||
c27a02cd YP |
479 | err_buffers: |
480 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
41d942d5 | 481 | mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); |
c27a02cd YP |
482 | |
483 | ring_ind = priv->rx_ring_num - 1; | |
484 | err_allocator: | |
485 | while (ring_ind >= 0) { | |
41d942d5 EE |
486 | if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) |
487 | priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; | |
488 | mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); | |
c27a02cd YP |
489 | ring_ind--; |
490 | } | |
491 | return err; | |
492 | } | |
493 | ||
07841f9d IS |
494 | /* We recover from out of memory by scheduling our napi poll |
495 | * function (mlx4_en_process_cq), which tries to allocate | |
496 | * all missing RX buffers (call to mlx4_en_refill_rx_buffers). | |
497 | */ | |
498 | void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) | |
499 | { | |
500 | int ring; | |
501 | ||
502 | if (!priv->port_up) | |
503 | return; | |
504 | ||
505 | for (ring = 0; ring < priv->rx_ring_num; ring++) { | |
506 | if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) | |
507 | napi_reschedule(&priv->rx_cq[ring]->napi); | |
508 | } | |
509 | } | |
510 | ||
c27a02cd | 511 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 EE |
512 | struct mlx4_en_rx_ring **pring, |
513 | u32 size, u16 stride) | |
c27a02cd YP |
514 | { |
515 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 516 | struct mlx4_en_rx_ring *ring = *pring; |
c27a02cd | 517 | |
c27a02cd | 518 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
68355f71 | 519 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
520 | vfree(ring->rx_info); |
521 | ring->rx_info = NULL; | |
41d942d5 EE |
522 | kfree(ring); |
523 | *pring = NULL; | |
1eb8c695 | 524 | #ifdef CONFIG_RFS_ACCEL |
41d942d5 | 525 | mlx4_en_cleanup_filters(priv); |
1eb8c695 | 526 | #endif |
c27a02cd YP |
527 | } |
528 | ||
529 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
530 | struct mlx4_en_rx_ring *ring) | |
531 | { | |
c27a02cd | 532 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
533 | if (ring->stride <= TXBB_SIZE) |
534 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
535 | mlx4_en_destroy_allocator(priv, ring); |
536 | } | |
537 | ||
538 | ||
c27a02cd YP |
539 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
540 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 541 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 542 | struct sk_buff *skb, |
c27a02cd YP |
543 | int length) |
544 | { | |
90278c9f | 545 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
546 | struct mlx4_en_frag_info *frag_info; |
547 | int nr; | |
548 | dma_addr_t dma; | |
549 | ||
4cce66cd | 550 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
551 | for (nr = 0; nr < priv->num_frags; nr++) { |
552 | frag_info = &priv->frag_info[nr]; | |
553 | if (length <= frag_info->frag_prefix_size) | |
554 | break; | |
4cce66cd TLSC |
555 | if (!frags[nr].page) |
556 | goto fail; | |
c27a02cd | 557 | |
c27a02cd | 558 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
559 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
560 | DMA_FROM_DEVICE); | |
c27a02cd | 561 | |
4cce66cd | 562 | /* Save page reference in skb */ |
4cce66cd TLSC |
563 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
564 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 565 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 566 | skb->truesize += frag_info->frag_stride; |
51151a16 | 567 | frags[nr].page = NULL; |
c27a02cd YP |
568 | } |
569 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 570 | if (nr > 0) |
9e903e08 ED |
571 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
572 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
573 | return nr; |
574 | ||
575 | fail: | |
c27a02cd YP |
576 | while (nr > 0) { |
577 | nr--; | |
311761c8 | 578 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
579 | } |
580 | return 0; | |
581 | } | |
582 | ||
583 | ||
584 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
585 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 586 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
587 | unsigned int length) |
588 | { | |
c27a02cd YP |
589 | struct sk_buff *skb; |
590 | void *va; | |
591 | int used_frags; | |
592 | dma_addr_t dma; | |
593 | ||
c056b734 | 594 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 595 | if (!skb) { |
453a6082 | 596 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
597 | return NULL; |
598 | } | |
c27a02cd YP |
599 | skb_reserve(skb, NET_IP_ALIGN); |
600 | skb->len = length; | |
c27a02cd YP |
601 | |
602 | /* Get pointer to first fragment so we could copy the headers into the | |
603 | * (linear part of the) skb */ | |
70fbe079 | 604 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
605 | |
606 | if (length <= SMALL_PACKET_SIZE) { | |
607 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 608 | * sync buffers for the copy */ |
c27a02cd | 609 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 610 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 611 | DMA_FROM_DEVICE); |
c27a02cd | 612 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
613 | skb->tail += length; |
614 | } else { | |
cfecec56 ED |
615 | unsigned int pull_len; |
616 | ||
c27a02cd | 617 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
618 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
619 | skb, length); | |
785a0982 YP |
620 | if (unlikely(!used_frags)) { |
621 | kfree_skb(skb); | |
622 | return NULL; | |
623 | } | |
c27a02cd YP |
624 | skb_shinfo(skb)->nr_frags = used_frags; |
625 | ||
cfecec56 | 626 | pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); |
c27a02cd | 627 | /* Copy headers into the skb linear buffer */ |
cfecec56 ED |
628 | memcpy(skb->data, va, pull_len); |
629 | skb->tail += pull_len; | |
c27a02cd YP |
630 | |
631 | /* Skip headers in first fragment */ | |
cfecec56 | 632 | skb_shinfo(skb)->frags[0].page_offset += pull_len; |
c27a02cd YP |
633 | |
634 | /* Adjust size of first fragment */ | |
cfecec56 ED |
635 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); |
636 | skb->data_len = length - pull_len; | |
c27a02cd YP |
637 | } |
638 | return skb; | |
639 | } | |
640 | ||
e7c1c2c4 YP |
641 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
642 | { | |
643 | int i; | |
644 | int offset = ETH_HLEN; | |
645 | ||
646 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
647 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
648 | goto out_loopback; | |
649 | } | |
650 | /* Loopback found */ | |
651 | priv->loopback_ok = 1; | |
652 | ||
653 | out_loopback: | |
654 | dev_kfree_skb_any(skb); | |
655 | } | |
c27a02cd | 656 | |
4cce66cd TLSC |
657 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
658 | struct mlx4_en_rx_ring *ring) | |
659 | { | |
660 | int index = ring->prod & ring->size_mask; | |
661 | ||
662 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
1ab25f86 IS |
663 | if (mlx4_en_prepare_rx_desc(priv, ring, index, |
664 | GFP_ATOMIC | __GFP_COLD)) | |
4cce66cd TLSC |
665 | break; |
666 | ring->prod++; | |
667 | index = ring->prod & ring->size_mask; | |
668 | } | |
669 | } | |
670 | ||
f8c6455b SM |
671 | /* When hardware doesn't strip the vlan, we need to calculate the checksum |
672 | * over it and add it to the hardware's checksum calculation | |
673 | */ | |
674 | static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, | |
675 | struct vlan_hdr *vlanh) | |
676 | { | |
677 | return csum_add(hw_checksum, *(__wsum *)vlanh); | |
678 | } | |
679 | ||
680 | /* Although the stack expects checksum which doesn't include the pseudo | |
681 | * header, the HW adds it. To address that, we are subtracting the pseudo | |
682 | * header checksum from the checksum value provided by the HW. | |
683 | */ | |
684 | static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, | |
685 | struct iphdr *iph) | |
686 | { | |
687 | __u16 length_for_csum = 0; | |
688 | __wsum csum_pseudo_header = 0; | |
689 | ||
690 | length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); | |
691 | csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, | |
692 | length_for_csum, iph->protocol, 0); | |
693 | skb->csum = csum_sub(hw_checksum, csum_pseudo_header); | |
694 | } | |
695 | ||
696 | #if IS_ENABLED(CONFIG_IPV6) | |
697 | /* In IPv6 packets, besides subtracting the pseudo header checksum, | |
698 | * we also compute/add the IP header checksum which | |
699 | * is not added by the HW. | |
700 | */ | |
701 | static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, | |
702 | struct ipv6hdr *ipv6h) | |
703 | { | |
704 | __wsum csum_pseudo_hdr = 0; | |
705 | ||
706 | if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS) | |
707 | return -1; | |
708 | hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8)); | |
709 | ||
710 | csum_pseudo_hdr = csum_partial(&ipv6h->saddr, | |
711 | sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); | |
712 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); | |
713 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); | |
714 | ||
715 | skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); | |
716 | skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); | |
717 | return 0; | |
718 | } | |
719 | #endif | |
720 | static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, | |
79a25852 | 721 | netdev_features_t dev_features) |
f8c6455b SM |
722 | { |
723 | __wsum hw_checksum = 0; | |
724 | ||
725 | void *hdr = (u8 *)va + sizeof(struct ethhdr); | |
726 | ||
727 | hw_checksum = csum_unfold((__force __sum16)cqe->checksum); | |
728 | ||
79a25852 IS |
729 | if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK) && |
730 | !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
f8c6455b SM |
731 | hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); |
732 | hdr += sizeof(struct vlan_hdr); | |
733 | } | |
734 | ||
735 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) | |
736 | get_fixed_ipv4_csum(hw_checksum, skb, hdr); | |
737 | #if IS_ENABLED(CONFIG_IPV6) | |
738 | else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) | |
739 | if (get_fixed_ipv6_csum(hw_checksum, skb, hdr)) | |
740 | return -1; | |
741 | #endif | |
742 | return 0; | |
743 | } | |
744 | ||
c27a02cd YP |
745 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
746 | { | |
747 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 748 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd | 749 | struct mlx4_cqe *cqe; |
41d942d5 | 750 | struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; |
4cce66cd | 751 | struct mlx4_en_rx_alloc *frags; |
c27a02cd YP |
752 | struct mlx4_en_rx_desc *rx_desc; |
753 | struct sk_buff *skb; | |
754 | int index; | |
755 | int nr; | |
756 | unsigned int length; | |
757 | int polled = 0; | |
758 | int ip_summed; | |
08ff3235 | 759 | int factor = priv->cqe_factor; |
ec693d47 | 760 | u64 timestamp; |
837052d0 | 761 | bool l2_tunnel; |
c27a02cd YP |
762 | |
763 | if (!priv->port_up) | |
764 | return 0; | |
765 | ||
38be0a34 EB |
766 | if (budget <= 0) |
767 | return polled; | |
768 | ||
c27a02cd YP |
769 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx |
770 | * descriptor offset can be deduced from the CQE index instead of | |
771 | * reading 'cqe->index' */ | |
772 | index = cq->mcq.cons_index & ring->size_mask; | |
b1b6b4da | 773 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
c27a02cd YP |
774 | |
775 | /* Process all completed CQEs */ | |
776 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
777 | cq->mcq.cons_index & cq->size)) { | |
778 | ||
4cce66cd | 779 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
780 | rx_desc = ring->buf + (index << ring->log_stride); |
781 | ||
782 | /* | |
783 | * make sure we read the CQE after we read the ownership bit | |
784 | */ | |
12b3375f | 785 | dma_rmb(); |
c27a02cd YP |
786 | |
787 | /* Drop packet on bad receive or bad checksum */ | |
788 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
789 | MLX4_CQE_OPCODE_ERROR)) { | |
1a91de28 JP |
790 | en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", |
791 | ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, | |
792 | ((struct mlx4_err_cqe *)cqe)->syndrome); | |
c27a02cd YP |
793 | goto next; |
794 | } | |
795 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 796 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
797 | goto next; |
798 | } | |
799 | ||
79aeaccd YB |
800 | /* Check if we need to drop the packet if SRIOV is not enabled |
801 | * and not performing the selftest or flb disabled | |
802 | */ | |
803 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
804 | struct ethhdr *ethh; | |
805 | dma_addr_t dma; | |
79aeaccd YB |
806 | /* Get pointer to first fragment since we haven't |
807 | * skb yet and cast it to ethhdr struct | |
808 | */ | |
809 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
810 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
811 | DMA_FROM_DEVICE); | |
812 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 813 | frags[0].page_offset); |
79aeaccd | 814 | |
c07cb4b0 YB |
815 | if (is_multicast_ether_addr(ethh->h_dest)) { |
816 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
817 | struct hlist_head *bucket; |
818 | unsigned int mac_hash; | |
819 | ||
820 | /* Drop the packet, since HW loopback-ed it */ | |
821 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
822 | bucket = &priv->mac_hash[mac_hash]; | |
823 | rcu_read_lock(); | |
b67bfe0d | 824 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 YB |
825 | if (ether_addr_equal_64bits(entry->mac, |
826 | ethh->h_source)) { | |
827 | rcu_read_unlock(); | |
828 | goto next; | |
829 | } | |
830 | } | |
831 | rcu_read_unlock(); | |
832 | } | |
79aeaccd | 833 | } |
5b4c4d36 | 834 | |
c27a02cd YP |
835 | /* |
836 | * Packet is OK - process it. | |
837 | */ | |
838 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 839 | length -= ring->fcs_del; |
c27a02cd YP |
840 | ring->bytes += length; |
841 | ring->packets++; | |
837052d0 OG |
842 | l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && |
843 | (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); | |
c27a02cd | 844 | |
c8c64cff | 845 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
f8c6455b SM |
846 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | |
847 | MLX4_CQE_STATUS_UDP)) { | |
848 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && | |
849 | cqe->checksum == cpu_to_be16(0xffff)) { | |
850 | ip_summed = CHECKSUM_UNNECESSARY; | |
851 | ring->csum_ok++; | |
852 | } else { | |
853 | ip_summed = CHECKSUM_NONE; | |
854 | ring->csum_none++; | |
855 | } | |
c27a02cd | 856 | } else { |
f8c6455b SM |
857 | if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && |
858 | (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | | |
859 | MLX4_CQE_STATUS_IPV6))) { | |
860 | ip_summed = CHECKSUM_COMPLETE; | |
861 | ring->csum_complete++; | |
862 | } else { | |
863 | ip_summed = CHECKSUM_NONE; | |
864 | ring->csum_none++; | |
865 | } | |
c27a02cd YP |
866 | } |
867 | } else { | |
868 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 869 | ring->csum_none++; |
c27a02cd YP |
870 | } |
871 | ||
dd65beac SM |
872 | /* This packet is eligible for GRO if it is: |
873 | * - DIX Ethernet (type interpretation) | |
874 | * - TCP/IP (v4) | |
875 | * - without IP options | |
876 | * - not an IP fragment | |
877 | * - no LLS polling in progress | |
878 | */ | |
879 | if (!mlx4_en_cq_busy_polling(cq) && | |
880 | (dev->features & NETIF_F_GRO)) { | |
881 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); | |
882 | if (!gro_skb) | |
883 | goto next; | |
884 | ||
885 | nr = mlx4_en_complete_rx_desc(priv, | |
886 | rx_desc, frags, gro_skb, | |
887 | length); | |
888 | if (!nr) | |
889 | goto next; | |
890 | ||
f8c6455b SM |
891 | if (ip_summed == CHECKSUM_COMPLETE) { |
892 | void *va = skb_frag_address(skb_shinfo(gro_skb)->frags); | |
79a25852 IS |
893 | if (check_csum(cqe, gro_skb, va, |
894 | dev->features)) { | |
f8c6455b SM |
895 | ip_summed = CHECKSUM_NONE; |
896 | ring->csum_none++; | |
897 | ring->csum_complete--; | |
898 | } | |
899 | } | |
900 | ||
dd65beac SM |
901 | skb_shinfo(gro_skb)->nr_frags = nr; |
902 | gro_skb->len = length; | |
903 | gro_skb->data_len = length; | |
904 | gro_skb->ip_summed = ip_summed; | |
905 | ||
906 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) | |
c58942f2 OG |
907 | gro_skb->csum_level = 1; |
908 | ||
dd65beac SM |
909 | if ((cqe->vlan_my_qpn & |
910 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) && | |
911 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
912 | u16 vid = be16_to_cpu(cqe->sl_vid); | |
913 | ||
914 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); | |
915 | } | |
916 | ||
917 | if (dev->features & NETIF_F_RXHASH) | |
918 | skb_set_hash(gro_skb, | |
919 | be32_to_cpu(cqe->immed_rss_invalid), | |
920 | PKT_HASH_TYPE_L3); | |
921 | ||
922 | skb_record_rx_queue(gro_skb, cq->ring); | |
923 | skb_mark_napi_id(gro_skb, &cq->napi); | |
924 | ||
925 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { | |
926 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
927 | mlx4_en_fill_hwtstamps(mdev, | |
928 | skb_hwtstamps(gro_skb), | |
929 | timestamp); | |
930 | } | |
931 | ||
932 | napi_gro_frags(&cq->napi); | |
933 | goto next; | |
934 | } | |
935 | ||
936 | /* GRO not possible, complete processing here */ | |
4cce66cd | 937 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
c27a02cd YP |
938 | if (!skb) { |
939 | priv->stats.rx_dropped++; | |
940 | goto next; | |
941 | } | |
942 | ||
e7c1c2c4 YP |
943 | if (unlikely(priv->validate_loopback)) { |
944 | validate_loopback(priv, skb); | |
945 | goto next; | |
946 | } | |
947 | ||
f8c6455b | 948 | if (ip_summed == CHECKSUM_COMPLETE) { |
79a25852 | 949 | if (check_csum(cqe, skb, skb->data, dev->features)) { |
f8c6455b SM |
950 | ip_summed = CHECKSUM_NONE; |
951 | ring->csum_complete--; | |
952 | ring->csum_none++; | |
953 | } | |
954 | } | |
955 | ||
c27a02cd YP |
956 | skb->ip_summed = ip_summed; |
957 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 958 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 959 | |
9ca8600e TH |
960 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) |
961 | skb->csum_level = 1; | |
837052d0 | 962 | |
ad86107f | 963 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
964 | skb_set_hash(skb, |
965 | be32_to_cpu(cqe->immed_rss_invalid), | |
966 | PKT_HASH_TYPE_L3); | |
ad86107f | 967 | |
ec693d47 AV |
968 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
969 | MLX4_CQE_VLAN_PRESENT_MASK) && | |
970 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) | |
86a9bad3 | 971 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
f1b553fb | 972 | |
ec693d47 AV |
973 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
974 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
975 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
976 | timestamp); | |
977 | } | |
978 | ||
8b80cda5 | 979 | skb_mark_napi_id(skb, &cq->napi); |
9e77a2b8 | 980 | |
e6a76758 ED |
981 | if (!mlx4_en_cq_busy_polling(cq)) |
982 | napi_gro_receive(&cq->napi, skb); | |
983 | else | |
984 | netif_receive_skb(skb); | |
c27a02cd | 985 | |
c27a02cd | 986 | next: |
4cce66cd TLSC |
987 | for (nr = 0; nr < priv->num_frags; nr++) |
988 | mlx4_en_free_frag(priv, frags, nr); | |
989 | ||
c27a02cd YP |
990 | ++cq->mcq.cons_index; |
991 | index = (cq->mcq.cons_index) & ring->size_mask; | |
b1b6b4da | 992 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
f1d29a3f | 993 | if (++polled == budget) |
c27a02cd | 994 | goto out; |
c27a02cd YP |
995 | } |
996 | ||
c27a02cd YP |
997 | out: |
998 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
999 | mlx4_cq_set_ci(&cq->mcq); | |
1000 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
1001 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 1002 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
1003 | mlx4_en_update_rx_prod_db(ring); |
1004 | return polled; | |
1005 | } | |
1006 | ||
1007 | ||
1008 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
1009 | { | |
1010 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
1011 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
1012 | ||
477b35b4 ED |
1013 | if (likely(priv->port_up)) |
1014 | napi_schedule_irqoff(&cq->napi); | |
c27a02cd YP |
1015 | else |
1016 | mlx4_en_arm_cq(priv, cq); | |
1017 | } | |
1018 | ||
1019 | /* Rx CQ polling - called by NAPI */ | |
1020 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
1021 | { | |
1022 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
1023 | struct net_device *dev = cq->dev; | |
1024 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1025 | int done; | |
1026 | ||
9e77a2b8 AV |
1027 | if (!mlx4_en_cq_lock_napi(cq)) |
1028 | return budget; | |
1029 | ||
c27a02cd YP |
1030 | done = mlx4_en_process_rx_cq(dev, cq, budget); |
1031 | ||
9e77a2b8 AV |
1032 | mlx4_en_cq_unlock_napi(cq); |
1033 | ||
c27a02cd | 1034 | /* If we used up all the quota - we're probably not done yet... */ |
2eacc23c | 1035 | if (done == budget) { |
35f6f453 AV |
1036 | int cpu_curr; |
1037 | const struct cpumask *aff; | |
1038 | ||
c27a02cd | 1039 | INC_PERF_COUNTER(priv->pstats.napi_quota); |
35f6f453 AV |
1040 | |
1041 | cpu_curr = smp_processor_id(); | |
1042 | aff = irq_desc_get_irq_data(cq->irq_desc)->affinity; | |
1043 | ||
2e1af7d7 ED |
1044 | if (likely(cpumask_test_cpu(cpu_curr, aff))) |
1045 | return budget; | |
1046 | ||
1047 | /* Current cpu is not according to smp_irq_affinity - | |
1048 | * probably affinity changed. need to stop this NAPI | |
1049 | * poll, and restart it on the right CPU | |
1050 | */ | |
1051 | done = 0; | |
c27a02cd | 1052 | } |
1a288172 ED |
1053 | /* Done for now */ |
1054 | napi_complete_done(napi, done); | |
1055 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
1056 | return done; |
1057 | } | |
1058 | ||
51151a16 | 1059 | static const int frag_sizes[] = { |
c27a02cd YP |
1060 | FRAG_SZ0, |
1061 | FRAG_SZ1, | |
1062 | FRAG_SZ2, | |
1063 | FRAG_SZ3 | |
1064 | }; | |
1065 | ||
1066 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
1067 | { | |
1068 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
d5b8dff0 | 1069 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN; |
c27a02cd YP |
1070 | int buf_size = 0; |
1071 | int i = 0; | |
1072 | ||
1073 | while (buf_size < eff_mtu) { | |
1074 | priv->frag_info[i].frag_size = | |
1075 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
1076 | frag_sizes[i] : eff_mtu - buf_size; | |
1077 | priv->frag_info[i].frag_prefix_size = buf_size; | |
e8e7f018 IS |
1078 | priv->frag_info[i].frag_stride = |
1079 | ALIGN(priv->frag_info[i].frag_size, | |
1080 | SMP_CACHE_BYTES); | |
c27a02cd YP |
1081 | buf_size += priv->frag_info[i].frag_size; |
1082 | i++; | |
1083 | } | |
1084 | ||
1085 | priv->num_frags = i; | |
1086 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 1087 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 1088 | |
1a91de28 JP |
1089 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", |
1090 | eff_mtu, priv->num_frags); | |
c27a02cd | 1091 | for (i = 0; i < priv->num_frags; i++) { |
51151a16 | 1092 | en_err(priv, |
5f6e9800 | 1093 | " frag:%d - size:%d prefix:%d stride:%d\n", |
51151a16 ED |
1094 | i, |
1095 | priv->frag_info[i].frag_size, | |
1096 | priv->frag_info[i].frag_prefix_size, | |
51151a16 | 1097 | priv->frag_info[i].frag_stride); |
c27a02cd YP |
1098 | } |
1099 | } | |
1100 | ||
1101 | /* RSS related functions */ | |
1102 | ||
9f519f68 YP |
1103 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
1104 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
1105 | enum mlx4_qp_state *state, |
1106 | struct mlx4_qp *qp) | |
1107 | { | |
1108 | struct mlx4_en_dev *mdev = priv->mdev; | |
1109 | struct mlx4_qp_context *context; | |
1110 | int err = 0; | |
1111 | ||
14f8dc49 JP |
1112 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
1113 | if (!context) | |
c27a02cd | 1114 | return -ENOMEM; |
c27a02cd | 1115 | |
40f2287b | 1116 | err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); |
c27a02cd | 1117 | if (err) { |
453a6082 | 1118 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 1119 | goto out; |
c27a02cd YP |
1120 | } |
1121 | qp->event = mlx4_en_sqp_event; | |
1122 | ||
1123 | memset(context, 0, sizeof *context); | |
00d7d7bc | 1124 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 1125 | qpn, ring->cqn, -1, context); |
9f519f68 | 1126 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 1127 | |
f3a9d1f2 | 1128 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 1129 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 1130 | context->param3 |= cpu_to_be32(1 << 29); |
f0df3503 MM |
1131 | if (priv->dev->features & NETIF_F_RXFCS) |
1132 | ring->fcs_del = 0; | |
1133 | else | |
1134 | ring->fcs_del = ETH_FCS_LEN; | |
4a5f4dd8 YP |
1135 | } else |
1136 | ring->fcs_del = 0; | |
f3a9d1f2 | 1137 | |
9f519f68 | 1138 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
1139 | if (err) { |
1140 | mlx4_qp_remove(mdev->dev, qp); | |
1141 | mlx4_qp_free(mdev->dev, qp); | |
1142 | } | |
9f519f68 | 1143 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
1144 | out: |
1145 | kfree(context); | |
1146 | return err; | |
1147 | } | |
1148 | ||
cabdc8ee HHZ |
1149 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
1150 | { | |
1151 | int err; | |
1152 | u32 qpn; | |
1153 | ||
d57febe1 MB |
1154 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, |
1155 | MLX4_RESERVE_A0_QP); | |
cabdc8ee HHZ |
1156 | if (err) { |
1157 | en_err(priv, "Failed reserving drop qpn\n"); | |
1158 | return err; | |
1159 | } | |
40f2287b | 1160 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); |
cabdc8ee HHZ |
1161 | if (err) { |
1162 | en_err(priv, "Failed allocating drop qp\n"); | |
1163 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1164 | return err; | |
1165 | } | |
1166 | ||
1167 | return 0; | |
1168 | } | |
1169 | ||
1170 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
1171 | { | |
1172 | u32 qpn; | |
1173 | ||
1174 | qpn = priv->drop_qp.qpn; | |
1175 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
1176 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
1177 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1178 | } | |
1179 | ||
c27a02cd YP |
1180 | /* Allocate rx qp's and configure them according to rss map */ |
1181 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
1182 | { | |
1183 | struct mlx4_en_dev *mdev = priv->mdev; | |
1184 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1185 | struct mlx4_qp_context context; | |
876f6e67 | 1186 | struct mlx4_rss_context *rss_context; |
93d3e367 | 1187 | int rss_rings; |
c27a02cd | 1188 | void *ptr; |
876f6e67 | 1189 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 1190 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 1191 | int i, qpn; |
c27a02cd YP |
1192 | int err = 0; |
1193 | int good_qps = 0; | |
1194 | ||
453a6082 | 1195 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
1196 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
1197 | priv->rx_ring_num, | |
ddae0349 | 1198 | &rss_map->base_qpn, 0); |
c27a02cd | 1199 | if (err) { |
b6b912e0 | 1200 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
1201 | return err; |
1202 | } | |
1203 | ||
b6b912e0 | 1204 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 1205 | qpn = rss_map->base_qpn + i; |
41d942d5 | 1206 | err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], |
c27a02cd YP |
1207 | &rss_map->state[i], |
1208 | &rss_map->qps[i]); | |
1209 | if (err) | |
1210 | goto rss_err; | |
1211 | ||
1212 | ++good_qps; | |
1213 | } | |
1214 | ||
1215 | /* Configure RSS indirection qp */ | |
40f2287b | 1216 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); |
c27a02cd | 1217 | if (err) { |
453a6082 | 1218 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1219 | goto rss_err; |
c27a02cd YP |
1220 | } |
1221 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1222 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
41d942d5 | 1223 | priv->rx_ring[0]->cqn, -1, &context); |
c27a02cd | 1224 | |
93d3e367 YP |
1225 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1226 | rss_rings = priv->rx_ring_num; | |
1227 | else | |
1228 | rss_rings = priv->prof->rss_rings; | |
1229 | ||
876f6e67 OG |
1230 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1231 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1232 | rss_context = ptr; |
93d3e367 | 1233 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1234 | (rss_map->base_qpn)); |
89efea25 | 1235 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1236 | if (priv->mdev->profile.udp_rss) { |
1237 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1238 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1239 | } | |
837052d0 OG |
1240 | |
1241 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { | |
1242 | en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); | |
1243 | rss_mask |= MLX4_RSS_BY_INNER_HEADERS; | |
1244 | } | |
1245 | ||
0533943c | 1246 | rss_context->flags = rss_mask; |
876f6e67 | 1247 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
947cbb0a EP |
1248 | if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { |
1249 | rss_context->hash_fn = MLX4_RSS_HASH_XOR; | |
1250 | } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { | |
1251 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; | |
1252 | memcpy(rss_context->rss_key, priv->rss_key, | |
1253 | MLX4_EN_RSS_KEY_SIZE); | |
1254 | netdev_rss_key_fill(rss_context->rss_key, | |
1255 | MLX4_EN_RSS_KEY_SIZE); | |
1256 | } else { | |
1257 | en_err(priv, "Unknown RSS hash function requested\n"); | |
1258 | err = -EINVAL; | |
1259 | goto indir_err; | |
1260 | } | |
c27a02cd YP |
1261 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, |
1262 | &rss_map->indir_qp, &rss_map->indir_state); | |
1263 | if (err) | |
1264 | goto indir_err; | |
1265 | ||
1266 | return 0; | |
1267 | ||
1268 | indir_err: | |
1269 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1270 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1271 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1272 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1273 | rss_err: |
1274 | for (i = 0; i < good_qps; i++) { | |
1275 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1276 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1277 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1278 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1279 | } | |
b6b912e0 | 1280 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1281 | return err; |
1282 | } | |
1283 | ||
1284 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1285 | { | |
1286 | struct mlx4_en_dev *mdev = priv->mdev; | |
1287 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1288 | int i; | |
1289 | ||
1290 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1291 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1292 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1293 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1294 | |
b6b912e0 | 1295 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1296 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1297 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1298 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1299 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1300 | } | |
b6b912e0 | 1301 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1302 | } |