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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
47a38e15 | 35 | #include <linux/bpf.h> |
c27a02cd | 36 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c27a02cd YP |
38 | #include <linux/mlx4/qp.h> |
39 | #include <linux/skbuff.h> | |
b67bfe0d | 40 | #include <linux/rculist.h> |
c27a02cd YP |
41 | #include <linux/if_ether.h> |
42 | #include <linux/if_vlan.h> | |
43 | #include <linux/vmalloc.h> | |
35f6f453 | 44 | #include <linux/irq.h> |
c27a02cd | 45 | |
f8c6455b SM |
46 | #if IS_ENABLED(CONFIG_IPV6) |
47 | #include <net/ip6_checksum.h> | |
48 | #endif | |
49 | ||
c27a02cd YP |
50 | #include "mlx4_en.h" |
51 | ||
51151a16 ED |
52 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
53 | struct mlx4_en_rx_alloc *page_alloc, | |
54 | const struct mlx4_en_frag_info *frag_info, | |
55 | gfp_t _gfp) | |
56 | { | |
57 | int order; | |
58 | struct page *page; | |
59 | dma_addr_t dma; | |
60 | ||
d576acf0 | 61 | for (order = frag_info->order; ;) { |
51151a16 ED |
62 | gfp_t gfp = _gfp; |
63 | ||
64 | if (order) | |
04aeb56a | 65 | gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC; |
51151a16 ED |
66 | page = alloc_pages(gfp, order); |
67 | if (likely(page)) | |
68 | break; | |
69 | if (--order < 0 || | |
70 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
71 | return -ENOMEM; | |
72 | } | |
73 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
d576acf0 | 74 | frag_info->dma_dir); |
de3d6fa8 | 75 | if (unlikely(dma_mapping_error(priv->ddev, dma))) { |
51151a16 ED |
76 | put_page(page); |
77 | return -ENOMEM; | |
78 | } | |
70fbe079 | 79 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
80 | page_alloc->page = page; |
81 | page_alloc->dma = dma; | |
5f6e9800 | 82 | page_alloc->page_offset = 0; |
51151a16 | 83 | /* Not doing get_page() for each frag is a big win |
98226208 | 84 | * on asymetric workloads. Note we can not use atomic_set(). |
51151a16 | 85 | */ |
fe896d18 | 86 | page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1); |
51151a16 ED |
87 | return 0; |
88 | } | |
89 | ||
4cce66cd TLSC |
90 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
91 | struct mlx4_en_rx_desc *rx_desc, | |
92 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
93 | struct mlx4_en_rx_alloc *ring_alloc, |
94 | gfp_t gfp) | |
c27a02cd | 95 | { |
4cce66cd | 96 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 97 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd | 98 | struct page *page; |
4cce66cd | 99 | int i; |
c27a02cd | 100 | |
4cce66cd TLSC |
101 | for (i = 0; i < priv->num_frags; i++) { |
102 | frag_info = &priv->frag_info[i]; | |
51151a16 | 103 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
104 | page_alloc[i].page_offset += frag_info->frag_stride; |
105 | ||
106 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
107 | ring_alloc[i].page_size) | |
51151a16 | 108 | continue; |
70fbe079 | 109 | |
de3d6fa8 TT |
110 | if (unlikely(mlx4_alloc_pages(priv, &page_alloc[i], |
111 | frag_info, gfp))) | |
51151a16 | 112 | goto out; |
4cce66cd | 113 | } |
c27a02cd | 114 | |
4cce66cd TLSC |
115 | for (i = 0; i < priv->num_frags; i++) { |
116 | frags[i] = ring_alloc[i]; | |
ea3349a0 MKL |
117 | frags[i].page_offset += priv->frag_info[i].rx_headroom; |
118 | rx_desc->data[i].addr = cpu_to_be64(frags[i].dma + | |
119 | frags[i].page_offset); | |
4cce66cd | 120 | ring_alloc[i] = page_alloc[i]; |
c27a02cd | 121 | } |
4cce66cd | 122 | |
c27a02cd | 123 | return 0; |
4cce66cd | 124 | |
4cce66cd TLSC |
125 | out: |
126 | while (i--) { | |
51151a16 | 127 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 128 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
d576acf0 BB |
129 | page_alloc[i].page_size, |
130 | priv->frag_info[i].dma_dir); | |
51151a16 | 131 | page = page_alloc[i].page; |
851b10d6 KK |
132 | /* Revert changes done by mlx4_alloc_pages */ |
133 | page_ref_sub(page, page_alloc[i].page_size / | |
134 | priv->frag_info[i].frag_stride - 1); | |
51151a16 ED |
135 | put_page(page); |
136 | } | |
4cce66cd TLSC |
137 | } |
138 | return -ENOMEM; | |
139 | } | |
140 | ||
141 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
142 | struct mlx4_en_rx_alloc *frags, | |
143 | int i) | |
144 | { | |
51151a16 | 145 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
021f1107 | 146 | u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; |
4cce66cd | 147 | |
021f1107 AV |
148 | |
149 | if (next_frag_end > frags[i].page_size) | |
70fbe079 | 150 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, |
d576acf0 | 151 | frag_info->dma_dir); |
51151a16 | 152 | |
4cce66cd TLSC |
153 | if (frags[i].page) |
154 | put_page(frags[i].page); | |
c27a02cd YP |
155 | } |
156 | ||
157 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
158 | struct mlx4_en_rx_ring *ring) | |
159 | { | |
c27a02cd | 160 | int i; |
51151a16 | 161 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
162 | |
163 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 164 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 165 | |
51151a16 | 166 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
1ab25f86 | 167 | frag_info, GFP_KERNEL | __GFP_COLD)) |
4cce66cd | 168 | goto out; |
b110d2ce IS |
169 | |
170 | en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n", | |
171 | i, ring->page_alloc[i].page_size, | |
fe896d18 | 172 | page_ref_count(ring->page_alloc[i].page)); |
c27a02cd YP |
173 | } |
174 | return 0; | |
175 | ||
176 | out: | |
177 | while (i--) { | |
51151a16 ED |
178 | struct page *page; |
179 | ||
c27a02cd | 180 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 181 | dma_unmap_page(priv->ddev, page_alloc->dma, |
d576acf0 BB |
182 | page_alloc->page_size, |
183 | priv->frag_info[i].dma_dir); | |
51151a16 | 184 | page = page_alloc->page; |
851b10d6 KK |
185 | /* Revert changes done by mlx4_alloc_pages */ |
186 | page_ref_sub(page, page_alloc->page_size / | |
187 | priv->frag_info[i].frag_stride - 1); | |
51151a16 | 188 | put_page(page); |
c27a02cd YP |
189 | page_alloc->page = NULL; |
190 | } | |
191 | return -ENOMEM; | |
192 | } | |
193 | ||
194 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
195 | struct mlx4_en_rx_ring *ring) | |
196 | { | |
197 | struct mlx4_en_rx_alloc *page_alloc; | |
198 | int i; | |
199 | ||
200 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
201 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
202 | ||
c27a02cd | 203 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
204 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
205 | i, page_count(page_alloc->page)); | |
c27a02cd | 206 | |
4cce66cd | 207 | dma_unmap_page(priv->ddev, page_alloc->dma, |
d576acf0 | 208 | page_alloc->page_size, frag_info->dma_dir); |
70fbe079 AV |
209 | while (page_alloc->page_offset + frag_info->frag_stride < |
210 | page_alloc->page_size) { | |
51151a16 | 211 | put_page(page_alloc->page); |
70fbe079 | 212 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 213 | } |
c27a02cd YP |
214 | page_alloc->page = NULL; |
215 | } | |
216 | } | |
217 | ||
c27a02cd YP |
218 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
219 | struct mlx4_en_rx_ring *ring, int index) | |
220 | { | |
221 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
222 | int possible_frags; |
223 | int i; | |
224 | ||
c27a02cd YP |
225 | /* Set size and memtype fields */ |
226 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
227 | rx_desc->data[i].byte_count = |
228 | cpu_to_be32(priv->frag_info[i].frag_size); | |
229 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
230 | } | |
231 | ||
232 | /* If the number of used fragments does not fill up the ring stride, | |
233 | * remaining (unused) fragments must be padded with null address/size | |
234 | * and a special memory key */ | |
235 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
236 | for (i = priv->num_frags; i < possible_frags; i++) { | |
237 | rx_desc->data[i].byte_count = 0; | |
238 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
239 | rx_desc->data[i].addr = 0; | |
240 | } | |
241 | } | |
242 | ||
c27a02cd | 243 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
244 | struct mlx4_en_rx_ring *ring, int index, |
245 | gfp_t gfp) | |
c27a02cd YP |
246 | { |
247 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
248 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
249 | (index << priv->log_rx_info); | |
c27a02cd | 250 | |
d576acf0 BB |
251 | if (ring->page_cache.index > 0) { |
252 | frags[0] = ring->page_cache.buf[--ring->page_cache.index]; | |
ea3349a0 MKL |
253 | rx_desc->data[0].addr = cpu_to_be64(frags[0].dma + |
254 | frags[0].page_offset); | |
d576acf0 BB |
255 | return 0; |
256 | } | |
257 | ||
51151a16 | 258 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
259 | } |
260 | ||
07841f9d IS |
261 | static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring) |
262 | { | |
07841f9d IS |
263 | return ring->prod == ring->cons; |
264 | } | |
265 | ||
c27a02cd YP |
266 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) |
267 | { | |
268 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
269 | } | |
270 | ||
38aab07c YP |
271 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
272 | struct mlx4_en_rx_ring *ring, | |
273 | int index) | |
274 | { | |
4cce66cd | 275 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
276 | int nr; |
277 | ||
4cce66cd | 278 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 279 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 280 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 281 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
282 | } |
283 | } | |
284 | ||
c27a02cd YP |
285 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
286 | { | |
c27a02cd YP |
287 | struct mlx4_en_rx_ring *ring; |
288 | int ring_ind; | |
289 | int buf_ind; | |
38aab07c | 290 | int new_size; |
c27a02cd YP |
291 | |
292 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
293 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 294 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
295 | |
296 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 | 297 | ring->actual_size, |
1ab25f86 | 298 | GFP_KERNEL | __GFP_COLD)) { |
c27a02cd | 299 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
1a91de28 | 300 | en_err(priv, "Failed to allocate enough rx buffers\n"); |
c27a02cd YP |
301 | return -ENOMEM; |
302 | } else { | |
38aab07c | 303 | new_size = rounddown_pow_of_two(ring->actual_size); |
1a91de28 | 304 | en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", |
453a6082 | 305 | ring->actual_size, new_size); |
38aab07c | 306 | goto reduce_rings; |
c27a02cd YP |
307 | } |
308 | } | |
309 | ring->actual_size++; | |
310 | ring->prod++; | |
311 | } | |
312 | } | |
38aab07c YP |
313 | return 0; |
314 | ||
315 | reduce_rings: | |
316 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 317 | ring = priv->rx_ring[ring_ind]; |
38aab07c YP |
318 | while (ring->actual_size > new_size) { |
319 | ring->actual_size--; | |
320 | ring->prod--; | |
321 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
322 | } | |
38aab07c YP |
323 | } |
324 | ||
c27a02cd YP |
325 | return 0; |
326 | } | |
327 | ||
c27a02cd YP |
328 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
329 | struct mlx4_en_rx_ring *ring) | |
330 | { | |
c27a02cd | 331 | int index; |
c27a02cd | 332 | |
453a6082 YP |
333 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
334 | ring->cons, ring->prod); | |
c27a02cd YP |
335 | |
336 | /* Unmap and free Rx buffers */ | |
07841f9d | 337 | while (!mlx4_en_is_ring_empty(ring)) { |
c27a02cd | 338 | index = ring->cons & ring->size_mask; |
453a6082 | 339 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 340 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
341 | ++ring->cons; |
342 | } | |
343 | } | |
344 | ||
02512482 IS |
345 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) |
346 | { | |
347 | int i; | |
348 | int num_of_eqs; | |
bb2146bc | 349 | int num_rx_rings; |
02512482 IS |
350 | struct mlx4_dev *dev = mdev->dev; |
351 | ||
352 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
c66fa19c MB |
353 | num_of_eqs = max_t(int, MIN_RX_RINGS, |
354 | min_t(int, | |
355 | mlx4_get_eqs_per_port(mdev->dev, i), | |
356 | DEF_RX_RINGS)); | |
02512482 | 357 | |
ea1c1af1 AV |
358 | num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : |
359 | min_t(int, num_of_eqs, | |
360 | netif_get_num_default_rss_queues()); | |
02512482 | 361 | mdev->profile.prof[i].rx_ring_num = |
bb2146bc | 362 | rounddown_pow_of_two(num_rx_rings); |
02512482 IS |
363 | } |
364 | } | |
365 | ||
c27a02cd | 366 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 367 | struct mlx4_en_rx_ring **pring, |
163561a4 | 368 | u32 size, u16 stride, int node) |
c27a02cd YP |
369 | { |
370 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 371 | struct mlx4_en_rx_ring *ring; |
4cce66cd | 372 | int err = -ENOMEM; |
c27a02cd YP |
373 | int tmp; |
374 | ||
163561a4 | 375 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 376 | if (!ring) { |
163561a4 EE |
377 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
378 | if (!ring) { | |
379 | en_err(priv, "Failed to allocate RX ring structure\n"); | |
380 | return -ENOMEM; | |
381 | } | |
41d942d5 EE |
382 | } |
383 | ||
c27a02cd YP |
384 | ring->prod = 0; |
385 | ring->cons = 0; | |
386 | ring->size = size; | |
387 | ring->size_mask = size - 1; | |
388 | ring->stride = stride; | |
389 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 390 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
391 | |
392 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 393 | sizeof(struct mlx4_en_rx_alloc)); |
163561a4 | 394 | ring->rx_info = vmalloc_node(tmp, node); |
41d942d5 | 395 | if (!ring->rx_info) { |
163561a4 EE |
396 | ring->rx_info = vmalloc(tmp); |
397 | if (!ring->rx_info) { | |
398 | err = -ENOMEM; | |
399 | goto err_ring; | |
400 | } | |
41d942d5 | 401 | } |
e404decb | 402 | |
453a6082 | 403 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
404 | ring->rx_info, tmp); |
405 | ||
163561a4 | 406 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 407 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
73898db0 | 408 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); |
872bf2fb | 409 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 410 | if (err) |
41d942d5 | 411 | goto err_info; |
c27a02cd | 412 | |
c27a02cd YP |
413 | ring->buf = ring->wqres.buf.direct.buf; |
414 | ||
ec693d47 AV |
415 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
416 | ||
41d942d5 | 417 | *pring = ring; |
c27a02cd YP |
418 | return 0; |
419 | ||
41d942d5 | 420 | err_info: |
c27a02cd YP |
421 | vfree(ring->rx_info); |
422 | ring->rx_info = NULL; | |
41d942d5 EE |
423 | err_ring: |
424 | kfree(ring); | |
425 | *pring = NULL; | |
426 | ||
c27a02cd YP |
427 | return err; |
428 | } | |
429 | ||
430 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
431 | { | |
c27a02cd YP |
432 | struct mlx4_en_rx_ring *ring; |
433 | int i; | |
434 | int ring_ind; | |
435 | int err; | |
436 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
437 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
438 | |
439 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 440 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
441 | |
442 | ring->prod = 0; | |
443 | ring->cons = 0; | |
444 | ring->actual_size = 0; | |
41d942d5 | 445 | ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
c27a02cd YP |
446 | |
447 | ring->stride = stride; | |
6496bbf0 EE |
448 | if (ring->stride <= TXBB_SIZE) { |
449 | /* Stamp first unused send wqe */ | |
450 | __be32 *ptr = (__be32 *)ring->buf; | |
451 | __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT); | |
452 | *ptr = stamp; | |
453 | /* Move pointer to start of rx section */ | |
9f519f68 | 454 | ring->buf += TXBB_SIZE; |
6496bbf0 | 455 | } |
9f519f68 | 456 | |
c27a02cd YP |
457 | ring->log_stride = ffs(ring->stride) - 1; |
458 | ring->buf_size = ring->size * ring->stride; | |
459 | ||
460 | memset(ring->buf, 0, ring->buf_size); | |
461 | mlx4_en_update_rx_prod_db(ring); | |
462 | ||
4cce66cd | 463 | /* Initialize all descriptors */ |
c27a02cd YP |
464 | for (i = 0; i < ring->size; i++) |
465 | mlx4_en_init_rx_desc(priv, ring, i); | |
466 | ||
467 | /* Initialize page allocators */ | |
468 | err = mlx4_en_init_allocator(priv, ring); | |
469 | if (err) { | |
453a6082 | 470 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
471 | if (ring->stride <= TXBB_SIZE) |
472 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
473 | ring_ind--; |
474 | goto err_allocator; | |
c27a02cd | 475 | } |
c27a02cd | 476 | } |
b58515be IM |
477 | err = mlx4_en_fill_rx_buffers(priv); |
478 | if (err) | |
c27a02cd YP |
479 | goto err_buffers; |
480 | ||
481 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 482 | ring = priv->rx_ring[ring_ind]; |
c27a02cd | 483 | |
00d7d7bc | 484 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 485 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
486 | } |
487 | ||
488 | return 0; | |
489 | ||
c27a02cd YP |
490 | err_buffers: |
491 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
41d942d5 | 492 | mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); |
c27a02cd YP |
493 | |
494 | ring_ind = priv->rx_ring_num - 1; | |
495 | err_allocator: | |
496 | while (ring_ind >= 0) { | |
41d942d5 EE |
497 | if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) |
498 | priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; | |
499 | mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); | |
c27a02cd YP |
500 | ring_ind--; |
501 | } | |
502 | return err; | |
503 | } | |
504 | ||
07841f9d IS |
505 | /* We recover from out of memory by scheduling our napi poll |
506 | * function (mlx4_en_process_cq), which tries to allocate | |
507 | * all missing RX buffers (call to mlx4_en_refill_rx_buffers). | |
508 | */ | |
509 | void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) | |
510 | { | |
511 | int ring; | |
512 | ||
513 | if (!priv->port_up) | |
514 | return; | |
515 | ||
516 | for (ring = 0; ring < priv->rx_ring_num; ring++) { | |
517 | if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) | |
518 | napi_reschedule(&priv->rx_cq[ring]->napi); | |
519 | } | |
520 | } | |
521 | ||
d576acf0 BB |
522 | /* When the rx ring is running in page-per-packet mode, a released frame can go |
523 | * directly into a small cache, to avoid unmapping or touching the page | |
524 | * allocator. In bpf prog performance scenarios, buffers are either forwarded | |
525 | * or dropped, never converted to skbs, so every page can come directly from | |
526 | * this cache when it is sized to be a multiple of the napi budget. | |
527 | */ | |
528 | bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, | |
529 | struct mlx4_en_rx_alloc *frame) | |
530 | { | |
531 | struct mlx4_en_page_cache *cache = &ring->page_cache; | |
532 | ||
533 | if (cache->index >= MLX4_EN_CACHE_SIZE) | |
534 | return false; | |
535 | ||
536 | cache->buf[cache->index++] = *frame; | |
537 | return true; | |
538 | } | |
539 | ||
c27a02cd | 540 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 EE |
541 | struct mlx4_en_rx_ring **pring, |
542 | u32 size, u16 stride) | |
c27a02cd YP |
543 | { |
544 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 545 | struct mlx4_en_rx_ring *ring = *pring; |
cb7386d3 | 546 | struct bpf_prog *old_prog; |
c27a02cd | 547 | |
326fe02d BB |
548 | old_prog = rcu_dereference_protected( |
549 | ring->xdp_prog, | |
550 | lockdep_is_held(&mdev->state_lock)); | |
cb7386d3 BB |
551 | if (old_prog) |
552 | bpf_prog_put(old_prog); | |
68355f71 | 553 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
554 | vfree(ring->rx_info); |
555 | ring->rx_info = NULL; | |
41d942d5 EE |
556 | kfree(ring); |
557 | *pring = NULL; | |
c27a02cd YP |
558 | } |
559 | ||
560 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
561 | struct mlx4_en_rx_ring *ring) | |
562 | { | |
d576acf0 BB |
563 | int i; |
564 | ||
565 | for (i = 0; i < ring->page_cache.index; i++) { | |
566 | struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i]; | |
567 | ||
568 | dma_unmap_page(priv->ddev, frame->dma, frame->page_size, | |
569 | priv->frag_info[0].dma_dir); | |
570 | put_page(frame->page); | |
571 | } | |
572 | ring->page_cache.index = 0; | |
c27a02cd | 573 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
574 | if (ring->stride <= TXBB_SIZE) |
575 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
576 | mlx4_en_destroy_allocator(priv, ring); |
577 | } | |
578 | ||
579 | ||
c27a02cd YP |
580 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
581 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 582 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 583 | struct sk_buff *skb, |
c27a02cd YP |
584 | int length) |
585 | { | |
90278c9f | 586 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
587 | struct mlx4_en_frag_info *frag_info; |
588 | int nr; | |
589 | dma_addr_t dma; | |
590 | ||
4cce66cd | 591 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
592 | for (nr = 0; nr < priv->num_frags; nr++) { |
593 | frag_info = &priv->frag_info[nr]; | |
594 | if (length <= frag_info->frag_prefix_size) | |
595 | break; | |
de3d6fa8 | 596 | if (unlikely(!frags[nr].page)) |
4cce66cd | 597 | goto fail; |
c27a02cd | 598 | |
c27a02cd | 599 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
600 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
601 | DMA_FROM_DEVICE); | |
c27a02cd | 602 | |
4cce66cd | 603 | /* Save page reference in skb */ |
4cce66cd TLSC |
604 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
605 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 606 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 607 | skb->truesize += frag_info->frag_stride; |
51151a16 | 608 | frags[nr].page = NULL; |
c27a02cd YP |
609 | } |
610 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 611 | if (nr > 0) |
9e903e08 ED |
612 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
613 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
614 | return nr; |
615 | ||
616 | fail: | |
c27a02cd YP |
617 | while (nr > 0) { |
618 | nr--; | |
311761c8 | 619 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
620 | } |
621 | return 0; | |
622 | } | |
623 | ||
624 | ||
625 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
626 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 627 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
628 | unsigned int length) |
629 | { | |
c27a02cd YP |
630 | struct sk_buff *skb; |
631 | void *va; | |
632 | int used_frags; | |
633 | dma_addr_t dma; | |
634 | ||
c056b734 | 635 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
de3d6fa8 | 636 | if (unlikely(!skb)) { |
453a6082 | 637 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
638 | return NULL; |
639 | } | |
c27a02cd YP |
640 | skb_reserve(skb, NET_IP_ALIGN); |
641 | skb->len = length; | |
c27a02cd YP |
642 | |
643 | /* Get pointer to first fragment so we could copy the headers into the | |
644 | * (linear part of the) skb */ | |
70fbe079 | 645 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
646 | |
647 | if (length <= SMALL_PACKET_SIZE) { | |
648 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 649 | * sync buffers for the copy */ |
c27a02cd | 650 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 651 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 652 | DMA_FROM_DEVICE); |
c27a02cd | 653 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
654 | skb->tail += length; |
655 | } else { | |
cfecec56 ED |
656 | unsigned int pull_len; |
657 | ||
c27a02cd | 658 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
659 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
660 | skb, length); | |
785a0982 YP |
661 | if (unlikely(!used_frags)) { |
662 | kfree_skb(skb); | |
663 | return NULL; | |
664 | } | |
c27a02cd YP |
665 | skb_shinfo(skb)->nr_frags = used_frags; |
666 | ||
cfecec56 | 667 | pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); |
c27a02cd | 668 | /* Copy headers into the skb linear buffer */ |
cfecec56 ED |
669 | memcpy(skb->data, va, pull_len); |
670 | skb->tail += pull_len; | |
c27a02cd YP |
671 | |
672 | /* Skip headers in first fragment */ | |
cfecec56 | 673 | skb_shinfo(skb)->frags[0].page_offset += pull_len; |
c27a02cd YP |
674 | |
675 | /* Adjust size of first fragment */ | |
cfecec56 ED |
676 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); |
677 | skb->data_len = length - pull_len; | |
c27a02cd YP |
678 | } |
679 | return skb; | |
680 | } | |
681 | ||
e7c1c2c4 YP |
682 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
683 | { | |
684 | int i; | |
685 | int offset = ETH_HLEN; | |
686 | ||
687 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
688 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
689 | goto out_loopback; | |
690 | } | |
691 | /* Loopback found */ | |
692 | priv->loopback_ok = 1; | |
693 | ||
694 | out_loopback: | |
695 | dev_kfree_skb_any(skb); | |
696 | } | |
c27a02cd | 697 | |
dad42c30 ED |
698 | static bool mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
699 | struct mlx4_en_rx_ring *ring) | |
4cce66cd | 700 | { |
dad42c30 | 701 | u32 missing = ring->actual_size - (ring->prod - ring->cons); |
4cce66cd | 702 | |
dad42c30 ED |
703 | /* Try to batch allocations, but not too much. */ |
704 | if (missing < 8) | |
705 | return false; | |
706 | do { | |
707 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
708 | ring->prod & ring->size_mask, | |
1ab25f86 | 709 | GFP_ATOMIC | __GFP_COLD)) |
4cce66cd TLSC |
710 | break; |
711 | ring->prod++; | |
dad42c30 ED |
712 | } while (--missing); |
713 | ||
714 | return true; | |
4cce66cd TLSC |
715 | } |
716 | ||
f8c6455b SM |
717 | /* When hardware doesn't strip the vlan, we need to calculate the checksum |
718 | * over it and add it to the hardware's checksum calculation | |
719 | */ | |
720 | static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, | |
721 | struct vlan_hdr *vlanh) | |
722 | { | |
723 | return csum_add(hw_checksum, *(__wsum *)vlanh); | |
724 | } | |
725 | ||
726 | /* Although the stack expects checksum which doesn't include the pseudo | |
727 | * header, the HW adds it. To address that, we are subtracting the pseudo | |
728 | * header checksum from the checksum value provided by the HW. | |
729 | */ | |
730 | static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, | |
731 | struct iphdr *iph) | |
732 | { | |
733 | __u16 length_for_csum = 0; | |
734 | __wsum csum_pseudo_header = 0; | |
735 | ||
736 | length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); | |
737 | csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, | |
738 | length_for_csum, iph->protocol, 0); | |
739 | skb->csum = csum_sub(hw_checksum, csum_pseudo_header); | |
740 | } | |
741 | ||
742 | #if IS_ENABLED(CONFIG_IPV6) | |
743 | /* In IPv6 packets, besides subtracting the pseudo header checksum, | |
744 | * we also compute/add the IP header checksum which | |
745 | * is not added by the HW. | |
746 | */ | |
747 | static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, | |
748 | struct ipv6hdr *ipv6h) | |
749 | { | |
750 | __wsum csum_pseudo_hdr = 0; | |
751 | ||
de3d6fa8 TT |
752 | if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT || |
753 | ipv6h->nexthdr == IPPROTO_HOPOPTS)) | |
f8c6455b | 754 | return -1; |
82d69203 | 755 | hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr)); |
f8c6455b SM |
756 | |
757 | csum_pseudo_hdr = csum_partial(&ipv6h->saddr, | |
758 | sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); | |
759 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); | |
760 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); | |
761 | ||
762 | skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); | |
763 | skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); | |
764 | return 0; | |
765 | } | |
766 | #endif | |
767 | static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, | |
79a25852 | 768 | netdev_features_t dev_features) |
f8c6455b SM |
769 | { |
770 | __wsum hw_checksum = 0; | |
771 | ||
772 | void *hdr = (u8 *)va + sizeof(struct ethhdr); | |
773 | ||
774 | hw_checksum = csum_unfold((__force __sum16)cqe->checksum); | |
775 | ||
e802f8e4 | 776 | if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) && |
79a25852 | 777 | !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { |
f8c6455b SM |
778 | hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); |
779 | hdr += sizeof(struct vlan_hdr); | |
780 | } | |
781 | ||
782 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) | |
783 | get_fixed_ipv4_csum(hw_checksum, skb, hdr); | |
784 | #if IS_ENABLED(CONFIG_IPV6) | |
785 | else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) | |
de3d6fa8 | 786 | if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr))) |
f8c6455b SM |
787 | return -1; |
788 | #endif | |
789 | return 0; | |
790 | } | |
791 | ||
c27a02cd YP |
792 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
793 | { | |
794 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 795 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd | 796 | struct mlx4_cqe *cqe; |
41d942d5 | 797 | struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; |
4cce66cd | 798 | struct mlx4_en_rx_alloc *frags; |
c27a02cd | 799 | struct mlx4_en_rx_desc *rx_desc; |
47a38e15 | 800 | struct bpf_prog *xdp_prog; |
9ecc2d86 | 801 | int doorbell_pending; |
c27a02cd YP |
802 | struct sk_buff *skb; |
803 | int index; | |
804 | int nr; | |
805 | unsigned int length; | |
806 | int polled = 0; | |
807 | int ip_summed; | |
08ff3235 | 808 | int factor = priv->cqe_factor; |
ec693d47 | 809 | u64 timestamp; |
837052d0 | 810 | bool l2_tunnel; |
c27a02cd | 811 | |
de3d6fa8 | 812 | if (unlikely(!priv->port_up)) |
c27a02cd YP |
813 | return 0; |
814 | ||
de3d6fa8 | 815 | if (unlikely(budget <= 0)) |
38be0a34 EB |
816 | return polled; |
817 | ||
326fe02d BB |
818 | /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */ |
819 | rcu_read_lock(); | |
820 | xdp_prog = rcu_dereference(ring->xdp_prog); | |
9ecc2d86 | 821 | doorbell_pending = 0; |
47a38e15 | 822 | |
c27a02cd YP |
823 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx |
824 | * descriptor offset can be deduced from the CQE index instead of | |
825 | * reading 'cqe->index' */ | |
826 | index = cq->mcq.cons_index & ring->size_mask; | |
b1b6b4da | 827 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
c27a02cd YP |
828 | |
829 | /* Process all completed CQEs */ | |
830 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
831 | cq->mcq.cons_index & cq->size)) { | |
832 | ||
4cce66cd | 833 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
834 | rx_desc = ring->buf + (index << ring->log_stride); |
835 | ||
836 | /* | |
837 | * make sure we read the CQE after we read the ownership bit | |
838 | */ | |
12b3375f | 839 | dma_rmb(); |
c27a02cd YP |
840 | |
841 | /* Drop packet on bad receive or bad checksum */ | |
842 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
843 | MLX4_CQE_OPCODE_ERROR)) { | |
1a91de28 JP |
844 | en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", |
845 | ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, | |
846 | ((struct mlx4_err_cqe *)cqe)->syndrome); | |
c27a02cd YP |
847 | goto next; |
848 | } | |
849 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 850 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
851 | goto next; |
852 | } | |
853 | ||
79aeaccd YB |
854 | /* Check if we need to drop the packet if SRIOV is not enabled |
855 | * and not performing the selftest or flb disabled | |
856 | */ | |
857 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
858 | struct ethhdr *ethh; | |
859 | dma_addr_t dma; | |
79aeaccd YB |
860 | /* Get pointer to first fragment since we haven't |
861 | * skb yet and cast it to ethhdr struct | |
862 | */ | |
863 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
864 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
865 | DMA_FROM_DEVICE); | |
866 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 867 | frags[0].page_offset); |
79aeaccd | 868 | |
c07cb4b0 YB |
869 | if (is_multicast_ether_addr(ethh->h_dest)) { |
870 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
871 | struct hlist_head *bucket; |
872 | unsigned int mac_hash; | |
873 | ||
874 | /* Drop the packet, since HW loopback-ed it */ | |
875 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
876 | bucket = &priv->mac_hash[mac_hash]; | |
b67bfe0d | 877 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 | 878 | if (ether_addr_equal_64bits(entry->mac, |
326fe02d | 879 | ethh->h_source)) |
c07cb4b0 | 880 | goto next; |
c07cb4b0 | 881 | } |
c07cb4b0 | 882 | } |
79aeaccd | 883 | } |
5b4c4d36 | 884 | |
c27a02cd YP |
885 | /* |
886 | * Packet is OK - process it. | |
887 | */ | |
888 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 889 | length -= ring->fcs_del; |
837052d0 OG |
890 | l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && |
891 | (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); | |
c27a02cd | 892 | |
47a38e15 BB |
893 | /* A bpf program gets first chance to drop the packet. It may |
894 | * read bytes but not past the end of the frag. | |
895 | */ | |
896 | if (xdp_prog) { | |
897 | struct xdp_buff xdp; | |
898 | dma_addr_t dma; | |
ea3349a0 | 899 | void *orig_data; |
47a38e15 BB |
900 | u32 act; |
901 | ||
902 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
903 | dma_sync_single_for_cpu(priv->ddev, dma, | |
904 | priv->frag_info[0].frag_size, | |
905 | DMA_FROM_DEVICE); | |
906 | ||
ea3349a0 MKL |
907 | xdp.data_hard_start = page_address(frags[0].page); |
908 | xdp.data = xdp.data_hard_start + frags[0].page_offset; | |
47a38e15 | 909 | xdp.data_end = xdp.data + length; |
ea3349a0 | 910 | orig_data = xdp.data; |
47a38e15 BB |
911 | |
912 | act = bpf_prog_run_xdp(xdp_prog, &xdp); | |
ea3349a0 MKL |
913 | |
914 | if (xdp.data != orig_data) { | |
915 | length = xdp.data_end - xdp.data; | |
916 | frags[0].page_offset = xdp.data - | |
917 | xdp.data_hard_start; | |
918 | } | |
919 | ||
47a38e15 BB |
920 | switch (act) { |
921 | case XDP_PASS: | |
922 | break; | |
9ecc2d86 | 923 | case XDP_TX: |
15fca2c8 | 924 | if (likely(!mlx4_en_xmit_frame(ring, frags, dev, |
67f8b1dc | 925 | length, cq->ring, |
de3d6fa8 | 926 | &doorbell_pending))) |
9ecc2d86 | 927 | goto consumed; |
15fca2c8 | 928 | goto xdp_drop_no_cnt; /* Drop on xmit failure */ |
47a38e15 BB |
929 | default: |
930 | bpf_warn_invalid_xdp_action(act); | |
931 | case XDP_ABORTED: | |
932 | case XDP_DROP: | |
15fca2c8 TT |
933 | ring->xdp_drop++; |
934 | xdp_drop_no_cnt: | |
de3d6fa8 | 935 | if (likely(mlx4_en_rx_recycle(ring, frags))) |
d576acf0 | 936 | goto consumed; |
47a38e15 BB |
937 | goto next; |
938 | } | |
939 | } | |
940 | ||
15fca2c8 TT |
941 | ring->bytes += length; |
942 | ring->packets++; | |
943 | ||
c8c64cff | 944 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
f8c6455b SM |
945 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | |
946 | MLX4_CQE_STATUS_UDP)) { | |
947 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && | |
948 | cqe->checksum == cpu_to_be16(0xffff)) { | |
949 | ip_summed = CHECKSUM_UNNECESSARY; | |
950 | ring->csum_ok++; | |
951 | } else { | |
952 | ip_summed = CHECKSUM_NONE; | |
953 | ring->csum_none++; | |
954 | } | |
c27a02cd | 955 | } else { |
f8c6455b SM |
956 | if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && |
957 | (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | | |
958 | MLX4_CQE_STATUS_IPV6))) { | |
959 | ip_summed = CHECKSUM_COMPLETE; | |
960 | ring->csum_complete++; | |
961 | } else { | |
962 | ip_summed = CHECKSUM_NONE; | |
963 | ring->csum_none++; | |
964 | } | |
c27a02cd YP |
965 | } |
966 | } else { | |
967 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 968 | ring->csum_none++; |
c27a02cd YP |
969 | } |
970 | ||
dd65beac SM |
971 | /* This packet is eligible for GRO if it is: |
972 | * - DIX Ethernet (type interpretation) | |
973 | * - TCP/IP (v4) | |
974 | * - without IP options | |
975 | * - not an IP fragment | |
dd65beac | 976 | */ |
868fdb06 | 977 | if (dev->features & NETIF_F_GRO) { |
dd65beac SM |
978 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); |
979 | if (!gro_skb) | |
980 | goto next; | |
981 | ||
982 | nr = mlx4_en_complete_rx_desc(priv, | |
983 | rx_desc, frags, gro_skb, | |
984 | length); | |
985 | if (!nr) | |
986 | goto next; | |
987 | ||
f8c6455b SM |
988 | if (ip_summed == CHECKSUM_COMPLETE) { |
989 | void *va = skb_frag_address(skb_shinfo(gro_skb)->frags); | |
79a25852 IS |
990 | if (check_csum(cqe, gro_skb, va, |
991 | dev->features)) { | |
f8c6455b SM |
992 | ip_summed = CHECKSUM_NONE; |
993 | ring->csum_none++; | |
994 | ring->csum_complete--; | |
995 | } | |
996 | } | |
997 | ||
dd65beac SM |
998 | skb_shinfo(gro_skb)->nr_frags = nr; |
999 | gro_skb->len = length; | |
1000 | gro_skb->data_len = length; | |
1001 | gro_skb->ip_summed = ip_summed; | |
1002 | ||
1003 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) | |
c58942f2 OG |
1004 | gro_skb->csum_level = 1; |
1005 | ||
dd65beac | 1006 | if ((cqe->vlan_my_qpn & |
e802f8e4 | 1007 | cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) && |
dd65beac SM |
1008 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { |
1009 | u16 vid = be16_to_cpu(cqe->sl_vid); | |
1010 | ||
1011 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); | |
e38af4fa HHZ |
1012 | } else if ((be32_to_cpu(cqe->vlan_my_qpn) & |
1013 | MLX4_CQE_SVLAN_PRESENT_MASK) && | |
1014 | (dev->features & NETIF_F_HW_VLAN_STAG_RX)) { | |
1015 | __vlan_hwaccel_put_tag(gro_skb, | |
1016 | htons(ETH_P_8021AD), | |
1017 | be16_to_cpu(cqe->sl_vid)); | |
dd65beac SM |
1018 | } |
1019 | ||
1020 | if (dev->features & NETIF_F_RXHASH) | |
1021 | skb_set_hash(gro_skb, | |
1022 | be32_to_cpu(cqe->immed_rss_invalid), | |
0a6d4245 ED |
1023 | (ip_summed == CHECKSUM_UNNECESSARY) ? |
1024 | PKT_HASH_TYPE_L4 : | |
1025 | PKT_HASH_TYPE_L3); | |
dd65beac SM |
1026 | |
1027 | skb_record_rx_queue(gro_skb, cq->ring); | |
dd65beac SM |
1028 | |
1029 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { | |
1030 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
1031 | mlx4_en_fill_hwtstamps(mdev, | |
1032 | skb_hwtstamps(gro_skb), | |
1033 | timestamp); | |
1034 | } | |
1035 | ||
1036 | napi_gro_frags(&cq->napi); | |
1037 | goto next; | |
1038 | } | |
1039 | ||
1040 | /* GRO not possible, complete processing here */ | |
4cce66cd | 1041 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
de3d6fa8 | 1042 | if (unlikely(!skb)) { |
d21ed3a3 | 1043 | ring->dropped++; |
c27a02cd YP |
1044 | goto next; |
1045 | } | |
1046 | ||
57c970c2 | 1047 | if (unlikely(priv->validate_loopback)) { |
e7c1c2c4 YP |
1048 | validate_loopback(priv, skb); |
1049 | goto next; | |
1050 | } | |
1051 | ||
f8c6455b | 1052 | if (ip_summed == CHECKSUM_COMPLETE) { |
79a25852 | 1053 | if (check_csum(cqe, skb, skb->data, dev->features)) { |
f8c6455b SM |
1054 | ip_summed = CHECKSUM_NONE; |
1055 | ring->csum_complete--; | |
1056 | ring->csum_none++; | |
1057 | } | |
1058 | } | |
1059 | ||
c27a02cd YP |
1060 | skb->ip_summed = ip_summed; |
1061 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 1062 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 1063 | |
9ca8600e TH |
1064 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) |
1065 | skb->csum_level = 1; | |
837052d0 | 1066 | |
ad86107f | 1067 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
1068 | skb_set_hash(skb, |
1069 | be32_to_cpu(cqe->immed_rss_invalid), | |
0a6d4245 ED |
1070 | (ip_summed == CHECKSUM_UNNECESSARY) ? |
1071 | PKT_HASH_TYPE_L4 : | |
1072 | PKT_HASH_TYPE_L3); | |
ad86107f | 1073 | |
ec693d47 | 1074 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
e802f8e4 | 1075 | MLX4_CQE_CVLAN_PRESENT_MASK) && |
ec693d47 | 1076 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) |
86a9bad3 | 1077 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
e38af4fa HHZ |
1078 | else if ((be32_to_cpu(cqe->vlan_my_qpn) & |
1079 | MLX4_CQE_SVLAN_PRESENT_MASK) && | |
1080 | (dev->features & NETIF_F_HW_VLAN_STAG_RX)) | |
1081 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), | |
1082 | be16_to_cpu(cqe->sl_vid)); | |
f1b553fb | 1083 | |
ec693d47 AV |
1084 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
1085 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
1086 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
1087 | timestamp); | |
1088 | } | |
1089 | ||
868fdb06 | 1090 | napi_gro_receive(&cq->napi, skb); |
c27a02cd | 1091 | next: |
4cce66cd TLSC |
1092 | for (nr = 0; nr < priv->num_frags; nr++) |
1093 | mlx4_en_free_frag(priv, frags, nr); | |
1094 | ||
d576acf0 | 1095 | consumed: |
c27a02cd YP |
1096 | ++cq->mcq.cons_index; |
1097 | index = (cq->mcq.cons_index) & ring->size_mask; | |
b1b6b4da | 1098 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
f1d29a3f | 1099 | if (++polled == budget) |
c27a02cd | 1100 | goto out; |
c27a02cd YP |
1101 | } |
1102 | ||
c27a02cd | 1103 | out: |
326fe02d | 1104 | rcu_read_unlock(); |
9ecc2d86 | 1105 | |
dad42c30 ED |
1106 | if (polled) { |
1107 | if (doorbell_pending) | |
1108 | mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]); | |
1109 | ||
1110 | mlx4_cq_set_ci(&cq->mcq); | |
1111 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
1112 | ring->cons = cq->mcq.cons_index; | |
1113 | } | |
c27a02cd | 1114 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); |
dad42c30 ED |
1115 | |
1116 | if (mlx4_en_refill_rx_buffers(priv, ring)) | |
1117 | mlx4_en_update_rx_prod_db(ring); | |
1118 | ||
c27a02cd YP |
1119 | return polled; |
1120 | } | |
1121 | ||
1122 | ||
1123 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
1124 | { | |
1125 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
1126 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
1127 | ||
477b35b4 ED |
1128 | if (likely(priv->port_up)) |
1129 | napi_schedule_irqoff(&cq->napi); | |
c27a02cd YP |
1130 | else |
1131 | mlx4_en_arm_cq(priv, cq); | |
1132 | } | |
1133 | ||
1134 | /* Rx CQ polling - called by NAPI */ | |
1135 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
1136 | { | |
1137 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
1138 | struct net_device *dev = cq->dev; | |
1139 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1140 | int done; | |
1141 | ||
1142 | done = mlx4_en_process_rx_cq(dev, cq, budget); | |
1143 | ||
1144 | /* If we used up all the quota - we're probably not done yet... */ | |
2eacc23c | 1145 | if (done == budget) { |
35f6f453 | 1146 | const struct cpumask *aff; |
dc2ec62f TG |
1147 | struct irq_data *idata; |
1148 | int cpu_curr; | |
35f6f453 | 1149 | |
c27a02cd | 1150 | INC_PERF_COUNTER(priv->pstats.napi_quota); |
35f6f453 AV |
1151 | |
1152 | cpu_curr = smp_processor_id(); | |
dc2ec62f TG |
1153 | idata = irq_desc_get_irq_data(cq->irq_desc); |
1154 | aff = irq_data_get_affinity_mask(idata); | |
35f6f453 | 1155 | |
2e1af7d7 ED |
1156 | if (likely(cpumask_test_cpu(cpu_curr, aff))) |
1157 | return budget; | |
1158 | ||
1159 | /* Current cpu is not according to smp_irq_affinity - | |
dad42c30 ED |
1160 | * probably affinity changed. Need to stop this NAPI |
1161 | * poll, and restart it on the right CPU. | |
1162 | * Try to avoid returning a too small value (like 0), | |
1163 | * to not fool net_rx_action() and its netdev_budget | |
2e1af7d7 | 1164 | */ |
dad42c30 ED |
1165 | if (done) |
1166 | done--; | |
c27a02cd | 1167 | } |
1a288172 | 1168 | /* Done for now */ |
2e713283 ED |
1169 | if (napi_complete_done(napi, done)) |
1170 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
1171 | return done; |
1172 | } | |
1173 | ||
51151a16 | 1174 | static const int frag_sizes[] = { |
c27a02cd YP |
1175 | FRAG_SZ0, |
1176 | FRAG_SZ1, | |
1177 | FRAG_SZ2, | |
1178 | FRAG_SZ3 | |
1179 | }; | |
1180 | ||
1181 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
1182 | { | |
1183 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
47a38e15 | 1184 | int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu); |
c27a02cd YP |
1185 | int i = 0; |
1186 | ||
d576acf0 BB |
1187 | /* bpf requires buffers to be set up as 1 packet per page. |
1188 | * This only works when num_frags == 1. | |
1189 | */ | |
67f8b1dc | 1190 | if (priv->tx_ring_num[TX_XDP]) { |
b45f0674 MKL |
1191 | priv->frag_info[0].order = 0; |
1192 | priv->frag_info[0].frag_size = eff_mtu; | |
1193 | priv->frag_info[0].frag_prefix_size = 0; | |
1194 | /* This will gain efficient xdp frame recycling at the | |
1195 | * expense of more costly truesize accounting | |
d576acf0 | 1196 | */ |
b45f0674 MKL |
1197 | priv->frag_info[0].frag_stride = PAGE_SIZE; |
1198 | priv->frag_info[0].dma_dir = PCI_DMA_BIDIRECTIONAL; | |
ea3349a0 | 1199 | priv->frag_info[0].rx_headroom = XDP_PACKET_HEADROOM; |
b45f0674 MKL |
1200 | i = 1; |
1201 | } else { | |
1202 | int buf_size = 0; | |
1203 | ||
1204 | while (buf_size < eff_mtu) { | |
1205 | priv->frag_info[i].order = MLX4_EN_ALLOC_PREFER_ORDER; | |
1206 | priv->frag_info[i].frag_size = | |
1207 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
1208 | frag_sizes[i] : eff_mtu - buf_size; | |
1209 | priv->frag_info[i].frag_prefix_size = buf_size; | |
1210 | priv->frag_info[i].frag_stride = | |
1211 | ALIGN(priv->frag_info[i].frag_size, | |
1212 | SMP_CACHE_BYTES); | |
1213 | priv->frag_info[i].dma_dir = PCI_DMA_FROMDEVICE; | |
ea3349a0 | 1214 | priv->frag_info[i].rx_headroom = 0; |
b45f0674 MKL |
1215 | buf_size += priv->frag_info[i].frag_size; |
1216 | i++; | |
1217 | } | |
c27a02cd YP |
1218 | } |
1219 | ||
1220 | priv->num_frags = i; | |
1221 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 1222 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 1223 | |
1a91de28 JP |
1224 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", |
1225 | eff_mtu, priv->num_frags); | |
c27a02cd | 1226 | for (i = 0; i < priv->num_frags; i++) { |
51151a16 | 1227 | en_err(priv, |
5f6e9800 | 1228 | " frag:%d - size:%d prefix:%d stride:%d\n", |
51151a16 ED |
1229 | i, |
1230 | priv->frag_info[i].frag_size, | |
1231 | priv->frag_info[i].frag_prefix_size, | |
51151a16 | 1232 | priv->frag_info[i].frag_stride); |
c27a02cd YP |
1233 | } |
1234 | } | |
1235 | ||
1236 | /* RSS related functions */ | |
1237 | ||
9f519f68 YP |
1238 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
1239 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
1240 | enum mlx4_qp_state *state, |
1241 | struct mlx4_qp *qp) | |
1242 | { | |
1243 | struct mlx4_en_dev *mdev = priv->mdev; | |
1244 | struct mlx4_qp_context *context; | |
1245 | int err = 0; | |
1246 | ||
14f8dc49 JP |
1247 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
1248 | if (!context) | |
c27a02cd | 1249 | return -ENOMEM; |
c27a02cd | 1250 | |
40f2287b | 1251 | err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); |
c27a02cd | 1252 | if (err) { |
453a6082 | 1253 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 1254 | goto out; |
c27a02cd YP |
1255 | } |
1256 | qp->event = mlx4_en_sqp_event; | |
1257 | ||
1258 | memset(context, 0, sizeof *context); | |
00d7d7bc | 1259 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 1260 | qpn, ring->cqn, -1, context); |
9f519f68 | 1261 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 1262 | |
f3a9d1f2 | 1263 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 1264 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 1265 | context->param3 |= cpu_to_be32(1 << 29); |
f0df3503 MM |
1266 | if (priv->dev->features & NETIF_F_RXFCS) |
1267 | ring->fcs_del = 0; | |
1268 | else | |
1269 | ring->fcs_del = ETH_FCS_LEN; | |
4a5f4dd8 YP |
1270 | } else |
1271 | ring->fcs_del = 0; | |
f3a9d1f2 | 1272 | |
9f519f68 | 1273 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
1274 | if (err) { |
1275 | mlx4_qp_remove(mdev->dev, qp); | |
1276 | mlx4_qp_free(mdev->dev, qp); | |
1277 | } | |
9f519f68 | 1278 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
1279 | out: |
1280 | kfree(context); | |
1281 | return err; | |
1282 | } | |
1283 | ||
cabdc8ee HHZ |
1284 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
1285 | { | |
1286 | int err; | |
1287 | u32 qpn; | |
1288 | ||
d57febe1 MB |
1289 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, |
1290 | MLX4_RESERVE_A0_QP); | |
cabdc8ee HHZ |
1291 | if (err) { |
1292 | en_err(priv, "Failed reserving drop qpn\n"); | |
1293 | return err; | |
1294 | } | |
40f2287b | 1295 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); |
cabdc8ee HHZ |
1296 | if (err) { |
1297 | en_err(priv, "Failed allocating drop qp\n"); | |
1298 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1299 | return err; | |
1300 | } | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
1306 | { | |
1307 | u32 qpn; | |
1308 | ||
1309 | qpn = priv->drop_qp.qpn; | |
1310 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
1311 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
1312 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1313 | } | |
1314 | ||
c27a02cd YP |
1315 | /* Allocate rx qp's and configure them according to rss map */ |
1316 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
1317 | { | |
1318 | struct mlx4_en_dev *mdev = priv->mdev; | |
1319 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1320 | struct mlx4_qp_context context; | |
876f6e67 | 1321 | struct mlx4_rss_context *rss_context; |
93d3e367 | 1322 | int rss_rings; |
c27a02cd | 1323 | void *ptr; |
876f6e67 | 1324 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 1325 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 1326 | int i, qpn; |
c27a02cd YP |
1327 | int err = 0; |
1328 | int good_qps = 0; | |
1329 | ||
453a6082 | 1330 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
1331 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
1332 | priv->rx_ring_num, | |
ddae0349 | 1333 | &rss_map->base_qpn, 0); |
c27a02cd | 1334 | if (err) { |
b6b912e0 | 1335 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
1336 | return err; |
1337 | } | |
1338 | ||
b6b912e0 | 1339 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 1340 | qpn = rss_map->base_qpn + i; |
41d942d5 | 1341 | err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], |
c27a02cd YP |
1342 | &rss_map->state[i], |
1343 | &rss_map->qps[i]); | |
1344 | if (err) | |
1345 | goto rss_err; | |
1346 | ||
1347 | ++good_qps; | |
1348 | } | |
1349 | ||
1350 | /* Configure RSS indirection qp */ | |
40f2287b | 1351 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); |
c27a02cd | 1352 | if (err) { |
453a6082 | 1353 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1354 | goto rss_err; |
c27a02cd YP |
1355 | } |
1356 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1357 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
41d942d5 | 1358 | priv->rx_ring[0]->cqn, -1, &context); |
c27a02cd | 1359 | |
93d3e367 YP |
1360 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1361 | rss_rings = priv->rx_ring_num; | |
1362 | else | |
1363 | rss_rings = priv->prof->rss_rings; | |
1364 | ||
876f6e67 OG |
1365 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1366 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1367 | rss_context = ptr; |
93d3e367 | 1368 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1369 | (rss_map->base_qpn)); |
89efea25 | 1370 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1371 | if (priv->mdev->profile.udp_rss) { |
1372 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1373 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1374 | } | |
837052d0 OG |
1375 | |
1376 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { | |
1377 | en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); | |
1378 | rss_mask |= MLX4_RSS_BY_INNER_HEADERS; | |
1379 | } | |
1380 | ||
0533943c | 1381 | rss_context->flags = rss_mask; |
876f6e67 | 1382 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
947cbb0a EP |
1383 | if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { |
1384 | rss_context->hash_fn = MLX4_RSS_HASH_XOR; | |
1385 | } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { | |
1386 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; | |
1387 | memcpy(rss_context->rss_key, priv->rss_key, | |
1388 | MLX4_EN_RSS_KEY_SIZE); | |
947cbb0a EP |
1389 | } else { |
1390 | en_err(priv, "Unknown RSS hash function requested\n"); | |
1391 | err = -EINVAL; | |
1392 | goto indir_err; | |
1393 | } | |
c27a02cd YP |
1394 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, |
1395 | &rss_map->indir_qp, &rss_map->indir_state); | |
1396 | if (err) | |
1397 | goto indir_err; | |
1398 | ||
1399 | return 0; | |
1400 | ||
1401 | indir_err: | |
1402 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1403 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1404 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1405 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1406 | rss_err: |
1407 | for (i = 0; i < good_qps; i++) { | |
1408 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1409 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1410 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1411 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1412 | } | |
b6b912e0 | 1413 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1414 | return err; |
1415 | } | |
1416 | ||
1417 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1418 | { | |
1419 | struct mlx4_en_dev *mdev = priv->mdev; | |
1420 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1421 | int i; | |
1422 | ||
1423 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1424 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1425 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1426 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1427 | |
b6b912e0 | 1428 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1429 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1430 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1431 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1432 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1433 | } | |
b6b912e0 | 1434 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1435 | } |