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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / en_rx.c
CommitLineData
c27a02cd
YP
1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/mlx4/cq.h>
5a0e3ad6 35#include <linux/slab.h>
c27a02cd
YP
36#include <linux/mlx4/qp.h>
37#include <linux/skbuff.h>
38#include <linux/if_ether.h>
39#include <linux/if_vlan.h>
40#include <linux/vmalloc.h>
41
42#include "mlx4_en.h"
43
c27a02cd 44
c27a02cd
YP
45static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
46 struct mlx4_en_rx_desc *rx_desc,
311761c8 47 struct page_frag *skb_frags,
c27a02cd
YP
48 struct mlx4_en_rx_alloc *ring_alloc,
49 int i)
50{
51 struct mlx4_en_dev *mdev = priv->mdev;
52 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
53 struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
54 struct page *page;
55 dma_addr_t dma;
56
57 if (page_alloc->offset == frag_info->last_offset) {
58 /* Allocate new page */
59 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
60 if (!page)
61 return -ENOMEM;
62
63 skb_frags[i].page = page_alloc->page;
311761c8 64 skb_frags[i].offset = page_alloc->offset;
c27a02cd
YP
65 page_alloc->page = page;
66 page_alloc->offset = frag_info->frag_align;
67 } else {
68 page = page_alloc->page;
69 get_page(page);
70
71 skb_frags[i].page = page;
311761c8 72 skb_frags[i].offset = page_alloc->offset;
c27a02cd
YP
73 page_alloc->offset += frag_info->frag_stride;
74 }
75 dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
311761c8 76 skb_frags[i].offset, frag_info->frag_size,
c27a02cd
YP
77 PCI_DMA_FROMDEVICE);
78 rx_desc->data[i].addr = cpu_to_be64(dma);
79 return 0;
80}
81
82static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
83 struct mlx4_en_rx_ring *ring)
84{
85 struct mlx4_en_rx_alloc *page_alloc;
86 int i;
87
88 for (i = 0; i < priv->num_frags; i++) {
89 page_alloc = &ring->page_alloc[i];
90 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
91 MLX4_EN_ALLOC_ORDER);
92 if (!page_alloc->page)
93 goto out;
94
95 page_alloc->offset = priv->frag_info[i].frag_align;
453a6082
YP
96 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
97 i, page_alloc->page);
c27a02cd
YP
98 }
99 return 0;
100
101out:
102 while (i--) {
103 page_alloc = &ring->page_alloc[i];
104 put_page(page_alloc->page);
105 page_alloc->page = NULL;
106 }
107 return -ENOMEM;
108}
109
110static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
111 struct mlx4_en_rx_ring *ring)
112{
113 struct mlx4_en_rx_alloc *page_alloc;
114 int i;
115
116 for (i = 0; i < priv->num_frags; i++) {
117 page_alloc = &ring->page_alloc[i];
453a6082
YP
118 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
119 i, page_count(page_alloc->page));
c27a02cd
YP
120
121 put_page(page_alloc->page);
122 page_alloc->page = NULL;
123 }
124}
125
126
127static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
128 struct mlx4_en_rx_ring *ring, int index)
129{
130 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
131 struct skb_frag_struct *skb_frags = ring->rx_info +
132 (index << priv->log_rx_info);
133 int possible_frags;
134 int i;
135
c27a02cd
YP
136 /* Set size and memtype fields */
137 for (i = 0; i < priv->num_frags; i++) {
9e903e08 138 skb_frag_size_set(&skb_frags[i], priv->frag_info[i].frag_size);
c27a02cd
YP
139 rx_desc->data[i].byte_count =
140 cpu_to_be32(priv->frag_info[i].frag_size);
141 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
142 }
143
144 /* If the number of used fragments does not fill up the ring stride,
145 * remaining (unused) fragments must be padded with null address/size
146 * and a special memory key */
147 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
148 for (i = priv->num_frags; i < possible_frags; i++) {
149 rx_desc->data[i].byte_count = 0;
150 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
151 rx_desc->data[i].addr = 0;
152 }
153}
154
155
156static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
157 struct mlx4_en_rx_ring *ring, int index)
158{
159 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
311761c8
IC
160 struct page_frag *skb_frags = ring->rx_info +
161 (index << priv->log_rx_info);
c27a02cd
YP
162 int i;
163
164 for (i = 0; i < priv->num_frags; i++)
165 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
166 goto err;
167
168 return 0;
169
170err:
171 while (i--)
172 put_page(skb_frags[i].page);
173 return -ENOMEM;
174}
175
176static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
177{
178 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
179}
180
38aab07c
YP
181static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
182 struct mlx4_en_rx_ring *ring,
183 int index)
184{
185 struct mlx4_en_dev *mdev = priv->mdev;
311761c8 186 struct page_frag *skb_frags;
38aab07c
YP
187 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
188 dma_addr_t dma;
189 int nr;
190
191 skb_frags = ring->rx_info + (index << priv->log_rx_info);
192 for (nr = 0; nr < priv->num_frags; nr++) {
453a6082 193 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
38aab07c
YP
194 dma = be64_to_cpu(rx_desc->data[nr].addr);
195
af901ca1 196 en_dbg(DRV, priv, "Unmapping buffer at dma:0x%llx\n", (u64) dma);
311761c8 197 pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
38aab07c
YP
198 PCI_DMA_FROMDEVICE);
199 put_page(skb_frags[nr].page);
200 }
201}
202
c27a02cd
YP
203static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
204{
c27a02cd
YP
205 struct mlx4_en_rx_ring *ring;
206 int ring_ind;
207 int buf_ind;
38aab07c 208 int new_size;
c27a02cd
YP
209
210 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
211 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
212 ring = &priv->rx_ring[ring_ind];
213
214 if (mlx4_en_prepare_rx_desc(priv, ring,
215 ring->actual_size)) {
216 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
453a6082
YP
217 en_err(priv, "Failed to allocate "
218 "enough rx buffers\n");
c27a02cd
YP
219 return -ENOMEM;
220 } else {
38aab07c 221 new_size = rounddown_pow_of_two(ring->actual_size);
453a6082
YP
222 en_warn(priv, "Only %d buffers allocated "
223 "reducing ring size to %d",
224 ring->actual_size, new_size);
38aab07c 225 goto reduce_rings;
c27a02cd
YP
226 }
227 }
228 ring->actual_size++;
229 ring->prod++;
230 }
231 }
38aab07c
YP
232 return 0;
233
234reduce_rings:
235 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
236 ring = &priv->rx_ring[ring_ind];
237 while (ring->actual_size > new_size) {
238 ring->actual_size--;
239 ring->prod--;
240 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
241 }
38aab07c
YP
242 }
243
c27a02cd
YP
244 return 0;
245}
246
c27a02cd
YP
247static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
248 struct mlx4_en_rx_ring *ring)
249{
c27a02cd 250 int index;
c27a02cd 251
453a6082
YP
252 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
253 ring->cons, ring->prod);
c27a02cd
YP
254
255 /* Unmap and free Rx buffers */
38aab07c 256 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
c27a02cd
YP
257 while (ring->cons != ring->prod) {
258 index = ring->cons & ring->size_mask;
453a6082 259 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
38aab07c 260 mlx4_en_free_rx_desc(priv, ring, index);
c27a02cd
YP
261 ++ring->cons;
262 }
263}
264
c27a02cd
YP
265int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
266 struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
267{
268 struct mlx4_en_dev *mdev = priv->mdev;
269 int err;
270 int tmp;
271
c27a02cd
YP
272
273 ring->prod = 0;
274 ring->cons = 0;
275 ring->size = size;
276 ring->size_mask = size - 1;
277 ring->stride = stride;
278 ring->log_stride = ffs(ring->stride) - 1;
9f519f68 279 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
c27a02cd
YP
280
281 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
282 sizeof(struct skb_frag_struct));
283 ring->rx_info = vmalloc(tmp);
284 if (!ring->rx_info) {
453a6082 285 en_err(priv, "Failed allocating rx_info ring\n");
c27a02cd
YP
286 return -ENOMEM;
287 }
453a6082 288 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
c27a02cd
YP
289 ring->rx_info, tmp);
290
291 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
292 ring->buf_size, 2 * PAGE_SIZE);
293 if (err)
294 goto err_ring;
295
296 err = mlx4_en_map_buffer(&ring->wqres.buf);
297 if (err) {
453a6082 298 en_err(priv, "Failed to map RX buffer\n");
c27a02cd
YP
299 goto err_hwq;
300 }
301 ring->buf = ring->wqres.buf.direct.buf;
302
c27a02cd
YP
303 return 0;
304
c27a02cd
YP
305err_hwq:
306 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
307err_ring:
308 vfree(ring->rx_info);
309 ring->rx_info = NULL;
310 return err;
311}
312
313int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
314{
c27a02cd
YP
315 struct mlx4_en_rx_ring *ring;
316 int i;
317 int ring_ind;
318 int err;
319 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
320 DS_SIZE * priv->num_frags);
c27a02cd
YP
321
322 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
323 ring = &priv->rx_ring[ring_ind];
324
325 ring->prod = 0;
326 ring->cons = 0;
327 ring->actual_size = 0;
328 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
329
330 ring->stride = stride;
9f519f68
YP
331 if (ring->stride <= TXBB_SIZE)
332 ring->buf += TXBB_SIZE;
333
c27a02cd
YP
334 ring->log_stride = ffs(ring->stride) - 1;
335 ring->buf_size = ring->size * ring->stride;
336
337 memset(ring->buf, 0, ring->buf_size);
338 mlx4_en_update_rx_prod_db(ring);
339
340 /* Initailize all descriptors */
341 for (i = 0; i < ring->size; i++)
342 mlx4_en_init_rx_desc(priv, ring, i);
343
344 /* Initialize page allocators */
345 err = mlx4_en_init_allocator(priv, ring);
346 if (err) {
453a6082 347 en_err(priv, "Failed initializing ring allocator\n");
60b1809f
YP
348 if (ring->stride <= TXBB_SIZE)
349 ring->buf -= TXBB_SIZE;
9a4f92a6
YP
350 ring_ind--;
351 goto err_allocator;
c27a02cd 352 }
c27a02cd 353 }
b58515be
IM
354 err = mlx4_en_fill_rx_buffers(priv);
355 if (err)
c27a02cd
YP
356 goto err_buffers;
357
358 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
359 ring = &priv->rx_ring[ring_ind];
360
00d7d7bc 361 ring->size_mask = ring->actual_size - 1;
c27a02cd 362 mlx4_en_update_rx_prod_db(ring);
c27a02cd
YP
363 }
364
365 return 0;
366
c27a02cd
YP
367err_buffers:
368 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
369 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
370
371 ring_ind = priv->rx_ring_num - 1;
372err_allocator:
373 while (ring_ind >= 0) {
60b1809f
YP
374 if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE)
375 priv->rx_ring[ring_ind].buf -= TXBB_SIZE;
c27a02cd
YP
376 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
377 ring_ind--;
378 }
379 return err;
380}
381
382void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
383 struct mlx4_en_rx_ring *ring)
384{
385 struct mlx4_en_dev *mdev = priv->mdev;
386
c27a02cd 387 mlx4_en_unmap_buffer(&ring->wqres.buf);
9f519f68 388 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size + TXBB_SIZE);
c27a02cd
YP
389 vfree(ring->rx_info);
390 ring->rx_info = NULL;
391}
392
393void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
394 struct mlx4_en_rx_ring *ring)
395{
c27a02cd 396 mlx4_en_free_rx_buf(priv, ring);
9f519f68
YP
397 if (ring->stride <= TXBB_SIZE)
398 ring->buf -= TXBB_SIZE;
c27a02cd
YP
399 mlx4_en_destroy_allocator(priv, ring);
400}
401
402
403/* Unmap a completed descriptor and free unused pages */
404static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
405 struct mlx4_en_rx_desc *rx_desc,
311761c8 406 struct page_frag *skb_frags,
90278c9f 407 struct sk_buff *skb,
c27a02cd
YP
408 struct mlx4_en_rx_alloc *page_alloc,
409 int length)
410{
90278c9f 411 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
c27a02cd
YP
412 struct mlx4_en_dev *mdev = priv->mdev;
413 struct mlx4_en_frag_info *frag_info;
414 int nr;
415 dma_addr_t dma;
416
417 /* Collect used fragments while replacing them in the HW descirptors */
418 for (nr = 0; nr < priv->num_frags; nr++) {
419 frag_info = &priv->frag_info[nr];
420 if (length <= frag_info->frag_prefix_size)
421 break;
422
423 /* Save page reference in skb */
311761c8
IC
424 __skb_frag_set_page(&skb_frags_rx[nr], skb_frags[nr].page);
425 skb_frag_size_set(&skb_frags_rx[nr], skb_frags[nr].size);
426 skb_frags_rx[nr].page_offset = skb_frags[nr].offset;
90278c9f 427 skb->truesize += frag_info->frag_stride;
c27a02cd
YP
428 dma = be64_to_cpu(rx_desc->data[nr].addr);
429
430 /* Allocate a replacement page */
431 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
432 goto fail;
433
434 /* Unmap buffer */
9e903e08 435 pci_unmap_single(mdev->pdev, dma, skb_frag_size(&skb_frags_rx[nr]),
c27a02cd
YP
436 PCI_DMA_FROMDEVICE);
437 }
438 /* Adjust size of last fragment to match actual length */
973507cb 439 if (nr > 0)
9e903e08
ED
440 skb_frag_size_set(&skb_frags_rx[nr - 1],
441 length - priv->frag_info[nr - 1].frag_prefix_size);
c27a02cd
YP
442 return nr;
443
444fail:
445 /* Drop all accumulated fragments (which have already been replaced in
446 * the descriptor) of this packet; remaining fragments are reused... */
447 while (nr > 0) {
448 nr--;
311761c8 449 __skb_frag_unref(&skb_frags_rx[nr]);
c27a02cd
YP
450 }
451 return 0;
452}
453
454
455static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
456 struct mlx4_en_rx_desc *rx_desc,
311761c8 457 struct page_frag *skb_frags,
c27a02cd
YP
458 struct mlx4_en_rx_alloc *page_alloc,
459 unsigned int length)
460{
461 struct mlx4_en_dev *mdev = priv->mdev;
462 struct sk_buff *skb;
463 void *va;
464 int used_frags;
465 dma_addr_t dma;
466
467 skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
468 if (!skb) {
453a6082 469 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
c27a02cd
YP
470 return NULL;
471 }
472 skb->dev = priv->dev;
473 skb_reserve(skb, NET_IP_ALIGN);
474 skb->len = length;
c27a02cd
YP
475
476 /* Get pointer to first fragment so we could copy the headers into the
477 * (linear part of the) skb */
311761c8 478 va = page_address(skb_frags[0].page) + skb_frags[0].offset;
c27a02cd
YP
479
480 if (length <= SMALL_PACKET_SIZE) {
481 /* We are copying all relevant data to the skb - temporarily
482 * synch buffers for the copy */
483 dma = be64_to_cpu(rx_desc->data[0].addr);
e4fc8560
FT
484 dma_sync_single_for_cpu(&mdev->pdev->dev, dma, length,
485 DMA_FROM_DEVICE);
c27a02cd 486 skb_copy_to_linear_data(skb, va, length);
e4fc8560
FT
487 dma_sync_single_for_device(&mdev->pdev->dev, dma, length,
488 DMA_FROM_DEVICE);
c27a02cd
YP
489 skb->tail += length;
490 } else {
491
492 /* Move relevant fragments to skb */
493 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
90278c9f 494 skb, page_alloc, length);
785a0982
YP
495 if (unlikely(!used_frags)) {
496 kfree_skb(skb);
497 return NULL;
498 }
c27a02cd
YP
499 skb_shinfo(skb)->nr_frags = used_frags;
500
501 /* Copy headers into the skb linear buffer */
502 memcpy(skb->data, va, HEADER_COPY_SIZE);
503 skb->tail += HEADER_COPY_SIZE;
504
505 /* Skip headers in first fragment */
506 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
507
508 /* Adjust size of first fragment */
9e903e08 509 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
c27a02cd
YP
510 skb->data_len = length - HEADER_COPY_SIZE;
511 }
512 return skb;
513}
514
e7c1c2c4
YP
515static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
516{
517 int i;
518 int offset = ETH_HLEN;
519
520 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
521 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
522 goto out_loopback;
523 }
524 /* Loopback found */
525 priv->loopback_ok = 1;
526
527out_loopback:
528 dev_kfree_skb_any(skb);
529}
c27a02cd
YP
530
531int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
532{
533 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd
YP
534 struct mlx4_cqe *cqe;
535 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
311761c8 536 struct page_frag *skb_frags;
c27a02cd
YP
537 struct mlx4_en_rx_desc *rx_desc;
538 struct sk_buff *skb;
539 int index;
540 int nr;
541 unsigned int length;
542 int polled = 0;
543 int ip_summed;
5b4c4d36
EE
544 struct ethhdr *ethh;
545 u64 s_mac;
c27a02cd
YP
546
547 if (!priv->port_up)
548 return 0;
549
550 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
551 * descriptor offset can be deduced from the CQE index instead of
552 * reading 'cqe->index' */
553 index = cq->mcq.cons_index & ring->size_mask;
554 cqe = &cq->buf[index];
555
556 /* Process all completed CQEs */
557 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
558 cq->mcq.cons_index & cq->size)) {
559
560 skb_frags = ring->rx_info + (index << priv->log_rx_info);
561 rx_desc = ring->buf + (index << ring->log_stride);
562
563 /*
564 * make sure we read the CQE after we read the ownership bit
565 */
566 rmb();
567
568 /* Drop packet on bad receive or bad checksum */
569 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
570 MLX4_CQE_OPCODE_ERROR)) {
453a6082 571 en_err(priv, "CQE completed in error - vendor "
c27a02cd
YP
572 "syndrom:%d syndrom:%d\n",
573 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
574 ((struct mlx4_err_cqe *) cqe)->syndrome);
575 goto next;
576 }
577 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
453a6082 578 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
c27a02cd
YP
579 goto next;
580 }
581
5b4c4d36
EE
582 /* Get pointer to first fragment since we haven't skb yet and
583 * cast it to ethhdr struct */
584 ethh = (struct ethhdr *)(page_address(skb_frags[0].page) +
585 skb_frags[0].offset);
586 s_mac = mlx4_en_mac_to_u64(ethh->h_source);
587
588 /* If source MAC is equal to our own MAC and not performing
589 * the selftest or flb disabled - drop the packet */
590 if (s_mac == priv->mac &&
591 (!(dev->features & NETIF_F_LOOPBACK) ||
592 !priv->validate_loopback))
593 goto next;
594
c27a02cd
YP
595 /*
596 * Packet is OK - process it.
597 */
598 length = be32_to_cpu(cqe->byte_cnt);
4a5f4dd8 599 length -= ring->fcs_del;
c27a02cd
YP
600 ring->bytes += length;
601 ring->packets++;
602
c8c64cff 603 if (likely(dev->features & NETIF_F_RXCSUM)) {
c27a02cd
YP
604 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
605 (cqe->checksum == cpu_to_be16(0xffff))) {
ad04378c 606 ring->csum_ok++;
c27a02cd
YP
607 /* This packet is eligible for LRO if it is:
608 * - DIX Ethernet (type interpretation)
609 * - TCP/IP (v4)
610 * - without IP options
611 * - not an IP fragment */
fa37a958
YP
612 if (dev->features & NETIF_F_GRO) {
613 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
ebc872c7
YP
614 if (!gro_skb)
615 goto next;
c27a02cd
YP
616
617 nr = mlx4_en_complete_rx_desc(
618 priv, rx_desc,
90278c9f 619 skb_frags, gro_skb,
c27a02cd
YP
620 ring->page_alloc, length);
621 if (!nr)
622 goto next;
623
fa37a958
YP
624 skb_shinfo(gro_skb)->nr_frags = nr;
625 gro_skb->len = length;
626 gro_skb->data_len = length;
fa37a958
YP
627 gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
628
f1b553fb
JP
629 if (cqe->vlan_my_qpn &
630 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) {
631 u16 vid = be16_to_cpu(cqe->sl_vid);
632
633 __vlan_hwaccel_put_tag(gro_skb, vid);
634 }
635
ad86107f
YP
636 if (dev->features & NETIF_F_RXHASH)
637 gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
638
3b61008d 639 skb_record_rx_queue(gro_skb, cq->ring);
f1b553fb 640 napi_gro_frags(&cq->napi);
c27a02cd
YP
641
642 goto next;
643 }
644
645 /* LRO not possible, complete processing here */
646 ip_summed = CHECKSUM_UNNECESSARY;
c27a02cd
YP
647 } else {
648 ip_summed = CHECKSUM_NONE;
ad04378c 649 ring->csum_none++;
c27a02cd
YP
650 }
651 } else {
652 ip_summed = CHECKSUM_NONE;
ad04378c 653 ring->csum_none++;
c27a02cd
YP
654 }
655
656 skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
657 ring->page_alloc, length);
658 if (!skb) {
659 priv->stats.rx_dropped++;
660 goto next;
661 }
662
e7c1c2c4
YP
663 if (unlikely(priv->validate_loopback)) {
664 validate_loopback(priv, skb);
665 goto next;
666 }
667
c27a02cd
YP
668 skb->ip_summed = ip_summed;
669 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 670 skb_record_rx_queue(skb, cq->ring);
c27a02cd 671
ad86107f
YP
672 if (dev->features & NETIF_F_RXHASH)
673 skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
674
f1b553fb
JP
675 if (be32_to_cpu(cqe->vlan_my_qpn) &
676 MLX4_CQE_VLAN_PRESENT_MASK)
677 __vlan_hwaccel_put_tag(skb, be16_to_cpu(cqe->sl_vid));
678
c27a02cd 679 /* Push it up the stack */
f1b553fb 680 netif_receive_skb(skb);
c27a02cd 681
c27a02cd
YP
682next:
683 ++cq->mcq.cons_index;
684 index = (cq->mcq.cons_index) & ring->size_mask;
685 cqe = &cq->buf[index];
686 if (++polled == budget) {
687 /* We are here because we reached the NAPI budget -
688 * flush only pending LRO sessions */
c27a02cd
YP
689 goto out;
690 }
691 }
692
c27a02cd
YP
693out:
694 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
695 mlx4_cq_set_ci(&cq->mcq);
696 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
697 ring->cons = cq->mcq.cons_index;
698 ring->prod += polled; /* Polled descriptors were realocated in place */
c27a02cd
YP
699 mlx4_en_update_rx_prod_db(ring);
700 return polled;
701}
702
703
704void mlx4_en_rx_irq(struct mlx4_cq *mcq)
705{
706 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
707 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
708
709 if (priv->port_up)
288379f0 710 napi_schedule(&cq->napi);
c27a02cd
YP
711 else
712 mlx4_en_arm_cq(priv, cq);
713}
714
715/* Rx CQ polling - called by NAPI */
716int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
717{
718 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
719 struct net_device *dev = cq->dev;
720 struct mlx4_en_priv *priv = netdev_priv(dev);
721 int done;
722
723 done = mlx4_en_process_rx_cq(dev, cq, budget);
724
725 /* If we used up all the quota - we're probably not done yet... */
726 if (done == budget)
727 INC_PERF_COUNTER(priv->pstats.napi_quota);
728 else {
729 /* Done for now */
288379f0 730 napi_complete(napi);
c27a02cd
YP
731 mlx4_en_arm_cq(priv, cq);
732 }
733 return done;
734}
735
736
25985edc 737/* Calculate the last offset position that accommodates a full fragment
c27a02cd
YP
738 * (assuming fagment size = stride-align) */
739static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
740{
741 u16 res = MLX4_EN_ALLOC_SIZE % stride;
742 u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
743
453a6082 744 en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
c27a02cd
YP
745 "res:%d offset:%d\n", stride, align, res, offset);
746 return offset;
747}
748
749
750static int frag_sizes[] = {
751 FRAG_SZ0,
752 FRAG_SZ1,
753 FRAG_SZ2,
754 FRAG_SZ3
755};
756
757void mlx4_en_calc_rx_buf(struct net_device *dev)
758{
759 struct mlx4_en_priv *priv = netdev_priv(dev);
760 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
761 int buf_size = 0;
762 int i = 0;
763
764 while (buf_size < eff_mtu) {
765 priv->frag_info[i].frag_size =
766 (eff_mtu > buf_size + frag_sizes[i]) ?
767 frag_sizes[i] : eff_mtu - buf_size;
768 priv->frag_info[i].frag_prefix_size = buf_size;
769 if (!i) {
770 priv->frag_info[i].frag_align = NET_IP_ALIGN;
771 priv->frag_info[i].frag_stride =
772 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
773 } else {
774 priv->frag_info[i].frag_align = 0;
775 priv->frag_info[i].frag_stride =
776 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
777 }
778 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
779 priv, priv->frag_info[i].frag_stride,
780 priv->frag_info[i].frag_align);
781 buf_size += priv->frag_info[i].frag_size;
782 i++;
783 }
784
785 priv->num_frags = i;
786 priv->rx_skb_size = eff_mtu;
787 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
788
453a6082 789 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
c27a02cd
YP
790 "num_frags:%d):\n", eff_mtu, priv->num_frags);
791 for (i = 0; i < priv->num_frags; i++) {
453a6082 792 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
c27a02cd
YP
793 "stride:%d last_offset:%d\n", i,
794 priv->frag_info[i].frag_size,
795 priv->frag_info[i].frag_prefix_size,
796 priv->frag_info[i].frag_align,
797 priv->frag_info[i].frag_stride,
798 priv->frag_info[i].last_offset);
799 }
800}
801
802/* RSS related functions */
803
9f519f68
YP
804static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
805 struct mlx4_en_rx_ring *ring,
c27a02cd
YP
806 enum mlx4_qp_state *state,
807 struct mlx4_qp *qp)
808{
809 struct mlx4_en_dev *mdev = priv->mdev;
810 struct mlx4_qp_context *context;
811 int err = 0;
812
813 context = kmalloc(sizeof *context , GFP_KERNEL);
814 if (!context) {
453a6082 815 en_err(priv, "Failed to allocate qp context\n");
c27a02cd
YP
816 return -ENOMEM;
817 }
818
819 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
820 if (err) {
453a6082 821 en_err(priv, "Failed to allocate qp #%x\n", qpn);
c27a02cd 822 goto out;
c27a02cd
YP
823 }
824 qp->event = mlx4_en_sqp_event;
825
826 memset(context, 0, sizeof *context);
00d7d7bc 827 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
9f519f68
YP
828 qpn, ring->cqn, context);
829 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
c27a02cd 830
f3a9d1f2 831 /* Cancel FCS removal if FW allows */
4a5f4dd8 832 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
f3a9d1f2 833 context->param3 |= cpu_to_be32(1 << 29);
4a5f4dd8
YP
834 ring->fcs_del = ETH_FCS_LEN;
835 } else
836 ring->fcs_del = 0;
f3a9d1f2 837
9f519f68 838 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
c27a02cd
YP
839 if (err) {
840 mlx4_qp_remove(mdev->dev, qp);
841 mlx4_qp_free(mdev->dev, qp);
842 }
9f519f68 843 mlx4_en_update_rx_prod_db(ring);
c27a02cd
YP
844out:
845 kfree(context);
846 return err;
847}
848
849/* Allocate rx qp's and configure them according to rss map */
850int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
851{
852 struct mlx4_en_dev *mdev = priv->mdev;
853 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
854 struct mlx4_qp_context context;
876f6e67 855 struct mlx4_rss_context *rss_context;
c27a02cd 856 void *ptr;
876f6e67 857 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1202d460 858 MLX4_RSS_TCP_IPV6);
9f519f68 859 int i, qpn;
c27a02cd
YP
860 int err = 0;
861 int good_qps = 0;
ad86107f
YP
862 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
863 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
864 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
c27a02cd 865
453a6082 866 en_dbg(DRV, priv, "Configuring rss steering\n");
b6b912e0
YP
867 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
868 priv->rx_ring_num,
869 &rss_map->base_qpn);
c27a02cd 870 if (err) {
b6b912e0 871 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
c27a02cd
YP
872 return err;
873 }
874
b6b912e0 875 for (i = 0; i < priv->rx_ring_num; i++) {
c27a02cd 876 qpn = rss_map->base_qpn + i;
9f519f68 877 err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
c27a02cd
YP
878 &rss_map->state[i],
879 &rss_map->qps[i]);
880 if (err)
881 goto rss_err;
882
883 ++good_qps;
884 }
885
886 /* Configure RSS indirection qp */
c27a02cd
YP
887 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
888 if (err) {
453a6082 889 en_err(priv, "Failed to allocate RSS indirection QP\n");
1679200f 890 goto rss_err;
c27a02cd
YP
891 }
892 rss_map->indir_qp.event = mlx4_en_sqp_event;
893 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
9f519f68 894 priv->rx_ring[0].cqn, &context);
c27a02cd 895
876f6e67
OG
896 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
897 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
43d620c8 898 rss_context = ptr;
b6b912e0 899 rss_context->base_qpn = cpu_to_be32(ilog2(priv->rx_ring_num) << 24 |
c27a02cd 900 (rss_map->base_qpn));
89efea25 901 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1202d460
OG
902 if (priv->mdev->profile.udp_rss) {
903 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
904 rss_context->base_qpn_udp = rss_context->default_qpn;
905 }
0533943c 906 rss_context->flags = rss_mask;
876f6e67 907 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
ad86107f
YP
908 for (i = 0; i < 10; i++)
909 rss_context->rss_key[i] = rsskey[i];
c27a02cd
YP
910
911 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
912 &rss_map->indir_qp, &rss_map->indir_state);
913 if (err)
914 goto indir_err;
915
916 return 0;
917
918indir_err:
919 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
920 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
921 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
922 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
c27a02cd
YP
923rss_err:
924 for (i = 0; i < good_qps; i++) {
925 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
926 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
927 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
928 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
929 }
b6b912e0 930 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
c27a02cd
YP
931 return err;
932}
933
934void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
935{
936 struct mlx4_en_dev *mdev = priv->mdev;
937 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
938 int i;
939
940 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
941 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
942 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
943 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
c27a02cd 944
b6b912e0 945 for (i = 0; i < priv->rx_ring_num; i++) {
c27a02cd
YP
946 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
947 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
948 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
949 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
950 }
b6b912e0 951 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
c27a02cd
YP
952}
953
954
955
956
957