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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
29d40c90 | 40 | #include <linux/prefetch.h> |
c27a02cd | 41 | #include <linux/vmalloc.h> |
fa37a958 | 42 | #include <linux/tcp.h> |
837052d0 | 43 | #include <linux/ip.h> |
6eb07caf | 44 | #include <linux/moduleparam.h> |
c27a02cd YP |
45 | |
46 | #include "mlx4_en.h" | |
47 | ||
c27a02cd | 48 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
ddae0349 | 49 | struct mlx4_en_tx_ring **pring, u32 size, |
d03a68f8 | 50 | u16 stride, int node, int queue_index) |
c27a02cd YP |
51 | { |
52 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 53 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
54 | int tmp; |
55 | int err; | |
56 | ||
163561a4 | 57 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 58 | if (!ring) { |
163561a4 EE |
59 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
60 | if (!ring) { | |
61 | en_err(priv, "Failed allocating TX ring\n"); | |
62 | return -ENOMEM; | |
63 | } | |
41d942d5 EE |
64 | } |
65 | ||
c27a02cd YP |
66 | ring->size = size; |
67 | ring->size_mask = size - 1; | |
68 | ring->stride = stride; | |
488a9b48 | 69 | ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; |
c27a02cd | 70 | |
c27a02cd | 71 | tmp = size * sizeof(struct mlx4_en_tx_info); |
dc9b06d1 | 72 | ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node); |
41d942d5 | 73 | if (!ring->tx_info) { |
163561a4 EE |
74 | ring->tx_info = vmalloc(tmp); |
75 | if (!ring->tx_info) { | |
76 | err = -ENOMEM; | |
77 | goto err_ring; | |
78 | } | |
41d942d5 | 79 | } |
e404decb | 80 | |
453a6082 | 81 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
82 | ring->tx_info, tmp); |
83 | ||
163561a4 | 84 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
c27a02cd | 85 | if (!ring->bounce_buf) { |
163561a4 EE |
86 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
87 | if (!ring->bounce_buf) { | |
88 | err = -ENOMEM; | |
89 | goto err_info; | |
90 | } | |
c27a02cd YP |
91 | } |
92 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); | |
93 | ||
163561a4 | 94 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 95 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
c27a02cd YP |
96 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, |
97 | 2 * PAGE_SIZE); | |
872bf2fb | 98 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 99 | if (err) { |
453a6082 | 100 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
101 | goto err_bounce; |
102 | } | |
103 | ||
104 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
105 | if (err) { | |
453a6082 | 106 | en_err(priv, "Failed to map TX buffer\n"); |
c27a02cd YP |
107 | goto err_hwq_res; |
108 | } | |
109 | ||
110 | ring->buf = ring->wqres.buf.direct.buf; | |
111 | ||
1a91de28 JP |
112 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", |
113 | ring, ring->buf, ring->size, ring->buf_size, | |
114 | (unsigned long long) ring->wqres.buf.direct.map); | |
c27a02cd | 115 | |
ddae0349 EE |
116 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, |
117 | MLX4_RESERVE_ETH_BF_QP); | |
118 | if (err) { | |
119 | en_err(priv, "failed reserving qp for TX ring\n"); | |
120 | goto err_map; | |
121 | } | |
122 | ||
40f2287b | 123 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); |
c27a02cd | 124 | if (err) { |
453a6082 | 125 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
ddae0349 | 126 | goto err_reserve; |
c27a02cd | 127 | } |
966508f7 | 128 | ring->qp.event = mlx4_en_sqp_event; |
c27a02cd | 129 | |
163561a4 | 130 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 | 131 | if (err) { |
1a91de28 | 132 | en_dbg(DRV, priv, "working without blueflame (%d)\n", err); |
87a5c389 YP |
133 | ring->bf.uar = &mdev->priv_uar; |
134 | ring->bf.uar->map = mdev->uar_map; | |
135 | ring->bf_enabled = false; | |
0fef9d03 AV |
136 | ring->bf_alloced = false; |
137 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
138 | } else { | |
139 | ring->bf_alloced = true; | |
140 | ring->bf_enabled = !!(priv->pflags & | |
141 | MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
142 | } | |
87a5c389 | 143 | |
ec693d47 | 144 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
145 | ring->queue_index = queue_index; |
146 | ||
42eab005 | 147 | if (queue_index < priv->num_tx_rings_p_up) |
f36963c9 RR |
148 | cpumask_set_cpu(cpumask_local_spread(queue_index, |
149 | priv->mdev->dev->numa_node), | |
150 | &ring->affinity_mask); | |
ec693d47 | 151 | |
41d942d5 | 152 | *pring = ring; |
c27a02cd YP |
153 | return 0; |
154 | ||
ddae0349 EE |
155 | err_reserve: |
156 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
c27a02cd YP |
157 | err_map: |
158 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
159 | err_hwq_res: | |
160 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
161 | err_bounce: | |
162 | kfree(ring->bounce_buf); | |
163 | ring->bounce_buf = NULL; | |
41d942d5 | 164 | err_info: |
dc9b06d1 | 165 | kvfree(ring->tx_info); |
c27a02cd | 166 | ring->tx_info = NULL; |
41d942d5 EE |
167 | err_ring: |
168 | kfree(ring); | |
169 | *pring = NULL; | |
c27a02cd YP |
170 | return err; |
171 | } | |
172 | ||
173 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 174 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
175 | { |
176 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 177 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 178 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 179 | |
0fef9d03 | 180 | if (ring->bf_alloced) |
87a5c389 | 181 | mlx4_bf_free(mdev->dev, &ring->bf); |
c27a02cd YP |
182 | mlx4_qp_remove(mdev->dev, &ring->qp); |
183 | mlx4_qp_free(mdev->dev, &ring->qp); | |
0eb08514 | 184 | mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); |
c27a02cd YP |
185 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
186 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
187 | kfree(ring->bounce_buf); | |
188 | ring->bounce_buf = NULL; | |
dc9b06d1 | 189 | kvfree(ring->tx_info); |
c27a02cd | 190 | ring->tx_info = NULL; |
41d942d5 EE |
191 | kfree(ring); |
192 | *pring = NULL; | |
c27a02cd YP |
193 | } |
194 | ||
195 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
196 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 197 | int cq, int user_prio) |
c27a02cd YP |
198 | { |
199 | struct mlx4_en_dev *mdev = priv->mdev; | |
200 | int err; | |
201 | ||
202 | ring->cqn = cq; | |
203 | ring->prod = 0; | |
204 | ring->cons = 0xffffffff; | |
205 | ring->last_nr_txbb = 1; | |
c27a02cd YP |
206 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
207 | memset(ring->buf, 0, ring->buf_size); | |
208 | ||
209 | ring->qp_state = MLX4_QP_STATE_RST; | |
6a4e8121 ED |
210 | ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8); |
211 | ring->mr_key = cpu_to_be32(mdev->mr.key); | |
c27a02cd YP |
212 | |
213 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, | |
0e98b523 | 214 | ring->cqn, user_prio, &ring->context); |
0fef9d03 | 215 | if (ring->bf_alloced) |
85743f1e HN |
216 | ring->context.usr_page = |
217 | cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, | |
218 | ring->bf.uar->index)); | |
c27a02cd YP |
219 | |
220 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, | |
221 | &ring->qp, &ring->qp_state); | |
42eab005 | 222 | if (!cpumask_empty(&ring->affinity_mask)) |
d03a68f8 IS |
223 | netif_set_xps_queue(priv->dev, &ring->affinity_mask, |
224 | ring->queue_index); | |
c27a02cd YP |
225 | |
226 | return err; | |
227 | } | |
228 | ||
229 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
230 | struct mlx4_en_tx_ring *ring) | |
231 | { | |
232 | struct mlx4_en_dev *mdev = priv->mdev; | |
233 | ||
234 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, | |
235 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); | |
236 | } | |
237 | ||
488a9b48 IS |
238 | static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) |
239 | { | |
240 | return ring->prod - ring->cons > ring->full_size; | |
241 | } | |
242 | ||
2d4b6466 EE |
243 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
244 | struct mlx4_en_tx_ring *ring, int index, | |
245 | u8 owner) | |
246 | { | |
247 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
248 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
249 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
250 | void *end = ring->buf + ring->buf_size; | |
251 | __be32 *ptr = (__be32 *)tx_desc; | |
252 | int i; | |
253 | ||
254 | /* Optimize the common case when there are no wraparounds */ | |
255 | if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
256 | /* Stamp the freed descriptor */ | |
257 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
258 | i += STAMP_STRIDE) { | |
259 | *ptr = stamp; | |
260 | ptr += STAMP_DWORDS; | |
261 | } | |
262 | } else { | |
263 | /* Stamp the freed descriptor */ | |
264 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
265 | i += STAMP_STRIDE) { | |
266 | *ptr = stamp; | |
267 | ptr += STAMP_DWORDS; | |
268 | if ((void *)ptr >= end) { | |
269 | ptr = ring->buf; | |
270 | stamp ^= cpu_to_be32(0x80000000); | |
271 | } | |
272 | } | |
273 | } | |
274 | } | |
275 | ||
c27a02cd YP |
276 | |
277 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, | |
278 | struct mlx4_en_tx_ring *ring, | |
b4a53379 JDB |
279 | int index, u8 owner, u64 timestamp, |
280 | int napi_mode) | |
c27a02cd | 281 | { |
c27a02cd YP |
282 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
283 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
284 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
c27a02cd | 285 | void *end = ring->buf + ring->buf_size; |
3d03641c ED |
286 | struct sk_buff *skb = tx_info->skb; |
287 | int nr_maps = tx_info->nr_maps; | |
c27a02cd | 288 | int i; |
ec693d47 | 289 | |
29d40c90 ED |
290 | /* We do not touch skb here, so prefetch skb->users location |
291 | * to speedup consume_skb() | |
292 | */ | |
293 | prefetchw(&skb->users); | |
294 | ||
3d03641c ED |
295 | if (unlikely(timestamp)) { |
296 | struct skb_shared_hwtstamps hwts; | |
297 | ||
298 | mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); | |
ec693d47 AV |
299 | skb_tstamp_tx(skb, &hwts); |
300 | } | |
c27a02cd YP |
301 | |
302 | /* Optimize the common case when there are no wraparounds */ | |
303 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a | 304 | if (!tx_info->inl) { |
3d03641c | 305 | if (tx_info->linear) |
ebf8c9aa | 306 | dma_unmap_single(priv->ddev, |
3d03641c ED |
307 | tx_info->map0_dma, |
308 | tx_info->map0_byte_count, | |
309 | PCI_DMA_TODEVICE); | |
310 | else | |
311 | dma_unmap_page(priv->ddev, | |
312 | tx_info->map0_dma, | |
313 | tx_info->map0_byte_count, | |
314 | PCI_DMA_TODEVICE); | |
315 | for (i = 1; i < nr_maps; i++) { | |
316 | data++; | |
ebf8c9aa | 317 | dma_unmap_page(priv->ddev, |
3d03641c ED |
318 | (dma_addr_t)be64_to_cpu(data->addr), |
319 | be32_to_cpu(data->byte_count), | |
320 | PCI_DMA_TODEVICE); | |
41efea5a | 321 | } |
c27a02cd | 322 | } |
c27a02cd | 323 | } else { |
41efea5a YP |
324 | if (!tx_info->inl) { |
325 | if ((void *) data >= end) { | |
43d620c8 | 326 | data = ring->buf + ((void *)data - end); |
41efea5a | 327 | } |
c27a02cd | 328 | |
3d03641c | 329 | if (tx_info->linear) |
ebf8c9aa | 330 | dma_unmap_single(priv->ddev, |
3d03641c ED |
331 | tx_info->map0_dma, |
332 | tx_info->map0_byte_count, | |
333 | PCI_DMA_TODEVICE); | |
334 | else | |
335 | dma_unmap_page(priv->ddev, | |
336 | tx_info->map0_dma, | |
337 | tx_info->map0_byte_count, | |
338 | PCI_DMA_TODEVICE); | |
339 | for (i = 1; i < nr_maps; i++) { | |
340 | data++; | |
41efea5a YP |
341 | /* Check for wraparound before unmapping */ |
342 | if ((void *) data >= end) | |
43d620c8 | 343 | data = ring->buf; |
ebf8c9aa | 344 | dma_unmap_page(priv->ddev, |
3d03641c ED |
345 | (dma_addr_t)be64_to_cpu(data->addr), |
346 | be32_to_cpu(data->byte_count), | |
347 | PCI_DMA_TODEVICE); | |
41efea5a | 348 | } |
c27a02cd | 349 | } |
c27a02cd | 350 | } |
b4a53379 JDB |
351 | napi_consume_skb(skb, napi_mode); |
352 | ||
c27a02cd YP |
353 | return tx_info->nr_txbb; |
354 | } | |
355 | ||
356 | ||
357 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
358 | { | |
359 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
360 | int cnt = 0; | |
361 | ||
362 | /* Skip last polled descriptor */ | |
363 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 364 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
365 | ring->cons, ring->prod); |
366 | ||
367 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
368 | if (netif_msg_tx_err(priv)) | |
453a6082 | 369 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
370 | return 0; |
371 | } | |
372 | ||
373 | while (ring->cons != ring->prod) { | |
374 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, | |
375 | ring->cons & ring->size_mask, | |
b4a53379 JDB |
376 | !!(ring->cons & ring->size), 0, |
377 | 0 /* Non-NAPI caller */); | |
c27a02cd YP |
378 | ring->cons += ring->last_nr_txbb; |
379 | cnt++; | |
380 | } | |
381 | ||
41b74920 TH |
382 | netdev_tx_reset_queue(ring->tx_queue); |
383 | ||
c27a02cd | 384 | if (cnt) |
453a6082 | 385 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
386 | |
387 | return cnt; | |
388 | } | |
389 | ||
fbc6daf1 | 390 | static bool mlx4_en_process_tx_cq(struct net_device *dev, |
b4a53379 | 391 | struct mlx4_en_cq *cq, int napi_budget) |
c27a02cd YP |
392 | { |
393 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
394 | struct mlx4_cq *mcq = &cq->mcq; | |
41d942d5 | 395 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; |
f0ab34f0 | 396 | struct mlx4_cqe *cqe; |
c27a02cd | 397 | u16 index; |
2d4b6466 | 398 | u16 new_index, ring_index, stamp_index; |
c27a02cd | 399 | u32 txbbs_skipped = 0; |
2d4b6466 | 400 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
401 | u32 cons_index = mcq->cons_index; |
402 | int size = cq->size; | |
403 | u32 size_mask = ring->size_mask; | |
404 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
405 | u32 packets = 0; |
406 | u32 bytes = 0; | |
08ff3235 | 407 | int factor = priv->cqe_factor; |
0276a330 | 408 | int done = 0; |
fbc6daf1 | 409 | int budget = priv->tx_work_limit; |
fb1843ee ED |
410 | u32 last_nr_txbb; |
411 | u32 ring_cons; | |
c27a02cd YP |
412 | |
413 | if (!priv->port_up) | |
fbc6daf1 | 414 | return true; |
c27a02cd | 415 | |
53511453 ED |
416 | netdev_txq_bql_complete_prefetchw(ring->tx_queue); |
417 | ||
f0ab34f0 | 418 | index = cons_index & size_mask; |
b1b6b4da | 419 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
fb1843ee ED |
420 | last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); |
421 | ring_cons = ACCESS_ONCE(ring->cons); | |
422 | ring_index = ring_cons & size_mask; | |
2d4b6466 | 423 | stamp_index = ring_index; |
f0ab34f0 YP |
424 | |
425 | /* Process all completed CQEs */ | |
426 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 427 | cons_index & size) && (done < budget)) { |
f0ab34f0 YP |
428 | /* |
429 | * make sure we read the CQE after we read the | |
430 | * ownership bit | |
431 | */ | |
12b3375f | 432 | dma_rmb(); |
f0ab34f0 | 433 | |
bd2f631d AV |
434 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
435 | MLX4_CQE_OPCODE_ERROR)) { | |
436 | struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; | |
437 | ||
438 | en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", | |
439 | cqe_err->vendor_err_syndrome, | |
440 | cqe_err->syndrome); | |
441 | } | |
442 | ||
f0ab34f0 YP |
443 | /* Skip over last polled CQE */ |
444 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
445 | ||
c27a02cd | 446 | do { |
fc96256c ED |
447 | u64 timestamp = 0; |
448 | ||
fb1843ee ED |
449 | txbbs_skipped += last_nr_txbb; |
450 | ring_index = (ring_index + last_nr_txbb) & size_mask; | |
fc96256c ED |
451 | |
452 | if (unlikely(ring->tx_info[ring_index].ts_requested)) | |
ec693d47 AV |
453 | timestamp = mlx4_en_get_cqe_ts(cqe); |
454 | ||
f0ab34f0 | 455 | /* free next descriptor */ |
fb1843ee | 456 | last_nr_txbb = mlx4_en_free_tx_desc( |
f0ab34f0 | 457 | priv, ring, ring_index, |
fb1843ee | 458 | !!((ring_cons + txbbs_skipped) & |
b4a53379 | 459 | ring->size), timestamp, napi_budget); |
2d4b6466 EE |
460 | |
461 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
fb1843ee | 462 | !!((ring_cons + txbbs_stamp) & |
2d4b6466 EE |
463 | ring->size)); |
464 | stamp_index = ring_index; | |
465 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
466 | packets++; |
467 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 468 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
469 | |
470 | ++cons_index; | |
471 | index = cons_index & size_mask; | |
b1b6b4da | 472 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
f0ab34f0 | 473 | } |
c27a02cd | 474 | |
c27a02cd YP |
475 | |
476 | /* | |
477 | * To prevent CQ overflow we first update CQ consumer and only then | |
478 | * the ring consumer. | |
479 | */ | |
f0ab34f0 | 480 | mcq->cons_index = cons_index; |
c27a02cd YP |
481 | mlx4_cq_set_ci(mcq); |
482 | wmb(); | |
fb1843ee ED |
483 | |
484 | /* we want to dirty this cache line once */ | |
485 | ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; | |
486 | ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; | |
487 | ||
5b263f53 | 488 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 489 | |
488a9b48 | 490 | /* Wakeup Tx queue if this stopped, and ring is not full. |
c18520bd | 491 | */ |
488a9b48 IS |
492 | if (netif_tx_queue_stopped(ring->tx_queue) && |
493 | !mlx4_en_is_tx_ring_full(ring)) { | |
c18520bd | 494 | netif_tx_wake_queue(ring->tx_queue); |
15bffdff | 495 | ring->wake_queue++; |
c27a02cd | 496 | } |
fbc6daf1 | 497 | return done < budget; |
c27a02cd YP |
498 | } |
499 | ||
500 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
501 | { | |
502 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
503 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 504 | |
477b35b4 ED |
505 | if (likely(priv->port_up)) |
506 | napi_schedule_irqoff(&cq->napi); | |
0276a330 EE |
507 | else |
508 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
509 | } |
510 | ||
0276a330 EE |
511 | /* TX CQ polling - called by NAPI */ |
512 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
513 | { | |
514 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
515 | struct net_device *dev = cq->dev; | |
516 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
fbc6daf1 | 517 | int clean_complete; |
0276a330 | 518 | |
b4a53379 | 519 | clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); |
fbc6daf1 AV |
520 | if (!clean_complete) |
521 | return budget; | |
0276a330 | 522 | |
fbc6daf1 AV |
523 | napi_complete(napi); |
524 | mlx4_en_arm_cq(priv, cq); | |
525 | ||
526 | return 0; | |
0276a330 | 527 | } |
c27a02cd | 528 | |
c27a02cd YP |
529 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
530 | struct mlx4_en_tx_ring *ring, | |
531 | u32 index, | |
532 | unsigned int desc_size) | |
533 | { | |
534 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
535 | int i; | |
536 | ||
537 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
538 | if ((i & (TXBB_SIZE - 1)) == 0) | |
539 | wmb(); | |
540 | ||
541 | *((u32 *) (ring->buf + i)) = | |
542 | *((u32 *) (ring->bounce_buf + copy + i)); | |
543 | } | |
544 | ||
545 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
546 | if ((i & (TXBB_SIZE - 1)) == 0) | |
547 | wmb(); | |
548 | ||
549 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
550 | *((u32 *) (ring->bounce_buf + i)); | |
551 | } | |
552 | ||
553 | /* Return real descriptor location */ | |
554 | return ring->buf + index * TXBB_SIZE; | |
555 | } | |
556 | ||
acea73d6 ED |
557 | /* Decide if skb can be inlined in tx descriptor to avoid dma mapping |
558 | * | |
559 | * It seems strange we do not simply use skb_copy_bits(). | |
560 | * This would allow to inline all skbs iff skb->len <= inline_thold | |
561 | * | |
562 | * Note that caller already checked skb was not a gso packet | |
563 | */ | |
7dfa4b41 | 564 | static bool is_inline(int inline_thold, const struct sk_buff *skb, |
b9d8839a | 565 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 566 | void **pfrag) |
c27a02cd YP |
567 | { |
568 | void *ptr; | |
569 | ||
acea73d6 ED |
570 | if (skb->len > inline_thold || !inline_thold) |
571 | return false; | |
c27a02cd | 572 | |
acea73d6 ED |
573 | if (shinfo->nr_frags == 1) { |
574 | ptr = skb_frag_address_safe(&shinfo->frags[0]); | |
575 | if (unlikely(!ptr)) | |
576 | return false; | |
577 | *pfrag = ptr; | |
578 | return true; | |
c27a02cd | 579 | } |
acea73d6 ED |
580 | if (shinfo->nr_frags) |
581 | return false; | |
582 | return true; | |
c27a02cd YP |
583 | } |
584 | ||
7dfa4b41 | 585 | static int inline_size(const struct sk_buff *skb) |
c27a02cd YP |
586 | { |
587 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
588 | <= MLX4_INLINE_ALIGN) | |
589 | return ALIGN(skb->len + CTRL_SIZE + | |
590 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
591 | else | |
592 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
593 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
594 | } | |
595 | ||
7dfa4b41 | 596 | static int get_real_size(const struct sk_buff *skb, |
b9d8839a | 597 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 598 | struct net_device *dev, |
acea73d6 ED |
599 | int *lso_header_size, |
600 | bool *inline_ok, | |
601 | void **pfrag) | |
c27a02cd YP |
602 | { |
603 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
604 | int real_size; |
605 | ||
b9d8839a | 606 | if (shinfo->gso_size) { |
acea73d6 | 607 | *inline_ok = false; |
837052d0 OG |
608 | if (skb->encapsulation) |
609 | *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); | |
610 | else | |
611 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
b9d8839a | 612 | real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + |
c27a02cd YP |
613 | ALIGN(*lso_header_size + 4, DS_SIZE); |
614 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
615 | /* We add a segment for the skb linear buffer only if | |
616 | * it contains data */ | |
617 | if (*lso_header_size < skb_headlen(skb)) | |
618 | real_size += DS_SIZE; | |
619 | else { | |
620 | if (netif_msg_tx_err(priv)) | |
453a6082 | 621 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
622 | return 0; |
623 | } | |
624 | } | |
c27a02cd YP |
625 | } else { |
626 | *lso_header_size = 0; | |
acea73d6 ED |
627 | *inline_ok = is_inline(priv->prof->inline_thold, skb, |
628 | shinfo, pfrag); | |
629 | ||
630 | if (*inline_ok) | |
c27a02cd | 631 | real_size = inline_size(skb); |
acea73d6 ED |
632 | else |
633 | real_size = CTRL_SIZE + | |
634 | (shinfo->nr_frags + 1) * DS_SIZE; | |
c27a02cd YP |
635 | } |
636 | ||
637 | return real_size; | |
638 | } | |
639 | ||
7dfa4b41 ED |
640 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, |
641 | const struct sk_buff *skb, | |
b9d8839a | 642 | const struct skb_shared_info *shinfo, |
7dfa4b41 ED |
643 | int real_size, u16 *vlan_tag, |
644 | int tx_ind, void *fragptr) | |
c27a02cd YP |
645 | { |
646 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
647 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
e533ac7e | 648 | unsigned int hlen = skb_headlen(skb); |
c27a02cd YP |
649 | |
650 | if (skb->len <= spc) { | |
93591aaa EE |
651 | if (likely(skb->len >= MIN_PKT_LEN)) { |
652 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
653 | } else { | |
654 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); | |
655 | memset(((void *)(inl + 1)) + skb->len, 0, | |
656 | MIN_PKT_LEN - skb->len); | |
657 | } | |
e533ac7e | 658 | skb_copy_from_linear_data(skb, inl + 1, hlen); |
b9d8839a | 659 | if (shinfo->nr_frags) |
e533ac7e | 660 | memcpy(((void *)(inl + 1)) + hlen, fragptr, |
b9d8839a | 661 | skb_frag_size(&shinfo->frags[0])); |
c27a02cd YP |
662 | |
663 | } else { | |
664 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
e533ac7e ED |
665 | if (hlen <= spc) { |
666 | skb_copy_from_linear_data(skb, inl + 1, hlen); | |
667 | if (hlen < spc) { | |
668 | memcpy(((void *)(inl + 1)) + hlen, | |
669 | fragptr, spc - hlen); | |
670 | fragptr += spc - hlen; | |
c27a02cd YP |
671 | } |
672 | inl = (void *) (inl + 1) + spc; | |
673 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
674 | } else { | |
675 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
676 | inl = (void *) (inl + 1) + spc; | |
677 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
e533ac7e | 678 | hlen - spc); |
b9d8839a | 679 | if (shinfo->nr_frags) |
e533ac7e | 680 | memcpy(((void *)(inl + 1)) + hlen - spc, |
b9d8839a ED |
681 | fragptr, |
682 | skb_frag_size(&shinfo->frags[0])); | |
c27a02cd YP |
683 | } |
684 | ||
12b3375f | 685 | dma_wmb(); |
c27a02cd YP |
686 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); |
687 | } | |
c27a02cd YP |
688 | } |
689 | ||
f663dd9a | 690 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 691 | void *accel_priv, select_queue_fallback_t fallback) |
c27a02cd | 692 | { |
bc6a4744 | 693 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 694 | u16 rings_p_up = priv->num_tx_rings_p_up; |
bc6a4744 | 695 | u8 up = 0; |
c27a02cd | 696 | |
bc6a4744 AV |
697 | if (dev->num_tc) |
698 | return skb_tx_hash(dev, skb); | |
699 | ||
df8a39de JP |
700 | if (skb_vlan_tag_present(skb)) |
701 | up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT; | |
f813cad8 | 702 | |
99932d4f | 703 | return fallback(dev, skb) % rings_p_up + up * rings_p_up; |
c27a02cd YP |
704 | } |
705 | ||
7dfa4b41 ED |
706 | static void mlx4_bf_copy(void __iomem *dst, const void *src, |
707 | unsigned int bytecnt) | |
87a5c389 YP |
708 | { |
709 | __iowrite64_copy(dst, src, bytecnt / 8); | |
710 | } | |
711 | ||
61357325 | 712 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd | 713 | { |
b9d8839a | 714 | struct skb_shared_info *shinfo = skb_shinfo(skb); |
c27a02cd | 715 | struct mlx4_en_priv *priv = netdev_priv(dev); |
237a3a3b | 716 | struct device *ddev = priv->ddev; |
c27a02cd | 717 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
718 | struct mlx4_en_tx_desc *tx_desc; |
719 | struct mlx4_wqe_data_seg *data; | |
c27a02cd YP |
720 | struct mlx4_en_tx_info *tx_info; |
721 | int tx_ind = 0; | |
722 | int nr_txbb; | |
723 | int desc_size; | |
724 | int real_size; | |
87a5c389 | 725 | u32 index, bf_index; |
c27a02cd | 726 | __be32 op_own; |
f813cad8 | 727 | u16 vlan_tag = 0; |
e38af4fa | 728 | u16 vlan_proto = 0; |
b9d8839a | 729 | int i_frag; |
c27a02cd | 730 | int lso_header_size; |
acea73d6 | 731 | void *fragptr = NULL; |
87a5c389 | 732 | bool bounce = false; |
5804283d | 733 | bool send_doorbell; |
fe971b95 | 734 | bool stop_queue; |
acea73d6 | 735 | bool inline_ok; |
f905c79e | 736 | u32 ring_cons; |
c27a02cd | 737 | |
3005ad40 YP |
738 | if (!priv->port_up) |
739 | goto tx_drop; | |
740 | ||
f905c79e ED |
741 | tx_ind = skb_get_queue_mapping(skb); |
742 | ring = priv->tx_ring[tx_ind]; | |
743 | ||
744 | /* fetch ring->cons far ahead before needing it to avoid stall */ | |
745 | ring_cons = ACCESS_ONCE(ring->cons); | |
746 | ||
acea73d6 ED |
747 | real_size = get_real_size(skb, shinfo, dev, &lso_header_size, |
748 | &inline_ok, &fragptr); | |
c27a02cd | 749 | if (unlikely(!real_size)) |
7e230913 | 750 | goto tx_drop; |
c27a02cd | 751 | |
25985edc | 752 | /* Align descriptor to TXBB size */ |
c27a02cd YP |
753 | desc_size = ALIGN(real_size, TXBB_SIZE); |
754 | nr_txbb = desc_size / TXBB_SIZE; | |
755 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
756 | if (netif_msg_tx_err(priv)) | |
453a6082 | 757 | en_warn(priv, "Oversized header or SG list\n"); |
7e230913 | 758 | goto tx_drop; |
c27a02cd YP |
759 | } |
760 | ||
e38af4fa | 761 | if (skb_vlan_tag_present(skb)) { |
df8a39de | 762 | vlan_tag = skb_vlan_tag_get(skb); |
e38af4fa HHZ |
763 | vlan_proto = be16_to_cpu(skb->vlan_proto); |
764 | } | |
c27a02cd | 765 | |
53511453 | 766 | netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); |
29d40c90 | 767 | |
c27a02cd YP |
768 | /* Track current inflight packets for performance analysis */ |
769 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
f905c79e | 770 | (u32)(ring->prod - ring_cons - 1)); |
c27a02cd YP |
771 | |
772 | /* Packet is good - grab an index and transmit it */ | |
773 | index = ring->prod & ring->size_mask; | |
87a5c389 | 774 | bf_index = ring->prod; |
c27a02cd YP |
775 | |
776 | /* See if we have enough space for whole descriptor TXBB for setting | |
777 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
778 | if (likely(index + nr_txbb <= ring->size)) | |
779 | tx_desc = ring->buf + index * TXBB_SIZE; | |
87a5c389 | 780 | else { |
c27a02cd | 781 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 YP |
782 | bounce = true; |
783 | } | |
c27a02cd YP |
784 | |
785 | /* Save skb in tx_info ring */ | |
786 | tx_info = &ring->tx_info[index]; | |
787 | tx_info->skb = skb; | |
788 | tx_info->nr_txbb = nr_txbb; | |
789 | ||
7dfa4b41 | 790 | data = &tx_desc->data; |
237a3a3b AV |
791 | if (lso_header_size) |
792 | data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, | |
793 | DS_SIZE)); | |
237a3a3b AV |
794 | |
795 | /* valid only for none inline segments */ | |
796 | tx_info->data_offset = (void *)data - (void *)tx_desc; | |
797 | ||
acea73d6 ED |
798 | tx_info->inl = inline_ok; |
799 | ||
237a3a3b | 800 | tx_info->linear = (lso_header_size < skb_headlen(skb) && |
acea73d6 | 801 | !inline_ok) ? 1 : 0; |
237a3a3b | 802 | |
b9d8839a | 803 | tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; |
3d03641c | 804 | data += tx_info->nr_maps - 1; |
237a3a3b | 805 | |
acea73d6 | 806 | if (!tx_info->inl) { |
3d03641c ED |
807 | dma_addr_t dma = 0; |
808 | u32 byte_count = 0; | |
809 | ||
7dfa4b41 | 810 | /* Map fragments if any */ |
b9d8839a | 811 | for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { |
7dfa4b41 | 812 | const struct skb_frag_struct *frag; |
b9d8839a ED |
813 | |
814 | frag = &shinfo->frags[i_frag]; | |
3d03641c | 815 | byte_count = skb_frag_size(frag); |
237a3a3b | 816 | dma = skb_frag_dma_map(ddev, frag, |
3d03641c | 817 | 0, byte_count, |
237a3a3b AV |
818 | DMA_TO_DEVICE); |
819 | if (dma_mapping_error(ddev, dma)) | |
820 | goto tx_drop_unmap; | |
821 | ||
822 | data->addr = cpu_to_be64(dma); | |
6a4e8121 | 823 | data->lkey = ring->mr_key; |
12b3375f | 824 | dma_wmb(); |
3d03641c | 825 | data->byte_count = cpu_to_be32(byte_count); |
237a3a3b AV |
826 | --data; |
827 | } | |
828 | ||
7dfa4b41 | 829 | /* Map linear part if needed */ |
237a3a3b | 830 | if (tx_info->linear) { |
3d03641c | 831 | byte_count = skb_headlen(skb) - lso_header_size; |
5f1cd200 | 832 | |
237a3a3b AV |
833 | dma = dma_map_single(ddev, skb->data + |
834 | lso_header_size, byte_count, | |
835 | PCI_DMA_TODEVICE); | |
836 | if (dma_mapping_error(ddev, dma)) | |
837 | goto tx_drop_unmap; | |
838 | ||
839 | data->addr = cpu_to_be64(dma); | |
6a4e8121 | 840 | data->lkey = ring->mr_key; |
12b3375f | 841 | dma_wmb(); |
237a3a3b AV |
842 | data->byte_count = cpu_to_be32(byte_count); |
843 | } | |
3d03641c ED |
844 | /* tx completion can avoid cache line miss for common cases */ |
845 | tx_info->map0_dma = dma; | |
846 | tx_info->map0_byte_count = byte_count; | |
237a3a3b AV |
847 | } |
848 | ||
ec693d47 AV |
849 | /* |
850 | * For timestamping add flag to skb_shinfo and | |
851 | * set flag for further reference | |
852 | */ | |
e70602a8 | 853 | tx_info->ts_requested = 0; |
7dfa4b41 ED |
854 | if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && |
855 | shinfo->tx_flags & SKBTX_HW_TSTAMP)) { | |
856 | shinfo->tx_flags |= SKBTX_IN_PROGRESS; | |
ec693d47 AV |
857 | tx_info->ts_requested = 1; |
858 | } | |
859 | ||
c27a02cd YP |
860 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
861 | * whether LSO is used */ | |
60d6fe99 | 862 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd | 863 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
a4f2dacb OG |
864 | if (!skb->encapsulation) |
865 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
866 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
867 | else | |
868 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); | |
ad04378c | 869 | ring->tx_csum++; |
c27a02cd YP |
870 | } |
871 | ||
79aeaccd | 872 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
873 | struct ethhdr *ethh; |
874 | ||
213815a1 YB |
875 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
876 | * so that VFs and PF can communicate with each other | |
877 | */ | |
878 | ethh = (struct ethhdr *)skb->data; | |
879 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
880 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
881 | } | |
882 | ||
c27a02cd YP |
883 | /* Handle LSO (TSO) packets */ |
884 | if (lso_header_size) { | |
b9d8839a ED |
885 | int i; |
886 | ||
c27a02cd YP |
887 | /* Mark opcode as LSO */ |
888 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
889 | ((ring->prod & ring->size) ? | |
890 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
891 | ||
892 | /* Fill in the LSO prefix */ | |
893 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
b9d8839a | 894 | shinfo->gso_size << 16 | lso_header_size); |
c27a02cd YP |
895 | |
896 | /* Copy headers; | |
897 | * note that we already verified that it is linear */ | |
898 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
c27a02cd | 899 | |
9fab426d | 900 | ring->tso_packets++; |
b9d8839a ED |
901 | |
902 | i = ((skb->len - lso_header_size) / shinfo->gso_size) + | |
903 | !!((skb->len - lso_header_size) % shinfo->gso_size); | |
5b263f53 | 904 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
905 | ring->packets += i; |
906 | } else { | |
907 | /* Normal (Non LSO) packet */ | |
908 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
909 | ((ring->prod & ring->size) ? | |
910 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 911 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd | 912 | ring->packets++; |
c27a02cd | 913 | } |
5b263f53 YP |
914 | ring->bytes += tx_info->nr_bytes; |
915 | netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); | |
c27a02cd YP |
916 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
917 | ||
acea73d6 | 918 | if (tx_info->inl) |
b9d8839a ED |
919 | build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag, |
920 | tx_ind, fragptr); | |
c27a02cd | 921 | |
837052d0 OG |
922 | if (skb->encapsulation) { |
923 | struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb); | |
924 | if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP) | |
925 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); | |
926 | else | |
927 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
928 | } | |
929 | ||
c27a02cd YP |
930 | ring->prod += nr_txbb; |
931 | ||
932 | /* If we used a bounce buffer then copy descriptor back into place */ | |
7dfa4b41 | 933 | if (unlikely(bounce)) |
c27a02cd YP |
934 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
935 | ||
eb0cabbd AV |
936 | skb_tx_timestamp(skb); |
937 | ||
fe971b95 | 938 | /* Check available TXBBs And 2K spare for prefetch */ |
488a9b48 | 939 | stop_queue = mlx4_en_is_tx_ring_full(ring); |
fe971b95 ED |
940 | if (unlikely(stop_queue)) { |
941 | netif_tx_stop_queue(ring->tx_queue); | |
942 | ring->queue_stopped++; | |
943 | } | |
5804283d ED |
944 | send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); |
945 | ||
6a4e8121 ED |
946 | real_size = (real_size / 16) & 0x3f; |
947 | ||
5804283d | 948 | if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && |
df8a39de | 949 | !skb_vlan_tag_present(skb) && send_doorbell) { |
6a4e8121 ED |
950 | tx_desc->ctrl.bf_qpn = ring->doorbell_qpn | |
951 | cpu_to_be32(real_size); | |
ec570940 | 952 | |
87a5c389 | 953 | op_own |= htonl((bf_index & 0xffff) << 8); |
5804283d ED |
954 | /* Ensure new descriptor hits memory |
955 | * before setting ownership of this descriptor to HW | |
956 | */ | |
12b3375f | 957 | dma_wmb(); |
87a5c389 | 958 | tx_desc->ctrl.owner_opcode = op_own; |
c27a02cd | 959 | |
87a5c389 YP |
960 | wmb(); |
961 | ||
7dfa4b41 ED |
962 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, |
963 | desc_size); | |
87a5c389 YP |
964 | |
965 | wmb(); | |
966 | ||
967 | ring->bf.offset ^= ring->bf.buf_size; | |
968 | } else { | |
7dfa4b41 | 969 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); |
e38af4fa HHZ |
970 | if (vlan_proto == ETH_P_8021AD) |
971 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; | |
972 | else if (vlan_proto == ETH_P_8021Q) | |
973 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; | |
092bf0fc JM |
974 | else |
975 | tx_desc->ctrl.ins_vlan = 0; | |
e38af4fa | 976 | |
7dfa4b41 ED |
977 | tx_desc->ctrl.fence_size = real_size; |
978 | ||
5804283d ED |
979 | /* Ensure new descriptor hits memory |
980 | * before setting ownership of this descriptor to HW | |
981 | */ | |
12b3375f | 982 | dma_wmb(); |
87a5c389 | 983 | tx_desc->ctrl.owner_opcode = op_own; |
5804283d ED |
984 | if (send_doorbell) { |
985 | wmb(); | |
492f5add AV |
986 | /* Since there is no iowrite*_native() that writes the |
987 | * value as is, without byteswapping - using the one | |
988 | * the doesn't do byteswapping in the relevant arch | |
989 | * endianness. | |
990 | */ | |
991 | #if defined(__LITTLE_ENDIAN) | |
992 | iowrite32( | |
993 | #else | |
994 | iowrite32be( | |
995 | #endif | |
996 | ring->doorbell_qpn, | |
6a4e8121 | 997 | ring->bf.uar->map + MLX4_SEND_DOORBELL); |
9fab426d ED |
998 | } else { |
999 | ring->xmit_more++; | |
5804283d | 1000 | } |
87a5c389 | 1001 | } |
c27a02cd | 1002 | |
fe971b95 ED |
1003 | if (unlikely(stop_queue)) { |
1004 | /* If queue was emptied after the if (stop_queue) , and before | |
1005 | * the netif_tx_stop_queue() - need to wake the queue, | |
1006 | * or else it will remain stopped forever. | |
1007 | * Need a memory barrier to make sure ring->cons was not | |
1008 | * updated before queue was stopped. | |
1009 | */ | |
1010 | smp_rmb(); | |
1011 | ||
1012 | ring_cons = ACCESS_ONCE(ring->cons); | |
488a9b48 | 1013 | if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { |
fe971b95 ED |
1014 | netif_tx_wake_queue(ring->tx_queue); |
1015 | ring->wake_queue++; | |
1016 | } | |
1017 | } | |
ec634fe3 | 1018 | return NETDEV_TX_OK; |
7e230913 | 1019 | |
237a3a3b AV |
1020 | tx_drop_unmap: |
1021 | en_err(priv, "DMA mapping error\n"); | |
1022 | ||
b9d8839a ED |
1023 | while (++i_frag < shinfo->nr_frags) { |
1024 | ++data; | |
237a3a3b AV |
1025 | dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), |
1026 | be32_to_cpu(data->byte_count), | |
1027 | PCI_DMA_TODEVICE); | |
1028 | } | |
1029 | ||
7e230913 YP |
1030 | tx_drop: |
1031 | dev_kfree_skb_any(skb); | |
1032 | priv->stats.tx_dropped++; | |
1033 | return NETDEV_TX_OK; | |
c27a02cd YP |
1034 | } |
1035 |