]>
Commit | Line | Data |
---|---|---|
c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/vmalloc.h> | |
fa37a958 | 41 | #include <linux/tcp.h> |
6eb07caf | 42 | #include <linux/moduleparam.h> |
c27a02cd YP |
43 | |
44 | #include "mlx4_en.h" | |
45 | ||
46 | enum { | |
47 | MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ | |
87a5c389 | 48 | MAX_BF = 256, |
c27a02cd YP |
49 | }; |
50 | ||
51 | static int inline_thold __read_mostly = MAX_INLINE; | |
52 | ||
53 | module_param_named(inline_thold, inline_thold, int, 0444); | |
af901ca1 | 54 | MODULE_PARM_DESC(inline_thold, "threshold for using inline data"); |
c27a02cd YP |
55 | |
56 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, | |
87a5c389 | 57 | struct mlx4_en_tx_ring *ring, int qpn, u32 size, |
c27a02cd YP |
58 | u16 stride) |
59 | { | |
60 | struct mlx4_en_dev *mdev = priv->mdev; | |
61 | int tmp; | |
62 | int err; | |
63 | ||
64 | ring->size = size; | |
65 | ring->size_mask = size - 1; | |
66 | ring->stride = stride; | |
67 | ||
68 | inline_thold = min(inline_thold, MAX_INLINE); | |
69 | ||
70 | spin_lock_init(&ring->comp_lock); | |
71 | ||
72 | tmp = size * sizeof(struct mlx4_en_tx_info); | |
73 | ring->tx_info = vmalloc(tmp); | |
74 | if (!ring->tx_info) { | |
453a6082 | 75 | en_err(priv, "Failed allocating tx_info ring\n"); |
c27a02cd YP |
76 | return -ENOMEM; |
77 | } | |
453a6082 | 78 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
79 | ring->tx_info, tmp); |
80 | ||
81 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); | |
82 | if (!ring->bounce_buf) { | |
453a6082 | 83 | en_err(priv, "Failed allocating bounce buffer\n"); |
c27a02cd YP |
84 | err = -ENOMEM; |
85 | goto err_tx; | |
86 | } | |
87 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); | |
88 | ||
89 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, | |
90 | 2 * PAGE_SIZE); | |
91 | if (err) { | |
453a6082 | 92 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
93 | goto err_bounce; |
94 | } | |
95 | ||
96 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
97 | if (err) { | |
453a6082 | 98 | en_err(priv, "Failed to map TX buffer\n"); |
c27a02cd YP |
99 | goto err_hwq_res; |
100 | } | |
101 | ||
102 | ring->buf = ring->wqres.buf.direct.buf; | |
103 | ||
453a6082 YP |
104 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " |
105 | "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, | |
106 | ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); | |
c27a02cd | 107 | |
87a5c389 | 108 | ring->qpn = qpn; |
c27a02cd YP |
109 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); |
110 | if (err) { | |
453a6082 | 111 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
87a5c389 | 112 | goto err_map; |
c27a02cd | 113 | } |
966508f7 | 114 | ring->qp.event = mlx4_en_sqp_event; |
c27a02cd | 115 | |
87a5c389 YP |
116 | err = mlx4_bf_alloc(mdev->dev, &ring->bf); |
117 | if (err) { | |
118 | en_dbg(DRV, priv, "working without blueflame (%d)", err); | |
119 | ring->bf.uar = &mdev->priv_uar; | |
120 | ring->bf.uar->map = mdev->uar_map; | |
121 | ring->bf_enabled = false; | |
122 | } else | |
123 | ring->bf_enabled = true; | |
124 | ||
c27a02cd YP |
125 | return 0; |
126 | ||
c27a02cd YP |
127 | err_map: |
128 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
129 | err_hwq_res: | |
130 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
131 | err_bounce: | |
132 | kfree(ring->bounce_buf); | |
133 | ring->bounce_buf = NULL; | |
134 | err_tx: | |
135 | vfree(ring->tx_info); | |
136 | ring->tx_info = NULL; | |
137 | return err; | |
138 | } | |
139 | ||
140 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
141 | struct mlx4_en_tx_ring *ring) | |
142 | { | |
143 | struct mlx4_en_dev *mdev = priv->mdev; | |
453a6082 | 144 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 145 | |
87a5c389 YP |
146 | if (ring->bf_enabled) |
147 | mlx4_bf_free(mdev->dev, &ring->bf); | |
c27a02cd YP |
148 | mlx4_qp_remove(mdev->dev, &ring->qp); |
149 | mlx4_qp_free(mdev->dev, &ring->qp); | |
150 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
151 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
152 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
153 | kfree(ring->bounce_buf); | |
154 | ring->bounce_buf = NULL; | |
155 | vfree(ring->tx_info); | |
156 | ring->tx_info = NULL; | |
157 | } | |
158 | ||
159 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
160 | struct mlx4_en_tx_ring *ring, | |
9f519f68 | 161 | int cq) |
c27a02cd YP |
162 | { |
163 | struct mlx4_en_dev *mdev = priv->mdev; | |
164 | int err; | |
165 | ||
166 | ring->cqn = cq; | |
167 | ring->prod = 0; | |
168 | ring->cons = 0xffffffff; | |
169 | ring->last_nr_txbb = 1; | |
170 | ring->poll_cnt = 0; | |
171 | ring->blocked = 0; | |
172 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); | |
173 | memset(ring->buf, 0, ring->buf_size); | |
174 | ||
175 | ring->qp_state = MLX4_QP_STATE_RST; | |
c5d6136e | 176 | ring->doorbell_qpn = ring->qp.qpn << 8; |
c27a02cd YP |
177 | |
178 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, | |
9f519f68 | 179 | ring->cqn, &ring->context); |
87a5c389 YP |
180 | if (ring->bf_enabled) |
181 | ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); | |
c27a02cd YP |
182 | |
183 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, | |
184 | &ring->qp, &ring->qp_state); | |
185 | ||
186 | return err; | |
187 | } | |
188 | ||
189 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
190 | struct mlx4_en_tx_ring *ring) | |
191 | { | |
192 | struct mlx4_en_dev *mdev = priv->mdev; | |
193 | ||
194 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, | |
195 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); | |
196 | } | |
197 | ||
198 | ||
199 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, | |
200 | struct mlx4_en_tx_ring *ring, | |
201 | int index, u8 owner) | |
202 | { | |
203 | struct mlx4_en_dev *mdev = priv->mdev; | |
204 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
205 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
206 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
207 | struct sk_buff *skb = tx_info->skb; | |
208 | struct skb_frag_struct *frag; | |
209 | void *end = ring->buf + ring->buf_size; | |
210 | int frags = skb_shinfo(skb)->nr_frags; | |
211 | int i; | |
212 | __be32 *ptr = (__be32 *)tx_desc; | |
213 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
214 | ||
215 | /* Optimize the common case when there are no wraparounds */ | |
216 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a YP |
217 | if (!tx_info->inl) { |
218 | if (tx_info->linear) { | |
219 | pci_unmap_single(mdev->pdev, | |
220 | (dma_addr_t) be64_to_cpu(data->addr), | |
c27a02cd YP |
221 | be32_to_cpu(data->byte_count), |
222 | PCI_DMA_TODEVICE); | |
41efea5a YP |
223 | ++data; |
224 | } | |
c27a02cd | 225 | |
41efea5a YP |
226 | for (i = 0; i < frags; i++) { |
227 | frag = &skb_shinfo(skb)->frags[i]; | |
228 | pci_unmap_page(mdev->pdev, | |
229 | (dma_addr_t) be64_to_cpu(data[i].addr), | |
9e903e08 | 230 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
41efea5a | 231 | } |
c27a02cd YP |
232 | } |
233 | /* Stamp the freed descriptor */ | |
234 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { | |
235 | *ptr = stamp; | |
236 | ptr += STAMP_DWORDS; | |
237 | } | |
238 | ||
239 | } else { | |
41efea5a YP |
240 | if (!tx_info->inl) { |
241 | if ((void *) data >= end) { | |
43d620c8 | 242 | data = ring->buf + ((void *)data - end); |
41efea5a | 243 | } |
c27a02cd | 244 | |
41efea5a YP |
245 | if (tx_info->linear) { |
246 | pci_unmap_single(mdev->pdev, | |
247 | (dma_addr_t) be64_to_cpu(data->addr), | |
c27a02cd YP |
248 | be32_to_cpu(data->byte_count), |
249 | PCI_DMA_TODEVICE); | |
41efea5a YP |
250 | ++data; |
251 | } | |
c27a02cd | 252 | |
41efea5a YP |
253 | for (i = 0; i < frags; i++) { |
254 | /* Check for wraparound before unmapping */ | |
255 | if ((void *) data >= end) | |
43d620c8 | 256 | data = ring->buf; |
41efea5a YP |
257 | frag = &skb_shinfo(skb)->frags[i]; |
258 | pci_unmap_page(mdev->pdev, | |
c27a02cd | 259 | (dma_addr_t) be64_to_cpu(data->addr), |
9e903e08 | 260 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
eb4ad826 | 261 | ++data; |
41efea5a | 262 | } |
c27a02cd YP |
263 | } |
264 | /* Stamp the freed descriptor */ | |
265 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { | |
266 | *ptr = stamp; | |
267 | ptr += STAMP_DWORDS; | |
268 | if ((void *) ptr >= end) { | |
269 | ptr = ring->buf; | |
270 | stamp ^= cpu_to_be32(0x80000000); | |
271 | } | |
272 | } | |
273 | ||
274 | } | |
275 | dev_kfree_skb_any(skb); | |
276 | return tx_info->nr_txbb; | |
277 | } | |
278 | ||
279 | ||
280 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
281 | { | |
282 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
283 | int cnt = 0; | |
284 | ||
285 | /* Skip last polled descriptor */ | |
286 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 287 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
288 | ring->cons, ring->prod); |
289 | ||
290 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
291 | if (netif_msg_tx_err(priv)) | |
453a6082 | 292 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
293 | return 0; |
294 | } | |
295 | ||
296 | while (ring->cons != ring->prod) { | |
297 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, | |
298 | ring->cons & ring->size_mask, | |
299 | !!(ring->cons & ring->size)); | |
300 | ring->cons += ring->last_nr_txbb; | |
301 | cnt++; | |
302 | } | |
303 | ||
304 | if (cnt) | |
453a6082 | 305 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
306 | |
307 | return cnt; | |
308 | } | |
309 | ||
c27a02cd YP |
310 | static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq) |
311 | { | |
312 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
313 | struct mlx4_cq *mcq = &cq->mcq; | |
314 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
f0ab34f0 | 315 | struct mlx4_cqe *cqe; |
c27a02cd | 316 | u16 index; |
f0ab34f0 | 317 | u16 new_index, ring_index; |
c27a02cd | 318 | u32 txbbs_skipped = 0; |
f0ab34f0 YP |
319 | u32 cons_index = mcq->cons_index; |
320 | int size = cq->size; | |
321 | u32 size_mask = ring->size_mask; | |
322 | struct mlx4_cqe *buf = cq->buf; | |
c27a02cd YP |
323 | |
324 | if (!priv->port_up) | |
325 | return; | |
326 | ||
f0ab34f0 YP |
327 | index = cons_index & size_mask; |
328 | cqe = &buf[index]; | |
329 | ring_index = ring->cons & size_mask; | |
330 | ||
331 | /* Process all completed CQEs */ | |
332 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
333 | cons_index & size)) { | |
334 | /* | |
335 | * make sure we read the CQE after we read the | |
336 | * ownership bit | |
337 | */ | |
338 | rmb(); | |
339 | ||
340 | /* Skip over last polled CQE */ | |
341 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
342 | ||
c27a02cd | 343 | do { |
c27a02cd | 344 | txbbs_skipped += ring->last_nr_txbb; |
f0ab34f0 YP |
345 | ring_index = (ring_index + ring->last_nr_txbb) & size_mask; |
346 | /* free next descriptor */ | |
c27a02cd | 347 | ring->last_nr_txbb = mlx4_en_free_tx_desc( |
f0ab34f0 YP |
348 | priv, ring, ring_index, |
349 | !!((ring->cons + txbbs_skipped) & | |
350 | ring->size)); | |
351 | } while (ring_index != new_index); | |
352 | ||
353 | ++cons_index; | |
354 | index = cons_index & size_mask; | |
355 | cqe = &buf[index]; | |
356 | } | |
c27a02cd | 357 | |
c27a02cd YP |
358 | |
359 | /* | |
360 | * To prevent CQ overflow we first update CQ consumer and only then | |
361 | * the ring consumer. | |
362 | */ | |
f0ab34f0 | 363 | mcq->cons_index = cons_index; |
c27a02cd YP |
364 | mlx4_cq_set_ci(mcq); |
365 | wmb(); | |
366 | ring->cons += txbbs_skipped; | |
367 | ||
368 | /* Wakeup Tx queue if this ring stopped it */ | |
369 | if (unlikely(ring->blocked)) { | |
c03ea21f YP |
370 | if ((u32) (ring->prod - ring->cons) <= |
371 | ring->size - HEADROOM - MAX_DESC_TXBBS) { | |
c27a02cd | 372 | ring->blocked = 0; |
f813cad8 | 373 | netif_tx_wake_queue(netdev_get_tx_queue(dev, cq->ring)); |
c27a02cd YP |
374 | priv->port_stats.wake_queue++; |
375 | } | |
376 | } | |
377 | } | |
378 | ||
379 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
380 | { | |
381 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
382 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
383 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
384 | ||
48374ddc YP |
385 | if (!spin_trylock(&ring->comp_lock)) |
386 | return; | |
c27a02cd | 387 | mlx4_en_process_tx_cq(cq->dev, cq); |
48374ddc YP |
388 | mod_timer(&cq->timer, jiffies + 1); |
389 | spin_unlock(&ring->comp_lock); | |
c27a02cd YP |
390 | } |
391 | ||
392 | ||
393 | void mlx4_en_poll_tx_cq(unsigned long data) | |
394 | { | |
395 | struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data; | |
396 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
397 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
398 | u32 inflight; | |
399 | ||
400 | INC_PERF_COUNTER(priv->pstats.tx_poll); | |
401 | ||
465440d2 | 402 | if (!spin_trylock_irq(&ring->comp_lock)) { |
48374ddc YP |
403 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); |
404 | return; | |
405 | } | |
c27a02cd YP |
406 | mlx4_en_process_tx_cq(cq->dev, cq); |
407 | inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb); | |
408 | ||
409 | /* If there are still packets in flight and the timer has not already | |
410 | * been scheduled by the Tx routine then schedule it here to guarantee | |
411 | * completion processing of these packets */ | |
412 | if (inflight && priv->port_up) | |
413 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); | |
414 | ||
465440d2 | 415 | spin_unlock_irq(&ring->comp_lock); |
c27a02cd YP |
416 | } |
417 | ||
418 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, | |
419 | struct mlx4_en_tx_ring *ring, | |
420 | u32 index, | |
421 | unsigned int desc_size) | |
422 | { | |
423 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
424 | int i; | |
425 | ||
426 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
427 | if ((i & (TXBB_SIZE - 1)) == 0) | |
428 | wmb(); | |
429 | ||
430 | *((u32 *) (ring->buf + i)) = | |
431 | *((u32 *) (ring->bounce_buf + copy + i)); | |
432 | } | |
433 | ||
434 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
435 | if ((i & (TXBB_SIZE - 1)) == 0) | |
436 | wmb(); | |
437 | ||
438 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
439 | *((u32 *) (ring->bounce_buf + i)); | |
440 | } | |
441 | ||
442 | /* Return real descriptor location */ | |
443 | return ring->buf + index * TXBB_SIZE; | |
444 | } | |
445 | ||
446 | static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind) | |
447 | { | |
448 | struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind]; | |
449 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind]; | |
4871953c | 450 | unsigned long flags; |
c27a02cd YP |
451 | |
452 | /* If we don't have a pending timer, set one up to catch our recent | |
453 | post in case the interface becomes idle */ | |
454 | if (!timer_pending(&cq->timer)) | |
455 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); | |
456 | ||
457 | /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */ | |
458 | if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0) | |
4871953c | 459 | if (spin_trylock_irqsave(&ring->comp_lock, flags)) { |
48374ddc | 460 | mlx4_en_process_tx_cq(priv->dev, cq); |
4871953c | 461 | spin_unlock_irqrestore(&ring->comp_lock, flags); |
48374ddc | 462 | } |
c27a02cd YP |
463 | } |
464 | ||
c27a02cd YP |
465 | static int is_inline(struct sk_buff *skb, void **pfrag) |
466 | { | |
467 | void *ptr; | |
468 | ||
469 | if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { | |
470 | if (skb_shinfo(skb)->nr_frags == 1) { | |
311761c8 | 471 | ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]); |
c27a02cd YP |
472 | if (unlikely(!ptr)) |
473 | return 0; | |
474 | ||
475 | if (pfrag) | |
476 | *pfrag = ptr; | |
477 | ||
478 | return 1; | |
479 | } else if (unlikely(skb_shinfo(skb)->nr_frags)) | |
480 | return 0; | |
481 | else | |
482 | return 1; | |
483 | } | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int inline_size(struct sk_buff *skb) | |
489 | { | |
490 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
491 | <= MLX4_INLINE_ALIGN) | |
492 | return ALIGN(skb->len + CTRL_SIZE + | |
493 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
494 | else | |
495 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
496 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
497 | } | |
498 | ||
499 | static int get_real_size(struct sk_buff *skb, struct net_device *dev, | |
500 | int *lso_header_size) | |
501 | { | |
502 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
503 | int real_size; |
504 | ||
505 | if (skb_is_gso(skb)) { | |
506 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
507 | real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + | |
508 | ALIGN(*lso_header_size + 4, DS_SIZE); | |
509 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
510 | /* We add a segment for the skb linear buffer only if | |
511 | * it contains data */ | |
512 | if (*lso_header_size < skb_headlen(skb)) | |
513 | real_size += DS_SIZE; | |
514 | else { | |
515 | if (netif_msg_tx_err(priv)) | |
453a6082 | 516 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
517 | return 0; |
518 | } | |
519 | } | |
c27a02cd YP |
520 | } else { |
521 | *lso_header_size = 0; | |
522 | if (!is_inline(skb, NULL)) | |
523 | real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; | |
524 | else | |
525 | real_size = inline_size(skb); | |
526 | } | |
527 | ||
528 | return real_size; | |
529 | } | |
530 | ||
531 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, | |
532 | int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) | |
533 | { | |
534 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
535 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
536 | ||
537 | if (skb->len <= spc) { | |
538 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
539 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
540 | if (skb_shinfo(skb)->nr_frags) | |
541 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, | |
9e903e08 | 542 | skb_frag_size(&skb_shinfo(skb)->frags[0])); |
c27a02cd YP |
543 | |
544 | } else { | |
545 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
546 | if (skb_headlen(skb) <= spc) { | |
547 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
548 | if (skb_headlen(skb) < spc) { | |
549 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), | |
550 | fragptr, spc - skb_headlen(skb)); | |
551 | fragptr += spc - skb_headlen(skb); | |
552 | } | |
553 | inl = (void *) (inl + 1) + spc; | |
554 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
555 | } else { | |
556 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
557 | inl = (void *) (inl + 1) + spc; | |
558 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
559 | skb_headlen(skb) - spc); | |
560 | if (skb_shinfo(skb)->nr_frags) | |
561 | memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, | |
9e903e08 | 562 | fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0])); |
c27a02cd YP |
563 | } |
564 | ||
565 | wmb(); | |
566 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); | |
567 | } | |
568 | tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag); | |
c140d769 AV |
569 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * |
570 | (!!vlan_tx_tag_present(skb)); | |
c27a02cd YP |
571 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; |
572 | } | |
573 | ||
f813cad8 | 574 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb) |
c27a02cd | 575 | { |
f813cad8 YP |
576 | struct mlx4_en_priv *priv = netdev_priv(dev); |
577 | u16 vlan_tag = 0; | |
c27a02cd | 578 | |
f813cad8 YP |
579 | /* If we support per priority flow control and the packet contains |
580 | * a vlan tag, send the packet to the TX ring assigned to that priority | |
581 | */ | |
eab6d18d | 582 | if (priv->prof->rx_ppp && vlan_tx_tag_present(skb)) { |
f813cad8 YP |
583 | vlan_tag = vlan_tx_tag_get(skb); |
584 | return MLX4_EN_NUM_TX_RINGS + (vlan_tag >> 13); | |
c27a02cd | 585 | } |
f813cad8 YP |
586 | |
587 | return skb_tx_hash(dev, skb); | |
c27a02cd YP |
588 | } |
589 | ||
87a5c389 YP |
590 | static void mlx4_bf_copy(unsigned long *dst, unsigned long *src, unsigned bytecnt) |
591 | { | |
592 | __iowrite64_copy(dst, src, bytecnt / 8); | |
593 | } | |
594 | ||
61357325 | 595 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd YP |
596 | { |
597 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
598 | struct mlx4_en_dev *mdev = priv->mdev; | |
599 | struct mlx4_en_tx_ring *ring; | |
600 | struct mlx4_en_cq *cq; | |
601 | struct mlx4_en_tx_desc *tx_desc; | |
602 | struct mlx4_wqe_data_seg *data; | |
603 | struct skb_frag_struct *frag; | |
604 | struct mlx4_en_tx_info *tx_info; | |
e7c1c2c4 YP |
605 | struct ethhdr *ethh; |
606 | u64 mac; | |
607 | u32 mac_l, mac_h; | |
c27a02cd YP |
608 | int tx_ind = 0; |
609 | int nr_txbb; | |
610 | int desc_size; | |
611 | int real_size; | |
612 | dma_addr_t dma; | |
87a5c389 | 613 | u32 index, bf_index; |
c27a02cd | 614 | __be32 op_own; |
f813cad8 | 615 | u16 vlan_tag = 0; |
c27a02cd YP |
616 | int i; |
617 | int lso_header_size; | |
618 | void *fragptr; | |
87a5c389 | 619 | bool bounce = false; |
c27a02cd | 620 | |
3005ad40 YP |
621 | if (!priv->port_up) |
622 | goto tx_drop; | |
623 | ||
c27a02cd YP |
624 | real_size = get_real_size(skb, dev, &lso_header_size); |
625 | if (unlikely(!real_size)) | |
7e230913 | 626 | goto tx_drop; |
c27a02cd | 627 | |
25985edc | 628 | /* Align descriptor to TXBB size */ |
c27a02cd YP |
629 | desc_size = ALIGN(real_size, TXBB_SIZE); |
630 | nr_txbb = desc_size / TXBB_SIZE; | |
631 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
632 | if (netif_msg_tx_err(priv)) | |
453a6082 | 633 | en_warn(priv, "Oversized header or SG list\n"); |
7e230913 | 634 | goto tx_drop; |
c27a02cd YP |
635 | } |
636 | ||
f813cad8 | 637 | tx_ind = skb->queue_mapping; |
c27a02cd | 638 | ring = &priv->tx_ring[tx_ind]; |
eab6d18d | 639 | if (vlan_tx_tag_present(skb)) |
f813cad8 | 640 | vlan_tag = vlan_tx_tag_get(skb); |
c27a02cd YP |
641 | |
642 | /* Check available TXBBs And 2K spare for prefetch */ | |
643 | if (unlikely(((int)(ring->prod - ring->cons)) > | |
644 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { | |
f813cad8 YP |
645 | /* every full Tx ring stops queue */ |
646 | netif_tx_stop_queue(netdev_get_tx_queue(dev, tx_ind)); | |
c27a02cd YP |
647 | ring->blocked = 1; |
648 | priv->port_stats.queue_stopped++; | |
649 | ||
650 | /* Use interrupts to find out when queue opened */ | |
651 | cq = &priv->tx_cq[tx_ind]; | |
652 | mlx4_en_arm_cq(priv, cq); | |
653 | return NETDEV_TX_BUSY; | |
654 | } | |
655 | ||
c27a02cd YP |
656 | /* Track current inflight packets for performance analysis */ |
657 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
658 | (u32) (ring->prod - ring->cons - 1)); | |
659 | ||
660 | /* Packet is good - grab an index and transmit it */ | |
661 | index = ring->prod & ring->size_mask; | |
87a5c389 | 662 | bf_index = ring->prod; |
c27a02cd YP |
663 | |
664 | /* See if we have enough space for whole descriptor TXBB for setting | |
665 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
666 | if (likely(index + nr_txbb <= ring->size)) | |
667 | tx_desc = ring->buf + index * TXBB_SIZE; | |
87a5c389 | 668 | else { |
c27a02cd | 669 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 YP |
670 | bounce = true; |
671 | } | |
c27a02cd YP |
672 | |
673 | /* Save skb in tx_info ring */ | |
674 | tx_info = &ring->tx_info[index]; | |
675 | tx_info->skb = skb; | |
676 | tx_info->nr_txbb = nr_txbb; | |
677 | ||
678 | /* Prepare ctrl segement apart opcode+ownership, which depends on | |
679 | * whether LSO is used */ | |
680 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); | |
c140d769 AV |
681 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * |
682 | !!vlan_tx_tag_present(skb); | |
c27a02cd | 683 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; |
60d6fe99 | 684 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd YP |
685 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
686 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
687 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
ad04378c | 688 | ring->tx_csum++; |
c27a02cd YP |
689 | } |
690 | ||
5b4c4d36 EE |
691 | /* Copy dst mac address to wqe */ |
692 | skb_reset_mac_header(skb); | |
693 | ethh = eth_hdr(skb); | |
694 | if (ethh && ethh->h_dest) { | |
695 | mac = mlx4_en_mac_to_u64(ethh->h_dest); | |
696 | mac_h = (u32) ((mac & 0xffff00000000ULL) >> 16); | |
697 | mac_l = (u32) (mac & 0xffffffff); | |
698 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(mac_h); | |
699 | tx_desc->ctrl.imm = cpu_to_be32(mac_l); | |
e7c1c2c4 YP |
700 | } |
701 | ||
c27a02cd YP |
702 | /* Handle LSO (TSO) packets */ |
703 | if (lso_header_size) { | |
704 | /* Mark opcode as LSO */ | |
705 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
706 | ((ring->prod & ring->size) ? | |
707 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
708 | ||
709 | /* Fill in the LSO prefix */ | |
710 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
711 | skb_shinfo(skb)->gso_size << 16 | lso_header_size); | |
712 | ||
713 | /* Copy headers; | |
714 | * note that we already verified that it is linear */ | |
715 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
716 | data = ((void *) &tx_desc->lso + | |
717 | ALIGN(lso_header_size + 4, DS_SIZE)); | |
718 | ||
719 | priv->port_stats.tso_packets++; | |
720 | i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + | |
721 | !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); | |
722 | ring->bytes += skb->len + (i - 1) * lso_header_size; | |
723 | ring->packets += i; | |
724 | } else { | |
725 | /* Normal (Non LSO) packet */ | |
726 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
727 | ((ring->prod & ring->size) ? | |
728 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
729 | data = &tx_desc->data; | |
730 | ring->bytes += max(skb->len, (unsigned int) ETH_ZLEN); | |
731 | ring->packets++; | |
732 | ||
733 | } | |
734 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); | |
735 | ||
736 | ||
737 | /* valid only for none inline segments */ | |
738 | tx_info->data_offset = (void *) data - (void *) tx_desc; | |
739 | ||
740 | tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0; | |
741 | data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; | |
742 | ||
743 | if (!is_inline(skb, &fragptr)) { | |
744 | /* Map fragments */ | |
745 | for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { | |
746 | frag = &skb_shinfo(skb)->frags[i]; | |
311761c8 IC |
747 | dma = skb_frag_dma_map(&mdev->dev->pdev->dev, frag, |
748 | 0, skb_frag_size(frag), | |
749 | DMA_TO_DEVICE); | |
c27a02cd YP |
750 | data->addr = cpu_to_be64(dma); |
751 | data->lkey = cpu_to_be32(mdev->mr.key); | |
752 | wmb(); | |
9e903e08 | 753 | data->byte_count = cpu_to_be32(skb_frag_size(frag)); |
c27a02cd YP |
754 | --data; |
755 | } | |
756 | ||
757 | /* Map linear part */ | |
758 | if (tx_info->linear) { | |
759 | dma = pci_map_single(mdev->dev->pdev, skb->data + lso_header_size, | |
760 | skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE); | |
761 | data->addr = cpu_to_be64(dma); | |
762 | data->lkey = cpu_to_be32(mdev->mr.key); | |
763 | wmb(); | |
764 | data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size); | |
765 | } | |
41efea5a YP |
766 | tx_info->inl = 0; |
767 | } else { | |
c27a02cd | 768 | build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); |
41efea5a YP |
769 | tx_info->inl = 1; |
770 | } | |
c27a02cd YP |
771 | |
772 | ring->prod += nr_txbb; | |
773 | ||
774 | /* If we used a bounce buffer then copy descriptor back into place */ | |
87a5c389 | 775 | if (bounce) |
c27a02cd YP |
776 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
777 | ||
778 | /* Run destructor before passing skb to HW */ | |
779 | if (likely(!skb_shared(skb))) | |
780 | skb_orphan(skb); | |
781 | ||
87a5c389 | 782 | if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tag) { |
c5d6136e | 783 | *(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn); |
87a5c389 YP |
784 | op_own |= htonl((bf_index & 0xffff) << 8); |
785 | /* Ensure new descirptor hits memory | |
786 | * before setting ownership of this descriptor to HW */ | |
787 | wmb(); | |
788 | tx_desc->ctrl.owner_opcode = op_own; | |
c27a02cd | 789 | |
87a5c389 YP |
790 | wmb(); |
791 | ||
792 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl, | |
793 | desc_size); | |
794 | ||
795 | wmb(); | |
796 | ||
797 | ring->bf.offset ^= ring->bf.buf_size; | |
798 | } else { | |
799 | /* Ensure new descirptor hits memory | |
800 | * before setting ownership of this descriptor to HW */ | |
801 | wmb(); | |
802 | tx_desc->ctrl.owner_opcode = op_own; | |
803 | wmb(); | |
c5d6136e | 804 | iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL); |
87a5c389 | 805 | } |
c27a02cd YP |
806 | |
807 | /* Poll CQ here */ | |
808 | mlx4_en_xmit_poll(priv, tx_ind); | |
809 | ||
ec634fe3 | 810 | return NETDEV_TX_OK; |
7e230913 YP |
811 | |
812 | tx_drop: | |
813 | dev_kfree_skb_any(skb); | |
814 | priv->stats.tx_dropped++; | |
815 | return NETDEV_TX_OK; | |
c27a02cd YP |
816 | } |
817 |