]>
Commit | Line | Data |
---|---|---|
c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/vmalloc.h> | |
fa37a958 | 41 | #include <linux/tcp.h> |
837052d0 | 42 | #include <linux/ip.h> |
6eb07caf | 43 | #include <linux/moduleparam.h> |
c27a02cd YP |
44 | |
45 | #include "mlx4_en.h" | |
46 | ||
c27a02cd | 47 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 48 | struct mlx4_en_tx_ring **pring, int qpn, u32 size, |
d03a68f8 | 49 | u16 stride, int node, int queue_index) |
c27a02cd YP |
50 | { |
51 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 52 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
53 | int tmp; |
54 | int err; | |
55 | ||
163561a4 | 56 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 57 | if (!ring) { |
163561a4 EE |
58 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
59 | if (!ring) { | |
60 | en_err(priv, "Failed allocating TX ring\n"); | |
61 | return -ENOMEM; | |
62 | } | |
41d942d5 EE |
63 | } |
64 | ||
c27a02cd YP |
65 | ring->size = size; |
66 | ring->size_mask = size - 1; | |
67 | ring->stride = stride; | |
b97b33a3 | 68 | ring->inline_thold = priv->prof->inline_thold; |
c27a02cd | 69 | |
c27a02cd | 70 | tmp = size * sizeof(struct mlx4_en_tx_info); |
163561a4 | 71 | ring->tx_info = vmalloc_node(tmp, node); |
41d942d5 | 72 | if (!ring->tx_info) { |
163561a4 EE |
73 | ring->tx_info = vmalloc(tmp); |
74 | if (!ring->tx_info) { | |
75 | err = -ENOMEM; | |
76 | goto err_ring; | |
77 | } | |
41d942d5 | 78 | } |
e404decb | 79 | |
453a6082 | 80 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
81 | ring->tx_info, tmp); |
82 | ||
163561a4 | 83 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
c27a02cd | 84 | if (!ring->bounce_buf) { |
163561a4 EE |
85 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
86 | if (!ring->bounce_buf) { | |
87 | err = -ENOMEM; | |
88 | goto err_info; | |
89 | } | |
c27a02cd YP |
90 | } |
91 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); | |
92 | ||
163561a4 EE |
93 | /* Allocate HW buffers on provided NUMA node */ |
94 | set_dev_node(&mdev->dev->pdev->dev, node); | |
c27a02cd YP |
95 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, |
96 | 2 * PAGE_SIZE); | |
163561a4 | 97 | set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 98 | if (err) { |
453a6082 | 99 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
100 | goto err_bounce; |
101 | } | |
102 | ||
103 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
104 | if (err) { | |
453a6082 | 105 | en_err(priv, "Failed to map TX buffer\n"); |
c27a02cd YP |
106 | goto err_hwq_res; |
107 | } | |
108 | ||
109 | ring->buf = ring->wqres.buf.direct.buf; | |
110 | ||
453a6082 YP |
111 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " |
112 | "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, | |
113 | ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); | |
c27a02cd | 114 | |
87a5c389 | 115 | ring->qpn = qpn; |
c27a02cd YP |
116 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); |
117 | if (err) { | |
453a6082 | 118 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
87a5c389 | 119 | goto err_map; |
c27a02cd | 120 | } |
966508f7 | 121 | ring->qp.event = mlx4_en_sqp_event; |
c27a02cd | 122 | |
163561a4 | 123 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 YP |
124 | if (err) { |
125 | en_dbg(DRV, priv, "working without blueflame (%d)", err); | |
126 | ring->bf.uar = &mdev->priv_uar; | |
127 | ring->bf.uar->map = mdev->uar_map; | |
128 | ring->bf_enabled = false; | |
129 | } else | |
130 | ring->bf_enabled = true; | |
131 | ||
ec693d47 | 132 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
133 | ring->queue_index = queue_index; |
134 | ||
135 | if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index)) | |
136 | cpumask_set_cpu(queue_index, &ring->affinity_mask); | |
ec693d47 | 137 | |
41d942d5 | 138 | *pring = ring; |
c27a02cd YP |
139 | return 0; |
140 | ||
c27a02cd YP |
141 | err_map: |
142 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
143 | err_hwq_res: | |
144 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
145 | err_bounce: | |
146 | kfree(ring->bounce_buf); | |
147 | ring->bounce_buf = NULL; | |
41d942d5 | 148 | err_info: |
c27a02cd YP |
149 | vfree(ring->tx_info); |
150 | ring->tx_info = NULL; | |
41d942d5 EE |
151 | err_ring: |
152 | kfree(ring); | |
153 | *pring = NULL; | |
c27a02cd YP |
154 | return err; |
155 | } | |
156 | ||
157 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 158 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
159 | { |
160 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 161 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 162 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 163 | |
87a5c389 YP |
164 | if (ring->bf_enabled) |
165 | mlx4_bf_free(mdev->dev, &ring->bf); | |
c27a02cd YP |
166 | mlx4_qp_remove(mdev->dev, &ring->qp); |
167 | mlx4_qp_free(mdev->dev, &ring->qp); | |
c27a02cd YP |
168 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
169 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
170 | kfree(ring->bounce_buf); | |
171 | ring->bounce_buf = NULL; | |
172 | vfree(ring->tx_info); | |
173 | ring->tx_info = NULL; | |
41d942d5 EE |
174 | kfree(ring); |
175 | *pring = NULL; | |
c27a02cd YP |
176 | } |
177 | ||
178 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
179 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 180 | int cq, int user_prio) |
c27a02cd YP |
181 | { |
182 | struct mlx4_en_dev *mdev = priv->mdev; | |
183 | int err; | |
184 | ||
185 | ring->cqn = cq; | |
186 | ring->prod = 0; | |
187 | ring->cons = 0xffffffff; | |
188 | ring->last_nr_txbb = 1; | |
189 | ring->poll_cnt = 0; | |
c27a02cd YP |
190 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
191 | memset(ring->buf, 0, ring->buf_size); | |
192 | ||
193 | ring->qp_state = MLX4_QP_STATE_RST; | |
c5d6136e | 194 | ring->doorbell_qpn = ring->qp.qpn << 8; |
c27a02cd YP |
195 | |
196 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, | |
0e98b523 | 197 | ring->cqn, user_prio, &ring->context); |
87a5c389 YP |
198 | if (ring->bf_enabled) |
199 | ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); | |
c27a02cd YP |
200 | |
201 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, | |
202 | &ring->qp, &ring->qp_state); | |
d03a68f8 IS |
203 | if (!user_prio && cpu_online(ring->queue_index)) |
204 | netif_set_xps_queue(priv->dev, &ring->affinity_mask, | |
205 | ring->queue_index); | |
c27a02cd YP |
206 | |
207 | return err; | |
208 | } | |
209 | ||
210 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
211 | struct mlx4_en_tx_ring *ring) | |
212 | { | |
213 | struct mlx4_en_dev *mdev = priv->mdev; | |
214 | ||
215 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, | |
216 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); | |
217 | } | |
218 | ||
2d4b6466 EE |
219 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
220 | struct mlx4_en_tx_ring *ring, int index, | |
221 | u8 owner) | |
222 | { | |
223 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
224 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
225 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
226 | void *end = ring->buf + ring->buf_size; | |
227 | __be32 *ptr = (__be32 *)tx_desc; | |
228 | int i; | |
229 | ||
230 | /* Optimize the common case when there are no wraparounds */ | |
231 | if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
232 | /* Stamp the freed descriptor */ | |
233 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
234 | i += STAMP_STRIDE) { | |
235 | *ptr = stamp; | |
236 | ptr += STAMP_DWORDS; | |
237 | } | |
238 | } else { | |
239 | /* Stamp the freed descriptor */ | |
240 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
241 | i += STAMP_STRIDE) { | |
242 | *ptr = stamp; | |
243 | ptr += STAMP_DWORDS; | |
244 | if ((void *)ptr >= end) { | |
245 | ptr = ring->buf; | |
246 | stamp ^= cpu_to_be32(0x80000000); | |
247 | } | |
248 | } | |
249 | } | |
250 | } | |
251 | ||
c27a02cd YP |
252 | |
253 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, | |
254 | struct mlx4_en_tx_ring *ring, | |
ec693d47 | 255 | int index, u8 owner, u64 timestamp) |
c27a02cd | 256 | { |
ec693d47 | 257 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd YP |
258 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
259 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
260 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
261 | struct sk_buff *skb = tx_info->skb; | |
262 | struct skb_frag_struct *frag; | |
263 | void *end = ring->buf + ring->buf_size; | |
264 | int frags = skb_shinfo(skb)->nr_frags; | |
265 | int i; | |
ec693d47 AV |
266 | struct skb_shared_hwtstamps hwts; |
267 | ||
268 | if (timestamp) { | |
269 | mlx4_en_fill_hwtstamps(mdev, &hwts, timestamp); | |
270 | skb_tstamp_tx(skb, &hwts); | |
271 | } | |
c27a02cd YP |
272 | |
273 | /* Optimize the common case when there are no wraparounds */ | |
274 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a YP |
275 | if (!tx_info->inl) { |
276 | if (tx_info->linear) { | |
ebf8c9aa | 277 | dma_unmap_single(priv->ddev, |
41efea5a | 278 | (dma_addr_t) be64_to_cpu(data->addr), |
c27a02cd YP |
279 | be32_to_cpu(data->byte_count), |
280 | PCI_DMA_TODEVICE); | |
41efea5a YP |
281 | ++data; |
282 | } | |
c27a02cd | 283 | |
41efea5a YP |
284 | for (i = 0; i < frags; i++) { |
285 | frag = &skb_shinfo(skb)->frags[i]; | |
ebf8c9aa | 286 | dma_unmap_page(priv->ddev, |
41efea5a | 287 | (dma_addr_t) be64_to_cpu(data[i].addr), |
9e903e08 | 288 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
41efea5a | 289 | } |
c27a02cd | 290 | } |
c27a02cd | 291 | } else { |
41efea5a YP |
292 | if (!tx_info->inl) { |
293 | if ((void *) data >= end) { | |
43d620c8 | 294 | data = ring->buf + ((void *)data - end); |
41efea5a | 295 | } |
c27a02cd | 296 | |
41efea5a | 297 | if (tx_info->linear) { |
ebf8c9aa | 298 | dma_unmap_single(priv->ddev, |
41efea5a | 299 | (dma_addr_t) be64_to_cpu(data->addr), |
c27a02cd YP |
300 | be32_to_cpu(data->byte_count), |
301 | PCI_DMA_TODEVICE); | |
41efea5a YP |
302 | ++data; |
303 | } | |
c27a02cd | 304 | |
41efea5a YP |
305 | for (i = 0; i < frags; i++) { |
306 | /* Check for wraparound before unmapping */ | |
307 | if ((void *) data >= end) | |
43d620c8 | 308 | data = ring->buf; |
41efea5a | 309 | frag = &skb_shinfo(skb)->frags[i]; |
ebf8c9aa | 310 | dma_unmap_page(priv->ddev, |
c27a02cd | 311 | (dma_addr_t) be64_to_cpu(data->addr), |
9e903e08 | 312 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
eb4ad826 | 313 | ++data; |
41efea5a | 314 | } |
c27a02cd | 315 | } |
c27a02cd | 316 | } |
0276a330 | 317 | dev_kfree_skb(skb); |
c27a02cd YP |
318 | return tx_info->nr_txbb; |
319 | } | |
320 | ||
321 | ||
322 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
323 | { | |
324 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
325 | int cnt = 0; | |
326 | ||
327 | /* Skip last polled descriptor */ | |
328 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 329 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
330 | ring->cons, ring->prod); |
331 | ||
332 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
333 | if (netif_msg_tx_err(priv)) | |
453a6082 | 334 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
335 | return 0; |
336 | } | |
337 | ||
338 | while (ring->cons != ring->prod) { | |
339 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, | |
340 | ring->cons & ring->size_mask, | |
ec693d47 | 341 | !!(ring->cons & ring->size), 0); |
c27a02cd YP |
342 | ring->cons += ring->last_nr_txbb; |
343 | cnt++; | |
344 | } | |
345 | ||
41b74920 TH |
346 | netdev_tx_reset_queue(ring->tx_queue); |
347 | ||
c27a02cd | 348 | if (cnt) |
453a6082 | 349 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
350 | |
351 | return cnt; | |
352 | } | |
353 | ||
0276a330 EE |
354 | static int mlx4_en_process_tx_cq(struct net_device *dev, |
355 | struct mlx4_en_cq *cq, | |
356 | int budget) | |
c27a02cd YP |
357 | { |
358 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
359 | struct mlx4_cq *mcq = &cq->mcq; | |
41d942d5 | 360 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; |
f0ab34f0 | 361 | struct mlx4_cqe *cqe; |
c27a02cd | 362 | u16 index; |
2d4b6466 | 363 | u16 new_index, ring_index, stamp_index; |
c27a02cd | 364 | u32 txbbs_skipped = 0; |
2d4b6466 | 365 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
366 | u32 cons_index = mcq->cons_index; |
367 | int size = cq->size; | |
368 | u32 size_mask = ring->size_mask; | |
369 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
370 | u32 packets = 0; |
371 | u32 bytes = 0; | |
08ff3235 | 372 | int factor = priv->cqe_factor; |
ec693d47 | 373 | u64 timestamp = 0; |
0276a330 | 374 | int done = 0; |
c27a02cd YP |
375 | |
376 | if (!priv->port_up) | |
0276a330 | 377 | return 0; |
c27a02cd | 378 | |
f0ab34f0 | 379 | index = cons_index & size_mask; |
08ff3235 | 380 | cqe = &buf[(index << factor) + factor]; |
f0ab34f0 | 381 | ring_index = ring->cons & size_mask; |
2d4b6466 | 382 | stamp_index = ring_index; |
f0ab34f0 YP |
383 | |
384 | /* Process all completed CQEs */ | |
385 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 386 | cons_index & size) && (done < budget)) { |
f0ab34f0 YP |
387 | /* |
388 | * make sure we read the CQE after we read the | |
389 | * ownership bit | |
390 | */ | |
391 | rmb(); | |
392 | ||
bd2f631d AV |
393 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
394 | MLX4_CQE_OPCODE_ERROR)) { | |
395 | struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; | |
396 | ||
397 | en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", | |
398 | cqe_err->vendor_err_syndrome, | |
399 | cqe_err->syndrome); | |
400 | } | |
401 | ||
f0ab34f0 YP |
402 | /* Skip over last polled CQE */ |
403 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
404 | ||
c27a02cd | 405 | do { |
c27a02cd | 406 | txbbs_skipped += ring->last_nr_txbb; |
f0ab34f0 | 407 | ring_index = (ring_index + ring->last_nr_txbb) & size_mask; |
ec693d47 AV |
408 | if (ring->tx_info[ring_index].ts_requested) |
409 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
410 | ||
f0ab34f0 | 411 | /* free next descriptor */ |
c27a02cd | 412 | ring->last_nr_txbb = mlx4_en_free_tx_desc( |
f0ab34f0 YP |
413 | priv, ring, ring_index, |
414 | !!((ring->cons + txbbs_skipped) & | |
ec693d47 | 415 | ring->size), timestamp); |
2d4b6466 EE |
416 | |
417 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
418 | !!((ring->cons + txbbs_stamp) & | |
419 | ring->size)); | |
420 | stamp_index = ring_index; | |
421 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
422 | packets++; |
423 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 424 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
425 | |
426 | ++cons_index; | |
427 | index = cons_index & size_mask; | |
08ff3235 | 428 | cqe = &buf[(index << factor) + factor]; |
f0ab34f0 | 429 | } |
c27a02cd | 430 | |
c27a02cd YP |
431 | |
432 | /* | |
433 | * To prevent CQ overflow we first update CQ consumer and only then | |
434 | * the ring consumer. | |
435 | */ | |
f0ab34f0 | 436 | mcq->cons_index = cons_index; |
c27a02cd YP |
437 | mlx4_cq_set_ci(mcq); |
438 | wmb(); | |
439 | ring->cons += txbbs_skipped; | |
5b263f53 | 440 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 441 | |
c18520bd YP |
442 | /* |
443 | * Wakeup Tx queue if this stopped, and at least 1 packet | |
444 | * was completed | |
445 | */ | |
446 | if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) { | |
447 | netif_tx_wake_queue(ring->tx_queue); | |
15bffdff | 448 | ring->wake_queue++; |
c27a02cd | 449 | } |
0276a330 | 450 | return done; |
c27a02cd YP |
451 | } |
452 | ||
453 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
454 | { | |
455 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
456 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 457 | |
0276a330 EE |
458 | if (priv->port_up) |
459 | napi_schedule(&cq->napi); | |
460 | else | |
461 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
462 | } |
463 | ||
0276a330 EE |
464 | /* TX CQ polling - called by NAPI */ |
465 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
466 | { | |
467 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
468 | struct net_device *dev = cq->dev; | |
469 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
470 | int done; | |
471 | ||
472 | done = mlx4_en_process_tx_cq(dev, cq, budget); | |
473 | ||
474 | /* If we used up all the quota - we're probably not done yet... */ | |
475 | if (done < budget) { | |
476 | /* Done for now */ | |
477 | napi_complete(napi); | |
478 | mlx4_en_arm_cq(priv, cq); | |
479 | return done; | |
480 | } | |
481 | return budget; | |
482 | } | |
c27a02cd | 483 | |
c27a02cd YP |
484 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
485 | struct mlx4_en_tx_ring *ring, | |
486 | u32 index, | |
487 | unsigned int desc_size) | |
488 | { | |
489 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
490 | int i; | |
491 | ||
492 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
493 | if ((i & (TXBB_SIZE - 1)) == 0) | |
494 | wmb(); | |
495 | ||
496 | *((u32 *) (ring->buf + i)) = | |
497 | *((u32 *) (ring->bounce_buf + copy + i)); | |
498 | } | |
499 | ||
500 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
501 | if ((i & (TXBB_SIZE - 1)) == 0) | |
502 | wmb(); | |
503 | ||
504 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
505 | *((u32 *) (ring->bounce_buf + i)); | |
506 | } | |
507 | ||
508 | /* Return real descriptor location */ | |
509 | return ring->buf + index * TXBB_SIZE; | |
510 | } | |
511 | ||
b97b33a3 | 512 | static int is_inline(int inline_thold, struct sk_buff *skb, void **pfrag) |
c27a02cd YP |
513 | { |
514 | void *ptr; | |
515 | ||
516 | if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { | |
517 | if (skb_shinfo(skb)->nr_frags == 1) { | |
311761c8 | 518 | ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]); |
c27a02cd YP |
519 | if (unlikely(!ptr)) |
520 | return 0; | |
521 | ||
522 | if (pfrag) | |
523 | *pfrag = ptr; | |
524 | ||
525 | return 1; | |
526 | } else if (unlikely(skb_shinfo(skb)->nr_frags)) | |
527 | return 0; | |
528 | else | |
529 | return 1; | |
530 | } | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static int inline_size(struct sk_buff *skb) | |
536 | { | |
537 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
538 | <= MLX4_INLINE_ALIGN) | |
539 | return ALIGN(skb->len + CTRL_SIZE + | |
540 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
541 | else | |
542 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
543 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
544 | } | |
545 | ||
546 | static int get_real_size(struct sk_buff *skb, struct net_device *dev, | |
547 | int *lso_header_size) | |
548 | { | |
549 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
550 | int real_size; |
551 | ||
552 | if (skb_is_gso(skb)) { | |
837052d0 OG |
553 | if (skb->encapsulation) |
554 | *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); | |
555 | else | |
556 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
c27a02cd YP |
557 | real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + |
558 | ALIGN(*lso_header_size + 4, DS_SIZE); | |
559 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
560 | /* We add a segment for the skb linear buffer only if | |
561 | * it contains data */ | |
562 | if (*lso_header_size < skb_headlen(skb)) | |
563 | real_size += DS_SIZE; | |
564 | else { | |
565 | if (netif_msg_tx_err(priv)) | |
453a6082 | 566 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
567 | return 0; |
568 | } | |
569 | } | |
c27a02cd YP |
570 | } else { |
571 | *lso_header_size = 0; | |
b97b33a3 | 572 | if (!is_inline(priv->prof->inline_thold, skb, NULL)) |
c27a02cd YP |
573 | real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; |
574 | else | |
575 | real_size = inline_size(skb); | |
576 | } | |
577 | ||
578 | return real_size; | |
579 | } | |
580 | ||
581 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, | |
582 | int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) | |
583 | { | |
584 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
585 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
586 | ||
587 | if (skb->len <= spc) { | |
93591aaa EE |
588 | if (likely(skb->len >= MIN_PKT_LEN)) { |
589 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
590 | } else { | |
591 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); | |
592 | memset(((void *)(inl + 1)) + skb->len, 0, | |
593 | MIN_PKT_LEN - skb->len); | |
594 | } | |
c27a02cd YP |
595 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); |
596 | if (skb_shinfo(skb)->nr_frags) | |
597 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, | |
9e903e08 | 598 | skb_frag_size(&skb_shinfo(skb)->frags[0])); |
c27a02cd YP |
599 | |
600 | } else { | |
601 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
602 | if (skb_headlen(skb) <= spc) { | |
603 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
604 | if (skb_headlen(skb) < spc) { | |
605 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), | |
606 | fragptr, spc - skb_headlen(skb)); | |
607 | fragptr += spc - skb_headlen(skb); | |
608 | } | |
609 | inl = (void *) (inl + 1) + spc; | |
610 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
611 | } else { | |
612 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
613 | inl = (void *) (inl + 1) + spc; | |
614 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
615 | skb_headlen(skb) - spc); | |
616 | if (skb_shinfo(skb)->nr_frags) | |
617 | memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, | |
9e903e08 | 618 | fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0])); |
c27a02cd YP |
619 | } |
620 | ||
621 | wmb(); | |
622 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); | |
623 | } | |
c27a02cd YP |
624 | } |
625 | ||
f663dd9a | 626 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 627 | void *accel_priv, select_queue_fallback_t fallback) |
c27a02cd | 628 | { |
bc6a4744 | 629 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 630 | u16 rings_p_up = priv->num_tx_rings_p_up; |
bc6a4744 | 631 | u8 up = 0; |
c27a02cd | 632 | |
bc6a4744 AV |
633 | if (dev->num_tc) |
634 | return skb_tx_hash(dev, skb); | |
635 | ||
636 | if (vlan_tx_tag_present(skb)) | |
637 | up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT; | |
f813cad8 | 638 | |
99932d4f | 639 | return fallback(dev, skb) % rings_p_up + up * rings_p_up; |
c27a02cd YP |
640 | } |
641 | ||
966684d5 | 642 | static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt) |
87a5c389 YP |
643 | { |
644 | __iowrite64_copy(dst, src, bytecnt / 8); | |
645 | } | |
646 | ||
61357325 | 647 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd YP |
648 | { |
649 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
650 | struct mlx4_en_dev *mdev = priv->mdev; | |
237a3a3b | 651 | struct device *ddev = priv->ddev; |
c27a02cd | 652 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
653 | struct mlx4_en_tx_desc *tx_desc; |
654 | struct mlx4_wqe_data_seg *data; | |
c27a02cd YP |
655 | struct mlx4_en_tx_info *tx_info; |
656 | int tx_ind = 0; | |
657 | int nr_txbb; | |
658 | int desc_size; | |
659 | int real_size; | |
87a5c389 | 660 | u32 index, bf_index; |
c27a02cd | 661 | __be32 op_own; |
f813cad8 | 662 | u16 vlan_tag = 0; |
c27a02cd YP |
663 | int i; |
664 | int lso_header_size; | |
665 | void *fragptr; | |
87a5c389 | 666 | bool bounce = false; |
c27a02cd | 667 | |
3005ad40 YP |
668 | if (!priv->port_up) |
669 | goto tx_drop; | |
670 | ||
c27a02cd YP |
671 | real_size = get_real_size(skb, dev, &lso_header_size); |
672 | if (unlikely(!real_size)) | |
7e230913 | 673 | goto tx_drop; |
c27a02cd | 674 | |
25985edc | 675 | /* Align descriptor to TXBB size */ |
c27a02cd YP |
676 | desc_size = ALIGN(real_size, TXBB_SIZE); |
677 | nr_txbb = desc_size / TXBB_SIZE; | |
678 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
679 | if (netif_msg_tx_err(priv)) | |
453a6082 | 680 | en_warn(priv, "Oversized header or SG list\n"); |
7e230913 | 681 | goto tx_drop; |
c27a02cd YP |
682 | } |
683 | ||
f813cad8 | 684 | tx_ind = skb->queue_mapping; |
41d942d5 | 685 | ring = priv->tx_ring[tx_ind]; |
eab6d18d | 686 | if (vlan_tx_tag_present(skb)) |
f813cad8 | 687 | vlan_tag = vlan_tx_tag_get(skb); |
c27a02cd YP |
688 | |
689 | /* Check available TXBBs And 2K spare for prefetch */ | |
690 | if (unlikely(((int)(ring->prod - ring->cons)) > | |
691 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { | |
f813cad8 | 692 | /* every full Tx ring stops queue */ |
5b263f53 | 693 | netif_tx_stop_queue(ring->tx_queue); |
15bffdff | 694 | ring->queue_stopped++; |
c27a02cd | 695 | |
72259225 AV |
696 | /* If queue was emptied after the if, and before the |
697 | * stop_queue - need to wake the queue, or else it will remain | |
698 | * stopped forever. | |
699 | * Need a memory barrier to make sure ring->cons was not | |
700 | * updated before queue was stopped. | |
701 | */ | |
702 | wmb(); | |
703 | ||
704 | if (unlikely(((int)(ring->prod - ring->cons)) <= | |
705 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { | |
706 | netif_tx_wake_queue(ring->tx_queue); | |
15bffdff | 707 | ring->wake_queue++; |
72259225 AV |
708 | } else { |
709 | return NETDEV_TX_BUSY; | |
710 | } | |
c27a02cd YP |
711 | } |
712 | ||
c27a02cd YP |
713 | /* Track current inflight packets for performance analysis */ |
714 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
715 | (u32) (ring->prod - ring->cons - 1)); | |
716 | ||
717 | /* Packet is good - grab an index and transmit it */ | |
718 | index = ring->prod & ring->size_mask; | |
87a5c389 | 719 | bf_index = ring->prod; |
c27a02cd YP |
720 | |
721 | /* See if we have enough space for whole descriptor TXBB for setting | |
722 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
723 | if (likely(index + nr_txbb <= ring->size)) | |
724 | tx_desc = ring->buf + index * TXBB_SIZE; | |
87a5c389 | 725 | else { |
c27a02cd | 726 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 YP |
727 | bounce = true; |
728 | } | |
c27a02cd YP |
729 | |
730 | /* Save skb in tx_info ring */ | |
731 | tx_info = &ring->tx_info[index]; | |
732 | tx_info->skb = skb; | |
733 | tx_info->nr_txbb = nr_txbb; | |
734 | ||
237a3a3b AV |
735 | if (lso_header_size) |
736 | data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, | |
737 | DS_SIZE)); | |
738 | else | |
739 | data = &tx_desc->data; | |
740 | ||
741 | /* valid only for none inline segments */ | |
742 | tx_info->data_offset = (void *)data - (void *)tx_desc; | |
743 | ||
744 | tx_info->linear = (lso_header_size < skb_headlen(skb) && | |
b97b33a3 | 745 | !is_inline(ring->inline_thold, skb, NULL)) ? 1 : 0; |
237a3a3b AV |
746 | |
747 | data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; | |
748 | ||
b97b33a3 | 749 | if (is_inline(ring->inline_thold, skb, &fragptr)) { |
237a3a3b AV |
750 | tx_info->inl = 1; |
751 | } else { | |
752 | /* Map fragments */ | |
753 | for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { | |
5f1cd200 AV |
754 | struct skb_frag_struct *frag; |
755 | dma_addr_t dma; | |
756 | ||
237a3a3b AV |
757 | frag = &skb_shinfo(skb)->frags[i]; |
758 | dma = skb_frag_dma_map(ddev, frag, | |
759 | 0, skb_frag_size(frag), | |
760 | DMA_TO_DEVICE); | |
761 | if (dma_mapping_error(ddev, dma)) | |
762 | goto tx_drop_unmap; | |
763 | ||
764 | data->addr = cpu_to_be64(dma); | |
765 | data->lkey = cpu_to_be32(mdev->mr.key); | |
766 | wmb(); | |
767 | data->byte_count = cpu_to_be32(skb_frag_size(frag)); | |
768 | --data; | |
769 | } | |
770 | ||
771 | /* Map linear part */ | |
772 | if (tx_info->linear) { | |
773 | u32 byte_count = skb_headlen(skb) - lso_header_size; | |
5f1cd200 AV |
774 | dma_addr_t dma; |
775 | ||
237a3a3b AV |
776 | dma = dma_map_single(ddev, skb->data + |
777 | lso_header_size, byte_count, | |
778 | PCI_DMA_TODEVICE); | |
779 | if (dma_mapping_error(ddev, dma)) | |
780 | goto tx_drop_unmap; | |
781 | ||
782 | data->addr = cpu_to_be64(dma); | |
783 | data->lkey = cpu_to_be32(mdev->mr.key); | |
784 | wmb(); | |
785 | data->byte_count = cpu_to_be32(byte_count); | |
786 | } | |
787 | tx_info->inl = 0; | |
788 | } | |
789 | ||
ec693d47 AV |
790 | /* |
791 | * For timestamping add flag to skb_shinfo and | |
792 | * set flag for further reference | |
793 | */ | |
794 | if (ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && | |
795 | skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { | |
796 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
797 | tx_info->ts_requested = 1; | |
798 | } | |
799 | ||
c27a02cd YP |
800 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
801 | * whether LSO is used */ | |
802 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); | |
c140d769 AV |
803 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * |
804 | !!vlan_tx_tag_present(skb); | |
c27a02cd | 805 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; |
60d6fe99 | 806 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd YP |
807 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
808 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
809 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
ad04378c | 810 | ring->tx_csum++; |
c27a02cd YP |
811 | } |
812 | ||
79aeaccd | 813 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
814 | struct ethhdr *ethh; |
815 | ||
213815a1 YB |
816 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
817 | * so that VFs and PF can communicate with each other | |
818 | */ | |
819 | ethh = (struct ethhdr *)skb->data; | |
820 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
821 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
822 | } | |
823 | ||
c27a02cd YP |
824 | /* Handle LSO (TSO) packets */ |
825 | if (lso_header_size) { | |
826 | /* Mark opcode as LSO */ | |
827 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
828 | ((ring->prod & ring->size) ? | |
829 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
830 | ||
831 | /* Fill in the LSO prefix */ | |
832 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
833 | skb_shinfo(skb)->gso_size << 16 | lso_header_size); | |
834 | ||
835 | /* Copy headers; | |
836 | * note that we already verified that it is linear */ | |
837 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
c27a02cd YP |
838 | |
839 | priv->port_stats.tso_packets++; | |
840 | i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + | |
841 | !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); | |
5b263f53 | 842 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
843 | ring->packets += i; |
844 | } else { | |
845 | /* Normal (Non LSO) packet */ | |
846 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
847 | ((ring->prod & ring->size) ? | |
848 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 849 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd YP |
850 | ring->packets++; |
851 | ||
852 | } | |
5b263f53 YP |
853 | ring->bytes += tx_info->nr_bytes; |
854 | netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); | |
c27a02cd YP |
855 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
856 | ||
237a3a3b | 857 | if (tx_info->inl) { |
c27a02cd | 858 | build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); |
41efea5a YP |
859 | tx_info->inl = 1; |
860 | } | |
c27a02cd | 861 | |
837052d0 OG |
862 | if (skb->encapsulation) { |
863 | struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb); | |
864 | if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP) | |
865 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); | |
866 | else | |
867 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
868 | } | |
869 | ||
c27a02cd YP |
870 | ring->prod += nr_txbb; |
871 | ||
872 | /* If we used a bounce buffer then copy descriptor back into place */ | |
87a5c389 | 873 | if (bounce) |
c27a02cd YP |
874 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
875 | ||
eb0cabbd AV |
876 | skb_tx_timestamp(skb); |
877 | ||
2b39a061 | 878 | if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tx_tag_present(skb)) { |
ec570940 AV |
879 | tx_desc->ctrl.bf_qpn |= cpu_to_be32(ring->doorbell_qpn); |
880 | ||
87a5c389 YP |
881 | op_own |= htonl((bf_index & 0xffff) << 8); |
882 | /* Ensure new descirptor hits memory | |
883 | * before setting ownership of this descriptor to HW */ | |
884 | wmb(); | |
885 | tx_desc->ctrl.owner_opcode = op_own; | |
c27a02cd | 886 | |
87a5c389 YP |
887 | wmb(); |
888 | ||
889 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl, | |
890 | desc_size); | |
891 | ||
892 | wmb(); | |
893 | ||
894 | ring->bf.offset ^= ring->bf.buf_size; | |
895 | } else { | |
896 | /* Ensure new descirptor hits memory | |
897 | * before setting ownership of this descriptor to HW */ | |
898 | wmb(); | |
899 | tx_desc->ctrl.owner_opcode = op_own; | |
900 | wmb(); | |
c5d6136e | 901 | iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL); |
87a5c389 | 902 | } |
c27a02cd | 903 | |
ec634fe3 | 904 | return NETDEV_TX_OK; |
7e230913 | 905 | |
237a3a3b AV |
906 | tx_drop_unmap: |
907 | en_err(priv, "DMA mapping error\n"); | |
908 | ||
909 | for (i++; i < skb_shinfo(skb)->nr_frags; i++) { | |
910 | data++; | |
911 | dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), | |
912 | be32_to_cpu(data->byte_count), | |
913 | PCI_DMA_TODEVICE); | |
914 | } | |
915 | ||
7e230913 YP |
916 | tx_drop: |
917 | dev_kfree_skb_any(skb); | |
918 | priv->stats.tx_dropped++; | |
919 | return NETDEV_TX_OK; | |
c27a02cd YP |
920 | } |
921 |