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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
29d40c90 | 40 | #include <linux/prefetch.h> |
c27a02cd | 41 | #include <linux/vmalloc.h> |
fa37a958 | 42 | #include <linux/tcp.h> |
837052d0 | 43 | #include <linux/ip.h> |
09067122 | 44 | #include <linux/ipv6.h> |
6eb07caf | 45 | #include <linux/moduleparam.h> |
c27a02cd YP |
46 | |
47 | #include "mlx4_en.h" | |
48 | ||
c27a02cd | 49 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
ddae0349 | 50 | struct mlx4_en_tx_ring **pring, u32 size, |
d03a68f8 | 51 | u16 stride, int node, int queue_index) |
c27a02cd YP |
52 | { |
53 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 54 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
55 | int tmp; |
56 | int err; | |
57 | ||
163561a4 | 58 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 59 | if (!ring) { |
163561a4 EE |
60 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
61 | if (!ring) { | |
62 | en_err(priv, "Failed allocating TX ring\n"); | |
63 | return -ENOMEM; | |
64 | } | |
41d942d5 EE |
65 | } |
66 | ||
c27a02cd YP |
67 | ring->size = size; |
68 | ring->size_mask = size - 1; | |
e3f42f84 | 69 | ring->sp_stride = stride; |
488a9b48 | 70 | ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; |
c27a02cd | 71 | |
c27a02cd | 72 | tmp = size * sizeof(struct mlx4_en_tx_info); |
752ade68 | 73 | ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); |
41d942d5 | 74 | if (!ring->tx_info) { |
752ade68 MH |
75 | err = -ENOMEM; |
76 | goto err_ring; | |
41d942d5 | 77 | } |
e404decb | 78 | |
453a6082 | 79 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
80 | ring->tx_info, tmp); |
81 | ||
163561a4 | 82 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
c27a02cd | 83 | if (!ring->bounce_buf) { |
163561a4 EE |
84 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
85 | if (!ring->bounce_buf) { | |
86 | err = -ENOMEM; | |
87 | goto err_info; | |
88 | } | |
c27a02cd | 89 | } |
e3f42f84 | 90 | ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); |
c27a02cd | 91 | |
163561a4 | 92 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 93 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
e3f42f84 | 94 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
872bf2fb | 95 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 96 | if (err) { |
453a6082 | 97 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
98 | goto err_bounce; |
99 | } | |
100 | ||
e3f42f84 | 101 | ring->buf = ring->sp_wqres.buf.direct.buf; |
c27a02cd | 102 | |
1a91de28 JP |
103 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", |
104 | ring, ring->buf, ring->size, ring->buf_size, | |
e3f42f84 | 105 | (unsigned long long) ring->sp_wqres.buf.direct.map); |
c27a02cd | 106 | |
ddae0349 | 107 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, |
f3301870 MS |
108 | MLX4_RESERVE_ETH_BF_QP, |
109 | MLX4_RES_USAGE_DRIVER); | |
ddae0349 EE |
110 | if (err) { |
111 | en_err(priv, "failed reserving qp for TX ring\n"); | |
73898db0 | 112 | goto err_hwq_res; |
ddae0349 EE |
113 | } |
114 | ||
8900b894 | 115 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp); |
c27a02cd | 116 | if (err) { |
453a6082 | 117 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
ddae0349 | 118 | goto err_reserve; |
c27a02cd | 119 | } |
e3f42f84 | 120 | ring->sp_qp.event = mlx4_en_sqp_event; |
c27a02cd | 121 | |
163561a4 | 122 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 | 123 | if (err) { |
1a91de28 | 124 | en_dbg(DRV, priv, "working without blueflame (%d)\n", err); |
87a5c389 YP |
125 | ring->bf.uar = &mdev->priv_uar; |
126 | ring->bf.uar->map = mdev->uar_map; | |
127 | ring->bf_enabled = false; | |
0fef9d03 AV |
128 | ring->bf_alloced = false; |
129 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
130 | } else { | |
131 | ring->bf_alloced = true; | |
132 | ring->bf_enabled = !!(priv->pflags & | |
133 | MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
134 | } | |
87a5c389 | 135 | |
ec693d47 | 136 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
137 | ring->queue_index = queue_index; |
138 | ||
42eab005 | 139 | if (queue_index < priv->num_tx_rings_p_up) |
f36963c9 RR |
140 | cpumask_set_cpu(cpumask_local_spread(queue_index, |
141 | priv->mdev->dev->numa_node), | |
e3f42f84 | 142 | &ring->sp_affinity_mask); |
ec693d47 | 143 | |
41d942d5 | 144 | *pring = ring; |
c27a02cd YP |
145 | return 0; |
146 | ||
ddae0349 EE |
147 | err_reserve: |
148 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
c27a02cd | 149 | err_hwq_res: |
e3f42f84 | 150 | mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
c27a02cd YP |
151 | err_bounce: |
152 | kfree(ring->bounce_buf); | |
153 | ring->bounce_buf = NULL; | |
41d942d5 | 154 | err_info: |
dc9b06d1 | 155 | kvfree(ring->tx_info); |
c27a02cd | 156 | ring->tx_info = NULL; |
41d942d5 EE |
157 | err_ring: |
158 | kfree(ring); | |
159 | *pring = NULL; | |
c27a02cd YP |
160 | return err; |
161 | } | |
162 | ||
163 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 164 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
165 | { |
166 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 167 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 168 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 169 | |
0fef9d03 | 170 | if (ring->bf_alloced) |
87a5c389 | 171 | mlx4_bf_free(mdev->dev, &ring->bf); |
e3f42f84 ED |
172 | mlx4_qp_remove(mdev->dev, &ring->sp_qp); |
173 | mlx4_qp_free(mdev->dev, &ring->sp_qp); | |
0eb08514 | 174 | mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); |
e3f42f84 | 175 | mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
c27a02cd YP |
176 | kfree(ring->bounce_buf); |
177 | ring->bounce_buf = NULL; | |
dc9b06d1 | 178 | kvfree(ring->tx_info); |
c27a02cd | 179 | ring->tx_info = NULL; |
41d942d5 EE |
180 | kfree(ring); |
181 | *pring = NULL; | |
c27a02cd YP |
182 | } |
183 | ||
184 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
185 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 186 | int cq, int user_prio) |
c27a02cd YP |
187 | { |
188 | struct mlx4_en_dev *mdev = priv->mdev; | |
189 | int err; | |
190 | ||
e3f42f84 | 191 | ring->sp_cqn = cq; |
c27a02cd YP |
192 | ring->prod = 0; |
193 | ring->cons = 0xffffffff; | |
194 | ring->last_nr_txbb = 1; | |
c27a02cd YP |
195 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
196 | memset(ring->buf, 0, ring->buf_size); | |
9ecc2d86 | 197 | ring->free_tx_desc = mlx4_en_free_tx_desc; |
c27a02cd | 198 | |
e3f42f84 ED |
199 | ring->sp_qp_state = MLX4_QP_STATE_RST; |
200 | ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); | |
6a4e8121 | 201 | ring->mr_key = cpu_to_be32(mdev->mr.key); |
c27a02cd | 202 | |
e3f42f84 ED |
203 | mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, |
204 | ring->sp_cqn, user_prio, &ring->sp_context); | |
0fef9d03 | 205 | if (ring->bf_alloced) |
e3f42f84 | 206 | ring->sp_context.usr_page = |
85743f1e HN |
207 | cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, |
208 | ring->bf.uar->index)); | |
c27a02cd | 209 | |
e3f42f84 ED |
210 | err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, |
211 | &ring->sp_qp, &ring->sp_qp_state); | |
212 | if (!cpumask_empty(&ring->sp_affinity_mask)) | |
213 | netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, | |
d03a68f8 | 214 | ring->queue_index); |
c27a02cd YP |
215 | |
216 | return err; | |
217 | } | |
218 | ||
219 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
220 | struct mlx4_en_tx_ring *ring) | |
221 | { | |
222 | struct mlx4_en_dev *mdev = priv->mdev; | |
223 | ||
e3f42f84 ED |
224 | mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, |
225 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); | |
c27a02cd YP |
226 | } |
227 | ||
488a9b48 IS |
228 | static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) |
229 | { | |
230 | return ring->prod - ring->cons > ring->full_size; | |
231 | } | |
232 | ||
2d4b6466 EE |
233 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
234 | struct mlx4_en_tx_ring *ring, int index, | |
235 | u8 owner) | |
236 | { | |
237 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
9573e0d3 | 238 | struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
2d4b6466 EE |
239 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
240 | void *end = ring->buf + ring->buf_size; | |
241 | __be32 *ptr = (__be32 *)tx_desc; | |
242 | int i; | |
243 | ||
244 | /* Optimize the common case when there are no wraparounds */ | |
9573e0d3 TT |
245 | if (likely((void *)tx_desc + |
246 | (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { | |
2d4b6466 | 247 | /* Stamp the freed descriptor */ |
9573e0d3 | 248 | for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; |
2d4b6466 EE |
249 | i += STAMP_STRIDE) { |
250 | *ptr = stamp; | |
251 | ptr += STAMP_DWORDS; | |
252 | } | |
253 | } else { | |
254 | /* Stamp the freed descriptor */ | |
9573e0d3 | 255 | for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; |
2d4b6466 EE |
256 | i += STAMP_STRIDE) { |
257 | *ptr = stamp; | |
258 | ptr += STAMP_DWORDS; | |
259 | if ((void *)ptr >= end) { | |
260 | ptr = ring->buf; | |
261 | stamp ^= cpu_to_be32(0x80000000); | |
262 | } | |
263 | } | |
264 | } | |
265 | } | |
266 | ||
c27a02cd | 267 | |
9ecc2d86 BB |
268 | u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, |
269 | struct mlx4_en_tx_ring *ring, | |
cf97050d | 270 | int index, u64 timestamp, |
9ecc2d86 | 271 | int napi_mode) |
c27a02cd | 272 | { |
c27a02cd | 273 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
9573e0d3 | 274 | struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
c27a02cd | 275 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; |
c27a02cd | 276 | void *end = ring->buf + ring->buf_size; |
3d03641c ED |
277 | struct sk_buff *skb = tx_info->skb; |
278 | int nr_maps = tx_info->nr_maps; | |
c27a02cd | 279 | int i; |
ec693d47 | 280 | |
29d40c90 ED |
281 | /* We do not touch skb here, so prefetch skb->users location |
282 | * to speedup consume_skb() | |
283 | */ | |
284 | prefetchw(&skb->users); | |
285 | ||
3d03641c ED |
286 | if (unlikely(timestamp)) { |
287 | struct skb_shared_hwtstamps hwts; | |
288 | ||
289 | mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); | |
ec693d47 AV |
290 | skb_tstamp_tx(skb, &hwts); |
291 | } | |
c27a02cd | 292 | |
4c07c132 TT |
293 | if (!tx_info->inl) { |
294 | if (tx_info->linear) | |
295 | dma_unmap_single(priv->ddev, | |
296 | tx_info->map0_dma, | |
297 | tx_info->map0_byte_count, | |
298 | PCI_DMA_TODEVICE); | |
299 | else | |
300 | dma_unmap_page(priv->ddev, | |
301 | tx_info->map0_dma, | |
302 | tx_info->map0_byte_count, | |
303 | PCI_DMA_TODEVICE); | |
304 | /* Optimize the common case when there are no wraparounds */ | |
305 | if (likely((void *)tx_desc + | |
306 | (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { | |
3d03641c ED |
307 | for (i = 1; i < nr_maps; i++) { |
308 | data++; | |
ebf8c9aa | 309 | dma_unmap_page(priv->ddev, |
3d03641c ED |
310 | (dma_addr_t)be64_to_cpu(data->addr), |
311 | be32_to_cpu(data->byte_count), | |
312 | PCI_DMA_TODEVICE); | |
41efea5a | 313 | } |
4c07c132 TT |
314 | } else { |
315 | if ((void *)data >= end) | |
43d620c8 | 316 | data = ring->buf + ((void *)data - end); |
c27a02cd | 317 | |
3d03641c ED |
318 | for (i = 1; i < nr_maps; i++) { |
319 | data++; | |
41efea5a YP |
320 | /* Check for wraparound before unmapping */ |
321 | if ((void *) data >= end) | |
43d620c8 | 322 | data = ring->buf; |
ebf8c9aa | 323 | dma_unmap_page(priv->ddev, |
3d03641c ED |
324 | (dma_addr_t)be64_to_cpu(data->addr), |
325 | be32_to_cpu(data->byte_count), | |
326 | PCI_DMA_TODEVICE); | |
41efea5a | 327 | } |
c27a02cd | 328 | } |
c27a02cd | 329 | } |
b4a53379 JDB |
330 | napi_consume_skb(skb, napi_mode); |
331 | ||
c27a02cd YP |
332 | return tx_info->nr_txbb; |
333 | } | |
334 | ||
9ecc2d86 BB |
335 | u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, |
336 | struct mlx4_en_tx_ring *ring, | |
cf97050d | 337 | int index, u64 timestamp, |
9ecc2d86 BB |
338 | int napi_mode) |
339 | { | |
340 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
341 | struct mlx4_en_rx_alloc frame = { | |
342 | .page = tx_info->page, | |
343 | .dma = tx_info->map0_dma, | |
9ecc2d86 BB |
344 | }; |
345 | ||
346 | if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { | |
347 | dma_unmap_page(priv->ddev, tx_info->map0_dma, | |
69ba9431 | 348 | PAGE_SIZE, priv->dma_dir); |
9ecc2d86 BB |
349 | put_page(tx_info->page); |
350 | } | |
351 | ||
352 | return tx_info->nr_txbb; | |
353 | } | |
c27a02cd YP |
354 | |
355 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
356 | { | |
357 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
358 | int cnt = 0; | |
359 | ||
360 | /* Skip last polled descriptor */ | |
361 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 362 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
363 | ring->cons, ring->prod); |
364 | ||
365 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
366 | if (netif_msg_tx_err(priv)) | |
453a6082 | 367 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
368 | return 0; |
369 | } | |
370 | ||
371 | while (ring->cons != ring->prod) { | |
9ecc2d86 | 372 | ring->last_nr_txbb = ring->free_tx_desc(priv, ring, |
c27a02cd | 373 | ring->cons & ring->size_mask, |
cf97050d | 374 | 0, 0 /* Non-NAPI caller */); |
c27a02cd YP |
375 | ring->cons += ring->last_nr_txbb; |
376 | cnt++; | |
377 | } | |
378 | ||
67f8b1dc TT |
379 | if (ring->tx_queue) |
380 | netdev_tx_reset_queue(ring->tx_queue); | |
41b74920 | 381 | |
c27a02cd | 382 | if (cnt) |
453a6082 | 383 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
384 | |
385 | return cnt; | |
386 | } | |
387 | ||
6c78511b TT |
388 | bool mlx4_en_process_tx_cq(struct net_device *dev, |
389 | struct mlx4_en_cq *cq, int napi_budget) | |
c27a02cd YP |
390 | { |
391 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
392 | struct mlx4_cq *mcq = &cq->mcq; | |
67f8b1dc | 393 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; |
f0ab34f0 | 394 | struct mlx4_cqe *cqe; |
cc26a490 | 395 | u16 index, ring_index, stamp_index; |
c27a02cd | 396 | u32 txbbs_skipped = 0; |
2d4b6466 | 397 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
398 | u32 cons_index = mcq->cons_index; |
399 | int size = cq->size; | |
400 | u32 size_mask = ring->size_mask; | |
401 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
402 | u32 packets = 0; |
403 | u32 bytes = 0; | |
08ff3235 | 404 | int factor = priv->cqe_factor; |
0276a330 | 405 | int done = 0; |
fbc6daf1 | 406 | int budget = priv->tx_work_limit; |
fb1843ee ED |
407 | u32 last_nr_txbb; |
408 | u32 ring_cons; | |
c27a02cd | 409 | |
cc26a490 | 410 | if (unlikely(!priv->port_up)) |
fbc6daf1 | 411 | return true; |
c27a02cd | 412 | |
53511453 ED |
413 | netdev_txq_bql_complete_prefetchw(ring->tx_queue); |
414 | ||
f0ab34f0 | 415 | index = cons_index & size_mask; |
b1b6b4da | 416 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
6aa7de05 MR |
417 | last_nr_txbb = READ_ONCE(ring->last_nr_txbb); |
418 | ring_cons = READ_ONCE(ring->cons); | |
fb1843ee | 419 | ring_index = ring_cons & size_mask; |
2d4b6466 | 420 | stamp_index = ring_index; |
f0ab34f0 YP |
421 | |
422 | /* Process all completed CQEs */ | |
423 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 424 | cons_index & size) && (done < budget)) { |
cc26a490 TT |
425 | u16 new_index; |
426 | ||
f0ab34f0 YP |
427 | /* |
428 | * make sure we read the CQE after we read the | |
429 | * ownership bit | |
430 | */ | |
12b3375f | 431 | dma_rmb(); |
f0ab34f0 | 432 | |
bd2f631d AV |
433 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
434 | MLX4_CQE_OPCODE_ERROR)) { | |
435 | struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; | |
436 | ||
437 | en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", | |
438 | cqe_err->vendor_err_syndrome, | |
439 | cqe_err->syndrome); | |
440 | } | |
441 | ||
f0ab34f0 YP |
442 | /* Skip over last polled CQE */ |
443 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
444 | ||
c27a02cd | 445 | do { |
fc96256c ED |
446 | u64 timestamp = 0; |
447 | ||
fb1843ee ED |
448 | txbbs_skipped += last_nr_txbb; |
449 | ring_index = (ring_index + last_nr_txbb) & size_mask; | |
fc96256c ED |
450 | |
451 | if (unlikely(ring->tx_info[ring_index].ts_requested)) | |
ec693d47 AV |
452 | timestamp = mlx4_en_get_cqe_ts(cqe); |
453 | ||
f0ab34f0 | 454 | /* free next descriptor */ |
9ecc2d86 | 455 | last_nr_txbb = ring->free_tx_desc( |
f0ab34f0 | 456 | priv, ring, ring_index, |
cf97050d | 457 | timestamp, napi_budget); |
2d4b6466 EE |
458 | |
459 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
fb1843ee | 460 | !!((ring_cons + txbbs_stamp) & |
2d4b6466 EE |
461 | ring->size)); |
462 | stamp_index = ring_index; | |
463 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
464 | packets++; |
465 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 466 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
467 | |
468 | ++cons_index; | |
469 | index = cons_index & size_mask; | |
b1b6b4da | 470 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
f0ab34f0 | 471 | } |
c27a02cd | 472 | |
c27a02cd YP |
473 | /* |
474 | * To prevent CQ overflow we first update CQ consumer and only then | |
475 | * the ring consumer. | |
476 | */ | |
f0ab34f0 | 477 | mcq->cons_index = cons_index; |
c27a02cd YP |
478 | mlx4_cq_set_ci(mcq); |
479 | wmb(); | |
fb1843ee ED |
480 | |
481 | /* we want to dirty this cache line once */ | |
6aa7de05 MR |
482 | WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb); |
483 | WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped); | |
fb1843ee | 484 | |
cc26a490 | 485 | if (cq->type == TX_XDP) |
9ecc2d86 BB |
486 | return done < budget; |
487 | ||
5b263f53 | 488 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 489 | |
488a9b48 | 490 | /* Wakeup Tx queue if this stopped, and ring is not full. |
c18520bd | 491 | */ |
488a9b48 IS |
492 | if (netif_tx_queue_stopped(ring->tx_queue) && |
493 | !mlx4_en_is_tx_ring_full(ring)) { | |
c18520bd | 494 | netif_tx_wake_queue(ring->tx_queue); |
15bffdff | 495 | ring->wake_queue++; |
c27a02cd | 496 | } |
cc26a490 | 497 | |
fbc6daf1 | 498 | return done < budget; |
c27a02cd YP |
499 | } |
500 | ||
501 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
502 | { | |
503 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
504 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 505 | |
477b35b4 ED |
506 | if (likely(priv->port_up)) |
507 | napi_schedule_irqoff(&cq->napi); | |
0276a330 EE |
508 | else |
509 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
510 | } |
511 | ||
0276a330 EE |
512 | /* TX CQ polling - called by NAPI */ |
513 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
514 | { | |
515 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
516 | struct net_device *dev = cq->dev; | |
517 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
cc26a490 | 518 | bool clean_complete; |
0276a330 | 519 | |
b4a53379 | 520 | clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); |
fbc6daf1 AV |
521 | if (!clean_complete) |
522 | return budget; | |
0276a330 | 523 | |
fbc6daf1 AV |
524 | napi_complete(napi); |
525 | mlx4_en_arm_cq(priv, cq); | |
526 | ||
527 | return 0; | |
0276a330 | 528 | } |
c27a02cd | 529 | |
c27a02cd YP |
530 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
531 | struct mlx4_en_tx_ring *ring, | |
532 | u32 index, | |
533 | unsigned int desc_size) | |
534 | { | |
9573e0d3 | 535 | u32 copy = (ring->size - index) << LOG_TXBB_SIZE; |
c27a02cd YP |
536 | int i; |
537 | ||
538 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
539 | if ((i & (TXBB_SIZE - 1)) == 0) | |
540 | wmb(); | |
541 | ||
542 | *((u32 *) (ring->buf + i)) = | |
543 | *((u32 *) (ring->bounce_buf + copy + i)); | |
544 | } | |
545 | ||
546 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
547 | if ((i & (TXBB_SIZE - 1)) == 0) | |
548 | wmb(); | |
549 | ||
9573e0d3 | 550 | *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) = |
c27a02cd YP |
551 | *((u32 *) (ring->bounce_buf + i)); |
552 | } | |
553 | ||
554 | /* Return real descriptor location */ | |
9573e0d3 | 555 | return ring->buf + (index << LOG_TXBB_SIZE); |
c27a02cd YP |
556 | } |
557 | ||
acea73d6 ED |
558 | /* Decide if skb can be inlined in tx descriptor to avoid dma mapping |
559 | * | |
560 | * It seems strange we do not simply use skb_copy_bits(). | |
561 | * This would allow to inline all skbs iff skb->len <= inline_thold | |
562 | * | |
563 | * Note that caller already checked skb was not a gso packet | |
564 | */ | |
7dfa4b41 | 565 | static bool is_inline(int inline_thold, const struct sk_buff *skb, |
b9d8839a | 566 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 567 | void **pfrag) |
c27a02cd YP |
568 | { |
569 | void *ptr; | |
570 | ||
acea73d6 ED |
571 | if (skb->len > inline_thold || !inline_thold) |
572 | return false; | |
c27a02cd | 573 | |
acea73d6 ED |
574 | if (shinfo->nr_frags == 1) { |
575 | ptr = skb_frag_address_safe(&shinfo->frags[0]); | |
576 | if (unlikely(!ptr)) | |
577 | return false; | |
578 | *pfrag = ptr; | |
579 | return true; | |
c27a02cd | 580 | } |
acea73d6 ED |
581 | if (shinfo->nr_frags) |
582 | return false; | |
583 | return true; | |
c27a02cd YP |
584 | } |
585 | ||
7dfa4b41 | 586 | static int inline_size(const struct sk_buff *skb) |
c27a02cd YP |
587 | { |
588 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
589 | <= MLX4_INLINE_ALIGN) | |
590 | return ALIGN(skb->len + CTRL_SIZE + | |
591 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
592 | else | |
593 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
594 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
595 | } | |
596 | ||
7dfa4b41 | 597 | static int get_real_size(const struct sk_buff *skb, |
b9d8839a | 598 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 599 | struct net_device *dev, |
acea73d6 ED |
600 | int *lso_header_size, |
601 | bool *inline_ok, | |
602 | void **pfrag) | |
c27a02cd YP |
603 | { |
604 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
605 | int real_size; |
606 | ||
b9d8839a | 607 | if (shinfo->gso_size) { |
acea73d6 | 608 | *inline_ok = false; |
837052d0 OG |
609 | if (skb->encapsulation) |
610 | *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); | |
611 | else | |
612 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
b9d8839a | 613 | real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + |
c27a02cd YP |
614 | ALIGN(*lso_header_size + 4, DS_SIZE); |
615 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
616 | /* We add a segment for the skb linear buffer only if | |
617 | * it contains data */ | |
618 | if (*lso_header_size < skb_headlen(skb)) | |
619 | real_size += DS_SIZE; | |
620 | else { | |
621 | if (netif_msg_tx_err(priv)) | |
453a6082 | 622 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
623 | return 0; |
624 | } | |
625 | } | |
c27a02cd YP |
626 | } else { |
627 | *lso_header_size = 0; | |
acea73d6 ED |
628 | *inline_ok = is_inline(priv->prof->inline_thold, skb, |
629 | shinfo, pfrag); | |
630 | ||
631 | if (*inline_ok) | |
c27a02cd | 632 | real_size = inline_size(skb); |
acea73d6 ED |
633 | else |
634 | real_size = CTRL_SIZE + | |
635 | (shinfo->nr_frags + 1) * DS_SIZE; | |
c27a02cd YP |
636 | } |
637 | ||
638 | return real_size; | |
639 | } | |
640 | ||
7dfa4b41 ED |
641 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, |
642 | const struct sk_buff *skb, | |
b9d8839a | 643 | const struct skb_shared_info *shinfo, |
224e92e0 | 644 | void *fragptr) |
c27a02cd YP |
645 | { |
646 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
31975e27 | 647 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl); |
e533ac7e | 648 | unsigned int hlen = skb_headlen(skb); |
c27a02cd YP |
649 | |
650 | if (skb->len <= spc) { | |
93591aaa EE |
651 | if (likely(skb->len >= MIN_PKT_LEN)) { |
652 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
653 | } else { | |
654 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); | |
655 | memset(((void *)(inl + 1)) + skb->len, 0, | |
656 | MIN_PKT_LEN - skb->len); | |
657 | } | |
e533ac7e | 658 | skb_copy_from_linear_data(skb, inl + 1, hlen); |
b9d8839a | 659 | if (shinfo->nr_frags) |
e533ac7e | 660 | memcpy(((void *)(inl + 1)) + hlen, fragptr, |
b9d8839a | 661 | skb_frag_size(&shinfo->frags[0])); |
c27a02cd YP |
662 | |
663 | } else { | |
664 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
e533ac7e ED |
665 | if (hlen <= spc) { |
666 | skb_copy_from_linear_data(skb, inl + 1, hlen); | |
667 | if (hlen < spc) { | |
668 | memcpy(((void *)(inl + 1)) + hlen, | |
669 | fragptr, spc - hlen); | |
670 | fragptr += spc - hlen; | |
c27a02cd YP |
671 | } |
672 | inl = (void *) (inl + 1) + spc; | |
673 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
674 | } else { | |
675 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
676 | inl = (void *) (inl + 1) + spc; | |
677 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
e533ac7e | 678 | hlen - spc); |
b9d8839a | 679 | if (shinfo->nr_frags) |
e533ac7e | 680 | memcpy(((void *)(inl + 1)) + hlen - spc, |
b9d8839a ED |
681 | fragptr, |
682 | skb_frag_size(&shinfo->frags[0])); | |
c27a02cd YP |
683 | } |
684 | ||
12b3375f | 685 | dma_wmb(); |
c27a02cd YP |
686 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); |
687 | } | |
c27a02cd YP |
688 | } |
689 | ||
f663dd9a | 690 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 691 | void *accel_priv, select_queue_fallback_t fallback) |
c27a02cd | 692 | { |
bc6a4744 | 693 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 694 | u16 rings_p_up = priv->num_tx_rings_p_up; |
c27a02cd | 695 | |
4b5e5b7e | 696 | if (netdev_get_num_tc(dev)) |
bc6a4744 AV |
697 | return skb_tx_hash(dev, skb); |
698 | ||
ec327f7a | 699 | return fallback(dev, skb) % rings_p_up; |
c27a02cd YP |
700 | } |
701 | ||
7dfa4b41 ED |
702 | static void mlx4_bf_copy(void __iomem *dst, const void *src, |
703 | unsigned int bytecnt) | |
87a5c389 YP |
704 | { |
705 | __iowrite64_copy(dst, src, bytecnt / 8); | |
706 | } | |
707 | ||
224e92e0 BB |
708 | void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) |
709 | { | |
710 | wmb(); | |
711 | /* Since there is no iowrite*_native() that writes the | |
712 | * value as is, without byteswapping - using the one | |
713 | * the doesn't do byteswapping in the relevant arch | |
714 | * endianness. | |
715 | */ | |
716 | #if defined(__LITTLE_ENDIAN) | |
717 | iowrite32( | |
718 | #else | |
719 | iowrite32be( | |
720 | #endif | |
7ba5e7bd | 721 | (__force u32)ring->doorbell_qpn, |
224e92e0 BB |
722 | ring->bf.uar->map + MLX4_SEND_DOORBELL); |
723 | } | |
724 | ||
725 | static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, | |
726 | struct mlx4_en_tx_desc *tx_desc, | |
727 | union mlx4_wqe_qpn_vlan qpn_vlan, | |
728 | int desc_size, int bf_index, | |
729 | __be32 op_own, bool bf_ok, | |
730 | bool send_doorbell) | |
731 | { | |
732 | tx_desc->ctrl.qpn_vlan = qpn_vlan; | |
733 | ||
734 | if (bf_ok) { | |
735 | op_own |= htonl((bf_index & 0xffff) << 8); | |
736 | /* Ensure new descriptor hits memory | |
737 | * before setting ownership of this descriptor to HW | |
738 | */ | |
739 | dma_wmb(); | |
740 | tx_desc->ctrl.owner_opcode = op_own; | |
741 | ||
742 | wmb(); | |
743 | ||
744 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, | |
745 | desc_size); | |
746 | ||
747 | wmb(); | |
748 | ||
749 | ring->bf.offset ^= ring->bf.buf_size; | |
750 | } else { | |
751 | /* Ensure new descriptor hits memory | |
752 | * before setting ownership of this descriptor to HW | |
753 | */ | |
754 | dma_wmb(); | |
755 | tx_desc->ctrl.owner_opcode = op_own; | |
756 | if (send_doorbell) | |
757 | mlx4_en_xmit_doorbell(ring); | |
758 | else | |
759 | ring->xmit_more++; | |
760 | } | |
761 | } | |
762 | ||
f28186d6 TT |
763 | static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv, |
764 | struct skb_shared_info *shinfo, | |
765 | struct mlx4_wqe_data_seg *data, | |
766 | struct sk_buff *skb, | |
767 | int lso_header_size, | |
768 | __be32 mr_key, | |
769 | struct mlx4_en_tx_info *tx_info) | |
770 | { | |
771 | struct device *ddev = priv->ddev; | |
772 | dma_addr_t dma = 0; | |
773 | u32 byte_count = 0; | |
774 | int i_frag; | |
775 | ||
776 | /* Map fragments if any */ | |
777 | for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { | |
778 | const struct skb_frag_struct *frag; | |
779 | ||
780 | frag = &shinfo->frags[i_frag]; | |
781 | byte_count = skb_frag_size(frag); | |
782 | dma = skb_frag_dma_map(ddev, frag, | |
783 | 0, byte_count, | |
784 | DMA_TO_DEVICE); | |
785 | if (dma_mapping_error(ddev, dma)) | |
786 | goto tx_drop_unmap; | |
787 | ||
788 | data->addr = cpu_to_be64(dma); | |
789 | data->lkey = mr_key; | |
790 | dma_wmb(); | |
791 | data->byte_count = cpu_to_be32(byte_count); | |
792 | --data; | |
793 | } | |
794 | ||
795 | /* Map linear part if needed */ | |
796 | if (tx_info->linear) { | |
797 | byte_count = skb_headlen(skb) - lso_header_size; | |
798 | ||
799 | dma = dma_map_single(ddev, skb->data + | |
800 | lso_header_size, byte_count, | |
801 | PCI_DMA_TODEVICE); | |
802 | if (dma_mapping_error(ddev, dma)) | |
803 | goto tx_drop_unmap; | |
804 | ||
805 | data->addr = cpu_to_be64(dma); | |
806 | data->lkey = mr_key; | |
807 | dma_wmb(); | |
808 | data->byte_count = cpu_to_be32(byte_count); | |
809 | } | |
810 | /* tx completion can avoid cache line miss for common cases */ | |
811 | tx_info->map0_dma = dma; | |
812 | tx_info->map0_byte_count = byte_count; | |
813 | ||
814 | return true; | |
815 | ||
816 | tx_drop_unmap: | |
817 | en_err(priv, "DMA mapping error\n"); | |
818 | ||
819 | while (++i_frag < shinfo->nr_frags) { | |
820 | ++data; | |
821 | dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr), | |
822 | be32_to_cpu(data->byte_count), | |
823 | PCI_DMA_TODEVICE); | |
824 | } | |
825 | ||
826 | return false; | |
827 | } | |
828 | ||
61357325 | 829 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd | 830 | { |
b9d8839a | 831 | struct skb_shared_info *shinfo = skb_shinfo(skb); |
c27a02cd | 832 | struct mlx4_en_priv *priv = netdev_priv(dev); |
224e92e0 | 833 | union mlx4_wqe_qpn_vlan qpn_vlan = {}; |
c27a02cd | 834 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
835 | struct mlx4_en_tx_desc *tx_desc; |
836 | struct mlx4_wqe_data_seg *data; | |
c27a02cd | 837 | struct mlx4_en_tx_info *tx_info; |
f28186d6 | 838 | int tx_ind; |
c27a02cd YP |
839 | int nr_txbb; |
840 | int desc_size; | |
841 | int real_size; | |
87a5c389 | 842 | u32 index, bf_index; |
c27a02cd | 843 | __be32 op_own; |
c27a02cd | 844 | int lso_header_size; |
acea73d6 | 845 | void *fragptr = NULL; |
87a5c389 | 846 | bool bounce = false; |
5804283d | 847 | bool send_doorbell; |
fe971b95 | 848 | bool stop_queue; |
acea73d6 | 849 | bool inline_ok; |
f28186d6 | 850 | u8 data_offset; |
f905c79e | 851 | u32 ring_cons; |
224e92e0 | 852 | bool bf_ok; |
c27a02cd | 853 | |
f905c79e | 854 | tx_ind = skb_get_queue_mapping(skb); |
67f8b1dc | 855 | ring = priv->tx_ring[TX][tx_ind]; |
f905c79e | 856 | |
f28186d6 | 857 | if (unlikely(!priv->port_up)) |
63a664b7 ED |
858 | goto tx_drop; |
859 | ||
f905c79e | 860 | /* fetch ring->cons far ahead before needing it to avoid stall */ |
6aa7de05 | 861 | ring_cons = READ_ONCE(ring->cons); |
f905c79e | 862 | |
acea73d6 ED |
863 | real_size = get_real_size(skb, shinfo, dev, &lso_header_size, |
864 | &inline_ok, &fragptr); | |
c27a02cd | 865 | if (unlikely(!real_size)) |
7a61fc86 | 866 | goto tx_drop_count; |
c27a02cd | 867 | |
25985edc | 868 | /* Align descriptor to TXBB size */ |
c27a02cd | 869 | desc_size = ALIGN(real_size, TXBB_SIZE); |
9573e0d3 | 870 | nr_txbb = desc_size >> LOG_TXBB_SIZE; |
c27a02cd YP |
871 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { |
872 | if (netif_msg_tx_err(priv)) | |
453a6082 | 873 | en_warn(priv, "Oversized header or SG list\n"); |
7a61fc86 | 874 | goto tx_drop_count; |
c27a02cd YP |
875 | } |
876 | ||
224e92e0 | 877 | bf_ok = ring->bf_enabled; |
e38af4fa | 878 | if (skb_vlan_tag_present(skb)) { |
f28186d6 TT |
879 | u16 vlan_proto; |
880 | ||
224e92e0 | 881 | qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); |
e38af4fa | 882 | vlan_proto = be16_to_cpu(skb->vlan_proto); |
224e92e0 BB |
883 | if (vlan_proto == ETH_P_8021AD) |
884 | qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; | |
885 | else if (vlan_proto == ETH_P_8021Q) | |
886 | qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; | |
887 | else | |
888 | qpn_vlan.ins_vlan = 0; | |
889 | bf_ok = false; | |
e38af4fa | 890 | } |
c27a02cd | 891 | |
53511453 | 892 | netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); |
29d40c90 | 893 | |
c27a02cd YP |
894 | /* Track current inflight packets for performance analysis */ |
895 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
f905c79e | 896 | (u32)(ring->prod - ring_cons - 1)); |
c27a02cd YP |
897 | |
898 | /* Packet is good - grab an index and transmit it */ | |
899 | index = ring->prod & ring->size_mask; | |
87a5c389 | 900 | bf_index = ring->prod; |
c27a02cd YP |
901 | |
902 | /* See if we have enough space for whole descriptor TXBB for setting | |
903 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
904 | if (likely(index + nr_txbb <= ring->size)) | |
9573e0d3 | 905 | tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
87a5c389 | 906 | else { |
c27a02cd | 907 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 | 908 | bounce = true; |
224e92e0 | 909 | bf_ok = false; |
87a5c389 | 910 | } |
c27a02cd YP |
911 | |
912 | /* Save skb in tx_info ring */ | |
913 | tx_info = &ring->tx_info[index]; | |
914 | tx_info->skb = skb; | |
915 | tx_info->nr_txbb = nr_txbb; | |
916 | ||
f28186d6 TT |
917 | if (!lso_header_size) { |
918 | data = &tx_desc->data; | |
919 | data_offset = offsetof(struct mlx4_en_tx_desc, data); | |
920 | } else { | |
921 | int lso_align = ALIGN(lso_header_size + 4, DS_SIZE); | |
922 | ||
923 | data = (void *)&tx_desc->lso + lso_align; | |
924 | data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align; | |
925 | } | |
237a3a3b AV |
926 | |
927 | /* valid only for none inline segments */ | |
f28186d6 | 928 | tx_info->data_offset = data_offset; |
237a3a3b | 929 | |
acea73d6 ED |
930 | tx_info->inl = inline_ok; |
931 | ||
f28186d6 | 932 | tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok; |
237a3a3b | 933 | |
b9d8839a | 934 | tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; |
3d03641c | 935 | data += tx_info->nr_maps - 1; |
237a3a3b | 936 | |
f28186d6 TT |
937 | if (!tx_info->inl) |
938 | if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb, | |
939 | lso_header_size, ring->mr_key, | |
940 | tx_info)) | |
941 | goto tx_drop_count; | |
237a3a3b | 942 | |
ec693d47 AV |
943 | /* |
944 | * For timestamping add flag to skb_shinfo and | |
945 | * set flag for further reference | |
946 | */ | |
e70602a8 | 947 | tx_info->ts_requested = 0; |
7dfa4b41 ED |
948 | if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && |
949 | shinfo->tx_flags & SKBTX_HW_TSTAMP)) { | |
950 | shinfo->tx_flags |= SKBTX_IN_PROGRESS; | |
ec693d47 AV |
951 | tx_info->ts_requested = 1; |
952 | } | |
953 | ||
c27a02cd YP |
954 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
955 | * whether LSO is used */ | |
60d6fe99 | 956 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd | 957 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
a4f2dacb OG |
958 | if (!skb->encapsulation) |
959 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
960 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
961 | else | |
962 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); | |
ad04378c | 963 | ring->tx_csum++; |
c27a02cd YP |
964 | } |
965 | ||
79aeaccd | 966 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
967 | struct ethhdr *ethh; |
968 | ||
213815a1 YB |
969 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
970 | * so that VFs and PF can communicate with each other | |
971 | */ | |
972 | ethh = (struct ethhdr *)skb->data; | |
973 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
974 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
975 | } | |
976 | ||
c27a02cd YP |
977 | /* Handle LSO (TSO) packets */ |
978 | if (lso_header_size) { | |
b9d8839a ED |
979 | int i; |
980 | ||
c27a02cd YP |
981 | /* Mark opcode as LSO */ |
982 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
983 | ((ring->prod & ring->size) ? | |
984 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
985 | ||
986 | /* Fill in the LSO prefix */ | |
987 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
b9d8839a | 988 | shinfo->gso_size << 16 | lso_header_size); |
c27a02cd YP |
989 | |
990 | /* Copy headers; | |
991 | * note that we already verified that it is linear */ | |
992 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
c27a02cd | 993 | |
9fab426d | 994 | ring->tso_packets++; |
b9d8839a | 995 | |
75d04aa3 | 996 | i = shinfo->gso_segs; |
5b263f53 | 997 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
998 | ring->packets += i; |
999 | } else { | |
1000 | /* Normal (Non LSO) packet */ | |
1001 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
1002 | ((ring->prod & ring->size) ? | |
1003 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 1004 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd | 1005 | ring->packets++; |
c27a02cd | 1006 | } |
5b263f53 YP |
1007 | ring->bytes += tx_info->nr_bytes; |
1008 | netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); | |
c27a02cd YP |
1009 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
1010 | ||
acea73d6 | 1011 | if (tx_info->inl) |
224e92e0 | 1012 | build_inline_wqe(tx_desc, skb, shinfo, fragptr); |
c27a02cd | 1013 | |
837052d0 | 1014 | if (skb->encapsulation) { |
09067122 AD |
1015 | union { |
1016 | struct iphdr *v4; | |
1017 | struct ipv6hdr *v6; | |
1018 | unsigned char *hdr; | |
1019 | } ip; | |
1020 | u8 proto; | |
1021 | ||
1022 | ip.hdr = skb_inner_network_header(skb); | |
1023 | proto = (ip.v4->version == 4) ? ip.v4->protocol : | |
1024 | ip.v6->nexthdr; | |
1025 | ||
1026 | if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) | |
837052d0 OG |
1027 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); |
1028 | else | |
1029 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
1030 | } | |
1031 | ||
c27a02cd YP |
1032 | ring->prod += nr_txbb; |
1033 | ||
1034 | /* If we used a bounce buffer then copy descriptor back into place */ | |
7dfa4b41 | 1035 | if (unlikely(bounce)) |
c27a02cd YP |
1036 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
1037 | ||
eb0cabbd AV |
1038 | skb_tx_timestamp(skb); |
1039 | ||
fe971b95 | 1040 | /* Check available TXBBs And 2K spare for prefetch */ |
488a9b48 | 1041 | stop_queue = mlx4_en_is_tx_ring_full(ring); |
fe971b95 ED |
1042 | if (unlikely(stop_queue)) { |
1043 | netif_tx_stop_queue(ring->tx_queue); | |
1044 | ring->queue_stopped++; | |
1045 | } | |
5804283d ED |
1046 | send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); |
1047 | ||
6a4e8121 ED |
1048 | real_size = (real_size / 16) & 0x3f; |
1049 | ||
224e92e0 | 1050 | bf_ok &= desc_size <= MAX_BF && send_doorbell; |
e38af4fa | 1051 | |
224e92e0 BB |
1052 | if (bf_ok) |
1053 | qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); | |
1054 | else | |
1055 | qpn_vlan.fence_size = real_size; | |
7dfa4b41 | 1056 | |
224e92e0 BB |
1057 | mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, |
1058 | op_own, bf_ok, send_doorbell); | |
c27a02cd | 1059 | |
fe971b95 ED |
1060 | if (unlikely(stop_queue)) { |
1061 | /* If queue was emptied after the if (stop_queue) , and before | |
1062 | * the netif_tx_stop_queue() - need to wake the queue, | |
1063 | * or else it will remain stopped forever. | |
1064 | * Need a memory barrier to make sure ring->cons was not | |
1065 | * updated before queue was stopped. | |
1066 | */ | |
1067 | smp_rmb(); | |
1068 | ||
6aa7de05 | 1069 | ring_cons = READ_ONCE(ring->cons); |
488a9b48 | 1070 | if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { |
fe971b95 ED |
1071 | netif_tx_wake_queue(ring->tx_queue); |
1072 | ring->wake_queue++; | |
1073 | } | |
1074 | } | |
ec634fe3 | 1075 | return NETDEV_TX_OK; |
7e230913 | 1076 | |
7a61fc86 MS |
1077 | tx_drop_count: |
1078 | ring->tx_dropped++; | |
7e230913 YP |
1079 | tx_drop: |
1080 | dev_kfree_skb_any(skb); | |
7e230913 | 1081 | return NETDEV_TX_OK; |
c27a02cd YP |
1082 | } |
1083 | ||
36ea7964 TT |
1084 | #define MLX4_EN_XDP_TX_NRTXBB 1 |
1085 | #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \ | |
1086 | / 16) & 0x3f) | |
1087 | ||
f025fd60 TT |
1088 | void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, |
1089 | struct mlx4_en_tx_ring *ring) | |
1090 | { | |
1091 | int i; | |
1092 | ||
1093 | for (i = 0; i < ring->size; i++) { | |
1094 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[i]; | |
1095 | struct mlx4_en_tx_desc *tx_desc = ring->buf + | |
1096 | (i << LOG_TXBB_SIZE); | |
1097 | ||
1098 | tx_info->map0_byte_count = PAGE_SIZE; | |
1099 | tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB; | |
1100 | tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data); | |
1101 | tx_info->ts_requested = 0; | |
1102 | tx_info->nr_maps = 1; | |
1103 | tx_info->linear = 1; | |
1104 | tx_info->inl = 0; | |
1105 | ||
1106 | tx_desc->data.lkey = ring->mr_key; | |
1107 | tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ; | |
1108 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; | |
1109 | } | |
1110 | } | |
1111 | ||
15fca2c8 TT |
1112 | netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, |
1113 | struct mlx4_en_rx_alloc *frame, | |
5dad61b8 | 1114 | struct mlx4_en_priv *priv, unsigned int length, |
36ea7964 | 1115 | int tx_ind, bool *doorbell_pending) |
9ecc2d86 | 1116 | { |
9ecc2d86 | 1117 | struct mlx4_en_tx_desc *tx_desc; |
9ecc2d86 | 1118 | struct mlx4_en_tx_info *tx_info; |
36ea7964 TT |
1119 | struct mlx4_wqe_data_seg *data; |
1120 | struct mlx4_en_tx_ring *ring; | |
9ecc2d86 | 1121 | dma_addr_t dma; |
9ecc2d86 | 1122 | __be32 op_own; |
36ea7964 | 1123 | int index; |
9ecc2d86 | 1124 | |
36ea7964 TT |
1125 | if (unlikely(!priv->port_up)) |
1126 | goto tx_drop; | |
9ecc2d86 | 1127 | |
67f8b1dc | 1128 | ring = priv->tx_ring[TX_XDP][tx_ind]; |
9ecc2d86 | 1129 | |
36ea7964 | 1130 | if (unlikely(mlx4_en_is_tx_ring_full(ring))) |
7a61fc86 | 1131 | goto tx_drop_count; |
9ecc2d86 | 1132 | |
9ecc2d86 BB |
1133 | index = ring->prod & ring->size_mask; |
1134 | tx_info = &ring->tx_info[index]; | |
1135 | ||
9ecc2d86 BB |
1136 | /* Track current inflight packets for performance analysis */ |
1137 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
36ea7964 | 1138 | (u32)(ring->prod - READ_ONCE(ring->cons) - 1)); |
9ecc2d86 | 1139 | |
9573e0d3 | 1140 | tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
9ecc2d86 BB |
1141 | data = &tx_desc->data; |
1142 | ||
1143 | dma = frame->dma; | |
1144 | ||
1145 | tx_info->page = frame->page; | |
1146 | frame->page = NULL; | |
1147 | tx_info->map0_dma = dma; | |
9ecc2d86 | 1148 | tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); |
9ecc2d86 | 1149 | |
ea3349a0 MKL |
1150 | dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, |
1151 | length, PCI_DMA_TODEVICE); | |
9ecc2d86 | 1152 | |
ea3349a0 | 1153 | data->addr = cpu_to_be64(dma + frame->page_offset); |
9ecc2d86 BB |
1154 | dma_wmb(); |
1155 | data->byte_count = cpu_to_be32(length); | |
1156 | ||
1157 | /* tx completion can avoid cache line miss for common cases */ | |
9ecc2d86 BB |
1158 | |
1159 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
1160 | ((ring->prod & ring->size) ? | |
1161 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
1162 | ||
15fca2c8 | 1163 | rx_ring->xdp_tx++; |
9ecc2d86 BB |
1164 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length); |
1165 | ||
36ea7964 | 1166 | ring->prod += MLX4_EN_XDP_TX_NRTXBB; |
9ecc2d86 | 1167 | |
f6f0aa97 TT |
1168 | /* Ensure new descriptor hits memory |
1169 | * before setting ownership of this descriptor to HW | |
1170 | */ | |
1171 | dma_wmb(); | |
1172 | tx_desc->ctrl.owner_opcode = op_own; | |
1173 | ring->xmit_more++; | |
9ecc2d86 | 1174 | |
36ea7964 | 1175 | *doorbell_pending = true; |
9ecc2d86 BB |
1176 | |
1177 | return NETDEV_TX_OK; | |
1178 | ||
7a61fc86 | 1179 | tx_drop_count: |
15fca2c8 | 1180 | rx_ring->xdp_tx_full++; |
6c78511b | 1181 | *doorbell_pending = true; |
7a61fc86 | 1182 | tx_drop: |
9ecc2d86 BB |
1183 | return NETDEV_TX_BUSY; |
1184 | } |