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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
51a379d0 | 4 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
5 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/errno.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 41 | #include <linux/slab.h> |
c1b43dca | 42 | #include <linux/io-mapping.h> |
ab9c17a0 | 43 | #include <linux/delay.h> |
b046ffe5 | 44 | #include <linux/kmod.h> |
225c7b1f RD |
45 | |
46 | #include <linux/mlx4/device.h> | |
47 | #include <linux/mlx4/doorbell.h> | |
48 | ||
49 | #include "mlx4.h" | |
50 | #include "fw.h" | |
51 | #include "icm.h" | |
52 | ||
53 | MODULE_AUTHOR("Roland Dreier"); | |
54 | MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); | |
55 | MODULE_LICENSE("Dual BSD/GPL"); | |
56 | MODULE_VERSION(DRV_VERSION); | |
57 | ||
27bf91d6 YP |
58 | struct workqueue_struct *mlx4_wq; |
59 | ||
225c7b1f RD |
60 | #ifdef CONFIG_MLX4_DEBUG |
61 | ||
62 | int mlx4_debug_level = 0; | |
63 | module_param_named(debug_level, mlx4_debug_level, int, 0644); | |
64 | MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); | |
65 | ||
66 | #endif /* CONFIG_MLX4_DEBUG */ | |
67 | ||
68 | #ifdef CONFIG_PCI_MSI | |
69 | ||
08fb1055 | 70 | static int msi_x = 1; |
225c7b1f RD |
71 | module_param(msi_x, int, 0444); |
72 | MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); | |
73 | ||
74 | #else /* CONFIG_PCI_MSI */ | |
75 | ||
76 | #define msi_x (0) | |
77 | ||
78 | #endif /* CONFIG_PCI_MSI */ | |
79 | ||
dd41cc3b | 80 | static uint8_t num_vfs[3] = {0, 0, 0}; |
effa4bc4 | 81 | static int num_vfs_argc; |
dd41cc3b MB |
82 | module_param_array(num_vfs, byte , &num_vfs_argc, 0444); |
83 | MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" | |
84 | "num_vfs=port1,port2,port1+2"); | |
85 | ||
86 | static uint8_t probe_vf[3] = {0, 0, 0}; | |
effa4bc4 | 87 | static int probe_vfs_argc; |
dd41cc3b MB |
88 | module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); |
89 | MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" | |
90 | "probe_vf=port1,port2,port1+2"); | |
ab9c17a0 | 91 | |
3c439b55 | 92 | int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; |
0ec2c0f8 EE |
93 | module_param_named(log_num_mgm_entry_size, |
94 | mlx4_log_num_mgm_entry_size, int, 0444); | |
95 | MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" | |
96 | " of qp per mcg, for example:" | |
3c439b55 | 97 | " 10 gives 248.range: 7 <=" |
0ff1fb65 | 98 | " log_num_mgm_entry_size <= 12." |
3c439b55 JM |
99 | " To activate device managed" |
100 | " flow steering when available, set to -1"); | |
0ec2c0f8 | 101 | |
be902ab1 | 102 | static bool enable_64b_cqe_eqe = true; |
08ff3235 OG |
103 | module_param(enable_64b_cqe_eqe, bool, 0444); |
104 | MODULE_PARM_DESC(enable_64b_cqe_eqe, | |
be902ab1 | 105 | "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); |
08ff3235 | 106 | |
77507aa2 IS |
107 | #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ |
108 | MLX4_FUNC_CAP_EQE_CQE_STRIDE) | |
ab9c17a0 | 109 | |
f57e6848 | 110 | static char mlx4_version[] = |
225c7b1f RD |
111 | DRV_NAME ": Mellanox ConnectX core driver v" |
112 | DRV_VERSION " (" DRV_RELDATE ")\n"; | |
113 | ||
114 | static struct mlx4_profile default_profile = { | |
ab9c17a0 | 115 | .num_qp = 1 << 18, |
225c7b1f | 116 | .num_srq = 1 << 16, |
c9f2ba5e | 117 | .rdmarc_per_qp = 1 << 4, |
225c7b1f RD |
118 | .num_cq = 1 << 16, |
119 | .num_mcg = 1 << 13, | |
ab9c17a0 | 120 | .num_mpt = 1 << 19, |
9fd7a1e1 | 121 | .num_mtt = 1 << 20, /* It is really num mtt segements */ |
225c7b1f RD |
122 | }; |
123 | ||
2599d858 AV |
124 | static struct mlx4_profile low_mem_profile = { |
125 | .num_qp = 1 << 17, | |
126 | .num_srq = 1 << 6, | |
127 | .rdmarc_per_qp = 1 << 4, | |
128 | .num_cq = 1 << 8, | |
129 | .num_mcg = 1 << 8, | |
130 | .num_mpt = 1 << 9, | |
131 | .num_mtt = 1 << 7, | |
132 | }; | |
133 | ||
ab9c17a0 | 134 | static int log_num_mac = 7; |
93fc9e1b YP |
135 | module_param_named(log_num_mac, log_num_mac, int, 0444); |
136 | MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); | |
137 | ||
138 | static int log_num_vlan; | |
139 | module_param_named(log_num_vlan, log_num_vlan, int, 0444); | |
140 | MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); | |
cb29688a OG |
141 | /* Log2 max number of VLANs per ETH port (0-7) */ |
142 | #define MLX4_LOG_NUM_VLANS 7 | |
2599d858 AV |
143 | #define MLX4_MIN_LOG_NUM_VLANS 0 |
144 | #define MLX4_MIN_LOG_NUM_MAC 1 | |
93fc9e1b | 145 | |
eb939922 | 146 | static bool use_prio; |
93fc9e1b | 147 | module_param_named(use_prio, use_prio, bool, 0444); |
ecc8fb11 | 148 | MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); |
93fc9e1b | 149 | |
2b8fb286 | 150 | int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); |
ab6bf42e | 151 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); |
0498628f | 152 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); |
ab6bf42e | 153 | |
8d0fc7b6 | 154 | static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; |
ab9c17a0 JM |
155 | static int arr_argc = 2; |
156 | module_param_array(port_type_array, int, &arr_argc, 0444); | |
8d0fc7b6 YP |
157 | MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " |
158 | "1 for IB, 2 for Ethernet"); | |
ab9c17a0 JM |
159 | |
160 | struct mlx4_port_config { | |
161 | struct list_head list; | |
162 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; | |
163 | struct pci_dev *pdev; | |
164 | }; | |
165 | ||
97989356 AV |
166 | static atomic_t pf_loading = ATOMIC_INIT(0); |
167 | ||
27bf91d6 YP |
168 | int mlx4_check_port_params(struct mlx4_dev *dev, |
169 | enum mlx4_port_type *port_type) | |
7ff93f8b YP |
170 | { |
171 | int i; | |
172 | ||
173 | for (i = 0; i < dev->caps.num_ports - 1; i++) { | |
27bf91d6 YP |
174 | if (port_type[i] != port_type[i + 1]) { |
175 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { | |
1a91de28 | 176 | mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); |
27bf91d6 YP |
177 | return -EINVAL; |
178 | } | |
7ff93f8b YP |
179 | } |
180 | } | |
7ff93f8b YP |
181 | |
182 | for (i = 0; i < dev->caps.num_ports; i++) { | |
183 | if (!(port_type[i] & dev->caps.supported_type[i+1])) { | |
1a91de28 JP |
184 | mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", |
185 | i + 1); | |
7ff93f8b YP |
186 | return -EINVAL; |
187 | } | |
188 | } | |
189 | return 0; | |
190 | } | |
191 | ||
192 | static void mlx4_set_port_mask(struct mlx4_dev *dev) | |
193 | { | |
194 | int i; | |
195 | ||
7ff93f8b | 196 | for (i = 1; i <= dev->caps.num_ports; ++i) |
65dab25d | 197 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
7ff93f8b | 198 | } |
f2a3f6a3 | 199 | |
7ae0e400 MB |
200 | enum { |
201 | MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, | |
202 | }; | |
203 | ||
204 | static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |
205 | { | |
206 | int err = 0; | |
207 | struct mlx4_func func; | |
208 | ||
209 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { | |
210 | err = mlx4_QUERY_FUNC(dev, &func, 0); | |
211 | if (err) { | |
212 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
213 | return err; | |
214 | } | |
215 | dev_cap->max_eqs = func.max_eq; | |
216 | dev_cap->reserved_eqs = func.rsvd_eqs; | |
217 | dev_cap->reserved_uars = func.rsvd_uars; | |
218 | err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; | |
219 | } | |
220 | return err; | |
221 | } | |
222 | ||
77507aa2 IS |
223 | static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) |
224 | { | |
225 | struct mlx4_caps *dev_cap = &dev->caps; | |
226 | ||
227 | /* FW not supporting or cancelled by user */ | |
228 | if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || | |
229 | !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) | |
230 | return; | |
231 | ||
232 | /* Must have 64B CQE_EQE enabled by FW to use bigger stride | |
233 | * When FW has NCSI it may decide not to report 64B CQE/EQEs | |
234 | */ | |
235 | if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || | |
236 | !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { | |
237 | dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; | |
238 | dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; | |
239 | return; | |
240 | } | |
241 | ||
242 | if (cache_line_size() == 128 || cache_line_size() == 256) { | |
243 | mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); | |
244 | /* Changing the real data inside CQE size to 32B */ | |
245 | dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; | |
246 | dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; | |
247 | ||
248 | if (mlx4_is_master(dev)) | |
249 | dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; | |
250 | } else { | |
251 | mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n"); | |
252 | dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; | |
253 | dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; | |
254 | } | |
255 | } | |
256 | ||
3d73c288 | 257 | static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
225c7b1f RD |
258 | { |
259 | int err; | |
5ae2a7a8 | 260 | int i; |
225c7b1f RD |
261 | |
262 | err = mlx4_QUERY_DEV_CAP(dev, dev_cap); | |
263 | if (err) { | |
1a91de28 | 264 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
225c7b1f RD |
265 | return err; |
266 | } | |
267 | ||
268 | if (dev_cap->min_page_sz > PAGE_SIZE) { | |
1a91de28 | 269 | mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", |
225c7b1f RD |
270 | dev_cap->min_page_sz, PAGE_SIZE); |
271 | return -ENODEV; | |
272 | } | |
273 | if (dev_cap->num_ports > MLX4_MAX_PORTS) { | |
1a91de28 | 274 | mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", |
225c7b1f RD |
275 | dev_cap->num_ports, MLX4_MAX_PORTS); |
276 | return -ENODEV; | |
277 | } | |
278 | ||
279 | if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { | |
1a91de28 | 280 | mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", |
225c7b1f RD |
281 | dev_cap->uar_size, |
282 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
283 | return -ENODEV; | |
284 | } | |
285 | ||
286 | dev->caps.num_ports = dev_cap->num_ports; | |
7ae0e400 MB |
287 | dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; |
288 | dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? | |
289 | dev->caps.num_sys_eqs : | |
290 | MLX4_MAX_EQ_NUM; | |
5ae2a7a8 RD |
291 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
292 | dev->caps.vl_cap[i] = dev_cap->max_vl[i]; | |
b79acb49 | 293 | dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; |
6634961c JM |
294 | dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; |
295 | dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; | |
296 | /* set gid and pkey table operating lengths by default | |
297 | * to non-sriov values */ | |
5ae2a7a8 RD |
298 | dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; |
299 | dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; | |
300 | dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; | |
b79acb49 YP |
301 | dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; |
302 | dev->caps.def_mac[i] = dev_cap->def_mac[i]; | |
7ff93f8b | 303 | dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; |
8d0fc7b6 YP |
304 | dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; |
305 | dev->caps.default_sense[i] = dev_cap->default_sense[i]; | |
7699517d YP |
306 | dev->caps.trans_type[i] = dev_cap->trans_type[i]; |
307 | dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; | |
308 | dev->caps.wavelength[i] = dev_cap->wavelength[i]; | |
309 | dev->caps.trans_code[i] = dev_cap->trans_code[i]; | |
5ae2a7a8 RD |
310 | } |
311 | ||
ab9c17a0 | 312 | dev->caps.uar_page_size = PAGE_SIZE; |
225c7b1f | 313 | dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; |
225c7b1f RD |
314 | dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; |
315 | dev->caps.bf_reg_size = dev_cap->bf_reg_size; | |
316 | dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; | |
317 | dev->caps.max_sq_sg = dev_cap->max_sq_sg; | |
318 | dev->caps.max_rq_sg = dev_cap->max_rq_sg; | |
319 | dev->caps.max_wqes = dev_cap->max_qp_sz; | |
320 | dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; | |
225c7b1f RD |
321 | dev->caps.max_srq_wqes = dev_cap->max_srq_sz; |
322 | dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; | |
323 | dev->caps.reserved_srqs = dev_cap->reserved_srqs; | |
324 | dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; | |
325 | dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; | |
225c7b1f RD |
326 | /* |
327 | * Subtract 1 from the limit because we need to allocate a | |
328 | * spare CQE so the HCA HW can tell the difference between an | |
329 | * empty CQ and a full CQ. | |
330 | */ | |
331 | dev->caps.max_cqes = dev_cap->max_cq_sz - 1; | |
332 | dev->caps.reserved_cqs = dev_cap->reserved_cqs; | |
333 | dev->caps.reserved_eqs = dev_cap->reserved_eqs; | |
2b8fb286 | 334 | dev->caps.reserved_mtts = dev_cap->reserved_mtts; |
225c7b1f | 335 | dev->caps.reserved_mrws = dev_cap->reserved_mrws; |
ab9c17a0 JM |
336 | |
337 | /* The first 128 UARs are used for EQ doorbells */ | |
338 | dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); | |
225c7b1f | 339 | dev->caps.reserved_pds = dev_cap->reserved_pds; |
012a8ff5 SH |
340 | dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? |
341 | dev_cap->reserved_xrcds : 0; | |
342 | dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? | |
343 | dev_cap->max_xrcds : 0; | |
2b8fb286 MA |
344 | dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; |
345 | ||
149983af | 346 | dev->caps.max_msg_sz = dev_cap->max_msg_sz; |
225c7b1f RD |
347 | dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); |
348 | dev->caps.flags = dev_cap->flags; | |
b3416f44 | 349 | dev->caps.flags2 = dev_cap->flags2; |
95d04f07 RD |
350 | dev->caps.bmme_flags = dev_cap->bmme_flags; |
351 | dev->caps.reserved_lkey = dev_cap->reserved_lkey; | |
225c7b1f | 352 | dev->caps.stat_rate_support = dev_cap->stat_rate_support; |
b832be1e | 353 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; |
b3416f44 | 354 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; |
225c7b1f | 355 | |
ca3e57a5 RD |
356 | /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ |
357 | if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) | |
58a60168 | 358 | dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; |
aadf4f3f RD |
359 | /* Don't do sense port on multifunction devices (for now at least) */ |
360 | if (mlx4_is_mfunc(dev)) | |
361 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; | |
58a60168 | 362 | |
2599d858 AV |
363 | if (mlx4_low_memory_profile()) { |
364 | dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; | |
365 | dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; | |
366 | } else { | |
367 | dev->caps.log_num_macs = log_num_mac; | |
368 | dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; | |
369 | } | |
93fc9e1b YP |
370 | |
371 | for (i = 1; i <= dev->caps.num_ports; ++i) { | |
ab9c17a0 JM |
372 | dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; |
373 | if (dev->caps.supported_type[i]) { | |
374 | /* if only ETH is supported - assign ETH */ | |
375 | if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) | |
376 | dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; | |
105c320f | 377 | /* if only IB is supported, assign IB */ |
ab9c17a0 | 378 | else if (dev->caps.supported_type[i] == |
105c320f JM |
379 | MLX4_PORT_TYPE_IB) |
380 | dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 381 | else { |
105c320f JM |
382 | /* if IB and ETH are supported, we set the port |
383 | * type according to user selection of port type; | |
384 | * if user selected none, take the FW hint */ | |
385 | if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) | |
8d0fc7b6 YP |
386 | dev->caps.port_type[i] = dev->caps.suggested_type[i] ? |
387 | MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 388 | else |
105c320f | 389 | dev->caps.port_type[i] = port_type_array[i - 1]; |
ab9c17a0 JM |
390 | } |
391 | } | |
8d0fc7b6 YP |
392 | /* |
393 | * Link sensing is allowed on the port if 3 conditions are true: | |
394 | * 1. Both protocols are supported on the port. | |
395 | * 2. Different types are supported on the port | |
396 | * 3. FW declared that it supports link sensing | |
397 | */ | |
27bf91d6 | 398 | mlx4_priv(dev)->sense.sense_allowed[i] = |
58a60168 | 399 | ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && |
8d0fc7b6 | 400 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
58a60168 | 401 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); |
7ff93f8b | 402 | |
8d0fc7b6 YP |
403 | /* |
404 | * If "default_sense" bit is set, we move the port to "AUTO" mode | |
405 | * and perform sense_port FW command to try and set the correct | |
406 | * port type from beginning | |
407 | */ | |
46c46747 | 408 | if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { |
8d0fc7b6 YP |
409 | enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; |
410 | dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; | |
411 | mlx4_SENSE_PORT(dev, i, &sensed_port); | |
412 | if (sensed_port != MLX4_PORT_TYPE_NONE) | |
413 | dev->caps.port_type[i] = sensed_port; | |
414 | } else { | |
415 | dev->caps.possible_type[i] = dev->caps.port_type[i]; | |
416 | } | |
417 | ||
93fc9e1b YP |
418 | if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { |
419 | dev->caps.log_num_macs = dev_cap->log_max_macs[i]; | |
1a91de28 | 420 | mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", |
93fc9e1b YP |
421 | i, 1 << dev->caps.log_num_macs); |
422 | } | |
423 | if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { | |
424 | dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; | |
1a91de28 | 425 | mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", |
93fc9e1b YP |
426 | i, 1 << dev->caps.log_num_vlans); |
427 | } | |
428 | } | |
429 | ||
f2a3f6a3 OG |
430 | dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); |
431 | ||
93fc9e1b YP |
432 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; |
433 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = | |
434 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = | |
435 | (1 << dev->caps.log_num_macs) * | |
436 | (1 << dev->caps.log_num_vlans) * | |
93fc9e1b YP |
437 | dev->caps.num_ports; |
438 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; | |
d57febe1 MB |
439 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = |
440 | MLX4_A0_STEERING_TABLE_SIZE; | |
93fc9e1b YP |
441 | |
442 | dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + | |
443 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + | |
444 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + | |
445 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; | |
446 | ||
e2c76824 | 447 | dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; |
08ff3235 | 448 | |
b3051320 | 449 | if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { |
08ff3235 OG |
450 | if (dev_cap->flags & |
451 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { | |
452 | mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); | |
453 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; | |
454 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; | |
455 | } | |
77507aa2 IS |
456 | |
457 | if (dev_cap->flags2 & | |
458 | (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | | |
459 | MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { | |
460 | mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); | |
461 | dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; | |
462 | dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; | |
463 | } | |
08ff3235 OG |
464 | } |
465 | ||
f97b4b5d | 466 | if ((dev->caps.flags & |
08ff3235 OG |
467 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && |
468 | mlx4_is_master(dev)) | |
469 | dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; | |
470 | ||
ddae0349 | 471 | if (!mlx4_is_slave(dev)) { |
77507aa2 | 472 | mlx4_enable_cqe_eqe_stride(dev); |
ddae0349 | 473 | dev->caps.alloc_res_qp_mask = |
d57febe1 MB |
474 | (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | |
475 | MLX4_RESERVE_A0_QP; | |
ddae0349 EE |
476 | } else { |
477 | dev->caps.alloc_res_qp_mask = 0; | |
478 | } | |
77507aa2 | 479 | |
225c7b1f RD |
480 | return 0; |
481 | } | |
b912b2f8 EP |
482 | |
483 | static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, | |
484 | enum pci_bus_speed *speed, | |
485 | enum pcie_link_width *width) | |
486 | { | |
487 | u32 lnkcap1, lnkcap2; | |
488 | int err1, err2; | |
489 | ||
490 | #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ | |
491 | ||
492 | *speed = PCI_SPEED_UNKNOWN; | |
493 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
494 | ||
495 | err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1); | |
496 | err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2); | |
497 | if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ | |
498 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
499 | *speed = PCIE_SPEED_8_0GT; | |
500 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
501 | *speed = PCIE_SPEED_5_0GT; | |
502 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
503 | *speed = PCIE_SPEED_2_5GT; | |
504 | } | |
505 | if (!err1) { | |
506 | *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; | |
507 | if (!lnkcap2) { /* pre-r3.0 */ | |
508 | if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) | |
509 | *speed = PCIE_SPEED_5_0GT; | |
510 | else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) | |
511 | *speed = PCIE_SPEED_2_5GT; | |
512 | } | |
513 | } | |
514 | ||
515 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { | |
516 | return err1 ? err1 : | |
517 | err2 ? err2 : -EINVAL; | |
518 | } | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static void mlx4_check_pcie_caps(struct mlx4_dev *dev) | |
523 | { | |
524 | enum pcie_link_width width, width_cap; | |
525 | enum pci_bus_speed speed, speed_cap; | |
526 | int err; | |
527 | ||
528 | #define PCIE_SPEED_STR(speed) \ | |
529 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ | |
530 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ | |
531 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ | |
532 | "Unknown") | |
533 | ||
534 | err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); | |
535 | if (err) { | |
536 | mlx4_warn(dev, | |
537 | "Unable to determine PCIe device BW capabilities\n"); | |
538 | return; | |
539 | } | |
540 | ||
541 | err = pcie_get_minimum_link(dev->pdev, &speed, &width); | |
542 | if (err || speed == PCI_SPEED_UNKNOWN || | |
543 | width == PCIE_LNK_WIDTH_UNKNOWN) { | |
544 | mlx4_warn(dev, | |
545 | "Unable to determine PCI device chain minimum BW\n"); | |
546 | return; | |
547 | } | |
548 | ||
549 | if (width != width_cap || speed != speed_cap) | |
550 | mlx4_warn(dev, | |
551 | "PCIe BW is different than device's capability\n"); | |
552 | ||
553 | mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", | |
554 | PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); | |
555 | mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", | |
556 | width, width_cap); | |
557 | return; | |
558 | } | |
559 | ||
ab9c17a0 JM |
560 | /*The function checks if there are live vf, return the num of them*/ |
561 | static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) | |
562 | { | |
563 | struct mlx4_priv *priv = mlx4_priv(dev); | |
564 | struct mlx4_slave_state *s_state; | |
565 | int i; | |
566 | int ret = 0; | |
567 | ||
568 | for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { | |
569 | s_state = &priv->mfunc.master.slave_state[i]; | |
570 | if (s_state->active && s_state->last_cmd != | |
571 | MLX4_COMM_CMD_RESET) { | |
572 | mlx4_warn(dev, "%s: slave: %d is still active\n", | |
573 | __func__, i); | |
574 | ret++; | |
575 | } | |
576 | } | |
577 | return ret; | |
578 | } | |
579 | ||
396f2feb JM |
580 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) |
581 | { | |
582 | u32 qk = MLX4_RESERVED_QKEY_BASE; | |
47605df9 JM |
583 | |
584 | if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || | |
585 | qpn < dev->phys_caps.base_proxy_sqpn) | |
396f2feb JM |
586 | return -EINVAL; |
587 | ||
47605df9 | 588 | if (qpn >= dev->phys_caps.base_tunnel_sqpn) |
396f2feb | 589 | /* tunnel qp */ |
47605df9 | 590 | qk += qpn - dev->phys_caps.base_tunnel_sqpn; |
396f2feb | 591 | else |
47605df9 | 592 | qk += qpn - dev->phys_caps.base_proxy_sqpn; |
396f2feb JM |
593 | *qkey = qk; |
594 | return 0; | |
595 | } | |
596 | EXPORT_SYMBOL(mlx4_get_parav_qkey); | |
597 | ||
54679e14 JM |
598 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) |
599 | { | |
600 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
601 | ||
602 | if (!mlx4_is_master(dev)) | |
603 | return; | |
604 | ||
605 | priv->virt2phys_pkey[slave][port - 1][i] = val; | |
606 | } | |
607 | EXPORT_SYMBOL(mlx4_sync_pkey_table); | |
608 | ||
afa8fd1d JM |
609 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) |
610 | { | |
611 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
612 | ||
613 | if (!mlx4_is_master(dev)) | |
614 | return; | |
615 | ||
616 | priv->slave_node_guids[slave] = guid; | |
617 | } | |
618 | EXPORT_SYMBOL(mlx4_put_slave_node_guid); | |
619 | ||
620 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) | |
621 | { | |
622 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
623 | ||
624 | if (!mlx4_is_master(dev)) | |
625 | return 0; | |
626 | ||
627 | return priv->slave_node_guids[slave]; | |
628 | } | |
629 | EXPORT_SYMBOL(mlx4_get_slave_node_guid); | |
630 | ||
e10903b0 | 631 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) |
ab9c17a0 JM |
632 | { |
633 | struct mlx4_priv *priv = mlx4_priv(dev); | |
634 | struct mlx4_slave_state *s_slave; | |
635 | ||
636 | if (!mlx4_is_master(dev)) | |
637 | return 0; | |
638 | ||
639 | s_slave = &priv->mfunc.master.slave_state[slave]; | |
640 | return !!s_slave->active; | |
641 | } | |
642 | EXPORT_SYMBOL(mlx4_is_slave_active); | |
643 | ||
7b8157be JM |
644 | static void slave_adjust_steering_mode(struct mlx4_dev *dev, |
645 | struct mlx4_dev_cap *dev_cap, | |
646 | struct mlx4_init_hca_param *hca_param) | |
647 | { | |
648 | dev->caps.steering_mode = hca_param->steering_mode; | |
649 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
650 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | |
651 | dev->caps.fs_log_max_ucast_qp_range_size = | |
652 | dev_cap->fs_log_max_ucast_qp_range_size; | |
653 | } else | |
654 | dev->caps.num_qp_per_mgm = | |
655 | 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); | |
656 | ||
657 | mlx4_dbg(dev, "Steering mode is: %s\n", | |
658 | mlx4_steering_mode_str(dev->caps.steering_mode)); | |
659 | } | |
660 | ||
ab9c17a0 JM |
661 | static int mlx4_slave_cap(struct mlx4_dev *dev) |
662 | { | |
663 | int err; | |
664 | u32 page_size; | |
665 | struct mlx4_dev_cap dev_cap; | |
666 | struct mlx4_func_cap func_cap; | |
667 | struct mlx4_init_hca_param hca_param; | |
225c6c8c | 668 | u8 i; |
ab9c17a0 JM |
669 | |
670 | memset(&hca_param, 0, sizeof(hca_param)); | |
671 | err = mlx4_QUERY_HCA(dev, &hca_param); | |
672 | if (err) { | |
1a91de28 | 673 | mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); |
ab9c17a0 JM |
674 | return err; |
675 | } | |
676 | ||
483e0132 EP |
677 | /* fail if the hca has an unknown global capability |
678 | * at this time global_caps should be always zeroed | |
679 | */ | |
680 | if (hca_param.global_caps) { | |
ab9c17a0 JM |
681 | mlx4_err(dev, "Unknown hca global capabilities\n"); |
682 | return -ENOSYS; | |
683 | } | |
684 | ||
685 | mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; | |
686 | ||
ddd8a6c1 EE |
687 | dev->caps.hca_core_clock = hca_param.hca_core_clock; |
688 | ||
ab9c17a0 | 689 | memset(&dev_cap, 0, sizeof(dev_cap)); |
b91cb3eb | 690 | dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; |
ab9c17a0 JM |
691 | err = mlx4_dev_cap(dev, &dev_cap); |
692 | if (err) { | |
1a91de28 | 693 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
ab9c17a0 JM |
694 | return err; |
695 | } | |
696 | ||
b91cb3eb JM |
697 | err = mlx4_QUERY_FW(dev); |
698 | if (err) | |
1a91de28 | 699 | mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); |
b91cb3eb | 700 | |
ab9c17a0 JM |
701 | page_size = ~dev->caps.page_size_cap + 1; |
702 | mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); | |
703 | if (page_size > PAGE_SIZE) { | |
1a91de28 | 704 | mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", |
ab9c17a0 JM |
705 | page_size, PAGE_SIZE); |
706 | return -ENODEV; | |
707 | } | |
708 | ||
709 | /* slave gets uar page size from QUERY_HCA fw command */ | |
710 | dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); | |
711 | ||
712 | /* TODO: relax this assumption */ | |
713 | if (dev->caps.uar_page_size != PAGE_SIZE) { | |
714 | mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", | |
715 | dev->caps.uar_page_size, PAGE_SIZE); | |
716 | return -ENODEV; | |
717 | } | |
718 | ||
719 | memset(&func_cap, 0, sizeof(func_cap)); | |
47605df9 | 720 | err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); |
ab9c17a0 | 721 | if (err) { |
1a91de28 JP |
722 | mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", |
723 | err); | |
ab9c17a0 JM |
724 | return err; |
725 | } | |
726 | ||
727 | if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != | |
728 | PF_CONTEXT_BEHAVIOUR_MASK) { | |
729 | mlx4_err(dev, "Unknown pf context behaviour\n"); | |
730 | return -ENOSYS; | |
731 | } | |
732 | ||
ab9c17a0 | 733 | dev->caps.num_ports = func_cap.num_ports; |
5a0d0a61 JM |
734 | dev->quotas.qp = func_cap.qp_quota; |
735 | dev->quotas.srq = func_cap.srq_quota; | |
736 | dev->quotas.cq = func_cap.cq_quota; | |
737 | dev->quotas.mpt = func_cap.mpt_quota; | |
738 | dev->quotas.mtt = func_cap.mtt_quota; | |
739 | dev->caps.num_qps = 1 << hca_param.log_num_qps; | |
740 | dev->caps.num_srqs = 1 << hca_param.log_num_srqs; | |
741 | dev->caps.num_cqs = 1 << hca_param.log_num_cqs; | |
742 | dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; | |
743 | dev->caps.num_eqs = func_cap.max_eq; | |
744 | dev->caps.reserved_eqs = func_cap.reserved_eq; | |
ab9c17a0 JM |
745 | dev->caps.num_pds = MLX4_NUM_PDS; |
746 | dev->caps.num_mgms = 0; | |
747 | dev->caps.num_amgms = 0; | |
748 | ||
ab9c17a0 | 749 | if (dev->caps.num_ports > MLX4_MAX_PORTS) { |
1a91de28 JP |
750 | mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", |
751 | dev->caps.num_ports, MLX4_MAX_PORTS); | |
ab9c17a0 JM |
752 | return -ENODEV; |
753 | } | |
754 | ||
99ec41d0 | 755 | dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL); |
47605df9 JM |
756 | dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); |
757 | dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
758 | dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
759 | dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
760 | ||
761 | if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || | |
99ec41d0 JM |
762 | !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy || |
763 | !dev->caps.qp0_qkey) { | |
47605df9 JM |
764 | err = -ENOMEM; |
765 | goto err_mem; | |
766 | } | |
767 | ||
6634961c | 768 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
225c6c8c | 769 | err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap); |
47605df9 | 770 | if (err) { |
1a91de28 JP |
771 | mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", |
772 | i, err); | |
47605df9 JM |
773 | goto err_mem; |
774 | } | |
99ec41d0 | 775 | dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey; |
47605df9 JM |
776 | dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; |
777 | dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; | |
778 | dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; | |
779 | dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; | |
6230bb23 | 780 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
8e1a28e8 | 781 | dev->caps.phys_port_id[i] = func_cap.phys_port_id; |
6634961c JM |
782 | if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, |
783 | &dev->caps.gid_table_len[i], | |
784 | &dev->caps.pkey_table_len[i])) | |
47605df9 | 785 | goto err_mem; |
6634961c | 786 | } |
6230bb23 | 787 | |
ab9c17a0 JM |
788 | if (dev->caps.uar_page_size * (dev->caps.num_uars - |
789 | dev->caps.reserved_uars) > | |
790 | pci_resource_len(dev->pdev, 2)) { | |
1a91de28 | 791 | mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", |
ab9c17a0 JM |
792 | dev->caps.uar_page_size * dev->caps.num_uars, |
793 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
47605df9 | 794 | goto err_mem; |
ab9c17a0 JM |
795 | } |
796 | ||
08ff3235 OG |
797 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { |
798 | dev->caps.eqe_size = 64; | |
799 | dev->caps.eqe_factor = 1; | |
800 | } else { | |
801 | dev->caps.eqe_size = 32; | |
802 | dev->caps.eqe_factor = 0; | |
803 | } | |
804 | ||
805 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { | |
806 | dev->caps.cqe_size = 64; | |
77507aa2 | 807 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; |
08ff3235 OG |
808 | } else { |
809 | dev->caps.cqe_size = 32; | |
810 | } | |
811 | ||
77507aa2 IS |
812 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { |
813 | dev->caps.eqe_size = hca_param.eqe_size; | |
814 | dev->caps.eqe_factor = 0; | |
815 | } | |
816 | ||
817 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { | |
818 | dev->caps.cqe_size = hca_param.cqe_size; | |
819 | /* User still need to know when CQE > 32B */ | |
820 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; | |
821 | } | |
822 | ||
f9bd2d7f | 823 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; |
1a91de28 | 824 | mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); |
f9bd2d7f | 825 | |
7b8157be JM |
826 | slave_adjust_steering_mode(dev, &dev_cap, &hca_param); |
827 | ||
ddae0349 EE |
828 | if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && |
829 | dev->caps.bf_reg_size) | |
830 | dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; | |
831 | ||
d57febe1 MB |
832 | if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) |
833 | dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; | |
834 | ||
ab9c17a0 | 835 | return 0; |
47605df9 JM |
836 | |
837 | err_mem: | |
99ec41d0 | 838 | kfree(dev->caps.qp0_qkey); |
47605df9 JM |
839 | kfree(dev->caps.qp0_tunnel); |
840 | kfree(dev->caps.qp0_proxy); | |
841 | kfree(dev->caps.qp1_tunnel); | |
842 | kfree(dev->caps.qp1_proxy); | |
99ec41d0 JM |
843 | dev->caps.qp0_qkey = NULL; |
844 | dev->caps.qp0_tunnel = NULL; | |
845 | dev->caps.qp0_proxy = NULL; | |
846 | dev->caps.qp1_tunnel = NULL; | |
847 | dev->caps.qp1_proxy = NULL; | |
47605df9 JM |
848 | |
849 | return err; | |
ab9c17a0 | 850 | } |
225c7b1f | 851 | |
b046ffe5 EP |
852 | static void mlx4_request_modules(struct mlx4_dev *dev) |
853 | { | |
854 | int port; | |
855 | int has_ib_port = false; | |
856 | int has_eth_port = false; | |
857 | #define EN_DRV_NAME "mlx4_en" | |
858 | #define IB_DRV_NAME "mlx4_ib" | |
859 | ||
860 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
861 | if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) | |
862 | has_ib_port = true; | |
863 | else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) | |
864 | has_eth_port = true; | |
865 | } | |
866 | ||
b046ffe5 EP |
867 | if (has_eth_port) |
868 | request_module_nowait(EN_DRV_NAME); | |
f24f790f OG |
869 | if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) |
870 | request_module_nowait(IB_DRV_NAME); | |
b046ffe5 EP |
871 | } |
872 | ||
7ff93f8b YP |
873 | /* |
874 | * Change the port configuration of the device. | |
875 | * Every user of this function must hold the port mutex. | |
876 | */ | |
27bf91d6 YP |
877 | int mlx4_change_port_types(struct mlx4_dev *dev, |
878 | enum mlx4_port_type *port_types) | |
7ff93f8b YP |
879 | { |
880 | int err = 0; | |
881 | int change = 0; | |
882 | int port; | |
883 | ||
884 | for (port = 0; port < dev->caps.num_ports; port++) { | |
27bf91d6 YP |
885 | /* Change the port type only if the new type is different |
886 | * from the current, and not set to Auto */ | |
3d8f9308 | 887 | if (port_types[port] != dev->caps.port_type[port + 1]) |
7ff93f8b | 888 | change = 1; |
7ff93f8b YP |
889 | } |
890 | if (change) { | |
891 | mlx4_unregister_device(dev); | |
892 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
893 | mlx4_CLOSE_PORT(dev, port); | |
1e0f03d5 | 894 | dev->caps.port_type[port] = port_types[port - 1]; |
6634961c | 895 | err = mlx4_SET_PORT(dev, port, -1); |
7ff93f8b | 896 | if (err) { |
1a91de28 JP |
897 | mlx4_err(dev, "Failed to set port %d, aborting\n", |
898 | port); | |
7ff93f8b YP |
899 | goto out; |
900 | } | |
901 | } | |
902 | mlx4_set_port_mask(dev); | |
903 | err = mlx4_register_device(dev); | |
b046ffe5 EP |
904 | if (err) { |
905 | mlx4_err(dev, "Failed to register device\n"); | |
906 | goto out; | |
907 | } | |
908 | mlx4_request_modules(dev); | |
7ff93f8b YP |
909 | } |
910 | ||
911 | out: | |
912 | return err; | |
913 | } | |
914 | ||
915 | static ssize_t show_port_type(struct device *dev, | |
916 | struct device_attribute *attr, | |
917 | char *buf) | |
918 | { | |
919 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
920 | port_attr); | |
921 | struct mlx4_dev *mdev = info->dev; | |
27bf91d6 YP |
922 | char type[8]; |
923 | ||
924 | sprintf(type, "%s", | |
925 | (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? | |
926 | "ib" : "eth"); | |
927 | if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) | |
928 | sprintf(buf, "auto (%s)\n", type); | |
929 | else | |
930 | sprintf(buf, "%s\n", type); | |
7ff93f8b | 931 | |
27bf91d6 | 932 | return strlen(buf); |
7ff93f8b YP |
933 | } |
934 | ||
935 | static ssize_t set_port_type(struct device *dev, | |
936 | struct device_attribute *attr, | |
937 | const char *buf, size_t count) | |
938 | { | |
939 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
940 | port_attr); | |
941 | struct mlx4_dev *mdev = info->dev; | |
942 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
943 | enum mlx4_port_type types[MLX4_MAX_PORTS]; | |
27bf91d6 | 944 | enum mlx4_port_type new_types[MLX4_MAX_PORTS]; |
0a984556 | 945 | static DEFINE_MUTEX(set_port_type_mutex); |
7ff93f8b YP |
946 | int i; |
947 | int err = 0; | |
948 | ||
0a984556 AV |
949 | mutex_lock(&set_port_type_mutex); |
950 | ||
7ff93f8b YP |
951 | if (!strcmp(buf, "ib\n")) |
952 | info->tmp_type = MLX4_PORT_TYPE_IB; | |
953 | else if (!strcmp(buf, "eth\n")) | |
954 | info->tmp_type = MLX4_PORT_TYPE_ETH; | |
27bf91d6 YP |
955 | else if (!strcmp(buf, "auto\n")) |
956 | info->tmp_type = MLX4_PORT_TYPE_AUTO; | |
7ff93f8b YP |
957 | else { |
958 | mlx4_err(mdev, "%s is not supported port type\n", buf); | |
0a984556 AV |
959 | err = -EINVAL; |
960 | goto err_out; | |
7ff93f8b YP |
961 | } |
962 | ||
27bf91d6 | 963 | mlx4_stop_sense(mdev); |
7ff93f8b | 964 | mutex_lock(&priv->port_mutex); |
27bf91d6 YP |
965 | /* Possible type is always the one that was delivered */ |
966 | mdev->caps.possible_type[info->port] = info->tmp_type; | |
967 | ||
968 | for (i = 0; i < mdev->caps.num_ports; i++) { | |
7ff93f8b | 969 | types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : |
27bf91d6 YP |
970 | mdev->caps.possible_type[i+1]; |
971 | if (types[i] == MLX4_PORT_TYPE_AUTO) | |
972 | types[i] = mdev->caps.port_type[i+1]; | |
973 | } | |
7ff93f8b | 974 | |
58a60168 YP |
975 | if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
976 | !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { | |
27bf91d6 YP |
977 | for (i = 1; i <= mdev->caps.num_ports; i++) { |
978 | if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { | |
979 | mdev->caps.possible_type[i] = mdev->caps.port_type[i]; | |
980 | err = -EINVAL; | |
981 | } | |
982 | } | |
983 | } | |
984 | if (err) { | |
1a91de28 | 985 | mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); |
27bf91d6 YP |
986 | goto out; |
987 | } | |
988 | ||
989 | mlx4_do_sense_ports(mdev, new_types, types); | |
990 | ||
991 | err = mlx4_check_port_params(mdev, new_types); | |
7ff93f8b YP |
992 | if (err) |
993 | goto out; | |
994 | ||
27bf91d6 YP |
995 | /* We are about to apply the changes after the configuration |
996 | * was verified, no need to remember the temporary types | |
997 | * any more */ | |
998 | for (i = 0; i < mdev->caps.num_ports; i++) | |
999 | priv->port[i + 1].tmp_type = 0; | |
7ff93f8b | 1000 | |
27bf91d6 | 1001 | err = mlx4_change_port_types(mdev, new_types); |
7ff93f8b YP |
1002 | |
1003 | out: | |
27bf91d6 | 1004 | mlx4_start_sense(mdev); |
7ff93f8b | 1005 | mutex_unlock(&priv->port_mutex); |
0a984556 AV |
1006 | err_out: |
1007 | mutex_unlock(&set_port_type_mutex); | |
1008 | ||
7ff93f8b YP |
1009 | return err ? err : count; |
1010 | } | |
1011 | ||
096335b3 OG |
1012 | enum ibta_mtu { |
1013 | IB_MTU_256 = 1, | |
1014 | IB_MTU_512 = 2, | |
1015 | IB_MTU_1024 = 3, | |
1016 | IB_MTU_2048 = 4, | |
1017 | IB_MTU_4096 = 5 | |
1018 | }; | |
1019 | ||
1020 | static inline int int_to_ibta_mtu(int mtu) | |
1021 | { | |
1022 | switch (mtu) { | |
1023 | case 256: return IB_MTU_256; | |
1024 | case 512: return IB_MTU_512; | |
1025 | case 1024: return IB_MTU_1024; | |
1026 | case 2048: return IB_MTU_2048; | |
1027 | case 4096: return IB_MTU_4096; | |
1028 | default: return -1; | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | static inline int ibta_mtu_to_int(enum ibta_mtu mtu) | |
1033 | { | |
1034 | switch (mtu) { | |
1035 | case IB_MTU_256: return 256; | |
1036 | case IB_MTU_512: return 512; | |
1037 | case IB_MTU_1024: return 1024; | |
1038 | case IB_MTU_2048: return 2048; | |
1039 | case IB_MTU_4096: return 4096; | |
1040 | default: return -1; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | static ssize_t show_port_ib_mtu(struct device *dev, | |
1045 | struct device_attribute *attr, | |
1046 | char *buf) | |
1047 | { | |
1048 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
1049 | port_mtu_attr); | |
1050 | struct mlx4_dev *mdev = info->dev; | |
1051 | ||
1052 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) | |
1053 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
1054 | ||
1055 | sprintf(buf, "%d\n", | |
1056 | ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); | |
1057 | return strlen(buf); | |
1058 | } | |
1059 | ||
1060 | static ssize_t set_port_ib_mtu(struct device *dev, | |
1061 | struct device_attribute *attr, | |
1062 | const char *buf, size_t count) | |
1063 | { | |
1064 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
1065 | port_mtu_attr); | |
1066 | struct mlx4_dev *mdev = info->dev; | |
1067 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
1068 | int err, port, mtu, ibta_mtu = -1; | |
1069 | ||
1070 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { | |
1071 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
1072 | return -EINVAL; | |
1073 | } | |
1074 | ||
618fad95 DB |
1075 | err = kstrtoint(buf, 0, &mtu); |
1076 | if (!err) | |
096335b3 OG |
1077 | ibta_mtu = int_to_ibta_mtu(mtu); |
1078 | ||
618fad95 | 1079 | if (err || ibta_mtu < 0) { |
096335b3 OG |
1080 | mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); |
1081 | return -EINVAL; | |
1082 | } | |
1083 | ||
1084 | mdev->caps.port_ib_mtu[info->port] = ibta_mtu; | |
1085 | ||
1086 | mlx4_stop_sense(mdev); | |
1087 | mutex_lock(&priv->port_mutex); | |
1088 | mlx4_unregister_device(mdev); | |
1089 | for (port = 1; port <= mdev->caps.num_ports; port++) { | |
1090 | mlx4_CLOSE_PORT(mdev, port); | |
6634961c | 1091 | err = mlx4_SET_PORT(mdev, port, -1); |
096335b3 | 1092 | if (err) { |
1a91de28 JP |
1093 | mlx4_err(mdev, "Failed to set port %d, aborting\n", |
1094 | port); | |
096335b3 OG |
1095 | goto err_set_port; |
1096 | } | |
1097 | } | |
1098 | err = mlx4_register_device(mdev); | |
1099 | err_set_port: | |
1100 | mutex_unlock(&priv->port_mutex); | |
1101 | mlx4_start_sense(mdev); | |
1102 | return err ? err : count; | |
1103 | } | |
1104 | ||
e8f9b2ed | 1105 | static int mlx4_load_fw(struct mlx4_dev *dev) |
225c7b1f RD |
1106 | { |
1107 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1108 | int err; | |
1109 | ||
1110 | priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, | |
5b0bf5e2 | 1111 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f | 1112 | if (!priv->fw.fw_icm) { |
1a91de28 | 1113 | mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); |
225c7b1f RD |
1114 | return -ENOMEM; |
1115 | } | |
1116 | ||
1117 | err = mlx4_MAP_FA(dev, priv->fw.fw_icm); | |
1118 | if (err) { | |
1a91de28 | 1119 | mlx4_err(dev, "MAP_FA command failed, aborting\n"); |
225c7b1f RD |
1120 | goto err_free; |
1121 | } | |
1122 | ||
1123 | err = mlx4_RUN_FW(dev); | |
1124 | if (err) { | |
1a91de28 | 1125 | mlx4_err(dev, "RUN_FW command failed, aborting\n"); |
225c7b1f RD |
1126 | goto err_unmap_fa; |
1127 | } | |
1128 | ||
1129 | return 0; | |
1130 | ||
1131 | err_unmap_fa: | |
1132 | mlx4_UNMAP_FA(dev); | |
1133 | ||
1134 | err_free: | |
5b0bf5e2 | 1135 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); |
225c7b1f RD |
1136 | return err; |
1137 | } | |
1138 | ||
e8f9b2ed RD |
1139 | static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, |
1140 | int cmpt_entry_sz) | |
225c7b1f RD |
1141 | { |
1142 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1143 | int err; | |
ab9c17a0 | 1144 | int num_eqs; |
225c7b1f RD |
1145 | |
1146 | err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, | |
1147 | cmpt_base + | |
1148 | ((u64) (MLX4_CMPT_TYPE_QP * | |
1149 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1150 | cmpt_entry_sz, dev->caps.num_qps, | |
93fc9e1b YP |
1151 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1152 | 0, 0); | |
225c7b1f RD |
1153 | if (err) |
1154 | goto err; | |
1155 | ||
1156 | err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, | |
1157 | cmpt_base + | |
1158 | ((u64) (MLX4_CMPT_TYPE_SRQ * | |
1159 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1160 | cmpt_entry_sz, dev->caps.num_srqs, | |
5b0bf5e2 | 1161 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
1162 | if (err) |
1163 | goto err_qp; | |
1164 | ||
1165 | err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, | |
1166 | cmpt_base + | |
1167 | ((u64) (MLX4_CMPT_TYPE_CQ * | |
1168 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1169 | cmpt_entry_sz, dev->caps.num_cqs, | |
5b0bf5e2 | 1170 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
1171 | if (err) |
1172 | goto err_srq; | |
1173 | ||
7ae0e400 | 1174 | num_eqs = dev->phys_caps.num_phys_eqs; |
225c7b1f RD |
1175 | err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, |
1176 | cmpt_base + | |
1177 | ((u64) (MLX4_CMPT_TYPE_EQ * | |
1178 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
ab9c17a0 | 1179 | cmpt_entry_sz, num_eqs, num_eqs, 0, 0); |
225c7b1f RD |
1180 | if (err) |
1181 | goto err_cq; | |
1182 | ||
1183 | return 0; | |
1184 | ||
1185 | err_cq: | |
1186 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1187 | ||
1188 | err_srq: | |
1189 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1190 | ||
1191 | err_qp: | |
1192 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
1193 | ||
1194 | err: | |
1195 | return err; | |
1196 | } | |
1197 | ||
3d73c288 RD |
1198 | static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, |
1199 | struct mlx4_init_hca_param *init_hca, u64 icm_size) | |
225c7b1f RD |
1200 | { |
1201 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1202 | u64 aux_pages; | |
ab9c17a0 | 1203 | int num_eqs; |
225c7b1f RD |
1204 | int err; |
1205 | ||
1206 | err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); | |
1207 | if (err) { | |
1a91de28 | 1208 | mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); |
225c7b1f RD |
1209 | return err; |
1210 | } | |
1211 | ||
1a91de28 | 1212 | mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", |
225c7b1f RD |
1213 | (unsigned long long) icm_size >> 10, |
1214 | (unsigned long long) aux_pages << 2); | |
1215 | ||
1216 | priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, | |
5b0bf5e2 | 1217 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f | 1218 | if (!priv->fw.aux_icm) { |
1a91de28 | 1219 | mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); |
225c7b1f RD |
1220 | return -ENOMEM; |
1221 | } | |
1222 | ||
1223 | err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); | |
1224 | if (err) { | |
1a91de28 | 1225 | mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); |
225c7b1f RD |
1226 | goto err_free_aux; |
1227 | } | |
1228 | ||
1229 | err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); | |
1230 | if (err) { | |
1a91de28 | 1231 | mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); |
225c7b1f RD |
1232 | goto err_unmap_aux; |
1233 | } | |
1234 | ||
ab9c17a0 | 1235 | |
7ae0e400 | 1236 | num_eqs = dev->phys_caps.num_phys_eqs; |
fa0681d2 RD |
1237 | err = mlx4_init_icm_table(dev, &priv->eq_table.table, |
1238 | init_hca->eqc_base, dev_cap->eqc_entry_sz, | |
ab9c17a0 | 1239 | num_eqs, num_eqs, 0, 0); |
225c7b1f | 1240 | if (err) { |
1a91de28 | 1241 | mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); |
225c7b1f RD |
1242 | goto err_unmap_cmpt; |
1243 | } | |
1244 | ||
d7bb58fb JM |
1245 | /* |
1246 | * Reserved MTT entries must be aligned up to a cacheline | |
1247 | * boundary, since the FW will write to them, while the driver | |
1248 | * writes to all other MTT entries. (The variable | |
1249 | * dev->caps.mtt_entry_sz below is really the MTT segment | |
1250 | * size, not the raw entry size) | |
1251 | */ | |
1252 | dev->caps.reserved_mtts = | |
1253 | ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, | |
1254 | dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; | |
1255 | ||
225c7b1f RD |
1256 | err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, |
1257 | init_hca->mtt_base, | |
1258 | dev->caps.mtt_entry_sz, | |
2b8fb286 | 1259 | dev->caps.num_mtts, |
5b0bf5e2 | 1260 | dev->caps.reserved_mtts, 1, 0); |
225c7b1f | 1261 | if (err) { |
1a91de28 | 1262 | mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); |
225c7b1f RD |
1263 | goto err_unmap_eq; |
1264 | } | |
1265 | ||
1266 | err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, | |
1267 | init_hca->dmpt_base, | |
1268 | dev_cap->dmpt_entry_sz, | |
1269 | dev->caps.num_mpts, | |
5b0bf5e2 | 1270 | dev->caps.reserved_mrws, 1, 1); |
225c7b1f | 1271 | if (err) { |
1a91de28 | 1272 | mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); |
225c7b1f RD |
1273 | goto err_unmap_mtt; |
1274 | } | |
1275 | ||
1276 | err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, | |
1277 | init_hca->qpc_base, | |
1278 | dev_cap->qpc_entry_sz, | |
1279 | dev->caps.num_qps, | |
93fc9e1b YP |
1280 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1281 | 0, 0); | |
225c7b1f | 1282 | if (err) { |
1a91de28 | 1283 | mlx4_err(dev, "Failed to map QP context memory, aborting\n"); |
225c7b1f RD |
1284 | goto err_unmap_dmpt; |
1285 | } | |
1286 | ||
1287 | err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, | |
1288 | init_hca->auxc_base, | |
1289 | dev_cap->aux_entry_sz, | |
1290 | dev->caps.num_qps, | |
93fc9e1b YP |
1291 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1292 | 0, 0); | |
225c7b1f | 1293 | if (err) { |
1a91de28 | 1294 | mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); |
225c7b1f RD |
1295 | goto err_unmap_qp; |
1296 | } | |
1297 | ||
1298 | err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, | |
1299 | init_hca->altc_base, | |
1300 | dev_cap->altc_entry_sz, | |
1301 | dev->caps.num_qps, | |
93fc9e1b YP |
1302 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1303 | 0, 0); | |
225c7b1f | 1304 | if (err) { |
1a91de28 | 1305 | mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); |
225c7b1f RD |
1306 | goto err_unmap_auxc; |
1307 | } | |
1308 | ||
1309 | err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, | |
1310 | init_hca->rdmarc_base, | |
1311 | dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, | |
1312 | dev->caps.num_qps, | |
93fc9e1b YP |
1313 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1314 | 0, 0); | |
225c7b1f RD |
1315 | if (err) { |
1316 | mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); | |
1317 | goto err_unmap_altc; | |
1318 | } | |
1319 | ||
1320 | err = mlx4_init_icm_table(dev, &priv->cq_table.table, | |
1321 | init_hca->cqc_base, | |
1322 | dev_cap->cqc_entry_sz, | |
1323 | dev->caps.num_cqs, | |
5b0bf5e2 | 1324 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f | 1325 | if (err) { |
1a91de28 | 1326 | mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); |
225c7b1f RD |
1327 | goto err_unmap_rdmarc; |
1328 | } | |
1329 | ||
1330 | err = mlx4_init_icm_table(dev, &priv->srq_table.table, | |
1331 | init_hca->srqc_base, | |
1332 | dev_cap->srq_entry_sz, | |
1333 | dev->caps.num_srqs, | |
5b0bf5e2 | 1334 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f | 1335 | if (err) { |
1a91de28 | 1336 | mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); |
225c7b1f RD |
1337 | goto err_unmap_cq; |
1338 | } | |
1339 | ||
1340 | /* | |
0ff1fb65 HHZ |
1341 | * For flow steering device managed mode it is required to use |
1342 | * mlx4_init_icm_table. For B0 steering mode it's not strictly | |
1343 | * required, but for simplicity just map the whole multicast | |
1344 | * group table now. The table isn't very big and it's a lot | |
1345 | * easier than trying to track ref counts. | |
225c7b1f RD |
1346 | */ |
1347 | err = mlx4_init_icm_table(dev, &priv->mcg_table.table, | |
0ec2c0f8 EE |
1348 | init_hca->mc_base, |
1349 | mlx4_get_mgm_entry_size(dev), | |
225c7b1f RD |
1350 | dev->caps.num_mgms + dev->caps.num_amgms, |
1351 | dev->caps.num_mgms + dev->caps.num_amgms, | |
5b0bf5e2 | 1352 | 0, 0); |
225c7b1f | 1353 | if (err) { |
1a91de28 | 1354 | mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); |
225c7b1f RD |
1355 | goto err_unmap_srq; |
1356 | } | |
1357 | ||
1358 | return 0; | |
1359 | ||
1360 | err_unmap_srq: | |
1361 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1362 | ||
1363 | err_unmap_cq: | |
1364 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1365 | ||
1366 | err_unmap_rdmarc: | |
1367 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1368 | ||
1369 | err_unmap_altc: | |
1370 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1371 | ||
1372 | err_unmap_auxc: | |
1373 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1374 | ||
1375 | err_unmap_qp: | |
1376 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1377 | ||
1378 | err_unmap_dmpt: | |
1379 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1380 | ||
1381 | err_unmap_mtt: | |
1382 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
1383 | ||
1384 | err_unmap_eq: | |
fa0681d2 | 1385 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1386 | |
1387 | err_unmap_cmpt: | |
1388 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); | |
1389 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1390 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1391 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
1392 | ||
1393 | err_unmap_aux: | |
1394 | mlx4_UNMAP_ICM_AUX(dev); | |
1395 | ||
1396 | err_free_aux: | |
5b0bf5e2 | 1397 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1398 | |
1399 | return err; | |
1400 | } | |
1401 | ||
1402 | static void mlx4_free_icms(struct mlx4_dev *dev) | |
1403 | { | |
1404 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1405 | ||
1406 | mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); | |
1407 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1408 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1409 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1410 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1411 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1412 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1413 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1414 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
fa0681d2 | 1415 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1416 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); |
1417 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1418 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1419 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
225c7b1f RD |
1420 | |
1421 | mlx4_UNMAP_ICM_AUX(dev); | |
5b0bf5e2 | 1422 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1423 | } |
1424 | ||
ab9c17a0 JM |
1425 | static void mlx4_slave_exit(struct mlx4_dev *dev) |
1426 | { | |
1427 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1428 | ||
f3d4c89e | 1429 | mutex_lock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 | 1430 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) |
1a91de28 | 1431 | mlx4_warn(dev, "Failed to close slave function\n"); |
f3d4c89e | 1432 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1433 | } |
1434 | ||
c1b43dca EC |
1435 | static int map_bf_area(struct mlx4_dev *dev) |
1436 | { | |
1437 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1438 | resource_size_t bf_start; | |
1439 | resource_size_t bf_len; | |
1440 | int err = 0; | |
1441 | ||
3d747473 JM |
1442 | if (!dev->caps.bf_reg_size) |
1443 | return -ENXIO; | |
1444 | ||
ab9c17a0 JM |
1445 | bf_start = pci_resource_start(dev->pdev, 2) + |
1446 | (dev->caps.num_uars << PAGE_SHIFT); | |
1447 | bf_len = pci_resource_len(dev->pdev, 2) - | |
1448 | (dev->caps.num_uars << PAGE_SHIFT); | |
c1b43dca EC |
1449 | priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); |
1450 | if (!priv->bf_mapping) | |
1451 | err = -ENOMEM; | |
1452 | ||
1453 | return err; | |
1454 | } | |
1455 | ||
1456 | static void unmap_bf_area(struct mlx4_dev *dev) | |
1457 | { | |
1458 | if (mlx4_priv(dev)->bf_mapping) | |
1459 | io_mapping_free(mlx4_priv(dev)->bf_mapping); | |
1460 | } | |
1461 | ||
ec693d47 AV |
1462 | cycle_t mlx4_read_clock(struct mlx4_dev *dev) |
1463 | { | |
1464 | u32 clockhi, clocklo, clockhi1; | |
1465 | cycle_t cycles; | |
1466 | int i; | |
1467 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1468 | ||
1469 | for (i = 0; i < 10; i++) { | |
1470 | clockhi = swab32(readl(priv->clock_mapping)); | |
1471 | clocklo = swab32(readl(priv->clock_mapping + 4)); | |
1472 | clockhi1 = swab32(readl(priv->clock_mapping)); | |
1473 | if (clockhi == clockhi1) | |
1474 | break; | |
1475 | } | |
1476 | ||
1477 | cycles = (u64) clockhi << 32 | (u64) clocklo; | |
1478 | ||
1479 | return cycles; | |
1480 | } | |
1481 | EXPORT_SYMBOL_GPL(mlx4_read_clock); | |
1482 | ||
1483 | ||
ddd8a6c1 EE |
1484 | static int map_internal_clock(struct mlx4_dev *dev) |
1485 | { | |
1486 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1487 | ||
1488 | priv->clock_mapping = | |
1489 | ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) + | |
1490 | priv->fw.clock_offset, MLX4_CLOCK_SIZE); | |
1491 | ||
1492 | if (!priv->clock_mapping) | |
1493 | return -ENOMEM; | |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | static void unmap_internal_clock(struct mlx4_dev *dev) | |
1499 | { | |
1500 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1501 | ||
1502 | if (priv->clock_mapping) | |
1503 | iounmap(priv->clock_mapping); | |
1504 | } | |
1505 | ||
225c7b1f RD |
1506 | static void mlx4_close_hca(struct mlx4_dev *dev) |
1507 | { | |
ddd8a6c1 | 1508 | unmap_internal_clock(dev); |
c1b43dca | 1509 | unmap_bf_area(dev); |
ab9c17a0 JM |
1510 | if (mlx4_is_slave(dev)) |
1511 | mlx4_slave_exit(dev); | |
1512 | else { | |
1513 | mlx4_CLOSE_HCA(dev, 0); | |
1514 | mlx4_free_icms(dev); | |
a0eacca9 MB |
1515 | } |
1516 | } | |
1517 | ||
1518 | static void mlx4_close_fw(struct mlx4_dev *dev) | |
1519 | { | |
1520 | if (!mlx4_is_slave(dev)) { | |
ab9c17a0 JM |
1521 | mlx4_UNMAP_FA(dev); |
1522 | mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); | |
1523 | } | |
1524 | } | |
1525 | ||
1526 | static int mlx4_init_slave(struct mlx4_dev *dev) | |
1527 | { | |
1528 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1529 | u64 dma = (u64) priv->mfunc.vhcr_dma; | |
ab9c17a0 JM |
1530 | int ret_from_reset = 0; |
1531 | u32 slave_read; | |
1532 | u32 cmd_channel_ver; | |
1533 | ||
97989356 | 1534 | if (atomic_read(&pf_loading)) { |
1a91de28 | 1535 | mlx4_warn(dev, "PF is not ready - Deferring probe\n"); |
97989356 AV |
1536 | return -EPROBE_DEFER; |
1537 | } | |
1538 | ||
f3d4c89e | 1539 | mutex_lock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1540 | priv->cmd.max_cmds = 1; |
1541 | mlx4_warn(dev, "Sending reset\n"); | |
1542 | ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, | |
1543 | MLX4_COMM_TIME); | |
1544 | /* if we are in the middle of flr the slave will try | |
1545 | * NUM_OF_RESET_RETRIES times before leaving.*/ | |
1546 | if (ret_from_reset) { | |
1547 | if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { | |
1a91de28 | 1548 | mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); |
5efe5355 JM |
1549 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
1550 | return -EPROBE_DEFER; | |
ab9c17a0 JM |
1551 | } else |
1552 | goto err; | |
1553 | } | |
1554 | ||
1555 | /* check the driver version - the slave I/F revision | |
1556 | * must match the master's */ | |
1557 | slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); | |
1558 | cmd_channel_ver = mlx4_comm_get_version(); | |
1559 | ||
1560 | if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != | |
1561 | MLX4_COMM_GET_IF_REV(slave_read)) { | |
1a91de28 | 1562 | mlx4_err(dev, "slave driver version is not supported by the master\n"); |
ab9c17a0 JM |
1563 | goto err; |
1564 | } | |
1565 | ||
1566 | mlx4_warn(dev, "Sending vhcr0\n"); | |
1567 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, | |
1568 | MLX4_COMM_TIME)) | |
1569 | goto err; | |
1570 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, | |
1571 | MLX4_COMM_TIME)) | |
1572 | goto err; | |
1573 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, | |
1574 | MLX4_COMM_TIME)) | |
1575 | goto err; | |
1576 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) | |
1577 | goto err; | |
f3d4c89e RD |
1578 | |
1579 | mutex_unlock(&priv->cmd.slave_cmd_mutex); | |
ab9c17a0 JM |
1580 | return 0; |
1581 | ||
1582 | err: | |
1583 | mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); | |
f3d4c89e | 1584 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 | 1585 | return -EIO; |
225c7b1f RD |
1586 | } |
1587 | ||
6634961c JM |
1588 | static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) |
1589 | { | |
1590 | int i; | |
1591 | ||
1592 | for (i = 1; i <= dev->caps.num_ports; i++) { | |
b6ffaeff JM |
1593 | if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) |
1594 | dev->caps.gid_table_len[i] = | |
449fc488 | 1595 | mlx4_get_slave_num_gids(dev, 0, i); |
b6ffaeff JM |
1596 | else |
1597 | dev->caps.gid_table_len[i] = 1; | |
6634961c JM |
1598 | dev->caps.pkey_table_len[i] = |
1599 | dev->phys_caps.pkey_phys_table_len[i] - 1; | |
1600 | } | |
1601 | } | |
1602 | ||
3c439b55 JM |
1603 | static int choose_log_fs_mgm_entry_size(int qp_per_entry) |
1604 | { | |
1605 | int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; | |
1606 | ||
1607 | for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; | |
1608 | i++) { | |
1609 | if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) | |
1610 | break; | |
1611 | } | |
1612 | ||
1613 | return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; | |
1614 | } | |
1615 | ||
7b8157be JM |
1616 | static void choose_steering_mode(struct mlx4_dev *dev, |
1617 | struct mlx4_dev_cap *dev_cap) | |
1618 | { | |
3c439b55 JM |
1619 | if (mlx4_log_num_mgm_entry_size == -1 && |
1620 | dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && | |
7b8157be | 1621 | (!mlx4_is_mfunc(dev) || |
449fc488 | 1622 | (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) && |
3c439b55 JM |
1623 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= |
1624 | MLX4_MIN_MGM_LOG_ENTRY_SIZE) { | |
1625 | dev->oper_log_mgm_entry_size = | |
1626 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); | |
7b8157be JM |
1627 | dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
1628 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | |
1629 | dev->caps.fs_log_max_ucast_qp_range_size = | |
1630 | dev_cap->fs_log_max_ucast_qp_range_size; | |
1631 | } else { | |
1632 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && | |
1633 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | |
1634 | dev->caps.steering_mode = MLX4_STEERING_MODE_B0; | |
1635 | else { | |
1636 | dev->caps.steering_mode = MLX4_STEERING_MODE_A0; | |
1637 | ||
1638 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || | |
1639 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | |
1a91de28 | 1640 | mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); |
7b8157be | 1641 | } |
3c439b55 JM |
1642 | dev->oper_log_mgm_entry_size = |
1643 | mlx4_log_num_mgm_entry_size > 0 ? | |
1644 | mlx4_log_num_mgm_entry_size : | |
1645 | MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; | |
7b8157be JM |
1646 | dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); |
1647 | } | |
1a91de28 | 1648 | mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", |
3c439b55 JM |
1649 | mlx4_steering_mode_str(dev->caps.steering_mode), |
1650 | dev->oper_log_mgm_entry_size, | |
1651 | mlx4_log_num_mgm_entry_size); | |
7b8157be JM |
1652 | } |
1653 | ||
7ffdf726 OG |
1654 | static void choose_tunnel_offload_mode(struct mlx4_dev *dev, |
1655 | struct mlx4_dev_cap *dev_cap) | |
1656 | { | |
1657 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && | |
1658 | dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) | |
1659 | dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; | |
1660 | else | |
1661 | dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; | |
1662 | ||
1663 | mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode | |
1664 | == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); | |
1665 | } | |
1666 | ||
a0eacca9 | 1667 | static int mlx4_init_fw(struct mlx4_dev *dev) |
225c7b1f | 1668 | { |
2d928651 | 1669 | struct mlx4_mod_stat_cfg mlx4_cfg; |
a0eacca9 | 1670 | int err = 0; |
225c7b1f | 1671 | |
ab9c17a0 JM |
1672 | if (!mlx4_is_slave(dev)) { |
1673 | err = mlx4_QUERY_FW(dev); | |
1674 | if (err) { | |
1675 | if (err == -EACCES) | |
1a91de28 | 1676 | mlx4_info(dev, "non-primary physical function, skipping\n"); |
ab9c17a0 | 1677 | else |
1a91de28 | 1678 | mlx4_err(dev, "QUERY_FW command failed, aborting\n"); |
bef772eb | 1679 | return err; |
ab9c17a0 | 1680 | } |
225c7b1f | 1681 | |
ab9c17a0 JM |
1682 | err = mlx4_load_fw(dev); |
1683 | if (err) { | |
1a91de28 | 1684 | mlx4_err(dev, "Failed to start FW, aborting\n"); |
bef772eb | 1685 | return err; |
ab9c17a0 | 1686 | } |
225c7b1f | 1687 | |
ab9c17a0 JM |
1688 | mlx4_cfg.log_pg_sz_m = 1; |
1689 | mlx4_cfg.log_pg_sz = 0; | |
1690 | err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); | |
1691 | if (err) | |
1692 | mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); | |
a0eacca9 | 1693 | } |
2d928651 | 1694 | |
a0eacca9 MB |
1695 | return err; |
1696 | } | |
1697 | ||
1698 | static int mlx4_init_hca(struct mlx4_dev *dev) | |
1699 | { | |
1700 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1701 | struct mlx4_adapter adapter; | |
1702 | struct mlx4_dev_cap dev_cap; | |
1703 | struct mlx4_profile profile; | |
1704 | struct mlx4_init_hca_param init_hca; | |
1705 | u64 icm_size; | |
1706 | struct mlx4_config_dev_params params; | |
1707 | int err; | |
1708 | ||
1709 | if (!mlx4_is_slave(dev)) { | |
ab9c17a0 JM |
1710 | err = mlx4_dev_cap(dev, &dev_cap); |
1711 | if (err) { | |
1a91de28 | 1712 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
ab9c17a0 JM |
1713 | goto err_stop_fw; |
1714 | } | |
225c7b1f | 1715 | |
7b8157be | 1716 | choose_steering_mode(dev, &dev_cap); |
7ffdf726 | 1717 | choose_tunnel_offload_mode(dev, &dev_cap); |
7b8157be | 1718 | |
8e1a28e8 HHZ |
1719 | err = mlx4_get_phys_port_id(dev); |
1720 | if (err) | |
1721 | mlx4_err(dev, "Fail to get physical port id\n"); | |
1722 | ||
6634961c JM |
1723 | if (mlx4_is_master(dev)) |
1724 | mlx4_parav_master_pf_caps(dev); | |
1725 | ||
2599d858 AV |
1726 | if (mlx4_low_memory_profile()) { |
1727 | mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); | |
1728 | profile = low_mem_profile; | |
1729 | } else { | |
1730 | profile = default_profile; | |
1731 | } | |
0ff1fb65 HHZ |
1732 | if (dev->caps.steering_mode == |
1733 | MLX4_STEERING_MODE_DEVICE_MANAGED) | |
1734 | profile.num_mcg = MLX4_FS_NUM_MCG; | |
225c7b1f | 1735 | |
ab9c17a0 JM |
1736 | icm_size = mlx4_make_profile(dev, &profile, &dev_cap, |
1737 | &init_hca); | |
1738 | if ((long long) icm_size < 0) { | |
1739 | err = icm_size; | |
1740 | goto err_stop_fw; | |
1741 | } | |
225c7b1f | 1742 | |
a5bbe892 EC |
1743 | dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; |
1744 | ||
ab9c17a0 JM |
1745 | init_hca.log_uar_sz = ilog2(dev->caps.num_uars); |
1746 | init_hca.uar_page_sz = PAGE_SHIFT - 12; | |
e448834e SM |
1747 | init_hca.mw_enabled = 0; |
1748 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || | |
1749 | dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) | |
1750 | init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; | |
c1b43dca | 1751 | |
ab9c17a0 JM |
1752 | err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); |
1753 | if (err) | |
1754 | goto err_stop_fw; | |
225c7b1f | 1755 | |
ab9c17a0 JM |
1756 | err = mlx4_INIT_HCA(dev, &init_hca); |
1757 | if (err) { | |
1a91de28 | 1758 | mlx4_err(dev, "INIT_HCA command failed, aborting\n"); |
ab9c17a0 JM |
1759 | goto err_free_icm; |
1760 | } | |
7ae0e400 MB |
1761 | |
1762 | if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { | |
1763 | err = mlx4_query_func(dev, &dev_cap); | |
1764 | if (err < 0) { | |
1765 | mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); | |
1766 | goto err_stop_fw; | |
1767 | } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { | |
1768 | dev->caps.num_eqs = dev_cap.max_eqs; | |
1769 | dev->caps.reserved_eqs = dev_cap.reserved_eqs; | |
1770 | dev->caps.reserved_uars = dev_cap.reserved_uars; | |
1771 | } | |
1772 | } | |
1773 | ||
ddd8a6c1 EE |
1774 | /* |
1775 | * If TS is supported by FW | |
1776 | * read HCA frequency by QUERY_HCA command | |
1777 | */ | |
1778 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { | |
1779 | memset(&init_hca, 0, sizeof(init_hca)); | |
1780 | err = mlx4_QUERY_HCA(dev, &init_hca); | |
1781 | if (err) { | |
1a91de28 | 1782 | mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); |
ddd8a6c1 EE |
1783 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; |
1784 | } else { | |
1785 | dev->caps.hca_core_clock = | |
1786 | init_hca.hca_core_clock; | |
1787 | } | |
1788 | ||
1789 | /* In case we got HCA frequency 0 - disable timestamping | |
1790 | * to avoid dividing by zero | |
1791 | */ | |
1792 | if (!dev->caps.hca_core_clock) { | |
1793 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1794 | mlx4_err(dev, | |
1a91de28 | 1795 | "HCA frequency is 0 - timestamping is not supported\n"); |
ddd8a6c1 EE |
1796 | } else if (map_internal_clock(dev)) { |
1797 | /* | |
1798 | * Map internal clock, | |
1799 | * in case of failure disable timestamping | |
1800 | */ | |
1801 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1a91de28 | 1802 | mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); |
ddd8a6c1 EE |
1803 | } |
1804 | } | |
ab9c17a0 JM |
1805 | } else { |
1806 | err = mlx4_init_slave(dev); | |
1807 | if (err) { | |
5efe5355 JM |
1808 | if (err != -EPROBE_DEFER) |
1809 | mlx4_err(dev, "Failed to initialize slave\n"); | |
bef772eb | 1810 | return err; |
ab9c17a0 | 1811 | } |
225c7b1f | 1812 | |
ab9c17a0 JM |
1813 | err = mlx4_slave_cap(dev); |
1814 | if (err) { | |
1815 | mlx4_err(dev, "Failed to obtain slave caps\n"); | |
1816 | goto err_close; | |
1817 | } | |
225c7b1f RD |
1818 | } |
1819 | ||
ab9c17a0 JM |
1820 | if (map_bf_area(dev)) |
1821 | mlx4_dbg(dev, "Failed to map blue flame area\n"); | |
1822 | ||
1823 | /*Only the master set the ports, all the rest got it from it.*/ | |
1824 | if (!mlx4_is_slave(dev)) | |
1825 | mlx4_set_port_mask(dev); | |
1826 | ||
225c7b1f RD |
1827 | err = mlx4_QUERY_ADAPTER(dev, &adapter); |
1828 | if (err) { | |
1a91de28 | 1829 | mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); |
bef772eb | 1830 | goto unmap_bf; |
225c7b1f RD |
1831 | } |
1832 | ||
f8c6455b SM |
1833 | /* Query CONFIG_DEV parameters */ |
1834 | err = mlx4_config_dev_retrieval(dev, ¶ms); | |
1835 | if (err && err != -ENOTSUPP) { | |
1836 | mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); | |
1837 | } else if (!err) { | |
1838 | dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; | |
1839 | dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; | |
1840 | } | |
225c7b1f | 1841 | priv->eq_table.inta_pin = adapter.inta_pin; |
cd9281d8 | 1842 | memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); |
225c7b1f RD |
1843 | |
1844 | return 0; | |
1845 | ||
bef772eb | 1846 | unmap_bf: |
ddd8a6c1 | 1847 | unmap_internal_clock(dev); |
bef772eb AY |
1848 | unmap_bf_area(dev); |
1849 | ||
b38f2879 | 1850 | if (mlx4_is_slave(dev)) { |
99ec41d0 | 1851 | kfree(dev->caps.qp0_qkey); |
b38f2879 DB |
1852 | kfree(dev->caps.qp0_tunnel); |
1853 | kfree(dev->caps.qp0_proxy); | |
1854 | kfree(dev->caps.qp1_tunnel); | |
1855 | kfree(dev->caps.qp1_proxy); | |
1856 | } | |
1857 | ||
225c7b1f | 1858 | err_close: |
41929ed2 DB |
1859 | if (mlx4_is_slave(dev)) |
1860 | mlx4_slave_exit(dev); | |
1861 | else | |
1862 | mlx4_CLOSE_HCA(dev, 0); | |
225c7b1f RD |
1863 | |
1864 | err_free_icm: | |
ab9c17a0 JM |
1865 | if (!mlx4_is_slave(dev)) |
1866 | mlx4_free_icms(dev); | |
225c7b1f RD |
1867 | |
1868 | err_stop_fw: | |
ab9c17a0 JM |
1869 | if (!mlx4_is_slave(dev)) { |
1870 | mlx4_UNMAP_FA(dev); | |
1871 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); | |
1872 | } | |
225c7b1f RD |
1873 | return err; |
1874 | } | |
1875 | ||
f2a3f6a3 OG |
1876 | static int mlx4_init_counters_table(struct mlx4_dev *dev) |
1877 | { | |
1878 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1879 | int nent; | |
1880 | ||
1881 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1882 | return -ENOENT; | |
1883 | ||
1884 | nent = dev->caps.max_counters; | |
1885 | return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); | |
1886 | } | |
1887 | ||
1888 | static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) | |
1889 | { | |
1890 | mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); | |
1891 | } | |
1892 | ||
ba062d52 | 1893 | int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) |
f2a3f6a3 OG |
1894 | { |
1895 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1896 | ||
1897 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1898 | return -ENOENT; | |
1899 | ||
1900 | *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); | |
1901 | if (*idx == -1) | |
1902 | return -ENOMEM; | |
1903 | ||
1904 | return 0; | |
1905 | } | |
ba062d52 JM |
1906 | |
1907 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) | |
1908 | { | |
1909 | u64 out_param; | |
1910 | int err; | |
1911 | ||
1912 | if (mlx4_is_mfunc(dev)) { | |
1913 | err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, | |
1914 | RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, | |
1915 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
1916 | if (!err) | |
1917 | *idx = get_param_l(&out_param); | |
1918 | ||
1919 | return err; | |
1920 | } | |
1921 | return __mlx4_counter_alloc(dev, idx); | |
1922 | } | |
f2a3f6a3 OG |
1923 | EXPORT_SYMBOL_GPL(mlx4_counter_alloc); |
1924 | ||
ba062d52 | 1925 | void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) |
f2a3f6a3 | 1926 | { |
7c6d74d2 | 1927 | mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); |
f2a3f6a3 OG |
1928 | return; |
1929 | } | |
ba062d52 JM |
1930 | |
1931 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) | |
1932 | { | |
e7dbeba8 | 1933 | u64 in_param = 0; |
ba062d52 JM |
1934 | |
1935 | if (mlx4_is_mfunc(dev)) { | |
1936 | set_param_l(&in_param, idx); | |
1937 | mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, | |
1938 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
1939 | MLX4_CMD_WRAPPED); | |
1940 | return; | |
1941 | } | |
1942 | __mlx4_counter_free(dev, idx); | |
1943 | } | |
f2a3f6a3 OG |
1944 | EXPORT_SYMBOL_GPL(mlx4_counter_free); |
1945 | ||
3d73c288 | 1946 | static int mlx4_setup_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1947 | { |
1948 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1949 | int err; | |
7ff93f8b | 1950 | int port; |
9a5aa622 | 1951 | __be32 ib_port_default_caps; |
225c7b1f | 1952 | |
225c7b1f RD |
1953 | err = mlx4_init_uar_table(dev); |
1954 | if (err) { | |
1a91de28 JP |
1955 | mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); |
1956 | return err; | |
225c7b1f RD |
1957 | } |
1958 | ||
1959 | err = mlx4_uar_alloc(dev, &priv->driver_uar); | |
1960 | if (err) { | |
1a91de28 | 1961 | mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); |
225c7b1f RD |
1962 | goto err_uar_table_free; |
1963 | } | |
1964 | ||
4979d18f | 1965 | priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); |
225c7b1f | 1966 | if (!priv->kar) { |
1a91de28 | 1967 | mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); |
225c7b1f RD |
1968 | err = -ENOMEM; |
1969 | goto err_uar_free; | |
1970 | } | |
1971 | ||
1972 | err = mlx4_init_pd_table(dev); | |
1973 | if (err) { | |
1a91de28 | 1974 | mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); |
225c7b1f RD |
1975 | goto err_kar_unmap; |
1976 | } | |
1977 | ||
012a8ff5 SH |
1978 | err = mlx4_init_xrcd_table(dev); |
1979 | if (err) { | |
1a91de28 | 1980 | mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); |
012a8ff5 SH |
1981 | goto err_pd_table_free; |
1982 | } | |
1983 | ||
225c7b1f RD |
1984 | err = mlx4_init_mr_table(dev); |
1985 | if (err) { | |
1a91de28 | 1986 | mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); |
012a8ff5 | 1987 | goto err_xrcd_table_free; |
225c7b1f RD |
1988 | } |
1989 | ||
fe6f700d YP |
1990 | if (!mlx4_is_slave(dev)) { |
1991 | err = mlx4_init_mcg_table(dev); | |
1992 | if (err) { | |
1a91de28 | 1993 | mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); |
fe6f700d YP |
1994 | goto err_mr_table_free; |
1995 | } | |
114840c3 JM |
1996 | err = mlx4_config_mad_demux(dev); |
1997 | if (err) { | |
1998 | mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); | |
1999 | goto err_mcg_table_free; | |
2000 | } | |
fe6f700d YP |
2001 | } |
2002 | ||
225c7b1f RD |
2003 | err = mlx4_init_eq_table(dev); |
2004 | if (err) { | |
1a91de28 | 2005 | mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); |
fe6f700d | 2006 | goto err_mcg_table_free; |
225c7b1f RD |
2007 | } |
2008 | ||
2009 | err = mlx4_cmd_use_events(dev); | |
2010 | if (err) { | |
1a91de28 | 2011 | mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); |
225c7b1f RD |
2012 | goto err_eq_table_free; |
2013 | } | |
2014 | ||
2015 | err = mlx4_NOP(dev); | |
2016 | if (err) { | |
08fb1055 | 2017 | if (dev->flags & MLX4_FLAG_MSI_X) { |
1a91de28 | 2018 | mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", |
b8dd786f | 2019 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
1a91de28 | 2020 | mlx4_warn(dev, "Trying again without MSI-X\n"); |
08fb1055 | 2021 | } else { |
1a91de28 | 2022 | mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", |
b8dd786f | 2023 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
225c7b1f | 2024 | mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); |
08fb1055 | 2025 | } |
225c7b1f RD |
2026 | |
2027 | goto err_cmd_poll; | |
2028 | } | |
2029 | ||
2030 | mlx4_dbg(dev, "NOP command IRQ test passed\n"); | |
2031 | ||
2032 | err = mlx4_init_cq_table(dev); | |
2033 | if (err) { | |
1a91de28 | 2034 | mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); |
225c7b1f RD |
2035 | goto err_cmd_poll; |
2036 | } | |
2037 | ||
2038 | err = mlx4_init_srq_table(dev); | |
2039 | if (err) { | |
1a91de28 | 2040 | mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); |
225c7b1f RD |
2041 | goto err_cq_table_free; |
2042 | } | |
2043 | ||
2044 | err = mlx4_init_qp_table(dev); | |
2045 | if (err) { | |
1a91de28 | 2046 | mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); |
225c7b1f RD |
2047 | goto err_srq_table_free; |
2048 | } | |
2049 | ||
f2a3f6a3 OG |
2050 | err = mlx4_init_counters_table(dev); |
2051 | if (err && err != -ENOENT) { | |
1a91de28 | 2052 | mlx4_err(dev, "Failed to initialize counters table, aborting\n"); |
fe6f700d | 2053 | goto err_qp_table_free; |
f2a3f6a3 OG |
2054 | } |
2055 | ||
ab9c17a0 JM |
2056 | if (!mlx4_is_slave(dev)) { |
2057 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
ab9c17a0 JM |
2058 | ib_port_default_caps = 0; |
2059 | err = mlx4_get_port_ib_caps(dev, port, | |
2060 | &ib_port_default_caps); | |
2061 | if (err) | |
1a91de28 JP |
2062 | mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", |
2063 | port, err); | |
ab9c17a0 JM |
2064 | dev->caps.ib_port_def_cap[port] = ib_port_default_caps; |
2065 | ||
2aca1172 JM |
2066 | /* initialize per-slave default ib port capabilities */ |
2067 | if (mlx4_is_master(dev)) { | |
2068 | int i; | |
2069 | for (i = 0; i < dev->num_slaves; i++) { | |
2070 | if (i == mlx4_master_func_num(dev)) | |
2071 | continue; | |
2072 | priv->mfunc.master.slave_state[i].ib_cap_mask[port] = | |
1a91de28 | 2073 | ib_port_default_caps; |
2aca1172 JM |
2074 | } |
2075 | } | |
2076 | ||
096335b3 OG |
2077 | if (mlx4_is_mfunc(dev)) |
2078 | dev->caps.port_ib_mtu[port] = IB_MTU_2048; | |
2079 | else | |
2080 | dev->caps.port_ib_mtu[port] = IB_MTU_4096; | |
97285b78 | 2081 | |
6634961c JM |
2082 | err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? |
2083 | dev->caps.pkey_table_len[port] : -1); | |
ab9c17a0 JM |
2084 | if (err) { |
2085 | mlx4_err(dev, "Failed to set port %d, aborting\n", | |
1a91de28 | 2086 | port); |
ab9c17a0 JM |
2087 | goto err_counters_table_free; |
2088 | } | |
7ff93f8b YP |
2089 | } |
2090 | } | |
2091 | ||
225c7b1f RD |
2092 | return 0; |
2093 | ||
f2a3f6a3 OG |
2094 | err_counters_table_free: |
2095 | mlx4_cleanup_counters_table(dev); | |
2096 | ||
225c7b1f RD |
2097 | err_qp_table_free: |
2098 | mlx4_cleanup_qp_table(dev); | |
2099 | ||
2100 | err_srq_table_free: | |
2101 | mlx4_cleanup_srq_table(dev); | |
2102 | ||
2103 | err_cq_table_free: | |
2104 | mlx4_cleanup_cq_table(dev); | |
2105 | ||
2106 | err_cmd_poll: | |
2107 | mlx4_cmd_use_polling(dev); | |
2108 | ||
2109 | err_eq_table_free: | |
2110 | mlx4_cleanup_eq_table(dev); | |
2111 | ||
fe6f700d YP |
2112 | err_mcg_table_free: |
2113 | if (!mlx4_is_slave(dev)) | |
2114 | mlx4_cleanup_mcg_table(dev); | |
2115 | ||
ee49bd93 | 2116 | err_mr_table_free: |
225c7b1f RD |
2117 | mlx4_cleanup_mr_table(dev); |
2118 | ||
012a8ff5 SH |
2119 | err_xrcd_table_free: |
2120 | mlx4_cleanup_xrcd_table(dev); | |
2121 | ||
225c7b1f RD |
2122 | err_pd_table_free: |
2123 | mlx4_cleanup_pd_table(dev); | |
2124 | ||
2125 | err_kar_unmap: | |
2126 | iounmap(priv->kar); | |
2127 | ||
2128 | err_uar_free: | |
2129 | mlx4_uar_free(dev, &priv->driver_uar); | |
2130 | ||
2131 | err_uar_table_free: | |
2132 | mlx4_cleanup_uar_table(dev); | |
2133 | return err; | |
2134 | } | |
2135 | ||
e8f9b2ed | 2136 | static void mlx4_enable_msi_x(struct mlx4_dev *dev) |
225c7b1f RD |
2137 | { |
2138 | struct mlx4_priv *priv = mlx4_priv(dev); | |
b8dd786f | 2139 | struct msix_entry *entries; |
225c7b1f RD |
2140 | int i; |
2141 | ||
2142 | if (msi_x) { | |
7ae0e400 MB |
2143 | int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ; |
2144 | ||
ca4c7b35 OG |
2145 | nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, |
2146 | nreq); | |
ab9c17a0 | 2147 | |
b8dd786f YP |
2148 | entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); |
2149 | if (!entries) | |
2150 | goto no_msi; | |
2151 | ||
2152 | for (i = 0; i < nreq; ++i) | |
225c7b1f RD |
2153 | entries[i].entry = i; |
2154 | ||
66e2f9c1 AG |
2155 | nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq); |
2156 | ||
2157 | if (nreq < 0) { | |
5bf0da7d | 2158 | kfree(entries); |
225c7b1f | 2159 | goto no_msi; |
66e2f9c1 | 2160 | } else if (nreq < MSIX_LEGACY_SZ + |
1a91de28 | 2161 | dev->caps.num_ports * MIN_MSIX_P_PORT) { |
0b7ca5a9 YP |
2162 | /*Working in legacy mode , all EQ's shared*/ |
2163 | dev->caps.comp_pool = 0; | |
2164 | dev->caps.num_comp_vectors = nreq - 1; | |
2165 | } else { | |
2166 | dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; | |
2167 | dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; | |
2168 | } | |
b8dd786f | 2169 | for (i = 0; i < nreq; ++i) |
225c7b1f RD |
2170 | priv->eq_table.eq[i].irq = entries[i].vector; |
2171 | ||
2172 | dev->flags |= MLX4_FLAG_MSI_X; | |
b8dd786f YP |
2173 | |
2174 | kfree(entries); | |
225c7b1f RD |
2175 | return; |
2176 | } | |
2177 | ||
2178 | no_msi: | |
b8dd786f | 2179 | dev->caps.num_comp_vectors = 1; |
0b7ca5a9 | 2180 | dev->caps.comp_pool = 0; |
b8dd786f YP |
2181 | |
2182 | for (i = 0; i < 2; ++i) | |
225c7b1f RD |
2183 | priv->eq_table.eq[i].irq = dev->pdev->irq; |
2184 | } | |
2185 | ||
7ff93f8b | 2186 | static int mlx4_init_port_info(struct mlx4_dev *dev, int port) |
2a2336f8 YP |
2187 | { |
2188 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
7ff93f8b | 2189 | int err = 0; |
2a2336f8 YP |
2190 | |
2191 | info->dev = dev; | |
2192 | info->port = port; | |
ab9c17a0 | 2193 | if (!mlx4_is_slave(dev)) { |
ab9c17a0 JM |
2194 | mlx4_init_mac_table(dev, &info->mac_table); |
2195 | mlx4_init_vlan_table(dev, &info->vlan_table); | |
111c6094 | 2196 | mlx4_init_roce_gid_table(dev, &info->gid_table); |
16a10ffd | 2197 | info->base_qpn = mlx4_get_base_qpn(dev, port); |
ab9c17a0 | 2198 | } |
7ff93f8b YP |
2199 | |
2200 | sprintf(info->dev_name, "mlx4_port%d", port); | |
2201 | info->port_attr.attr.name = info->dev_name; | |
ab9c17a0 JM |
2202 | if (mlx4_is_mfunc(dev)) |
2203 | info->port_attr.attr.mode = S_IRUGO; | |
2204 | else { | |
2205 | info->port_attr.attr.mode = S_IRUGO | S_IWUSR; | |
2206 | info->port_attr.store = set_port_type; | |
2207 | } | |
7ff93f8b | 2208 | info->port_attr.show = show_port_type; |
3691c964 | 2209 | sysfs_attr_init(&info->port_attr.attr); |
7ff93f8b YP |
2210 | |
2211 | err = device_create_file(&dev->pdev->dev, &info->port_attr); | |
2212 | if (err) { | |
2213 | mlx4_err(dev, "Failed to create file for port %d\n", port); | |
2214 | info->port = -1; | |
2215 | } | |
2216 | ||
096335b3 OG |
2217 | sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); |
2218 | info->port_mtu_attr.attr.name = info->dev_mtu_name; | |
2219 | if (mlx4_is_mfunc(dev)) | |
2220 | info->port_mtu_attr.attr.mode = S_IRUGO; | |
2221 | else { | |
2222 | info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; | |
2223 | info->port_mtu_attr.store = set_port_ib_mtu; | |
2224 | } | |
2225 | info->port_mtu_attr.show = show_port_ib_mtu; | |
2226 | sysfs_attr_init(&info->port_mtu_attr.attr); | |
2227 | ||
2228 | err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); | |
2229 | if (err) { | |
2230 | mlx4_err(dev, "Failed to create mtu file for port %d\n", port); | |
2231 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
2232 | info->port = -1; | |
2233 | } | |
2234 | ||
7ff93f8b YP |
2235 | return err; |
2236 | } | |
2237 | ||
2238 | static void mlx4_cleanup_port_info(struct mlx4_port_info *info) | |
2239 | { | |
2240 | if (info->port < 0) | |
2241 | return; | |
2242 | ||
2243 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
096335b3 | 2244 | device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); |
2a2336f8 YP |
2245 | } |
2246 | ||
b12d93d6 YP |
2247 | static int mlx4_init_steering(struct mlx4_dev *dev) |
2248 | { | |
2249 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2250 | int num_entries = dev->caps.num_ports; | |
2251 | int i, j; | |
2252 | ||
2253 | priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); | |
2254 | if (!priv->steer) | |
2255 | return -ENOMEM; | |
2256 | ||
45b51365 | 2257 | for (i = 0; i < num_entries; i++) |
b12d93d6 YP |
2258 | for (j = 0; j < MLX4_NUM_STEERS; j++) { |
2259 | INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); | |
2260 | INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); | |
2261 | } | |
b12d93d6 YP |
2262 | return 0; |
2263 | } | |
2264 | ||
2265 | static void mlx4_clear_steering(struct mlx4_dev *dev) | |
2266 | { | |
2267 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2268 | struct mlx4_steer_index *entry, *tmp_entry; | |
2269 | struct mlx4_promisc_qp *pqp, *tmp_pqp; | |
2270 | int num_entries = dev->caps.num_ports; | |
2271 | int i, j; | |
2272 | ||
2273 | for (i = 0; i < num_entries; i++) { | |
2274 | for (j = 0; j < MLX4_NUM_STEERS; j++) { | |
2275 | list_for_each_entry_safe(pqp, tmp_pqp, | |
2276 | &priv->steer[i].promisc_qps[j], | |
2277 | list) { | |
2278 | list_del(&pqp->list); | |
2279 | kfree(pqp); | |
2280 | } | |
2281 | list_for_each_entry_safe(entry, tmp_entry, | |
2282 | &priv->steer[i].steer_entries[j], | |
2283 | list) { | |
2284 | list_del(&entry->list); | |
2285 | list_for_each_entry_safe(pqp, tmp_pqp, | |
2286 | &entry->duplicates, | |
2287 | list) { | |
2288 | list_del(&pqp->list); | |
2289 | kfree(pqp); | |
2290 | } | |
2291 | kfree(entry); | |
2292 | } | |
2293 | } | |
2294 | } | |
2295 | kfree(priv->steer); | |
2296 | } | |
2297 | ||
ab9c17a0 JM |
2298 | static int extended_func_num(struct pci_dev *pdev) |
2299 | { | |
2300 | return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); | |
2301 | } | |
2302 | ||
2303 | #define MLX4_OWNER_BASE 0x8069c | |
2304 | #define MLX4_OWNER_SIZE 4 | |
2305 | ||
2306 | static int mlx4_get_ownership(struct mlx4_dev *dev) | |
2307 | { | |
2308 | void __iomem *owner; | |
2309 | u32 ret; | |
2310 | ||
57dbf29a KSS |
2311 | if (pci_channel_offline(dev->pdev)) |
2312 | return -EIO; | |
2313 | ||
ab9c17a0 JM |
2314 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, |
2315 | MLX4_OWNER_SIZE); | |
2316 | if (!owner) { | |
2317 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
2318 | return -ENOMEM; | |
2319 | } | |
2320 | ||
2321 | ret = readl(owner); | |
2322 | iounmap(owner); | |
2323 | return (int) !!ret; | |
2324 | } | |
2325 | ||
2326 | static void mlx4_free_ownership(struct mlx4_dev *dev) | |
2327 | { | |
2328 | void __iomem *owner; | |
2329 | ||
57dbf29a KSS |
2330 | if (pci_channel_offline(dev->pdev)) |
2331 | return; | |
2332 | ||
ab9c17a0 JM |
2333 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, |
2334 | MLX4_OWNER_SIZE); | |
2335 | if (!owner) { | |
2336 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
2337 | return; | |
2338 | } | |
2339 | writel(0, owner); | |
2340 | msleep(1000); | |
2341 | iounmap(owner); | |
2342 | } | |
2343 | ||
a0eacca9 MB |
2344 | #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ |
2345 | !!((flags) & MLX4_FLAG_MASTER)) | |
2346 | ||
2347 | static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, | |
2348 | u8 total_vfs, int existing_vfs) | |
2349 | { | |
2350 | u64 dev_flags = dev->flags; | |
2351 | ||
2352 | dev->dev_vfs = kzalloc( | |
2353 | total_vfs * sizeof(*dev->dev_vfs), | |
2354 | GFP_KERNEL); | |
2355 | if (NULL == dev->dev_vfs) { | |
2356 | mlx4_err(dev, "Failed to allocate memory for VFs\n"); | |
2357 | goto disable_sriov; | |
2358 | } else if (!(dev->flags & MLX4_FLAG_SRIOV)) { | |
2359 | int err = 0; | |
2360 | ||
2361 | atomic_inc(&pf_loading); | |
2362 | if (existing_vfs) { | |
2363 | if (existing_vfs != total_vfs) | |
2364 | mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", | |
2365 | existing_vfs, total_vfs); | |
2366 | } else { | |
2367 | mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); | |
2368 | err = pci_enable_sriov(pdev, total_vfs); | |
2369 | } | |
2370 | if (err) { | |
2371 | mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", | |
2372 | err); | |
2373 | atomic_dec(&pf_loading); | |
2374 | goto disable_sriov; | |
2375 | } else { | |
2376 | mlx4_warn(dev, "Running in master mode\n"); | |
2377 | dev_flags |= MLX4_FLAG_SRIOV | | |
2378 | MLX4_FLAG_MASTER; | |
2379 | dev_flags &= ~MLX4_FLAG_SLAVE; | |
2380 | dev->num_vfs = total_vfs; | |
2381 | } | |
2382 | } | |
2383 | return dev_flags; | |
2384 | ||
2385 | disable_sriov: | |
2386 | dev->num_vfs = 0; | |
2387 | kfree(dev->dev_vfs); | |
2388 | return dev_flags & ~MLX4_FLAG_MASTER; | |
2389 | } | |
2390 | ||
de966c59 MB |
2391 | enum { |
2392 | MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, | |
2393 | }; | |
2394 | ||
2395 | static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, | |
2396 | int *nvfs) | |
2397 | { | |
2398 | int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; | |
2399 | /* Checking for 64 VFs as a limitation of CX2 */ | |
2400 | if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && | |
2401 | requested_vfs >= 64) { | |
2402 | mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", | |
2403 | requested_vfs); | |
2404 | return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; | |
2405 | } | |
2406 | return 0; | |
2407 | } | |
2408 | ||
e1c00e10 MD |
2409 | static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, |
2410 | int total_vfs, int *nvfs, struct mlx4_priv *priv) | |
225c7b1f | 2411 | { |
225c7b1f | 2412 | struct mlx4_dev *dev; |
e1c00e10 | 2413 | unsigned sum = 0; |
225c7b1f | 2414 | int err; |
2a2336f8 | 2415 | int port; |
e1c00e10 | 2416 | int i; |
7ae0e400 | 2417 | struct mlx4_dev_cap *dev_cap = NULL; |
bbb07af4 | 2418 | int existing_vfs = 0; |
225c7b1f | 2419 | |
e1c00e10 | 2420 | dev = &priv->dev; |
225c7b1f | 2421 | |
b581401e RD |
2422 | INIT_LIST_HEAD(&priv->ctx_list); |
2423 | spin_lock_init(&priv->ctx_lock); | |
225c7b1f | 2424 | |
7ff93f8b YP |
2425 | mutex_init(&priv->port_mutex); |
2426 | ||
6296883c YP |
2427 | INIT_LIST_HEAD(&priv->pgdir_list); |
2428 | mutex_init(&priv->pgdir_mutex); | |
2429 | ||
c1b43dca EC |
2430 | INIT_LIST_HEAD(&priv->bf_list); |
2431 | mutex_init(&priv->bf_mutex); | |
2432 | ||
aca7a3ac | 2433 | dev->rev_id = pdev->revision; |
6e7136ed | 2434 | dev->numa_node = dev_to_node(&pdev->dev); |
e1c00e10 | 2435 | |
ab9c17a0 | 2436 | /* Detect if this device is a virtual function */ |
839f1243 | 2437 | if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { |
ab9c17a0 JM |
2438 | mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); |
2439 | dev->flags |= MLX4_FLAG_SLAVE; | |
2440 | } else { | |
2441 | /* We reset the device and enable SRIOV only for physical | |
2442 | * devices. Try to claim ownership on the device; | |
2443 | * if already taken, skip -- do not allow multiple PFs */ | |
2444 | err = mlx4_get_ownership(dev); | |
2445 | if (err) { | |
2446 | if (err < 0) | |
e1c00e10 | 2447 | return err; |
ab9c17a0 | 2448 | else { |
1a91de28 | 2449 | mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); |
e1c00e10 | 2450 | return -EINVAL; |
ab9c17a0 JM |
2451 | } |
2452 | } | |
aca7a3ac | 2453 | |
fe6f700d YP |
2454 | atomic_set(&priv->opreq_count, 0); |
2455 | INIT_WORK(&priv->opreq_task, mlx4_opreq_action); | |
2456 | ||
ab9c17a0 JM |
2457 | /* |
2458 | * Now reset the HCA before we touch the PCI capabilities or | |
2459 | * attempt a firmware command, since a boot ROM may have left | |
2460 | * the HCA in an undefined state. | |
2461 | */ | |
2462 | err = mlx4_reset(dev); | |
2463 | if (err) { | |
1a91de28 | 2464 | mlx4_err(dev, "Failed to reset HCA, aborting\n"); |
e1c00e10 | 2465 | goto err_sriov; |
ab9c17a0 | 2466 | } |
7ae0e400 MB |
2467 | |
2468 | if (total_vfs) { | |
2469 | existing_vfs = pci_num_vf(pdev); | |
2470 | dev->flags = MLX4_FLAG_MASTER; | |
2471 | dev->num_vfs = total_vfs; | |
2472 | } | |
225c7b1f RD |
2473 | } |
2474 | ||
ab9c17a0 | 2475 | slave_start: |
521130d1 EE |
2476 | err = mlx4_cmd_init(dev); |
2477 | if (err) { | |
1a91de28 | 2478 | mlx4_err(dev, "Failed to init command interface, aborting\n"); |
ab9c17a0 JM |
2479 | goto err_sriov; |
2480 | } | |
2481 | ||
2482 | /* In slave functions, the communication channel must be initialized | |
2483 | * before posting commands. Also, init num_slaves before calling | |
2484 | * mlx4_init_hca */ | |
2485 | if (mlx4_is_mfunc(dev)) { | |
7ae0e400 | 2486 | if (mlx4_is_master(dev)) { |
ab9c17a0 | 2487 | dev->num_slaves = MLX4_MAX_NUM_SLAVES; |
7ae0e400 MB |
2488 | |
2489 | } else { | |
ab9c17a0 | 2490 | dev->num_slaves = 0; |
f356fcbe JM |
2491 | err = mlx4_multi_func_init(dev); |
2492 | if (err) { | |
1a91de28 | 2493 | mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); |
ab9c17a0 JM |
2494 | goto err_cmd; |
2495 | } | |
2496 | } | |
225c7b1f RD |
2497 | } |
2498 | ||
a0eacca9 MB |
2499 | err = mlx4_init_fw(dev); |
2500 | if (err) { | |
2501 | mlx4_err(dev, "Failed to init fw, aborting.\n"); | |
2502 | goto err_mfunc; | |
2503 | } | |
2504 | ||
7ae0e400 MB |
2505 | if (mlx4_is_master(dev)) { |
2506 | if (!dev_cap) { | |
2507 | dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); | |
2508 | ||
2509 | if (!dev_cap) { | |
2510 | err = -ENOMEM; | |
2511 | goto err_fw; | |
2512 | } | |
2513 | ||
2514 | err = mlx4_QUERY_DEV_CAP(dev, dev_cap); | |
2515 | if (err) { | |
2516 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
2517 | goto err_fw; | |
2518 | } | |
2519 | ||
de966c59 MB |
2520 | if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) |
2521 | goto err_fw; | |
2522 | ||
7ae0e400 MB |
2523 | if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { |
2524 | u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, | |
2525 | existing_vfs); | |
2526 | ||
2527 | mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); | |
2528 | dev->flags = dev_flags; | |
2529 | if (!SRIOV_VALID_STATE(dev->flags)) { | |
2530 | mlx4_err(dev, "Invalid SRIOV state\n"); | |
2531 | goto err_sriov; | |
2532 | } | |
2533 | err = mlx4_reset(dev); | |
2534 | if (err) { | |
2535 | mlx4_err(dev, "Failed to reset HCA, aborting.\n"); | |
2536 | goto err_sriov; | |
2537 | } | |
2538 | goto slave_start; | |
2539 | } | |
2540 | } else { | |
2541 | /* Legacy mode FW requires SRIOV to be enabled before | |
2542 | * doing QUERY_DEV_CAP, since max_eq's value is different if | |
2543 | * SRIOV is enabled. | |
2544 | */ | |
2545 | memset(dev_cap, 0, sizeof(*dev_cap)); | |
2546 | err = mlx4_QUERY_DEV_CAP(dev, dev_cap); | |
2547 | if (err) { | |
2548 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
2549 | goto err_fw; | |
2550 | } | |
de966c59 MB |
2551 | |
2552 | if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) | |
2553 | goto err_fw; | |
7ae0e400 MB |
2554 | } |
2555 | } | |
2556 | ||
225c7b1f | 2557 | err = mlx4_init_hca(dev); |
ab9c17a0 JM |
2558 | if (err) { |
2559 | if (err == -EACCES) { | |
2560 | /* Not primary Physical function | |
2561 | * Running in slave mode */ | |
ffc39f6d | 2562 | mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); |
a0eacca9 MB |
2563 | /* We're not a PF */ |
2564 | if (dev->flags & MLX4_FLAG_SRIOV) { | |
2565 | if (!existing_vfs) | |
2566 | pci_disable_sriov(pdev); | |
2567 | if (mlx4_is_master(dev)) | |
2568 | atomic_dec(&pf_loading); | |
2569 | dev->flags &= ~MLX4_FLAG_SRIOV; | |
2570 | } | |
2571 | if (!mlx4_is_slave(dev)) | |
2572 | mlx4_free_ownership(dev); | |
ab9c17a0 JM |
2573 | dev->flags |= MLX4_FLAG_SLAVE; |
2574 | dev->flags &= ~MLX4_FLAG_MASTER; | |
2575 | goto slave_start; | |
2576 | } else | |
a0eacca9 | 2577 | goto err_fw; |
ab9c17a0 JM |
2578 | } |
2579 | ||
7ae0e400 MB |
2580 | if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { |
2581 | u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, existing_vfs); | |
2582 | ||
2583 | if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { | |
2584 | mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); | |
2585 | dev->flags = dev_flags; | |
2586 | err = mlx4_cmd_init(dev); | |
2587 | if (err) { | |
2588 | /* Only VHCR is cleaned up, so could still | |
2589 | * send FW commands | |
2590 | */ | |
2591 | mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); | |
2592 | goto err_close; | |
2593 | } | |
2594 | } else { | |
2595 | dev->flags = dev_flags; | |
2596 | } | |
2597 | ||
2598 | if (!SRIOV_VALID_STATE(dev->flags)) { | |
2599 | mlx4_err(dev, "Invalid SRIOV state\n"); | |
2600 | goto err_close; | |
2601 | } | |
2602 | } | |
2603 | ||
b912b2f8 EP |
2604 | /* check if the device is functioning at its maximum possible speed. |
2605 | * No return code for this call, just warn the user in case of PCI | |
2606 | * express device capabilities are under-satisfied by the bus. | |
2607 | */ | |
83d3459a EP |
2608 | if (!mlx4_is_slave(dev)) |
2609 | mlx4_check_pcie_caps(dev); | |
b912b2f8 | 2610 | |
ab9c17a0 JM |
2611 | /* In master functions, the communication channel must be initialized |
2612 | * after obtaining its address from fw */ | |
2613 | if (mlx4_is_master(dev)) { | |
e1c00e10 MD |
2614 | int ib_ports = 0; |
2615 | ||
2616 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) | |
2617 | ib_ports++; | |
2618 | ||
2619 | if (ib_ports && | |
2620 | (num_vfs_argc > 1 || probe_vfs_argc > 1)) { | |
2621 | mlx4_err(dev, | |
2622 | "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n"); | |
2623 | err = -EINVAL; | |
2624 | goto err_close; | |
2625 | } | |
2626 | if (dev->caps.num_ports < 2 && | |
2627 | num_vfs_argc > 1) { | |
2628 | err = -EINVAL; | |
2629 | mlx4_err(dev, | |
2630 | "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", | |
2631 | dev->caps.num_ports); | |
ab9c17a0 JM |
2632 | goto err_close; |
2633 | } | |
e1c00e10 | 2634 | memcpy(dev->nvfs, nvfs, sizeof(dev->nvfs)); |
dd41cc3b | 2635 | |
e1c00e10 MD |
2636 | for (i = 0; i < sizeof(dev->nvfs)/sizeof(dev->nvfs[0]); i++) { |
2637 | unsigned j; | |
2638 | ||
2639 | for (j = 0; j < dev->nvfs[i]; ++sum, ++j) { | |
2640 | dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; | |
2641 | dev->dev_vfs[sum].n_ports = i < 2 ? 1 : | |
2642 | dev->caps.num_ports; | |
1ab95d37 MB |
2643 | } |
2644 | } | |
e1c00e10 MD |
2645 | |
2646 | /* In master functions, the communication channel | |
2647 | * must be initialized after obtaining its address from fw | |
2648 | */ | |
2649 | err = mlx4_multi_func_init(dev); | |
2650 | if (err) { | |
2651 | mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); | |
2652 | goto err_close; | |
2653 | } | |
ab9c17a0 | 2654 | } |
225c7b1f | 2655 | |
b8dd786f YP |
2656 | err = mlx4_alloc_eq_table(dev); |
2657 | if (err) | |
ab9c17a0 | 2658 | goto err_master_mfunc; |
b8dd786f | 2659 | |
0b7ca5a9 | 2660 | priv->msix_ctl.pool_bm = 0; |
730c41d5 | 2661 | mutex_init(&priv->msix_ctl.pool_lock); |
0b7ca5a9 | 2662 | |
08fb1055 | 2663 | mlx4_enable_msi_x(dev); |
ab9c17a0 JM |
2664 | if ((mlx4_is_mfunc(dev)) && |
2665 | !(dev->flags & MLX4_FLAG_MSI_X)) { | |
f356fcbe | 2666 | err = -ENOSYS; |
1a91de28 | 2667 | mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); |
b12d93d6 | 2668 | goto err_free_eq; |
ab9c17a0 JM |
2669 | } |
2670 | ||
2671 | if (!mlx4_is_slave(dev)) { | |
2672 | err = mlx4_init_steering(dev); | |
2673 | if (err) | |
e1c00e10 | 2674 | goto err_disable_msix; |
ab9c17a0 | 2675 | } |
b12d93d6 | 2676 | |
225c7b1f | 2677 | err = mlx4_setup_hca(dev); |
ab9c17a0 JM |
2678 | if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && |
2679 | !mlx4_is_mfunc(dev)) { | |
08fb1055 | 2680 | dev->flags &= ~MLX4_FLAG_MSI_X; |
9858d2d1 YP |
2681 | dev->caps.num_comp_vectors = 1; |
2682 | dev->caps.comp_pool = 0; | |
08fb1055 MT |
2683 | pci_disable_msix(pdev); |
2684 | err = mlx4_setup_hca(dev); | |
2685 | } | |
2686 | ||
225c7b1f | 2687 | if (err) |
b12d93d6 | 2688 | goto err_steer; |
225c7b1f | 2689 | |
5a0d0a61 JM |
2690 | mlx4_init_quotas(dev); |
2691 | ||
7ff93f8b YP |
2692 | for (port = 1; port <= dev->caps.num_ports; port++) { |
2693 | err = mlx4_init_port_info(dev, port); | |
2694 | if (err) | |
2695 | goto err_port; | |
2696 | } | |
2a2336f8 | 2697 | |
225c7b1f RD |
2698 | err = mlx4_register_device(dev); |
2699 | if (err) | |
7ff93f8b | 2700 | goto err_port; |
225c7b1f | 2701 | |
b046ffe5 EP |
2702 | mlx4_request_modules(dev); |
2703 | ||
27bf91d6 YP |
2704 | mlx4_sense_init(dev); |
2705 | mlx4_start_sense(dev); | |
2706 | ||
befdf897 | 2707 | priv->removed = 0; |
225c7b1f | 2708 | |
e1a5ddc5 AV |
2709 | if (mlx4_is_master(dev) && dev->num_vfs) |
2710 | atomic_dec(&pf_loading); | |
2711 | ||
225c7b1f RD |
2712 | return 0; |
2713 | ||
7ff93f8b | 2714 | err_port: |
b4f77264 | 2715 | for (--port; port >= 1; --port) |
7ff93f8b YP |
2716 | mlx4_cleanup_port_info(&priv->port[port]); |
2717 | ||
f2a3f6a3 | 2718 | mlx4_cleanup_counters_table(dev); |
225c7b1f RD |
2719 | mlx4_cleanup_qp_table(dev); |
2720 | mlx4_cleanup_srq_table(dev); | |
2721 | mlx4_cleanup_cq_table(dev); | |
2722 | mlx4_cmd_use_polling(dev); | |
2723 | mlx4_cleanup_eq_table(dev); | |
fe6f700d | 2724 | mlx4_cleanup_mcg_table(dev); |
225c7b1f | 2725 | mlx4_cleanup_mr_table(dev); |
012a8ff5 | 2726 | mlx4_cleanup_xrcd_table(dev); |
225c7b1f RD |
2727 | mlx4_cleanup_pd_table(dev); |
2728 | mlx4_cleanup_uar_table(dev); | |
2729 | ||
b12d93d6 | 2730 | err_steer: |
ab9c17a0 JM |
2731 | if (!mlx4_is_slave(dev)) |
2732 | mlx4_clear_steering(dev); | |
b12d93d6 | 2733 | |
e1c00e10 MD |
2734 | err_disable_msix: |
2735 | if (dev->flags & MLX4_FLAG_MSI_X) | |
2736 | pci_disable_msix(pdev); | |
2737 | ||
b8dd786f YP |
2738 | err_free_eq: |
2739 | mlx4_free_eq_table(dev); | |
2740 | ||
ab9c17a0 JM |
2741 | err_master_mfunc: |
2742 | if (mlx4_is_master(dev)) | |
2743 | mlx4_multi_func_cleanup(dev); | |
2744 | ||
b38f2879 | 2745 | if (mlx4_is_slave(dev)) { |
99ec41d0 | 2746 | kfree(dev->caps.qp0_qkey); |
b38f2879 DB |
2747 | kfree(dev->caps.qp0_tunnel); |
2748 | kfree(dev->caps.qp0_proxy); | |
2749 | kfree(dev->caps.qp1_tunnel); | |
2750 | kfree(dev->caps.qp1_proxy); | |
2751 | } | |
2752 | ||
225c7b1f RD |
2753 | err_close: |
2754 | mlx4_close_hca(dev); | |
2755 | ||
a0eacca9 MB |
2756 | err_fw: |
2757 | mlx4_close_fw(dev); | |
2758 | ||
ab9c17a0 JM |
2759 | err_mfunc: |
2760 | if (mlx4_is_slave(dev)) | |
2761 | mlx4_multi_func_cleanup(dev); | |
2762 | ||
225c7b1f | 2763 | err_cmd: |
ffc39f6d | 2764 | mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); |
225c7b1f | 2765 | |
ab9c17a0 | 2766 | err_sriov: |
bbb07af4 | 2767 | if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) |
ab9c17a0 JM |
2768 | pci_disable_sriov(pdev); |
2769 | ||
e1a5ddc5 AV |
2770 | if (mlx4_is_master(dev) && dev->num_vfs) |
2771 | atomic_dec(&pf_loading); | |
2772 | ||
1ab95d37 MB |
2773 | kfree(priv->dev.dev_vfs); |
2774 | ||
e1c00e10 MD |
2775 | if (!mlx4_is_slave(dev)) |
2776 | mlx4_free_ownership(dev); | |
2777 | ||
7ae0e400 | 2778 | kfree(dev_cap); |
e1c00e10 MD |
2779 | return err; |
2780 | } | |
2781 | ||
2782 | static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, | |
2783 | struct mlx4_priv *priv) | |
2784 | { | |
2785 | int err; | |
2786 | int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; | |
2787 | int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; | |
2788 | const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { | |
2789 | {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; | |
2790 | unsigned total_vfs = 0; | |
2791 | unsigned int i; | |
2792 | ||
2793 | pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); | |
2794 | ||
2795 | err = pci_enable_device(pdev); | |
2796 | if (err) { | |
2797 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); | |
2798 | return err; | |
2799 | } | |
2800 | ||
2801 | /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS | |
2802 | * per port, we must limit the number of VFs to 63 (since their are | |
2803 | * 128 MACs) | |
2804 | */ | |
2805 | for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; | |
2806 | total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { | |
2807 | nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; | |
2808 | if (nvfs[i] < 0) { | |
2809 | dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); | |
2810 | err = -EINVAL; | |
2811 | goto err_disable_pdev; | |
2812 | } | |
2813 | } | |
2814 | for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; | |
2815 | i++) { | |
2816 | prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; | |
2817 | if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { | |
2818 | dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); | |
2819 | err = -EINVAL; | |
2820 | goto err_disable_pdev; | |
2821 | } | |
2822 | } | |
2823 | if (total_vfs >= MLX4_MAX_NUM_VF) { | |
2824 | dev_err(&pdev->dev, | |
2825 | "Requested more VF's (%d) than allowed (%d)\n", | |
2826 | total_vfs, MLX4_MAX_NUM_VF - 1); | |
2827 | err = -EINVAL; | |
2828 | goto err_disable_pdev; | |
2829 | } | |
2830 | ||
2831 | for (i = 0; i < MLX4_MAX_PORTS; i++) { | |
2832 | if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) { | |
2833 | dev_err(&pdev->dev, | |
2834 | "Requested more VF's (%d) for port (%d) than allowed (%d)\n", | |
2835 | nvfs[i] + nvfs[2], i + 1, | |
2836 | MLX4_MAX_NUM_VF_P_PORT - 1); | |
2837 | err = -EINVAL; | |
2838 | goto err_disable_pdev; | |
2839 | } | |
2840 | } | |
2841 | ||
2842 | /* Check for BARs. */ | |
2843 | if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && | |
2844 | !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
2845 | dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", | |
2846 | pci_dev_data, pci_resource_flags(pdev, 0)); | |
2847 | err = -ENODEV; | |
2848 | goto err_disable_pdev; | |
2849 | } | |
2850 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
2851 | dev_err(&pdev->dev, "Missing UAR, aborting\n"); | |
2852 | err = -ENODEV; | |
2853 | goto err_disable_pdev; | |
2854 | } | |
2855 | ||
2856 | err = pci_request_regions(pdev, DRV_NAME); | |
2857 | if (err) { | |
2858 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
2859 | goto err_disable_pdev; | |
2860 | } | |
2861 | ||
2862 | pci_set_master(pdev); | |
2863 | ||
2864 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
2865 | if (err) { | |
2866 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); | |
2867 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2868 | if (err) { | |
2869 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); | |
2870 | goto err_release_regions; | |
2871 | } | |
2872 | } | |
2873 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
2874 | if (err) { | |
2875 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); | |
2876 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2877 | if (err) { | |
2878 | dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); | |
2879 | goto err_release_regions; | |
2880 | } | |
2881 | } | |
2882 | ||
2883 | /* Allow large DMA segments, up to the firmware limit of 1 GB */ | |
2884 | dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); | |
2885 | /* Detect if this device is a virtual function */ | |
2886 | if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { | |
2887 | /* When acting as pf, we normally skip vfs unless explicitly | |
2888 | * requested to probe them. | |
2889 | */ | |
2890 | if (total_vfs) { | |
2891 | unsigned vfs_offset = 0; | |
2892 | ||
2893 | for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && | |
2894 | vfs_offset + nvfs[i] < extended_func_num(pdev); | |
2895 | vfs_offset += nvfs[i], i++) | |
2896 | ; | |
2897 | if (i == sizeof(nvfs)/sizeof(nvfs[0])) { | |
2898 | err = -ENODEV; | |
2899 | goto err_release_regions; | |
2900 | } | |
2901 | if ((extended_func_num(pdev) - vfs_offset) | |
2902 | > prb_vf[i]) { | |
2903 | dev_warn(&pdev->dev, "Skipping virtual function:%d\n", | |
2904 | extended_func_num(pdev)); | |
2905 | err = -ENODEV; | |
2906 | goto err_release_regions; | |
2907 | } | |
2908 | } | |
2909 | } | |
2910 | ||
2911 | err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv); | |
2912 | if (err) | |
2913 | goto err_release_regions; | |
2914 | return 0; | |
225c7b1f | 2915 | |
a01df0fe RD |
2916 | err_release_regions: |
2917 | pci_release_regions(pdev); | |
225c7b1f RD |
2918 | |
2919 | err_disable_pdev: | |
2920 | pci_disable_device(pdev); | |
2921 | pci_set_drvdata(pdev, NULL); | |
2922 | return err; | |
2923 | } | |
2924 | ||
1dd06ae8 | 2925 | static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
3d73c288 | 2926 | { |
befdf897 WY |
2927 | struct mlx4_priv *priv; |
2928 | struct mlx4_dev *dev; | |
e1c00e10 | 2929 | int ret; |
befdf897 | 2930 | |
0a645e80 | 2931 | printk_once(KERN_INFO "%s", mlx4_version); |
3d73c288 | 2932 | |
befdf897 WY |
2933 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
2934 | if (!priv) | |
2935 | return -ENOMEM; | |
2936 | ||
2937 | dev = &priv->dev; | |
e1c00e10 | 2938 | dev->pdev = pdev; |
befdf897 WY |
2939 | pci_set_drvdata(pdev, dev); |
2940 | priv->pci_dev_data = id->driver_data; | |
2941 | ||
e1c00e10 MD |
2942 | ret = __mlx4_init_one(pdev, id->driver_data, priv); |
2943 | if (ret) | |
2944 | kfree(priv); | |
2945 | ||
2946 | return ret; | |
3d73c288 RD |
2947 | } |
2948 | ||
e1c00e10 | 2949 | static void mlx4_unload_one(struct pci_dev *pdev) |
225c7b1f RD |
2950 | { |
2951 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
2952 | struct mlx4_priv *priv = mlx4_priv(dev); | |
befdf897 | 2953 | int pci_dev_data; |
225c7b1f | 2954 | int p; |
bbb07af4 | 2955 | int active_vfs = 0; |
225c7b1f | 2956 | |
befdf897 WY |
2957 | if (priv->removed) |
2958 | return; | |
225c7b1f | 2959 | |
befdf897 | 2960 | pci_dev_data = priv->pci_dev_data; |
225c7b1f | 2961 | |
bbb07af4 JM |
2962 | /* Disabling SR-IOV is not allowed while there are active vf's */ |
2963 | if (mlx4_is_master(dev)) { | |
2964 | active_vfs = mlx4_how_many_lives_vf(dev); | |
2965 | if (active_vfs) { | |
2966 | pr_warn("Removing PF when there are active VF's !!\n"); | |
2967 | pr_warn("Will not disable SR-IOV.\n"); | |
2968 | } | |
2969 | } | |
befdf897 WY |
2970 | mlx4_stop_sense(dev); |
2971 | mlx4_unregister_device(dev); | |
225c7b1f | 2972 | |
befdf897 WY |
2973 | for (p = 1; p <= dev->caps.num_ports; p++) { |
2974 | mlx4_cleanup_port_info(&priv->port[p]); | |
2975 | mlx4_CLOSE_PORT(dev, p); | |
2976 | } | |
2977 | ||
2978 | if (mlx4_is_master(dev)) | |
2979 | mlx4_free_resource_tracker(dev, | |
2980 | RES_TR_FREE_SLAVES_ONLY); | |
2981 | ||
2982 | mlx4_cleanup_counters_table(dev); | |
2983 | mlx4_cleanup_qp_table(dev); | |
2984 | mlx4_cleanup_srq_table(dev); | |
2985 | mlx4_cleanup_cq_table(dev); | |
2986 | mlx4_cmd_use_polling(dev); | |
2987 | mlx4_cleanup_eq_table(dev); | |
2988 | mlx4_cleanup_mcg_table(dev); | |
2989 | mlx4_cleanup_mr_table(dev); | |
2990 | mlx4_cleanup_xrcd_table(dev); | |
2991 | mlx4_cleanup_pd_table(dev); | |
225c7b1f | 2992 | |
befdf897 WY |
2993 | if (mlx4_is_master(dev)) |
2994 | mlx4_free_resource_tracker(dev, | |
2995 | RES_TR_FREE_STRUCTS_ONLY); | |
47605df9 | 2996 | |
befdf897 WY |
2997 | iounmap(priv->kar); |
2998 | mlx4_uar_free(dev, &priv->driver_uar); | |
2999 | mlx4_cleanup_uar_table(dev); | |
3000 | if (!mlx4_is_slave(dev)) | |
3001 | mlx4_clear_steering(dev); | |
3002 | mlx4_free_eq_table(dev); | |
3003 | if (mlx4_is_master(dev)) | |
3004 | mlx4_multi_func_cleanup(dev); | |
3005 | mlx4_close_hca(dev); | |
a0eacca9 | 3006 | mlx4_close_fw(dev); |
befdf897 WY |
3007 | if (mlx4_is_slave(dev)) |
3008 | mlx4_multi_func_cleanup(dev); | |
ffc39f6d | 3009 | mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); |
47605df9 | 3010 | |
befdf897 WY |
3011 | if (dev->flags & MLX4_FLAG_MSI_X) |
3012 | pci_disable_msix(pdev); | |
bbb07af4 | 3013 | if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { |
befdf897 WY |
3014 | mlx4_warn(dev, "Disabling SR-IOV\n"); |
3015 | pci_disable_sriov(pdev); | |
a0eacca9 | 3016 | dev->flags &= ~MLX4_FLAG_SRIOV; |
e1a5ddc5 | 3017 | dev->num_vfs = 0; |
225c7b1f | 3018 | } |
befdf897 WY |
3019 | |
3020 | if (!mlx4_is_slave(dev)) | |
3021 | mlx4_free_ownership(dev); | |
3022 | ||
99ec41d0 | 3023 | kfree(dev->caps.qp0_qkey); |
befdf897 WY |
3024 | kfree(dev->caps.qp0_tunnel); |
3025 | kfree(dev->caps.qp0_proxy); | |
3026 | kfree(dev->caps.qp1_tunnel); | |
3027 | kfree(dev->caps.qp1_proxy); | |
3028 | kfree(dev->dev_vfs); | |
3029 | ||
befdf897 WY |
3030 | memset(priv, 0, sizeof(*priv)); |
3031 | priv->pci_dev_data = pci_dev_data; | |
3032 | priv->removed = 1; | |
3033 | } | |
3034 | ||
3035 | static void mlx4_remove_one(struct pci_dev *pdev) | |
3036 | { | |
3037 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
3038 | struct mlx4_priv *priv = mlx4_priv(dev); | |
3039 | ||
e1c00e10 MD |
3040 | mlx4_unload_one(pdev); |
3041 | pci_release_regions(pdev); | |
3042 | pci_disable_device(pdev); | |
befdf897 WY |
3043 | kfree(priv); |
3044 | pci_set_drvdata(pdev, NULL); | |
225c7b1f RD |
3045 | } |
3046 | ||
ee49bd93 JM |
3047 | int mlx4_restart_one(struct pci_dev *pdev) |
3048 | { | |
839f1243 RD |
3049 | struct mlx4_dev *dev = pci_get_drvdata(pdev); |
3050 | struct mlx4_priv *priv = mlx4_priv(dev); | |
e1c00e10 MD |
3051 | int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; |
3052 | int pci_dev_data, err, total_vfs; | |
839f1243 RD |
3053 | |
3054 | pci_dev_data = priv->pci_dev_data; | |
e1c00e10 MD |
3055 | total_vfs = dev->num_vfs; |
3056 | memcpy(nvfs, dev->nvfs, sizeof(dev->nvfs)); | |
3057 | ||
3058 | mlx4_unload_one(pdev); | |
3059 | err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv); | |
3060 | if (err) { | |
3061 | mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", | |
3062 | __func__, pci_name(pdev), err); | |
3063 | return err; | |
3064 | } | |
3065 | ||
3066 | return err; | |
ee49bd93 JM |
3067 | } |
3068 | ||
9baa3c34 | 3069 | static const struct pci_device_id mlx4_pci_table[] = { |
ab9c17a0 | 3070 | /* MT25408 "Hermon" SDR */ |
ca3e57a5 | 3071 | { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3072 | /* MT25408 "Hermon" DDR */ |
ca3e57a5 | 3073 | { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3074 | /* MT25408 "Hermon" QDR */ |
ca3e57a5 | 3075 | { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3076 | /* MT25408 "Hermon" DDR PCIe gen2 */ |
ca3e57a5 | 3077 | { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3078 | /* MT25408 "Hermon" QDR PCIe gen2 */ |
ca3e57a5 | 3079 | { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3080 | /* MT25408 "Hermon" EN 10GigE */ |
ca3e57a5 | 3081 | { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3082 | /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ |
ca3e57a5 | 3083 | { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3084 | /* MT25458 ConnectX EN 10GBASE-T 10GigE */ |
ca3e57a5 | 3085 | { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3086 | /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ |
ca3e57a5 | 3087 | { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3088 | /* MT26468 ConnectX EN 10GigE PCIe gen2*/ |
ca3e57a5 | 3089 | { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3090 | /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ |
ca3e57a5 | 3091 | { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3092 | /* MT26478 ConnectX2 40GigE PCIe gen2 */ |
ca3e57a5 | 3093 | { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 3094 | /* MT25400 Family [ConnectX-2 Virtual Function] */ |
839f1243 | 3095 | { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, |
ab9c17a0 JM |
3096 | /* MT27500 Family [ConnectX-3] */ |
3097 | { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, | |
3098 | /* MT27500 Family [ConnectX-3 Virtual Function] */ | |
839f1243 | 3099 | { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, |
ab9c17a0 JM |
3100 | { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ |
3101 | { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ | |
3102 | { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ | |
3103 | { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ | |
3104 | { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ | |
3105 | { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ | |
3106 | { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ | |
3107 | { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ | |
3108 | { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ | |
3109 | { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ | |
3110 | { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ | |
3111 | { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ | |
225c7b1f RD |
3112 | { 0, } |
3113 | }; | |
3114 | ||
3115 | MODULE_DEVICE_TABLE(pci, mlx4_pci_table); | |
3116 | ||
57dbf29a KSS |
3117 | static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, |
3118 | pci_channel_state_t state) | |
3119 | { | |
e1c00e10 | 3120 | mlx4_unload_one(pdev); |
57dbf29a KSS |
3121 | |
3122 | return state == pci_channel_io_perm_failure ? | |
3123 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
3124 | } | |
3125 | ||
3126 | static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) | |
3127 | { | |
befdf897 WY |
3128 | struct mlx4_dev *dev = pci_get_drvdata(pdev); |
3129 | struct mlx4_priv *priv = mlx4_priv(dev); | |
3130 | int ret; | |
97a5221f | 3131 | |
e1c00e10 | 3132 | ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv); |
57dbf29a KSS |
3133 | |
3134 | return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
3135 | } | |
3136 | ||
3646f0e5 | 3137 | static const struct pci_error_handlers mlx4_err_handler = { |
57dbf29a KSS |
3138 | .error_detected = mlx4_pci_err_detected, |
3139 | .slot_reset = mlx4_pci_slot_reset, | |
3140 | }; | |
3141 | ||
225c7b1f RD |
3142 | static struct pci_driver mlx4_driver = { |
3143 | .name = DRV_NAME, | |
3144 | .id_table = mlx4_pci_table, | |
3145 | .probe = mlx4_init_one, | |
e1c00e10 | 3146 | .shutdown = mlx4_unload_one, |
f57e6848 | 3147 | .remove = mlx4_remove_one, |
57dbf29a | 3148 | .err_handler = &mlx4_err_handler, |
225c7b1f RD |
3149 | }; |
3150 | ||
7ff93f8b YP |
3151 | static int __init mlx4_verify_params(void) |
3152 | { | |
3153 | if ((log_num_mac < 0) || (log_num_mac > 7)) { | |
c20862c8 | 3154 | pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); |
7ff93f8b YP |
3155 | return -1; |
3156 | } | |
3157 | ||
cb29688a | 3158 | if (log_num_vlan != 0) |
c20862c8 AV |
3159 | pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", |
3160 | MLX4_LOG_NUM_VLANS); | |
7ff93f8b | 3161 | |
ecc8fb11 AV |
3162 | if (use_prio != 0) |
3163 | pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); | |
7ff93f8b | 3164 | |
0498628f | 3165 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { |
c20862c8 AV |
3166 | pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", |
3167 | log_mtts_per_seg); | |
ab6bf42e EC |
3168 | return -1; |
3169 | } | |
3170 | ||
ab9c17a0 JM |
3171 | /* Check if module param for ports type has legal combination */ |
3172 | if (port_type_array[0] == false && port_type_array[1] == true) { | |
c20862c8 | 3173 | pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); |
ab9c17a0 JM |
3174 | port_type_array[0] = true; |
3175 | } | |
3176 | ||
3c439b55 JM |
3177 | if (mlx4_log_num_mgm_entry_size != -1 && |
3178 | (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || | |
3179 | mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { | |
1a91de28 JP |
3180 | pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n", |
3181 | mlx4_log_num_mgm_entry_size, | |
3182 | MLX4_MIN_MGM_LOG_ENTRY_SIZE, | |
3183 | MLX4_MAX_MGM_LOG_ENTRY_SIZE); | |
3c439b55 JM |
3184 | return -1; |
3185 | } | |
3186 | ||
7ff93f8b YP |
3187 | return 0; |
3188 | } | |
3189 | ||
225c7b1f RD |
3190 | static int __init mlx4_init(void) |
3191 | { | |
3192 | int ret; | |
3193 | ||
7ff93f8b YP |
3194 | if (mlx4_verify_params()) |
3195 | return -EINVAL; | |
3196 | ||
27bf91d6 YP |
3197 | mlx4_catas_init(); |
3198 | ||
3199 | mlx4_wq = create_singlethread_workqueue("mlx4"); | |
3200 | if (!mlx4_wq) | |
3201 | return -ENOMEM; | |
ee49bd93 | 3202 | |
225c7b1f | 3203 | ret = pci_register_driver(&mlx4_driver); |
1b85ee09 WY |
3204 | if (ret < 0) |
3205 | destroy_workqueue(mlx4_wq); | |
225c7b1f RD |
3206 | return ret < 0 ? ret : 0; |
3207 | } | |
3208 | ||
3209 | static void __exit mlx4_cleanup(void) | |
3210 | { | |
3211 | pci_unregister_driver(&mlx4_driver); | |
27bf91d6 | 3212 | destroy_workqueue(mlx4_wq); |
225c7b1f RD |
3213 | } |
3214 | ||
3215 | module_init(mlx4_init); | |
3216 | module_exit(mlx4_cleanup); |