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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
51a379d0 | 4 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
5 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/errno.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 41 | #include <linux/slab.h> |
c1b43dca | 42 | #include <linux/io-mapping.h> |
ab9c17a0 | 43 | #include <linux/delay.h> |
b046ffe5 | 44 | #include <linux/kmod.h> |
225c7b1f RD |
45 | |
46 | #include <linux/mlx4/device.h> | |
47 | #include <linux/mlx4/doorbell.h> | |
48 | ||
49 | #include "mlx4.h" | |
50 | #include "fw.h" | |
51 | #include "icm.h" | |
52 | ||
53 | MODULE_AUTHOR("Roland Dreier"); | |
54 | MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); | |
55 | MODULE_LICENSE("Dual BSD/GPL"); | |
56 | MODULE_VERSION(DRV_VERSION); | |
57 | ||
27bf91d6 YP |
58 | struct workqueue_struct *mlx4_wq; |
59 | ||
225c7b1f RD |
60 | #ifdef CONFIG_MLX4_DEBUG |
61 | ||
62 | int mlx4_debug_level = 0; | |
63 | module_param_named(debug_level, mlx4_debug_level, int, 0644); | |
64 | MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); | |
65 | ||
66 | #endif /* CONFIG_MLX4_DEBUG */ | |
67 | ||
68 | #ifdef CONFIG_PCI_MSI | |
69 | ||
08fb1055 | 70 | static int msi_x = 1; |
225c7b1f RD |
71 | module_param(msi_x, int, 0444); |
72 | MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); | |
73 | ||
74 | #else /* CONFIG_PCI_MSI */ | |
75 | ||
76 | #define msi_x (0) | |
77 | ||
78 | #endif /* CONFIG_PCI_MSI */ | |
79 | ||
dd41cc3b MB |
80 | static uint8_t num_vfs[3] = {0, 0, 0}; |
81 | static int num_vfs_argc = 3; | |
82 | module_param_array(num_vfs, byte , &num_vfs_argc, 0444); | |
83 | MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" | |
84 | "num_vfs=port1,port2,port1+2"); | |
85 | ||
86 | static uint8_t probe_vf[3] = {0, 0, 0}; | |
87 | static int probe_vfs_argc = 3; | |
88 | module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); | |
89 | MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" | |
90 | "probe_vf=port1,port2,port1+2"); | |
ab9c17a0 | 91 | |
3c439b55 | 92 | int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; |
0ec2c0f8 EE |
93 | module_param_named(log_num_mgm_entry_size, |
94 | mlx4_log_num_mgm_entry_size, int, 0444); | |
95 | MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" | |
96 | " of qp per mcg, for example:" | |
3c439b55 | 97 | " 10 gives 248.range: 7 <=" |
0ff1fb65 | 98 | " log_num_mgm_entry_size <= 12." |
3c439b55 JM |
99 | " To activate device managed" |
100 | " flow steering when available, set to -1"); | |
0ec2c0f8 | 101 | |
be902ab1 | 102 | static bool enable_64b_cqe_eqe = true; |
08ff3235 OG |
103 | module_param(enable_64b_cqe_eqe, bool, 0444); |
104 | MODULE_PARM_DESC(enable_64b_cqe_eqe, | |
be902ab1 | 105 | "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); |
08ff3235 | 106 | |
08ff3235 | 107 | #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE |
ab9c17a0 | 108 | |
f57e6848 | 109 | static char mlx4_version[] = |
225c7b1f RD |
110 | DRV_NAME ": Mellanox ConnectX core driver v" |
111 | DRV_VERSION " (" DRV_RELDATE ")\n"; | |
112 | ||
113 | static struct mlx4_profile default_profile = { | |
ab9c17a0 | 114 | .num_qp = 1 << 18, |
225c7b1f | 115 | .num_srq = 1 << 16, |
c9f2ba5e | 116 | .rdmarc_per_qp = 1 << 4, |
225c7b1f RD |
117 | .num_cq = 1 << 16, |
118 | .num_mcg = 1 << 13, | |
ab9c17a0 | 119 | .num_mpt = 1 << 19, |
9fd7a1e1 | 120 | .num_mtt = 1 << 20, /* It is really num mtt segements */ |
225c7b1f RD |
121 | }; |
122 | ||
ab9c17a0 | 123 | static int log_num_mac = 7; |
93fc9e1b YP |
124 | module_param_named(log_num_mac, log_num_mac, int, 0444); |
125 | MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); | |
126 | ||
127 | static int log_num_vlan; | |
128 | module_param_named(log_num_vlan, log_num_vlan, int, 0444); | |
129 | MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); | |
cb29688a OG |
130 | /* Log2 max number of VLANs per ETH port (0-7) */ |
131 | #define MLX4_LOG_NUM_VLANS 7 | |
93fc9e1b | 132 | |
eb939922 | 133 | static bool use_prio; |
93fc9e1b | 134 | module_param_named(use_prio, use_prio, bool, 0444); |
ecc8fb11 | 135 | MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); |
93fc9e1b | 136 | |
2b8fb286 | 137 | int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); |
ab6bf42e | 138 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); |
0498628f | 139 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); |
ab6bf42e | 140 | |
8d0fc7b6 | 141 | static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; |
ab9c17a0 JM |
142 | static int arr_argc = 2; |
143 | module_param_array(port_type_array, int, &arr_argc, 0444); | |
8d0fc7b6 YP |
144 | MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " |
145 | "1 for IB, 2 for Ethernet"); | |
ab9c17a0 JM |
146 | |
147 | struct mlx4_port_config { | |
148 | struct list_head list; | |
149 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; | |
150 | struct pci_dev *pdev; | |
151 | }; | |
152 | ||
97989356 AV |
153 | static atomic_t pf_loading = ATOMIC_INIT(0); |
154 | ||
27bf91d6 YP |
155 | int mlx4_check_port_params(struct mlx4_dev *dev, |
156 | enum mlx4_port_type *port_type) | |
7ff93f8b YP |
157 | { |
158 | int i; | |
159 | ||
160 | for (i = 0; i < dev->caps.num_ports - 1; i++) { | |
27bf91d6 YP |
161 | if (port_type[i] != port_type[i + 1]) { |
162 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { | |
1a91de28 | 163 | mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); |
27bf91d6 YP |
164 | return -EINVAL; |
165 | } | |
7ff93f8b YP |
166 | } |
167 | } | |
7ff93f8b YP |
168 | |
169 | for (i = 0; i < dev->caps.num_ports; i++) { | |
170 | if (!(port_type[i] & dev->caps.supported_type[i+1])) { | |
1a91de28 JP |
171 | mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", |
172 | i + 1); | |
7ff93f8b YP |
173 | return -EINVAL; |
174 | } | |
175 | } | |
176 | return 0; | |
177 | } | |
178 | ||
179 | static void mlx4_set_port_mask(struct mlx4_dev *dev) | |
180 | { | |
181 | int i; | |
182 | ||
7ff93f8b | 183 | for (i = 1; i <= dev->caps.num_ports; ++i) |
65dab25d | 184 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
7ff93f8b | 185 | } |
f2a3f6a3 | 186 | |
3d73c288 | 187 | static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
225c7b1f RD |
188 | { |
189 | int err; | |
5ae2a7a8 | 190 | int i; |
225c7b1f RD |
191 | |
192 | err = mlx4_QUERY_DEV_CAP(dev, dev_cap); | |
193 | if (err) { | |
1a91de28 | 194 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
225c7b1f RD |
195 | return err; |
196 | } | |
197 | ||
198 | if (dev_cap->min_page_sz > PAGE_SIZE) { | |
1a91de28 | 199 | mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", |
225c7b1f RD |
200 | dev_cap->min_page_sz, PAGE_SIZE); |
201 | return -ENODEV; | |
202 | } | |
203 | if (dev_cap->num_ports > MLX4_MAX_PORTS) { | |
1a91de28 | 204 | mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", |
225c7b1f RD |
205 | dev_cap->num_ports, MLX4_MAX_PORTS); |
206 | return -ENODEV; | |
207 | } | |
208 | ||
209 | if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { | |
1a91de28 | 210 | mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", |
225c7b1f RD |
211 | dev_cap->uar_size, |
212 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
213 | return -ENODEV; | |
214 | } | |
215 | ||
216 | dev->caps.num_ports = dev_cap->num_ports; | |
3fc929e2 | 217 | dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM; |
5ae2a7a8 RD |
218 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
219 | dev->caps.vl_cap[i] = dev_cap->max_vl[i]; | |
b79acb49 | 220 | dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; |
6634961c JM |
221 | dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; |
222 | dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; | |
223 | /* set gid and pkey table operating lengths by default | |
224 | * to non-sriov values */ | |
5ae2a7a8 RD |
225 | dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; |
226 | dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; | |
227 | dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; | |
b79acb49 YP |
228 | dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; |
229 | dev->caps.def_mac[i] = dev_cap->def_mac[i]; | |
7ff93f8b | 230 | dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; |
8d0fc7b6 YP |
231 | dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; |
232 | dev->caps.default_sense[i] = dev_cap->default_sense[i]; | |
7699517d YP |
233 | dev->caps.trans_type[i] = dev_cap->trans_type[i]; |
234 | dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; | |
235 | dev->caps.wavelength[i] = dev_cap->wavelength[i]; | |
236 | dev->caps.trans_code[i] = dev_cap->trans_code[i]; | |
5ae2a7a8 RD |
237 | } |
238 | ||
ab9c17a0 | 239 | dev->caps.uar_page_size = PAGE_SIZE; |
225c7b1f | 240 | dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; |
225c7b1f RD |
241 | dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; |
242 | dev->caps.bf_reg_size = dev_cap->bf_reg_size; | |
243 | dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; | |
244 | dev->caps.max_sq_sg = dev_cap->max_sq_sg; | |
245 | dev->caps.max_rq_sg = dev_cap->max_rq_sg; | |
246 | dev->caps.max_wqes = dev_cap->max_qp_sz; | |
247 | dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; | |
225c7b1f RD |
248 | dev->caps.max_srq_wqes = dev_cap->max_srq_sz; |
249 | dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; | |
250 | dev->caps.reserved_srqs = dev_cap->reserved_srqs; | |
251 | dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; | |
252 | dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; | |
225c7b1f RD |
253 | /* |
254 | * Subtract 1 from the limit because we need to allocate a | |
255 | * spare CQE so the HCA HW can tell the difference between an | |
256 | * empty CQ and a full CQ. | |
257 | */ | |
258 | dev->caps.max_cqes = dev_cap->max_cq_sz - 1; | |
259 | dev->caps.reserved_cqs = dev_cap->reserved_cqs; | |
260 | dev->caps.reserved_eqs = dev_cap->reserved_eqs; | |
2b8fb286 | 261 | dev->caps.reserved_mtts = dev_cap->reserved_mtts; |
225c7b1f | 262 | dev->caps.reserved_mrws = dev_cap->reserved_mrws; |
ab9c17a0 JM |
263 | |
264 | /* The first 128 UARs are used for EQ doorbells */ | |
265 | dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); | |
225c7b1f | 266 | dev->caps.reserved_pds = dev_cap->reserved_pds; |
012a8ff5 SH |
267 | dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? |
268 | dev_cap->reserved_xrcds : 0; | |
269 | dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? | |
270 | dev_cap->max_xrcds : 0; | |
2b8fb286 MA |
271 | dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; |
272 | ||
149983af | 273 | dev->caps.max_msg_sz = dev_cap->max_msg_sz; |
225c7b1f RD |
274 | dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); |
275 | dev->caps.flags = dev_cap->flags; | |
b3416f44 | 276 | dev->caps.flags2 = dev_cap->flags2; |
95d04f07 RD |
277 | dev->caps.bmme_flags = dev_cap->bmme_flags; |
278 | dev->caps.reserved_lkey = dev_cap->reserved_lkey; | |
225c7b1f | 279 | dev->caps.stat_rate_support = dev_cap->stat_rate_support; |
b832be1e | 280 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; |
b3416f44 | 281 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; |
225c7b1f | 282 | |
ca3e57a5 RD |
283 | /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ |
284 | if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) | |
58a60168 | 285 | dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; |
aadf4f3f RD |
286 | /* Don't do sense port on multifunction devices (for now at least) */ |
287 | if (mlx4_is_mfunc(dev)) | |
288 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; | |
58a60168 | 289 | |
93fc9e1b | 290 | dev->caps.log_num_macs = log_num_mac; |
cb29688a | 291 | dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; |
93fc9e1b YP |
292 | |
293 | for (i = 1; i <= dev->caps.num_ports; ++i) { | |
ab9c17a0 JM |
294 | dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; |
295 | if (dev->caps.supported_type[i]) { | |
296 | /* if only ETH is supported - assign ETH */ | |
297 | if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) | |
298 | dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; | |
105c320f | 299 | /* if only IB is supported, assign IB */ |
ab9c17a0 | 300 | else if (dev->caps.supported_type[i] == |
105c320f JM |
301 | MLX4_PORT_TYPE_IB) |
302 | dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 303 | else { |
105c320f JM |
304 | /* if IB and ETH are supported, we set the port |
305 | * type according to user selection of port type; | |
306 | * if user selected none, take the FW hint */ | |
307 | if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) | |
8d0fc7b6 YP |
308 | dev->caps.port_type[i] = dev->caps.suggested_type[i] ? |
309 | MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 310 | else |
105c320f | 311 | dev->caps.port_type[i] = port_type_array[i - 1]; |
ab9c17a0 JM |
312 | } |
313 | } | |
8d0fc7b6 YP |
314 | /* |
315 | * Link sensing is allowed on the port if 3 conditions are true: | |
316 | * 1. Both protocols are supported on the port. | |
317 | * 2. Different types are supported on the port | |
318 | * 3. FW declared that it supports link sensing | |
319 | */ | |
27bf91d6 | 320 | mlx4_priv(dev)->sense.sense_allowed[i] = |
58a60168 | 321 | ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && |
8d0fc7b6 | 322 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
58a60168 | 323 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); |
7ff93f8b | 324 | |
8d0fc7b6 YP |
325 | /* |
326 | * If "default_sense" bit is set, we move the port to "AUTO" mode | |
327 | * and perform sense_port FW command to try and set the correct | |
328 | * port type from beginning | |
329 | */ | |
46c46747 | 330 | if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { |
8d0fc7b6 YP |
331 | enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; |
332 | dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; | |
333 | mlx4_SENSE_PORT(dev, i, &sensed_port); | |
334 | if (sensed_port != MLX4_PORT_TYPE_NONE) | |
335 | dev->caps.port_type[i] = sensed_port; | |
336 | } else { | |
337 | dev->caps.possible_type[i] = dev->caps.port_type[i]; | |
338 | } | |
339 | ||
93fc9e1b YP |
340 | if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { |
341 | dev->caps.log_num_macs = dev_cap->log_max_macs[i]; | |
1a91de28 | 342 | mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", |
93fc9e1b YP |
343 | i, 1 << dev->caps.log_num_macs); |
344 | } | |
345 | if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { | |
346 | dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; | |
1a91de28 | 347 | mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", |
93fc9e1b YP |
348 | i, 1 << dev->caps.log_num_vlans); |
349 | } | |
350 | } | |
351 | ||
f2a3f6a3 OG |
352 | dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); |
353 | ||
93fc9e1b YP |
354 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; |
355 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = | |
356 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = | |
357 | (1 << dev->caps.log_num_macs) * | |
358 | (1 << dev->caps.log_num_vlans) * | |
93fc9e1b YP |
359 | dev->caps.num_ports; |
360 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; | |
361 | ||
362 | dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + | |
363 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + | |
364 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + | |
365 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; | |
366 | ||
e2c76824 | 367 | dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; |
08ff3235 | 368 | |
b3051320 | 369 | if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { |
08ff3235 OG |
370 | if (dev_cap->flags & |
371 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { | |
372 | mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); | |
373 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; | |
374 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; | |
375 | } | |
376 | } | |
377 | ||
f97b4b5d | 378 | if ((dev->caps.flags & |
08ff3235 OG |
379 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && |
380 | mlx4_is_master(dev)) | |
381 | dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; | |
382 | ||
225c7b1f RD |
383 | return 0; |
384 | } | |
b912b2f8 EP |
385 | |
386 | static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, | |
387 | enum pci_bus_speed *speed, | |
388 | enum pcie_link_width *width) | |
389 | { | |
390 | u32 lnkcap1, lnkcap2; | |
391 | int err1, err2; | |
392 | ||
393 | #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ | |
394 | ||
395 | *speed = PCI_SPEED_UNKNOWN; | |
396 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
397 | ||
398 | err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1); | |
399 | err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2); | |
400 | if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ | |
401 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
402 | *speed = PCIE_SPEED_8_0GT; | |
403 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
404 | *speed = PCIE_SPEED_5_0GT; | |
405 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
406 | *speed = PCIE_SPEED_2_5GT; | |
407 | } | |
408 | if (!err1) { | |
409 | *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; | |
410 | if (!lnkcap2) { /* pre-r3.0 */ | |
411 | if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) | |
412 | *speed = PCIE_SPEED_5_0GT; | |
413 | else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) | |
414 | *speed = PCIE_SPEED_2_5GT; | |
415 | } | |
416 | } | |
417 | ||
418 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { | |
419 | return err1 ? err1 : | |
420 | err2 ? err2 : -EINVAL; | |
421 | } | |
422 | return 0; | |
423 | } | |
424 | ||
425 | static void mlx4_check_pcie_caps(struct mlx4_dev *dev) | |
426 | { | |
427 | enum pcie_link_width width, width_cap; | |
428 | enum pci_bus_speed speed, speed_cap; | |
429 | int err; | |
430 | ||
431 | #define PCIE_SPEED_STR(speed) \ | |
432 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ | |
433 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ | |
434 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ | |
435 | "Unknown") | |
436 | ||
437 | err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); | |
438 | if (err) { | |
439 | mlx4_warn(dev, | |
440 | "Unable to determine PCIe device BW capabilities\n"); | |
441 | return; | |
442 | } | |
443 | ||
444 | err = pcie_get_minimum_link(dev->pdev, &speed, &width); | |
445 | if (err || speed == PCI_SPEED_UNKNOWN || | |
446 | width == PCIE_LNK_WIDTH_UNKNOWN) { | |
447 | mlx4_warn(dev, | |
448 | "Unable to determine PCI device chain minimum BW\n"); | |
449 | return; | |
450 | } | |
451 | ||
452 | if (width != width_cap || speed != speed_cap) | |
453 | mlx4_warn(dev, | |
454 | "PCIe BW is different than device's capability\n"); | |
455 | ||
456 | mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", | |
457 | PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); | |
458 | mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", | |
459 | width, width_cap); | |
460 | return; | |
461 | } | |
462 | ||
ab9c17a0 JM |
463 | /*The function checks if there are live vf, return the num of them*/ |
464 | static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) | |
465 | { | |
466 | struct mlx4_priv *priv = mlx4_priv(dev); | |
467 | struct mlx4_slave_state *s_state; | |
468 | int i; | |
469 | int ret = 0; | |
470 | ||
471 | for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { | |
472 | s_state = &priv->mfunc.master.slave_state[i]; | |
473 | if (s_state->active && s_state->last_cmd != | |
474 | MLX4_COMM_CMD_RESET) { | |
475 | mlx4_warn(dev, "%s: slave: %d is still active\n", | |
476 | __func__, i); | |
477 | ret++; | |
478 | } | |
479 | } | |
480 | return ret; | |
481 | } | |
482 | ||
396f2feb JM |
483 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) |
484 | { | |
485 | u32 qk = MLX4_RESERVED_QKEY_BASE; | |
47605df9 JM |
486 | |
487 | if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || | |
488 | qpn < dev->phys_caps.base_proxy_sqpn) | |
396f2feb JM |
489 | return -EINVAL; |
490 | ||
47605df9 | 491 | if (qpn >= dev->phys_caps.base_tunnel_sqpn) |
396f2feb | 492 | /* tunnel qp */ |
47605df9 | 493 | qk += qpn - dev->phys_caps.base_tunnel_sqpn; |
396f2feb | 494 | else |
47605df9 | 495 | qk += qpn - dev->phys_caps.base_proxy_sqpn; |
396f2feb JM |
496 | *qkey = qk; |
497 | return 0; | |
498 | } | |
499 | EXPORT_SYMBOL(mlx4_get_parav_qkey); | |
500 | ||
54679e14 JM |
501 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) |
502 | { | |
503 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
504 | ||
505 | if (!mlx4_is_master(dev)) | |
506 | return; | |
507 | ||
508 | priv->virt2phys_pkey[slave][port - 1][i] = val; | |
509 | } | |
510 | EXPORT_SYMBOL(mlx4_sync_pkey_table); | |
511 | ||
afa8fd1d JM |
512 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) |
513 | { | |
514 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
515 | ||
516 | if (!mlx4_is_master(dev)) | |
517 | return; | |
518 | ||
519 | priv->slave_node_guids[slave] = guid; | |
520 | } | |
521 | EXPORT_SYMBOL(mlx4_put_slave_node_guid); | |
522 | ||
523 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) | |
524 | { | |
525 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
526 | ||
527 | if (!mlx4_is_master(dev)) | |
528 | return 0; | |
529 | ||
530 | return priv->slave_node_guids[slave]; | |
531 | } | |
532 | EXPORT_SYMBOL(mlx4_get_slave_node_guid); | |
533 | ||
e10903b0 | 534 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) |
ab9c17a0 JM |
535 | { |
536 | struct mlx4_priv *priv = mlx4_priv(dev); | |
537 | struct mlx4_slave_state *s_slave; | |
538 | ||
539 | if (!mlx4_is_master(dev)) | |
540 | return 0; | |
541 | ||
542 | s_slave = &priv->mfunc.master.slave_state[slave]; | |
543 | return !!s_slave->active; | |
544 | } | |
545 | EXPORT_SYMBOL(mlx4_is_slave_active); | |
546 | ||
7b8157be JM |
547 | static void slave_adjust_steering_mode(struct mlx4_dev *dev, |
548 | struct mlx4_dev_cap *dev_cap, | |
549 | struct mlx4_init_hca_param *hca_param) | |
550 | { | |
551 | dev->caps.steering_mode = hca_param->steering_mode; | |
552 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
553 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | |
554 | dev->caps.fs_log_max_ucast_qp_range_size = | |
555 | dev_cap->fs_log_max_ucast_qp_range_size; | |
556 | } else | |
557 | dev->caps.num_qp_per_mgm = | |
558 | 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); | |
559 | ||
560 | mlx4_dbg(dev, "Steering mode is: %s\n", | |
561 | mlx4_steering_mode_str(dev->caps.steering_mode)); | |
562 | } | |
563 | ||
ab9c17a0 JM |
564 | static int mlx4_slave_cap(struct mlx4_dev *dev) |
565 | { | |
566 | int err; | |
567 | u32 page_size; | |
568 | struct mlx4_dev_cap dev_cap; | |
569 | struct mlx4_func_cap func_cap; | |
570 | struct mlx4_init_hca_param hca_param; | |
571 | int i; | |
572 | ||
573 | memset(&hca_param, 0, sizeof(hca_param)); | |
574 | err = mlx4_QUERY_HCA(dev, &hca_param); | |
575 | if (err) { | |
1a91de28 | 576 | mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); |
ab9c17a0 JM |
577 | return err; |
578 | } | |
579 | ||
483e0132 EP |
580 | /* fail if the hca has an unknown global capability |
581 | * at this time global_caps should be always zeroed | |
582 | */ | |
583 | if (hca_param.global_caps) { | |
ab9c17a0 JM |
584 | mlx4_err(dev, "Unknown hca global capabilities\n"); |
585 | return -ENOSYS; | |
586 | } | |
587 | ||
588 | mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; | |
589 | ||
ddd8a6c1 EE |
590 | dev->caps.hca_core_clock = hca_param.hca_core_clock; |
591 | ||
ab9c17a0 | 592 | memset(&dev_cap, 0, sizeof(dev_cap)); |
b91cb3eb | 593 | dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; |
ab9c17a0 JM |
594 | err = mlx4_dev_cap(dev, &dev_cap); |
595 | if (err) { | |
1a91de28 | 596 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
ab9c17a0 JM |
597 | return err; |
598 | } | |
599 | ||
b91cb3eb JM |
600 | err = mlx4_QUERY_FW(dev); |
601 | if (err) | |
1a91de28 | 602 | mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); |
b91cb3eb | 603 | |
ab9c17a0 JM |
604 | page_size = ~dev->caps.page_size_cap + 1; |
605 | mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); | |
606 | if (page_size > PAGE_SIZE) { | |
1a91de28 | 607 | mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", |
ab9c17a0 JM |
608 | page_size, PAGE_SIZE); |
609 | return -ENODEV; | |
610 | } | |
611 | ||
612 | /* slave gets uar page size from QUERY_HCA fw command */ | |
613 | dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); | |
614 | ||
615 | /* TODO: relax this assumption */ | |
616 | if (dev->caps.uar_page_size != PAGE_SIZE) { | |
617 | mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", | |
618 | dev->caps.uar_page_size, PAGE_SIZE); | |
619 | return -ENODEV; | |
620 | } | |
621 | ||
622 | memset(&func_cap, 0, sizeof(func_cap)); | |
47605df9 | 623 | err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); |
ab9c17a0 | 624 | if (err) { |
1a91de28 JP |
625 | mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", |
626 | err); | |
ab9c17a0 JM |
627 | return err; |
628 | } | |
629 | ||
630 | if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != | |
631 | PF_CONTEXT_BEHAVIOUR_MASK) { | |
632 | mlx4_err(dev, "Unknown pf context behaviour\n"); | |
633 | return -ENOSYS; | |
634 | } | |
635 | ||
ab9c17a0 | 636 | dev->caps.num_ports = func_cap.num_ports; |
5a0d0a61 JM |
637 | dev->quotas.qp = func_cap.qp_quota; |
638 | dev->quotas.srq = func_cap.srq_quota; | |
639 | dev->quotas.cq = func_cap.cq_quota; | |
640 | dev->quotas.mpt = func_cap.mpt_quota; | |
641 | dev->quotas.mtt = func_cap.mtt_quota; | |
642 | dev->caps.num_qps = 1 << hca_param.log_num_qps; | |
643 | dev->caps.num_srqs = 1 << hca_param.log_num_srqs; | |
644 | dev->caps.num_cqs = 1 << hca_param.log_num_cqs; | |
645 | dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; | |
646 | dev->caps.num_eqs = func_cap.max_eq; | |
647 | dev->caps.reserved_eqs = func_cap.reserved_eq; | |
ab9c17a0 JM |
648 | dev->caps.num_pds = MLX4_NUM_PDS; |
649 | dev->caps.num_mgms = 0; | |
650 | dev->caps.num_amgms = 0; | |
651 | ||
ab9c17a0 | 652 | if (dev->caps.num_ports > MLX4_MAX_PORTS) { |
1a91de28 JP |
653 | mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", |
654 | dev->caps.num_ports, MLX4_MAX_PORTS); | |
ab9c17a0 JM |
655 | return -ENODEV; |
656 | } | |
657 | ||
99ec41d0 | 658 | dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL); |
47605df9 JM |
659 | dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); |
660 | dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
661 | dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
662 | dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
663 | ||
664 | if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || | |
99ec41d0 JM |
665 | !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy || |
666 | !dev->caps.qp0_qkey) { | |
47605df9 JM |
667 | err = -ENOMEM; |
668 | goto err_mem; | |
669 | } | |
670 | ||
6634961c | 671 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
47605df9 JM |
672 | err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap); |
673 | if (err) { | |
1a91de28 JP |
674 | mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", |
675 | i, err); | |
47605df9 JM |
676 | goto err_mem; |
677 | } | |
99ec41d0 | 678 | dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey; |
47605df9 JM |
679 | dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; |
680 | dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; | |
681 | dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; | |
682 | dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; | |
6230bb23 | 683 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
8e1a28e8 | 684 | dev->caps.phys_port_id[i] = func_cap.phys_port_id; |
6634961c JM |
685 | if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, |
686 | &dev->caps.gid_table_len[i], | |
687 | &dev->caps.pkey_table_len[i])) | |
47605df9 | 688 | goto err_mem; |
6634961c | 689 | } |
6230bb23 | 690 | |
ab9c17a0 JM |
691 | if (dev->caps.uar_page_size * (dev->caps.num_uars - |
692 | dev->caps.reserved_uars) > | |
693 | pci_resource_len(dev->pdev, 2)) { | |
1a91de28 | 694 | mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", |
ab9c17a0 JM |
695 | dev->caps.uar_page_size * dev->caps.num_uars, |
696 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
47605df9 | 697 | goto err_mem; |
ab9c17a0 JM |
698 | } |
699 | ||
08ff3235 OG |
700 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { |
701 | dev->caps.eqe_size = 64; | |
702 | dev->caps.eqe_factor = 1; | |
703 | } else { | |
704 | dev->caps.eqe_size = 32; | |
705 | dev->caps.eqe_factor = 0; | |
706 | } | |
707 | ||
708 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { | |
709 | dev->caps.cqe_size = 64; | |
710 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; | |
711 | } else { | |
712 | dev->caps.cqe_size = 32; | |
713 | } | |
714 | ||
f9bd2d7f | 715 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; |
1a91de28 | 716 | mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); |
f9bd2d7f | 717 | |
7b8157be JM |
718 | slave_adjust_steering_mode(dev, &dev_cap, &hca_param); |
719 | ||
ab9c17a0 | 720 | return 0; |
47605df9 JM |
721 | |
722 | err_mem: | |
99ec41d0 | 723 | kfree(dev->caps.qp0_qkey); |
47605df9 JM |
724 | kfree(dev->caps.qp0_tunnel); |
725 | kfree(dev->caps.qp0_proxy); | |
726 | kfree(dev->caps.qp1_tunnel); | |
727 | kfree(dev->caps.qp1_proxy); | |
99ec41d0 JM |
728 | dev->caps.qp0_qkey = NULL; |
729 | dev->caps.qp0_tunnel = NULL; | |
730 | dev->caps.qp0_proxy = NULL; | |
731 | dev->caps.qp1_tunnel = NULL; | |
732 | dev->caps.qp1_proxy = NULL; | |
47605df9 JM |
733 | |
734 | return err; | |
ab9c17a0 | 735 | } |
225c7b1f | 736 | |
b046ffe5 EP |
737 | static void mlx4_request_modules(struct mlx4_dev *dev) |
738 | { | |
739 | int port; | |
740 | int has_ib_port = false; | |
741 | int has_eth_port = false; | |
742 | #define EN_DRV_NAME "mlx4_en" | |
743 | #define IB_DRV_NAME "mlx4_ib" | |
744 | ||
745 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
746 | if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) | |
747 | has_ib_port = true; | |
748 | else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) | |
749 | has_eth_port = true; | |
750 | } | |
751 | ||
b046ffe5 EP |
752 | if (has_eth_port) |
753 | request_module_nowait(EN_DRV_NAME); | |
f24f790f OG |
754 | if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) |
755 | request_module_nowait(IB_DRV_NAME); | |
b046ffe5 EP |
756 | } |
757 | ||
7ff93f8b YP |
758 | /* |
759 | * Change the port configuration of the device. | |
760 | * Every user of this function must hold the port mutex. | |
761 | */ | |
27bf91d6 YP |
762 | int mlx4_change_port_types(struct mlx4_dev *dev, |
763 | enum mlx4_port_type *port_types) | |
7ff93f8b YP |
764 | { |
765 | int err = 0; | |
766 | int change = 0; | |
767 | int port; | |
768 | ||
769 | for (port = 0; port < dev->caps.num_ports; port++) { | |
27bf91d6 YP |
770 | /* Change the port type only if the new type is different |
771 | * from the current, and not set to Auto */ | |
3d8f9308 | 772 | if (port_types[port] != dev->caps.port_type[port + 1]) |
7ff93f8b | 773 | change = 1; |
7ff93f8b YP |
774 | } |
775 | if (change) { | |
776 | mlx4_unregister_device(dev); | |
777 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
778 | mlx4_CLOSE_PORT(dev, port); | |
1e0f03d5 | 779 | dev->caps.port_type[port] = port_types[port - 1]; |
6634961c | 780 | err = mlx4_SET_PORT(dev, port, -1); |
7ff93f8b | 781 | if (err) { |
1a91de28 JP |
782 | mlx4_err(dev, "Failed to set port %d, aborting\n", |
783 | port); | |
7ff93f8b YP |
784 | goto out; |
785 | } | |
786 | } | |
787 | mlx4_set_port_mask(dev); | |
788 | err = mlx4_register_device(dev); | |
b046ffe5 EP |
789 | if (err) { |
790 | mlx4_err(dev, "Failed to register device\n"); | |
791 | goto out; | |
792 | } | |
793 | mlx4_request_modules(dev); | |
7ff93f8b YP |
794 | } |
795 | ||
796 | out: | |
797 | return err; | |
798 | } | |
799 | ||
800 | static ssize_t show_port_type(struct device *dev, | |
801 | struct device_attribute *attr, | |
802 | char *buf) | |
803 | { | |
804 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
805 | port_attr); | |
806 | struct mlx4_dev *mdev = info->dev; | |
27bf91d6 YP |
807 | char type[8]; |
808 | ||
809 | sprintf(type, "%s", | |
810 | (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? | |
811 | "ib" : "eth"); | |
812 | if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) | |
813 | sprintf(buf, "auto (%s)\n", type); | |
814 | else | |
815 | sprintf(buf, "%s\n", type); | |
7ff93f8b | 816 | |
27bf91d6 | 817 | return strlen(buf); |
7ff93f8b YP |
818 | } |
819 | ||
820 | static ssize_t set_port_type(struct device *dev, | |
821 | struct device_attribute *attr, | |
822 | const char *buf, size_t count) | |
823 | { | |
824 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
825 | port_attr); | |
826 | struct mlx4_dev *mdev = info->dev; | |
827 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
828 | enum mlx4_port_type types[MLX4_MAX_PORTS]; | |
27bf91d6 | 829 | enum mlx4_port_type new_types[MLX4_MAX_PORTS]; |
7ff93f8b YP |
830 | int i; |
831 | int err = 0; | |
832 | ||
833 | if (!strcmp(buf, "ib\n")) | |
834 | info->tmp_type = MLX4_PORT_TYPE_IB; | |
835 | else if (!strcmp(buf, "eth\n")) | |
836 | info->tmp_type = MLX4_PORT_TYPE_ETH; | |
27bf91d6 YP |
837 | else if (!strcmp(buf, "auto\n")) |
838 | info->tmp_type = MLX4_PORT_TYPE_AUTO; | |
7ff93f8b YP |
839 | else { |
840 | mlx4_err(mdev, "%s is not supported port type\n", buf); | |
841 | return -EINVAL; | |
842 | } | |
843 | ||
27bf91d6 | 844 | mlx4_stop_sense(mdev); |
7ff93f8b | 845 | mutex_lock(&priv->port_mutex); |
27bf91d6 YP |
846 | /* Possible type is always the one that was delivered */ |
847 | mdev->caps.possible_type[info->port] = info->tmp_type; | |
848 | ||
849 | for (i = 0; i < mdev->caps.num_ports; i++) { | |
7ff93f8b | 850 | types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : |
27bf91d6 YP |
851 | mdev->caps.possible_type[i+1]; |
852 | if (types[i] == MLX4_PORT_TYPE_AUTO) | |
853 | types[i] = mdev->caps.port_type[i+1]; | |
854 | } | |
7ff93f8b | 855 | |
58a60168 YP |
856 | if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
857 | !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { | |
27bf91d6 YP |
858 | for (i = 1; i <= mdev->caps.num_ports; i++) { |
859 | if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { | |
860 | mdev->caps.possible_type[i] = mdev->caps.port_type[i]; | |
861 | err = -EINVAL; | |
862 | } | |
863 | } | |
864 | } | |
865 | if (err) { | |
1a91de28 | 866 | mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); |
27bf91d6 YP |
867 | goto out; |
868 | } | |
869 | ||
870 | mlx4_do_sense_ports(mdev, new_types, types); | |
871 | ||
872 | err = mlx4_check_port_params(mdev, new_types); | |
7ff93f8b YP |
873 | if (err) |
874 | goto out; | |
875 | ||
27bf91d6 YP |
876 | /* We are about to apply the changes after the configuration |
877 | * was verified, no need to remember the temporary types | |
878 | * any more */ | |
879 | for (i = 0; i < mdev->caps.num_ports; i++) | |
880 | priv->port[i + 1].tmp_type = 0; | |
7ff93f8b | 881 | |
27bf91d6 | 882 | err = mlx4_change_port_types(mdev, new_types); |
7ff93f8b YP |
883 | |
884 | out: | |
27bf91d6 | 885 | mlx4_start_sense(mdev); |
7ff93f8b YP |
886 | mutex_unlock(&priv->port_mutex); |
887 | return err ? err : count; | |
888 | } | |
889 | ||
096335b3 OG |
890 | enum ibta_mtu { |
891 | IB_MTU_256 = 1, | |
892 | IB_MTU_512 = 2, | |
893 | IB_MTU_1024 = 3, | |
894 | IB_MTU_2048 = 4, | |
895 | IB_MTU_4096 = 5 | |
896 | }; | |
897 | ||
898 | static inline int int_to_ibta_mtu(int mtu) | |
899 | { | |
900 | switch (mtu) { | |
901 | case 256: return IB_MTU_256; | |
902 | case 512: return IB_MTU_512; | |
903 | case 1024: return IB_MTU_1024; | |
904 | case 2048: return IB_MTU_2048; | |
905 | case 4096: return IB_MTU_4096; | |
906 | default: return -1; | |
907 | } | |
908 | } | |
909 | ||
910 | static inline int ibta_mtu_to_int(enum ibta_mtu mtu) | |
911 | { | |
912 | switch (mtu) { | |
913 | case IB_MTU_256: return 256; | |
914 | case IB_MTU_512: return 512; | |
915 | case IB_MTU_1024: return 1024; | |
916 | case IB_MTU_2048: return 2048; | |
917 | case IB_MTU_4096: return 4096; | |
918 | default: return -1; | |
919 | } | |
920 | } | |
921 | ||
922 | static ssize_t show_port_ib_mtu(struct device *dev, | |
923 | struct device_attribute *attr, | |
924 | char *buf) | |
925 | { | |
926 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
927 | port_mtu_attr); | |
928 | struct mlx4_dev *mdev = info->dev; | |
929 | ||
930 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) | |
931 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
932 | ||
933 | sprintf(buf, "%d\n", | |
934 | ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); | |
935 | return strlen(buf); | |
936 | } | |
937 | ||
938 | static ssize_t set_port_ib_mtu(struct device *dev, | |
939 | struct device_attribute *attr, | |
940 | const char *buf, size_t count) | |
941 | { | |
942 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
943 | port_mtu_attr); | |
944 | struct mlx4_dev *mdev = info->dev; | |
945 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
946 | int err, port, mtu, ibta_mtu = -1; | |
947 | ||
948 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { | |
949 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
950 | return -EINVAL; | |
951 | } | |
952 | ||
618fad95 DB |
953 | err = kstrtoint(buf, 0, &mtu); |
954 | if (!err) | |
096335b3 OG |
955 | ibta_mtu = int_to_ibta_mtu(mtu); |
956 | ||
618fad95 | 957 | if (err || ibta_mtu < 0) { |
096335b3 OG |
958 | mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); |
959 | return -EINVAL; | |
960 | } | |
961 | ||
962 | mdev->caps.port_ib_mtu[info->port] = ibta_mtu; | |
963 | ||
964 | mlx4_stop_sense(mdev); | |
965 | mutex_lock(&priv->port_mutex); | |
966 | mlx4_unregister_device(mdev); | |
967 | for (port = 1; port <= mdev->caps.num_ports; port++) { | |
968 | mlx4_CLOSE_PORT(mdev, port); | |
6634961c | 969 | err = mlx4_SET_PORT(mdev, port, -1); |
096335b3 | 970 | if (err) { |
1a91de28 JP |
971 | mlx4_err(mdev, "Failed to set port %d, aborting\n", |
972 | port); | |
096335b3 OG |
973 | goto err_set_port; |
974 | } | |
975 | } | |
976 | err = mlx4_register_device(mdev); | |
977 | err_set_port: | |
978 | mutex_unlock(&priv->port_mutex); | |
979 | mlx4_start_sense(mdev); | |
980 | return err ? err : count; | |
981 | } | |
982 | ||
e8f9b2ed | 983 | static int mlx4_load_fw(struct mlx4_dev *dev) |
225c7b1f RD |
984 | { |
985 | struct mlx4_priv *priv = mlx4_priv(dev); | |
986 | int err; | |
987 | ||
988 | priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, | |
5b0bf5e2 | 989 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f | 990 | if (!priv->fw.fw_icm) { |
1a91de28 | 991 | mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); |
225c7b1f RD |
992 | return -ENOMEM; |
993 | } | |
994 | ||
995 | err = mlx4_MAP_FA(dev, priv->fw.fw_icm); | |
996 | if (err) { | |
1a91de28 | 997 | mlx4_err(dev, "MAP_FA command failed, aborting\n"); |
225c7b1f RD |
998 | goto err_free; |
999 | } | |
1000 | ||
1001 | err = mlx4_RUN_FW(dev); | |
1002 | if (err) { | |
1a91de28 | 1003 | mlx4_err(dev, "RUN_FW command failed, aborting\n"); |
225c7b1f RD |
1004 | goto err_unmap_fa; |
1005 | } | |
1006 | ||
1007 | return 0; | |
1008 | ||
1009 | err_unmap_fa: | |
1010 | mlx4_UNMAP_FA(dev); | |
1011 | ||
1012 | err_free: | |
5b0bf5e2 | 1013 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); |
225c7b1f RD |
1014 | return err; |
1015 | } | |
1016 | ||
e8f9b2ed RD |
1017 | static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, |
1018 | int cmpt_entry_sz) | |
225c7b1f RD |
1019 | { |
1020 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1021 | int err; | |
ab9c17a0 | 1022 | int num_eqs; |
225c7b1f RD |
1023 | |
1024 | err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, | |
1025 | cmpt_base + | |
1026 | ((u64) (MLX4_CMPT_TYPE_QP * | |
1027 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1028 | cmpt_entry_sz, dev->caps.num_qps, | |
93fc9e1b YP |
1029 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1030 | 0, 0); | |
225c7b1f RD |
1031 | if (err) |
1032 | goto err; | |
1033 | ||
1034 | err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, | |
1035 | cmpt_base + | |
1036 | ((u64) (MLX4_CMPT_TYPE_SRQ * | |
1037 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1038 | cmpt_entry_sz, dev->caps.num_srqs, | |
5b0bf5e2 | 1039 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
1040 | if (err) |
1041 | goto err_qp; | |
1042 | ||
1043 | err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, | |
1044 | cmpt_base + | |
1045 | ((u64) (MLX4_CMPT_TYPE_CQ * | |
1046 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1047 | cmpt_entry_sz, dev->caps.num_cqs, | |
5b0bf5e2 | 1048 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
1049 | if (err) |
1050 | goto err_srq; | |
1051 | ||
3fc929e2 MA |
1052 | num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : |
1053 | dev->caps.num_eqs; | |
225c7b1f RD |
1054 | err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, |
1055 | cmpt_base + | |
1056 | ((u64) (MLX4_CMPT_TYPE_EQ * | |
1057 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
ab9c17a0 | 1058 | cmpt_entry_sz, num_eqs, num_eqs, 0, 0); |
225c7b1f RD |
1059 | if (err) |
1060 | goto err_cq; | |
1061 | ||
1062 | return 0; | |
1063 | ||
1064 | err_cq: | |
1065 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1066 | ||
1067 | err_srq: | |
1068 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1069 | ||
1070 | err_qp: | |
1071 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
1072 | ||
1073 | err: | |
1074 | return err; | |
1075 | } | |
1076 | ||
3d73c288 RD |
1077 | static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, |
1078 | struct mlx4_init_hca_param *init_hca, u64 icm_size) | |
225c7b1f RD |
1079 | { |
1080 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1081 | u64 aux_pages; | |
ab9c17a0 | 1082 | int num_eqs; |
225c7b1f RD |
1083 | int err; |
1084 | ||
1085 | err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); | |
1086 | if (err) { | |
1a91de28 | 1087 | mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); |
225c7b1f RD |
1088 | return err; |
1089 | } | |
1090 | ||
1a91de28 | 1091 | mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", |
225c7b1f RD |
1092 | (unsigned long long) icm_size >> 10, |
1093 | (unsigned long long) aux_pages << 2); | |
1094 | ||
1095 | priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, | |
5b0bf5e2 | 1096 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f | 1097 | if (!priv->fw.aux_icm) { |
1a91de28 | 1098 | mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); |
225c7b1f RD |
1099 | return -ENOMEM; |
1100 | } | |
1101 | ||
1102 | err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); | |
1103 | if (err) { | |
1a91de28 | 1104 | mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); |
225c7b1f RD |
1105 | goto err_free_aux; |
1106 | } | |
1107 | ||
1108 | err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); | |
1109 | if (err) { | |
1a91de28 | 1110 | mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); |
225c7b1f RD |
1111 | goto err_unmap_aux; |
1112 | } | |
1113 | ||
ab9c17a0 | 1114 | |
3fc929e2 MA |
1115 | num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : |
1116 | dev->caps.num_eqs; | |
fa0681d2 RD |
1117 | err = mlx4_init_icm_table(dev, &priv->eq_table.table, |
1118 | init_hca->eqc_base, dev_cap->eqc_entry_sz, | |
ab9c17a0 | 1119 | num_eqs, num_eqs, 0, 0); |
225c7b1f | 1120 | if (err) { |
1a91de28 | 1121 | mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); |
225c7b1f RD |
1122 | goto err_unmap_cmpt; |
1123 | } | |
1124 | ||
d7bb58fb JM |
1125 | /* |
1126 | * Reserved MTT entries must be aligned up to a cacheline | |
1127 | * boundary, since the FW will write to them, while the driver | |
1128 | * writes to all other MTT entries. (The variable | |
1129 | * dev->caps.mtt_entry_sz below is really the MTT segment | |
1130 | * size, not the raw entry size) | |
1131 | */ | |
1132 | dev->caps.reserved_mtts = | |
1133 | ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, | |
1134 | dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; | |
1135 | ||
225c7b1f RD |
1136 | err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, |
1137 | init_hca->mtt_base, | |
1138 | dev->caps.mtt_entry_sz, | |
2b8fb286 | 1139 | dev->caps.num_mtts, |
5b0bf5e2 | 1140 | dev->caps.reserved_mtts, 1, 0); |
225c7b1f | 1141 | if (err) { |
1a91de28 | 1142 | mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); |
225c7b1f RD |
1143 | goto err_unmap_eq; |
1144 | } | |
1145 | ||
1146 | err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, | |
1147 | init_hca->dmpt_base, | |
1148 | dev_cap->dmpt_entry_sz, | |
1149 | dev->caps.num_mpts, | |
5b0bf5e2 | 1150 | dev->caps.reserved_mrws, 1, 1); |
225c7b1f | 1151 | if (err) { |
1a91de28 | 1152 | mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); |
225c7b1f RD |
1153 | goto err_unmap_mtt; |
1154 | } | |
1155 | ||
1156 | err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, | |
1157 | init_hca->qpc_base, | |
1158 | dev_cap->qpc_entry_sz, | |
1159 | dev->caps.num_qps, | |
93fc9e1b YP |
1160 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1161 | 0, 0); | |
225c7b1f | 1162 | if (err) { |
1a91de28 | 1163 | mlx4_err(dev, "Failed to map QP context memory, aborting\n"); |
225c7b1f RD |
1164 | goto err_unmap_dmpt; |
1165 | } | |
1166 | ||
1167 | err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, | |
1168 | init_hca->auxc_base, | |
1169 | dev_cap->aux_entry_sz, | |
1170 | dev->caps.num_qps, | |
93fc9e1b YP |
1171 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1172 | 0, 0); | |
225c7b1f | 1173 | if (err) { |
1a91de28 | 1174 | mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); |
225c7b1f RD |
1175 | goto err_unmap_qp; |
1176 | } | |
1177 | ||
1178 | err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, | |
1179 | init_hca->altc_base, | |
1180 | dev_cap->altc_entry_sz, | |
1181 | dev->caps.num_qps, | |
93fc9e1b YP |
1182 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1183 | 0, 0); | |
225c7b1f | 1184 | if (err) { |
1a91de28 | 1185 | mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); |
225c7b1f RD |
1186 | goto err_unmap_auxc; |
1187 | } | |
1188 | ||
1189 | err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, | |
1190 | init_hca->rdmarc_base, | |
1191 | dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, | |
1192 | dev->caps.num_qps, | |
93fc9e1b YP |
1193 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1194 | 0, 0); | |
225c7b1f RD |
1195 | if (err) { |
1196 | mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); | |
1197 | goto err_unmap_altc; | |
1198 | } | |
1199 | ||
1200 | err = mlx4_init_icm_table(dev, &priv->cq_table.table, | |
1201 | init_hca->cqc_base, | |
1202 | dev_cap->cqc_entry_sz, | |
1203 | dev->caps.num_cqs, | |
5b0bf5e2 | 1204 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f | 1205 | if (err) { |
1a91de28 | 1206 | mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); |
225c7b1f RD |
1207 | goto err_unmap_rdmarc; |
1208 | } | |
1209 | ||
1210 | err = mlx4_init_icm_table(dev, &priv->srq_table.table, | |
1211 | init_hca->srqc_base, | |
1212 | dev_cap->srq_entry_sz, | |
1213 | dev->caps.num_srqs, | |
5b0bf5e2 | 1214 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f | 1215 | if (err) { |
1a91de28 | 1216 | mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); |
225c7b1f RD |
1217 | goto err_unmap_cq; |
1218 | } | |
1219 | ||
1220 | /* | |
0ff1fb65 HHZ |
1221 | * For flow steering device managed mode it is required to use |
1222 | * mlx4_init_icm_table. For B0 steering mode it's not strictly | |
1223 | * required, but for simplicity just map the whole multicast | |
1224 | * group table now. The table isn't very big and it's a lot | |
1225 | * easier than trying to track ref counts. | |
225c7b1f RD |
1226 | */ |
1227 | err = mlx4_init_icm_table(dev, &priv->mcg_table.table, | |
0ec2c0f8 EE |
1228 | init_hca->mc_base, |
1229 | mlx4_get_mgm_entry_size(dev), | |
225c7b1f RD |
1230 | dev->caps.num_mgms + dev->caps.num_amgms, |
1231 | dev->caps.num_mgms + dev->caps.num_amgms, | |
5b0bf5e2 | 1232 | 0, 0); |
225c7b1f | 1233 | if (err) { |
1a91de28 | 1234 | mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); |
225c7b1f RD |
1235 | goto err_unmap_srq; |
1236 | } | |
1237 | ||
1238 | return 0; | |
1239 | ||
1240 | err_unmap_srq: | |
1241 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1242 | ||
1243 | err_unmap_cq: | |
1244 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1245 | ||
1246 | err_unmap_rdmarc: | |
1247 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1248 | ||
1249 | err_unmap_altc: | |
1250 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1251 | ||
1252 | err_unmap_auxc: | |
1253 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1254 | ||
1255 | err_unmap_qp: | |
1256 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1257 | ||
1258 | err_unmap_dmpt: | |
1259 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1260 | ||
1261 | err_unmap_mtt: | |
1262 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
1263 | ||
1264 | err_unmap_eq: | |
fa0681d2 | 1265 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1266 | |
1267 | err_unmap_cmpt: | |
1268 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); | |
1269 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1270 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1271 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
1272 | ||
1273 | err_unmap_aux: | |
1274 | mlx4_UNMAP_ICM_AUX(dev); | |
1275 | ||
1276 | err_free_aux: | |
5b0bf5e2 | 1277 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1278 | |
1279 | return err; | |
1280 | } | |
1281 | ||
1282 | static void mlx4_free_icms(struct mlx4_dev *dev) | |
1283 | { | |
1284 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1285 | ||
1286 | mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); | |
1287 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1288 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1289 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1290 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1291 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1292 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1293 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1294 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
fa0681d2 | 1295 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1296 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); |
1297 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1298 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1299 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
225c7b1f RD |
1300 | |
1301 | mlx4_UNMAP_ICM_AUX(dev); | |
5b0bf5e2 | 1302 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1303 | } |
1304 | ||
ab9c17a0 JM |
1305 | static void mlx4_slave_exit(struct mlx4_dev *dev) |
1306 | { | |
1307 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1308 | ||
f3d4c89e | 1309 | mutex_lock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 | 1310 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) |
1a91de28 | 1311 | mlx4_warn(dev, "Failed to close slave function\n"); |
f3d4c89e | 1312 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1313 | } |
1314 | ||
c1b43dca EC |
1315 | static int map_bf_area(struct mlx4_dev *dev) |
1316 | { | |
1317 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1318 | resource_size_t bf_start; | |
1319 | resource_size_t bf_len; | |
1320 | int err = 0; | |
1321 | ||
3d747473 JM |
1322 | if (!dev->caps.bf_reg_size) |
1323 | return -ENXIO; | |
1324 | ||
ab9c17a0 JM |
1325 | bf_start = pci_resource_start(dev->pdev, 2) + |
1326 | (dev->caps.num_uars << PAGE_SHIFT); | |
1327 | bf_len = pci_resource_len(dev->pdev, 2) - | |
1328 | (dev->caps.num_uars << PAGE_SHIFT); | |
c1b43dca EC |
1329 | priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); |
1330 | if (!priv->bf_mapping) | |
1331 | err = -ENOMEM; | |
1332 | ||
1333 | return err; | |
1334 | } | |
1335 | ||
1336 | static void unmap_bf_area(struct mlx4_dev *dev) | |
1337 | { | |
1338 | if (mlx4_priv(dev)->bf_mapping) | |
1339 | io_mapping_free(mlx4_priv(dev)->bf_mapping); | |
1340 | } | |
1341 | ||
ec693d47 AV |
1342 | cycle_t mlx4_read_clock(struct mlx4_dev *dev) |
1343 | { | |
1344 | u32 clockhi, clocklo, clockhi1; | |
1345 | cycle_t cycles; | |
1346 | int i; | |
1347 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1348 | ||
1349 | for (i = 0; i < 10; i++) { | |
1350 | clockhi = swab32(readl(priv->clock_mapping)); | |
1351 | clocklo = swab32(readl(priv->clock_mapping + 4)); | |
1352 | clockhi1 = swab32(readl(priv->clock_mapping)); | |
1353 | if (clockhi == clockhi1) | |
1354 | break; | |
1355 | } | |
1356 | ||
1357 | cycles = (u64) clockhi << 32 | (u64) clocklo; | |
1358 | ||
1359 | return cycles; | |
1360 | } | |
1361 | EXPORT_SYMBOL_GPL(mlx4_read_clock); | |
1362 | ||
1363 | ||
ddd8a6c1 EE |
1364 | static int map_internal_clock(struct mlx4_dev *dev) |
1365 | { | |
1366 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1367 | ||
1368 | priv->clock_mapping = | |
1369 | ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) + | |
1370 | priv->fw.clock_offset, MLX4_CLOCK_SIZE); | |
1371 | ||
1372 | if (!priv->clock_mapping) | |
1373 | return -ENOMEM; | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
1378 | static void unmap_internal_clock(struct mlx4_dev *dev) | |
1379 | { | |
1380 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1381 | ||
1382 | if (priv->clock_mapping) | |
1383 | iounmap(priv->clock_mapping); | |
1384 | } | |
1385 | ||
225c7b1f RD |
1386 | static void mlx4_close_hca(struct mlx4_dev *dev) |
1387 | { | |
ddd8a6c1 | 1388 | unmap_internal_clock(dev); |
c1b43dca | 1389 | unmap_bf_area(dev); |
ab9c17a0 JM |
1390 | if (mlx4_is_slave(dev)) |
1391 | mlx4_slave_exit(dev); | |
1392 | else { | |
1393 | mlx4_CLOSE_HCA(dev, 0); | |
1394 | mlx4_free_icms(dev); | |
1395 | mlx4_UNMAP_FA(dev); | |
1396 | mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); | |
1397 | } | |
1398 | } | |
1399 | ||
1400 | static int mlx4_init_slave(struct mlx4_dev *dev) | |
1401 | { | |
1402 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1403 | u64 dma = (u64) priv->mfunc.vhcr_dma; | |
ab9c17a0 JM |
1404 | int ret_from_reset = 0; |
1405 | u32 slave_read; | |
1406 | u32 cmd_channel_ver; | |
1407 | ||
97989356 | 1408 | if (atomic_read(&pf_loading)) { |
1a91de28 | 1409 | mlx4_warn(dev, "PF is not ready - Deferring probe\n"); |
97989356 AV |
1410 | return -EPROBE_DEFER; |
1411 | } | |
1412 | ||
f3d4c89e | 1413 | mutex_lock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1414 | priv->cmd.max_cmds = 1; |
1415 | mlx4_warn(dev, "Sending reset\n"); | |
1416 | ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, | |
1417 | MLX4_COMM_TIME); | |
1418 | /* if we are in the middle of flr the slave will try | |
1419 | * NUM_OF_RESET_RETRIES times before leaving.*/ | |
1420 | if (ret_from_reset) { | |
1421 | if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { | |
1a91de28 | 1422 | mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); |
5efe5355 JM |
1423 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
1424 | return -EPROBE_DEFER; | |
ab9c17a0 JM |
1425 | } else |
1426 | goto err; | |
1427 | } | |
1428 | ||
1429 | /* check the driver version - the slave I/F revision | |
1430 | * must match the master's */ | |
1431 | slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); | |
1432 | cmd_channel_ver = mlx4_comm_get_version(); | |
1433 | ||
1434 | if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != | |
1435 | MLX4_COMM_GET_IF_REV(slave_read)) { | |
1a91de28 | 1436 | mlx4_err(dev, "slave driver version is not supported by the master\n"); |
ab9c17a0 JM |
1437 | goto err; |
1438 | } | |
1439 | ||
1440 | mlx4_warn(dev, "Sending vhcr0\n"); | |
1441 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, | |
1442 | MLX4_COMM_TIME)) | |
1443 | goto err; | |
1444 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, | |
1445 | MLX4_COMM_TIME)) | |
1446 | goto err; | |
1447 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, | |
1448 | MLX4_COMM_TIME)) | |
1449 | goto err; | |
1450 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) | |
1451 | goto err; | |
f3d4c89e RD |
1452 | |
1453 | mutex_unlock(&priv->cmd.slave_cmd_mutex); | |
ab9c17a0 JM |
1454 | return 0; |
1455 | ||
1456 | err: | |
1457 | mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); | |
f3d4c89e | 1458 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 | 1459 | return -EIO; |
225c7b1f RD |
1460 | } |
1461 | ||
6634961c JM |
1462 | static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) |
1463 | { | |
1464 | int i; | |
1465 | ||
1466 | for (i = 1; i <= dev->caps.num_ports; i++) { | |
b6ffaeff JM |
1467 | if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) |
1468 | dev->caps.gid_table_len[i] = | |
449fc488 | 1469 | mlx4_get_slave_num_gids(dev, 0, i); |
b6ffaeff JM |
1470 | else |
1471 | dev->caps.gid_table_len[i] = 1; | |
6634961c JM |
1472 | dev->caps.pkey_table_len[i] = |
1473 | dev->phys_caps.pkey_phys_table_len[i] - 1; | |
1474 | } | |
1475 | } | |
1476 | ||
3c439b55 JM |
1477 | static int choose_log_fs_mgm_entry_size(int qp_per_entry) |
1478 | { | |
1479 | int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; | |
1480 | ||
1481 | for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; | |
1482 | i++) { | |
1483 | if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) | |
1484 | break; | |
1485 | } | |
1486 | ||
1487 | return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; | |
1488 | } | |
1489 | ||
7b8157be JM |
1490 | static void choose_steering_mode(struct mlx4_dev *dev, |
1491 | struct mlx4_dev_cap *dev_cap) | |
1492 | { | |
3c439b55 JM |
1493 | if (mlx4_log_num_mgm_entry_size == -1 && |
1494 | dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && | |
7b8157be | 1495 | (!mlx4_is_mfunc(dev) || |
449fc488 | 1496 | (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) && |
3c439b55 JM |
1497 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= |
1498 | MLX4_MIN_MGM_LOG_ENTRY_SIZE) { | |
1499 | dev->oper_log_mgm_entry_size = | |
1500 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); | |
7b8157be JM |
1501 | dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
1502 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | |
1503 | dev->caps.fs_log_max_ucast_qp_range_size = | |
1504 | dev_cap->fs_log_max_ucast_qp_range_size; | |
1505 | } else { | |
1506 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && | |
1507 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | |
1508 | dev->caps.steering_mode = MLX4_STEERING_MODE_B0; | |
1509 | else { | |
1510 | dev->caps.steering_mode = MLX4_STEERING_MODE_A0; | |
1511 | ||
1512 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || | |
1513 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | |
1a91de28 | 1514 | mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); |
7b8157be | 1515 | } |
3c439b55 JM |
1516 | dev->oper_log_mgm_entry_size = |
1517 | mlx4_log_num_mgm_entry_size > 0 ? | |
1518 | mlx4_log_num_mgm_entry_size : | |
1519 | MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; | |
7b8157be JM |
1520 | dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); |
1521 | } | |
1a91de28 | 1522 | mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", |
3c439b55 JM |
1523 | mlx4_steering_mode_str(dev->caps.steering_mode), |
1524 | dev->oper_log_mgm_entry_size, | |
1525 | mlx4_log_num_mgm_entry_size); | |
7b8157be JM |
1526 | } |
1527 | ||
7ffdf726 OG |
1528 | static void choose_tunnel_offload_mode(struct mlx4_dev *dev, |
1529 | struct mlx4_dev_cap *dev_cap) | |
1530 | { | |
1531 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && | |
1532 | dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) | |
1533 | dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; | |
1534 | else | |
1535 | dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; | |
1536 | ||
1537 | mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode | |
1538 | == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); | |
1539 | } | |
1540 | ||
3d73c288 | 1541 | static int mlx4_init_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1542 | { |
1543 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1544 | struct mlx4_adapter adapter; | |
1545 | struct mlx4_dev_cap dev_cap; | |
2d928651 | 1546 | struct mlx4_mod_stat_cfg mlx4_cfg; |
225c7b1f RD |
1547 | struct mlx4_profile profile; |
1548 | struct mlx4_init_hca_param init_hca; | |
1549 | u64 icm_size; | |
1550 | int err; | |
1551 | ||
ab9c17a0 JM |
1552 | if (!mlx4_is_slave(dev)) { |
1553 | err = mlx4_QUERY_FW(dev); | |
1554 | if (err) { | |
1555 | if (err == -EACCES) | |
1a91de28 | 1556 | mlx4_info(dev, "non-primary physical function, skipping\n"); |
ab9c17a0 | 1557 | else |
1a91de28 | 1558 | mlx4_err(dev, "QUERY_FW command failed, aborting\n"); |
bef772eb | 1559 | return err; |
ab9c17a0 | 1560 | } |
225c7b1f | 1561 | |
ab9c17a0 JM |
1562 | err = mlx4_load_fw(dev); |
1563 | if (err) { | |
1a91de28 | 1564 | mlx4_err(dev, "Failed to start FW, aborting\n"); |
bef772eb | 1565 | return err; |
ab9c17a0 | 1566 | } |
225c7b1f | 1567 | |
ab9c17a0 JM |
1568 | mlx4_cfg.log_pg_sz_m = 1; |
1569 | mlx4_cfg.log_pg_sz = 0; | |
1570 | err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); | |
1571 | if (err) | |
1572 | mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); | |
2d928651 | 1573 | |
ab9c17a0 JM |
1574 | err = mlx4_dev_cap(dev, &dev_cap); |
1575 | if (err) { | |
1a91de28 | 1576 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
ab9c17a0 JM |
1577 | goto err_stop_fw; |
1578 | } | |
225c7b1f | 1579 | |
7b8157be | 1580 | choose_steering_mode(dev, &dev_cap); |
7ffdf726 | 1581 | choose_tunnel_offload_mode(dev, &dev_cap); |
7b8157be | 1582 | |
8e1a28e8 HHZ |
1583 | err = mlx4_get_phys_port_id(dev); |
1584 | if (err) | |
1585 | mlx4_err(dev, "Fail to get physical port id\n"); | |
1586 | ||
6634961c JM |
1587 | if (mlx4_is_master(dev)) |
1588 | mlx4_parav_master_pf_caps(dev); | |
1589 | ||
ab9c17a0 | 1590 | profile = default_profile; |
0ff1fb65 HHZ |
1591 | if (dev->caps.steering_mode == |
1592 | MLX4_STEERING_MODE_DEVICE_MANAGED) | |
1593 | profile.num_mcg = MLX4_FS_NUM_MCG; | |
225c7b1f | 1594 | |
ab9c17a0 JM |
1595 | icm_size = mlx4_make_profile(dev, &profile, &dev_cap, |
1596 | &init_hca); | |
1597 | if ((long long) icm_size < 0) { | |
1598 | err = icm_size; | |
1599 | goto err_stop_fw; | |
1600 | } | |
225c7b1f | 1601 | |
a5bbe892 EC |
1602 | dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; |
1603 | ||
ab9c17a0 JM |
1604 | init_hca.log_uar_sz = ilog2(dev->caps.num_uars); |
1605 | init_hca.uar_page_sz = PAGE_SHIFT - 12; | |
e448834e SM |
1606 | init_hca.mw_enabled = 0; |
1607 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || | |
1608 | dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) | |
1609 | init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; | |
c1b43dca | 1610 | |
ab9c17a0 JM |
1611 | err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); |
1612 | if (err) | |
1613 | goto err_stop_fw; | |
225c7b1f | 1614 | |
ab9c17a0 JM |
1615 | err = mlx4_INIT_HCA(dev, &init_hca); |
1616 | if (err) { | |
1a91de28 | 1617 | mlx4_err(dev, "INIT_HCA command failed, aborting\n"); |
ab9c17a0 JM |
1618 | goto err_free_icm; |
1619 | } | |
ddd8a6c1 EE |
1620 | /* |
1621 | * If TS is supported by FW | |
1622 | * read HCA frequency by QUERY_HCA command | |
1623 | */ | |
1624 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { | |
1625 | memset(&init_hca, 0, sizeof(init_hca)); | |
1626 | err = mlx4_QUERY_HCA(dev, &init_hca); | |
1627 | if (err) { | |
1a91de28 | 1628 | mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); |
ddd8a6c1 EE |
1629 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; |
1630 | } else { | |
1631 | dev->caps.hca_core_clock = | |
1632 | init_hca.hca_core_clock; | |
1633 | } | |
1634 | ||
1635 | /* In case we got HCA frequency 0 - disable timestamping | |
1636 | * to avoid dividing by zero | |
1637 | */ | |
1638 | if (!dev->caps.hca_core_clock) { | |
1639 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1640 | mlx4_err(dev, | |
1a91de28 | 1641 | "HCA frequency is 0 - timestamping is not supported\n"); |
ddd8a6c1 EE |
1642 | } else if (map_internal_clock(dev)) { |
1643 | /* | |
1644 | * Map internal clock, | |
1645 | * in case of failure disable timestamping | |
1646 | */ | |
1647 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1a91de28 | 1648 | mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); |
ddd8a6c1 EE |
1649 | } |
1650 | } | |
ab9c17a0 JM |
1651 | } else { |
1652 | err = mlx4_init_slave(dev); | |
1653 | if (err) { | |
5efe5355 JM |
1654 | if (err != -EPROBE_DEFER) |
1655 | mlx4_err(dev, "Failed to initialize slave\n"); | |
bef772eb | 1656 | return err; |
ab9c17a0 | 1657 | } |
225c7b1f | 1658 | |
ab9c17a0 JM |
1659 | err = mlx4_slave_cap(dev); |
1660 | if (err) { | |
1661 | mlx4_err(dev, "Failed to obtain slave caps\n"); | |
1662 | goto err_close; | |
1663 | } | |
225c7b1f RD |
1664 | } |
1665 | ||
ab9c17a0 JM |
1666 | if (map_bf_area(dev)) |
1667 | mlx4_dbg(dev, "Failed to map blue flame area\n"); | |
1668 | ||
1669 | /*Only the master set the ports, all the rest got it from it.*/ | |
1670 | if (!mlx4_is_slave(dev)) | |
1671 | mlx4_set_port_mask(dev); | |
1672 | ||
225c7b1f RD |
1673 | err = mlx4_QUERY_ADAPTER(dev, &adapter); |
1674 | if (err) { | |
1a91de28 | 1675 | mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); |
bef772eb | 1676 | goto unmap_bf; |
225c7b1f RD |
1677 | } |
1678 | ||
1679 | priv->eq_table.inta_pin = adapter.inta_pin; | |
cd9281d8 | 1680 | memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); |
225c7b1f RD |
1681 | |
1682 | return 0; | |
1683 | ||
bef772eb | 1684 | unmap_bf: |
ddd8a6c1 | 1685 | unmap_internal_clock(dev); |
bef772eb AY |
1686 | unmap_bf_area(dev); |
1687 | ||
b38f2879 | 1688 | if (mlx4_is_slave(dev)) { |
99ec41d0 | 1689 | kfree(dev->caps.qp0_qkey); |
b38f2879 DB |
1690 | kfree(dev->caps.qp0_tunnel); |
1691 | kfree(dev->caps.qp0_proxy); | |
1692 | kfree(dev->caps.qp1_tunnel); | |
1693 | kfree(dev->caps.qp1_proxy); | |
1694 | } | |
1695 | ||
225c7b1f | 1696 | err_close: |
41929ed2 DB |
1697 | if (mlx4_is_slave(dev)) |
1698 | mlx4_slave_exit(dev); | |
1699 | else | |
1700 | mlx4_CLOSE_HCA(dev, 0); | |
225c7b1f RD |
1701 | |
1702 | err_free_icm: | |
ab9c17a0 JM |
1703 | if (!mlx4_is_slave(dev)) |
1704 | mlx4_free_icms(dev); | |
225c7b1f RD |
1705 | |
1706 | err_stop_fw: | |
ab9c17a0 JM |
1707 | if (!mlx4_is_slave(dev)) { |
1708 | mlx4_UNMAP_FA(dev); | |
1709 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); | |
1710 | } | |
225c7b1f RD |
1711 | return err; |
1712 | } | |
1713 | ||
f2a3f6a3 OG |
1714 | static int mlx4_init_counters_table(struct mlx4_dev *dev) |
1715 | { | |
1716 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1717 | int nent; | |
1718 | ||
1719 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1720 | return -ENOENT; | |
1721 | ||
1722 | nent = dev->caps.max_counters; | |
1723 | return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); | |
1724 | } | |
1725 | ||
1726 | static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) | |
1727 | { | |
1728 | mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); | |
1729 | } | |
1730 | ||
ba062d52 | 1731 | int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) |
f2a3f6a3 OG |
1732 | { |
1733 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1734 | ||
1735 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1736 | return -ENOENT; | |
1737 | ||
1738 | *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); | |
1739 | if (*idx == -1) | |
1740 | return -ENOMEM; | |
1741 | ||
1742 | return 0; | |
1743 | } | |
ba062d52 JM |
1744 | |
1745 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) | |
1746 | { | |
1747 | u64 out_param; | |
1748 | int err; | |
1749 | ||
1750 | if (mlx4_is_mfunc(dev)) { | |
1751 | err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, | |
1752 | RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, | |
1753 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
1754 | if (!err) | |
1755 | *idx = get_param_l(&out_param); | |
1756 | ||
1757 | return err; | |
1758 | } | |
1759 | return __mlx4_counter_alloc(dev, idx); | |
1760 | } | |
f2a3f6a3 OG |
1761 | EXPORT_SYMBOL_GPL(mlx4_counter_alloc); |
1762 | ||
ba062d52 | 1763 | void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) |
f2a3f6a3 | 1764 | { |
7c6d74d2 | 1765 | mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); |
f2a3f6a3 OG |
1766 | return; |
1767 | } | |
ba062d52 JM |
1768 | |
1769 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) | |
1770 | { | |
e7dbeba8 | 1771 | u64 in_param = 0; |
ba062d52 JM |
1772 | |
1773 | if (mlx4_is_mfunc(dev)) { | |
1774 | set_param_l(&in_param, idx); | |
1775 | mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, | |
1776 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
1777 | MLX4_CMD_WRAPPED); | |
1778 | return; | |
1779 | } | |
1780 | __mlx4_counter_free(dev, idx); | |
1781 | } | |
f2a3f6a3 OG |
1782 | EXPORT_SYMBOL_GPL(mlx4_counter_free); |
1783 | ||
3d73c288 | 1784 | static int mlx4_setup_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1785 | { |
1786 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1787 | int err; | |
7ff93f8b | 1788 | int port; |
9a5aa622 | 1789 | __be32 ib_port_default_caps; |
225c7b1f | 1790 | |
225c7b1f RD |
1791 | err = mlx4_init_uar_table(dev); |
1792 | if (err) { | |
1a91de28 JP |
1793 | mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); |
1794 | return err; | |
225c7b1f RD |
1795 | } |
1796 | ||
1797 | err = mlx4_uar_alloc(dev, &priv->driver_uar); | |
1798 | if (err) { | |
1a91de28 | 1799 | mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); |
225c7b1f RD |
1800 | goto err_uar_table_free; |
1801 | } | |
1802 | ||
4979d18f | 1803 | priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); |
225c7b1f | 1804 | if (!priv->kar) { |
1a91de28 | 1805 | mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); |
225c7b1f RD |
1806 | err = -ENOMEM; |
1807 | goto err_uar_free; | |
1808 | } | |
1809 | ||
1810 | err = mlx4_init_pd_table(dev); | |
1811 | if (err) { | |
1a91de28 | 1812 | mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); |
225c7b1f RD |
1813 | goto err_kar_unmap; |
1814 | } | |
1815 | ||
012a8ff5 SH |
1816 | err = mlx4_init_xrcd_table(dev); |
1817 | if (err) { | |
1a91de28 | 1818 | mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); |
012a8ff5 SH |
1819 | goto err_pd_table_free; |
1820 | } | |
1821 | ||
225c7b1f RD |
1822 | err = mlx4_init_mr_table(dev); |
1823 | if (err) { | |
1a91de28 | 1824 | mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); |
012a8ff5 | 1825 | goto err_xrcd_table_free; |
225c7b1f RD |
1826 | } |
1827 | ||
fe6f700d YP |
1828 | if (!mlx4_is_slave(dev)) { |
1829 | err = mlx4_init_mcg_table(dev); | |
1830 | if (err) { | |
1a91de28 | 1831 | mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); |
fe6f700d YP |
1832 | goto err_mr_table_free; |
1833 | } | |
1834 | } | |
1835 | ||
225c7b1f RD |
1836 | err = mlx4_init_eq_table(dev); |
1837 | if (err) { | |
1a91de28 | 1838 | mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); |
fe6f700d | 1839 | goto err_mcg_table_free; |
225c7b1f RD |
1840 | } |
1841 | ||
1842 | err = mlx4_cmd_use_events(dev); | |
1843 | if (err) { | |
1a91de28 | 1844 | mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); |
225c7b1f RD |
1845 | goto err_eq_table_free; |
1846 | } | |
1847 | ||
1848 | err = mlx4_NOP(dev); | |
1849 | if (err) { | |
08fb1055 | 1850 | if (dev->flags & MLX4_FLAG_MSI_X) { |
1a91de28 | 1851 | mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", |
b8dd786f | 1852 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
1a91de28 | 1853 | mlx4_warn(dev, "Trying again without MSI-X\n"); |
08fb1055 | 1854 | } else { |
1a91de28 | 1855 | mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", |
b8dd786f | 1856 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
225c7b1f | 1857 | mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); |
08fb1055 | 1858 | } |
225c7b1f RD |
1859 | |
1860 | goto err_cmd_poll; | |
1861 | } | |
1862 | ||
1863 | mlx4_dbg(dev, "NOP command IRQ test passed\n"); | |
1864 | ||
1865 | err = mlx4_init_cq_table(dev); | |
1866 | if (err) { | |
1a91de28 | 1867 | mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); |
225c7b1f RD |
1868 | goto err_cmd_poll; |
1869 | } | |
1870 | ||
1871 | err = mlx4_init_srq_table(dev); | |
1872 | if (err) { | |
1a91de28 | 1873 | mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); |
225c7b1f RD |
1874 | goto err_cq_table_free; |
1875 | } | |
1876 | ||
1877 | err = mlx4_init_qp_table(dev); | |
1878 | if (err) { | |
1a91de28 | 1879 | mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); |
225c7b1f RD |
1880 | goto err_srq_table_free; |
1881 | } | |
1882 | ||
f2a3f6a3 OG |
1883 | err = mlx4_init_counters_table(dev); |
1884 | if (err && err != -ENOENT) { | |
1a91de28 | 1885 | mlx4_err(dev, "Failed to initialize counters table, aborting\n"); |
fe6f700d | 1886 | goto err_qp_table_free; |
f2a3f6a3 OG |
1887 | } |
1888 | ||
ab9c17a0 JM |
1889 | if (!mlx4_is_slave(dev)) { |
1890 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
ab9c17a0 JM |
1891 | ib_port_default_caps = 0; |
1892 | err = mlx4_get_port_ib_caps(dev, port, | |
1893 | &ib_port_default_caps); | |
1894 | if (err) | |
1a91de28 JP |
1895 | mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", |
1896 | port, err); | |
ab9c17a0 JM |
1897 | dev->caps.ib_port_def_cap[port] = ib_port_default_caps; |
1898 | ||
2aca1172 JM |
1899 | /* initialize per-slave default ib port capabilities */ |
1900 | if (mlx4_is_master(dev)) { | |
1901 | int i; | |
1902 | for (i = 0; i < dev->num_slaves; i++) { | |
1903 | if (i == mlx4_master_func_num(dev)) | |
1904 | continue; | |
1905 | priv->mfunc.master.slave_state[i].ib_cap_mask[port] = | |
1a91de28 | 1906 | ib_port_default_caps; |
2aca1172 JM |
1907 | } |
1908 | } | |
1909 | ||
096335b3 OG |
1910 | if (mlx4_is_mfunc(dev)) |
1911 | dev->caps.port_ib_mtu[port] = IB_MTU_2048; | |
1912 | else | |
1913 | dev->caps.port_ib_mtu[port] = IB_MTU_4096; | |
97285b78 | 1914 | |
6634961c JM |
1915 | err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? |
1916 | dev->caps.pkey_table_len[port] : -1); | |
ab9c17a0 JM |
1917 | if (err) { |
1918 | mlx4_err(dev, "Failed to set port %d, aborting\n", | |
1a91de28 | 1919 | port); |
ab9c17a0 JM |
1920 | goto err_counters_table_free; |
1921 | } | |
7ff93f8b YP |
1922 | } |
1923 | } | |
1924 | ||
225c7b1f RD |
1925 | return 0; |
1926 | ||
f2a3f6a3 OG |
1927 | err_counters_table_free: |
1928 | mlx4_cleanup_counters_table(dev); | |
1929 | ||
225c7b1f RD |
1930 | err_qp_table_free: |
1931 | mlx4_cleanup_qp_table(dev); | |
1932 | ||
1933 | err_srq_table_free: | |
1934 | mlx4_cleanup_srq_table(dev); | |
1935 | ||
1936 | err_cq_table_free: | |
1937 | mlx4_cleanup_cq_table(dev); | |
1938 | ||
1939 | err_cmd_poll: | |
1940 | mlx4_cmd_use_polling(dev); | |
1941 | ||
1942 | err_eq_table_free: | |
1943 | mlx4_cleanup_eq_table(dev); | |
1944 | ||
fe6f700d YP |
1945 | err_mcg_table_free: |
1946 | if (!mlx4_is_slave(dev)) | |
1947 | mlx4_cleanup_mcg_table(dev); | |
1948 | ||
ee49bd93 | 1949 | err_mr_table_free: |
225c7b1f RD |
1950 | mlx4_cleanup_mr_table(dev); |
1951 | ||
012a8ff5 SH |
1952 | err_xrcd_table_free: |
1953 | mlx4_cleanup_xrcd_table(dev); | |
1954 | ||
225c7b1f RD |
1955 | err_pd_table_free: |
1956 | mlx4_cleanup_pd_table(dev); | |
1957 | ||
1958 | err_kar_unmap: | |
1959 | iounmap(priv->kar); | |
1960 | ||
1961 | err_uar_free: | |
1962 | mlx4_uar_free(dev, &priv->driver_uar); | |
1963 | ||
1964 | err_uar_table_free: | |
1965 | mlx4_cleanup_uar_table(dev); | |
1966 | return err; | |
1967 | } | |
1968 | ||
e8f9b2ed | 1969 | static void mlx4_enable_msi_x(struct mlx4_dev *dev) |
225c7b1f RD |
1970 | { |
1971 | struct mlx4_priv *priv = mlx4_priv(dev); | |
b8dd786f | 1972 | struct msix_entry *entries; |
0b7ca5a9 | 1973 | int nreq = min_t(int, dev->caps.num_ports * |
bb2146bc | 1974 | min_t(int, num_online_cpus() + 1, |
90b1ebe7 | 1975 | MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX); |
225c7b1f RD |
1976 | int i; |
1977 | ||
1978 | if (msi_x) { | |
ca4c7b35 OG |
1979 | nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, |
1980 | nreq); | |
ab9c17a0 | 1981 | |
b8dd786f YP |
1982 | entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); |
1983 | if (!entries) | |
1984 | goto no_msi; | |
1985 | ||
1986 | for (i = 0; i < nreq; ++i) | |
225c7b1f RD |
1987 | entries[i].entry = i; |
1988 | ||
66e2f9c1 AG |
1989 | nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq); |
1990 | ||
1991 | if (nreq < 0) { | |
5bf0da7d | 1992 | kfree(entries); |
225c7b1f | 1993 | goto no_msi; |
66e2f9c1 | 1994 | } else if (nreq < MSIX_LEGACY_SZ + |
1a91de28 | 1995 | dev->caps.num_ports * MIN_MSIX_P_PORT) { |
0b7ca5a9 YP |
1996 | /*Working in legacy mode , all EQ's shared*/ |
1997 | dev->caps.comp_pool = 0; | |
1998 | dev->caps.num_comp_vectors = nreq - 1; | |
1999 | } else { | |
2000 | dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; | |
2001 | dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; | |
2002 | } | |
b8dd786f | 2003 | for (i = 0; i < nreq; ++i) |
225c7b1f RD |
2004 | priv->eq_table.eq[i].irq = entries[i].vector; |
2005 | ||
2006 | dev->flags |= MLX4_FLAG_MSI_X; | |
b8dd786f YP |
2007 | |
2008 | kfree(entries); | |
225c7b1f RD |
2009 | return; |
2010 | } | |
2011 | ||
2012 | no_msi: | |
b8dd786f | 2013 | dev->caps.num_comp_vectors = 1; |
0b7ca5a9 | 2014 | dev->caps.comp_pool = 0; |
b8dd786f YP |
2015 | |
2016 | for (i = 0; i < 2; ++i) | |
225c7b1f RD |
2017 | priv->eq_table.eq[i].irq = dev->pdev->irq; |
2018 | } | |
2019 | ||
7ff93f8b | 2020 | static int mlx4_init_port_info(struct mlx4_dev *dev, int port) |
2a2336f8 YP |
2021 | { |
2022 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
7ff93f8b | 2023 | int err = 0; |
2a2336f8 YP |
2024 | |
2025 | info->dev = dev; | |
2026 | info->port = port; | |
ab9c17a0 | 2027 | if (!mlx4_is_slave(dev)) { |
ab9c17a0 JM |
2028 | mlx4_init_mac_table(dev, &info->mac_table); |
2029 | mlx4_init_vlan_table(dev, &info->vlan_table); | |
111c6094 | 2030 | mlx4_init_roce_gid_table(dev, &info->gid_table); |
16a10ffd | 2031 | info->base_qpn = mlx4_get_base_qpn(dev, port); |
ab9c17a0 | 2032 | } |
7ff93f8b YP |
2033 | |
2034 | sprintf(info->dev_name, "mlx4_port%d", port); | |
2035 | info->port_attr.attr.name = info->dev_name; | |
ab9c17a0 JM |
2036 | if (mlx4_is_mfunc(dev)) |
2037 | info->port_attr.attr.mode = S_IRUGO; | |
2038 | else { | |
2039 | info->port_attr.attr.mode = S_IRUGO | S_IWUSR; | |
2040 | info->port_attr.store = set_port_type; | |
2041 | } | |
7ff93f8b | 2042 | info->port_attr.show = show_port_type; |
3691c964 | 2043 | sysfs_attr_init(&info->port_attr.attr); |
7ff93f8b YP |
2044 | |
2045 | err = device_create_file(&dev->pdev->dev, &info->port_attr); | |
2046 | if (err) { | |
2047 | mlx4_err(dev, "Failed to create file for port %d\n", port); | |
2048 | info->port = -1; | |
2049 | } | |
2050 | ||
096335b3 OG |
2051 | sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); |
2052 | info->port_mtu_attr.attr.name = info->dev_mtu_name; | |
2053 | if (mlx4_is_mfunc(dev)) | |
2054 | info->port_mtu_attr.attr.mode = S_IRUGO; | |
2055 | else { | |
2056 | info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; | |
2057 | info->port_mtu_attr.store = set_port_ib_mtu; | |
2058 | } | |
2059 | info->port_mtu_attr.show = show_port_ib_mtu; | |
2060 | sysfs_attr_init(&info->port_mtu_attr.attr); | |
2061 | ||
2062 | err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); | |
2063 | if (err) { | |
2064 | mlx4_err(dev, "Failed to create mtu file for port %d\n", port); | |
2065 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
2066 | info->port = -1; | |
2067 | } | |
2068 | ||
7ff93f8b YP |
2069 | return err; |
2070 | } | |
2071 | ||
2072 | static void mlx4_cleanup_port_info(struct mlx4_port_info *info) | |
2073 | { | |
2074 | if (info->port < 0) | |
2075 | return; | |
2076 | ||
2077 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
096335b3 | 2078 | device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); |
2a2336f8 YP |
2079 | } |
2080 | ||
b12d93d6 YP |
2081 | static int mlx4_init_steering(struct mlx4_dev *dev) |
2082 | { | |
2083 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2084 | int num_entries = dev->caps.num_ports; | |
2085 | int i, j; | |
2086 | ||
2087 | priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); | |
2088 | if (!priv->steer) | |
2089 | return -ENOMEM; | |
2090 | ||
45b51365 | 2091 | for (i = 0; i < num_entries; i++) |
b12d93d6 YP |
2092 | for (j = 0; j < MLX4_NUM_STEERS; j++) { |
2093 | INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); | |
2094 | INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); | |
2095 | } | |
b12d93d6 YP |
2096 | return 0; |
2097 | } | |
2098 | ||
2099 | static void mlx4_clear_steering(struct mlx4_dev *dev) | |
2100 | { | |
2101 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2102 | struct mlx4_steer_index *entry, *tmp_entry; | |
2103 | struct mlx4_promisc_qp *pqp, *tmp_pqp; | |
2104 | int num_entries = dev->caps.num_ports; | |
2105 | int i, j; | |
2106 | ||
2107 | for (i = 0; i < num_entries; i++) { | |
2108 | for (j = 0; j < MLX4_NUM_STEERS; j++) { | |
2109 | list_for_each_entry_safe(pqp, tmp_pqp, | |
2110 | &priv->steer[i].promisc_qps[j], | |
2111 | list) { | |
2112 | list_del(&pqp->list); | |
2113 | kfree(pqp); | |
2114 | } | |
2115 | list_for_each_entry_safe(entry, tmp_entry, | |
2116 | &priv->steer[i].steer_entries[j], | |
2117 | list) { | |
2118 | list_del(&entry->list); | |
2119 | list_for_each_entry_safe(pqp, tmp_pqp, | |
2120 | &entry->duplicates, | |
2121 | list) { | |
2122 | list_del(&pqp->list); | |
2123 | kfree(pqp); | |
2124 | } | |
2125 | kfree(entry); | |
2126 | } | |
2127 | } | |
2128 | } | |
2129 | kfree(priv->steer); | |
2130 | } | |
2131 | ||
ab9c17a0 JM |
2132 | static int extended_func_num(struct pci_dev *pdev) |
2133 | { | |
2134 | return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); | |
2135 | } | |
2136 | ||
2137 | #define MLX4_OWNER_BASE 0x8069c | |
2138 | #define MLX4_OWNER_SIZE 4 | |
2139 | ||
2140 | static int mlx4_get_ownership(struct mlx4_dev *dev) | |
2141 | { | |
2142 | void __iomem *owner; | |
2143 | u32 ret; | |
2144 | ||
57dbf29a KSS |
2145 | if (pci_channel_offline(dev->pdev)) |
2146 | return -EIO; | |
2147 | ||
ab9c17a0 JM |
2148 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, |
2149 | MLX4_OWNER_SIZE); | |
2150 | if (!owner) { | |
2151 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
2152 | return -ENOMEM; | |
2153 | } | |
2154 | ||
2155 | ret = readl(owner); | |
2156 | iounmap(owner); | |
2157 | return (int) !!ret; | |
2158 | } | |
2159 | ||
2160 | static void mlx4_free_ownership(struct mlx4_dev *dev) | |
2161 | { | |
2162 | void __iomem *owner; | |
2163 | ||
57dbf29a KSS |
2164 | if (pci_channel_offline(dev->pdev)) |
2165 | return; | |
2166 | ||
ab9c17a0 JM |
2167 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, |
2168 | MLX4_OWNER_SIZE); | |
2169 | if (!owner) { | |
2170 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
2171 | return; | |
2172 | } | |
2173 | writel(0, owner); | |
2174 | msleep(1000); | |
2175 | iounmap(owner); | |
2176 | } | |
2177 | ||
839f1243 | 2178 | static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data) |
225c7b1f | 2179 | { |
225c7b1f RD |
2180 | struct mlx4_priv *priv; |
2181 | struct mlx4_dev *dev; | |
2182 | int err; | |
2a2336f8 | 2183 | int port; |
dd41cc3b MB |
2184 | int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; |
2185 | int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; | |
2186 | const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { | |
2187 | {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; | |
1ab95d37 MB |
2188 | unsigned total_vfs = 0; |
2189 | int sriov_initialized = 0; | |
2190 | unsigned int i; | |
225c7b1f | 2191 | |
0a645e80 | 2192 | pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); |
225c7b1f RD |
2193 | |
2194 | err = pci_enable_device(pdev); | |
2195 | if (err) { | |
1a91de28 | 2196 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
225c7b1f RD |
2197 | return err; |
2198 | } | |
5a0d0a61 JM |
2199 | |
2200 | /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS | |
2201 | * per port, we must limit the number of VFs to 63 (since their are | |
2202 | * 128 MACs) | |
2203 | */ | |
dd41cc3b MB |
2204 | for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; |
2205 | total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { | |
2206 | nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; | |
1ab95d37 MB |
2207 | if (nvfs[i] < 0) { |
2208 | dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); | |
2209 | return -EINVAL; | |
2210 | } | |
2211 | } | |
dd41cc3b MB |
2212 | for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; |
2213 | i++) { | |
2214 | prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; | |
1ab95d37 MB |
2215 | if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { |
2216 | dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); | |
2217 | return -EINVAL; | |
2218 | } | |
2219 | } | |
2220 | if (total_vfs >= MLX4_MAX_NUM_VF) { | |
5a0d0a61 JM |
2221 | dev_err(&pdev->dev, |
2222 | "Requested more VF's (%d) than allowed (%d)\n", | |
1ab95d37 | 2223 | total_vfs, MLX4_MAX_NUM_VF - 1); |
ab9c17a0 JM |
2224 | return -EINVAL; |
2225 | } | |
30e514a7 | 2226 | |
1ab95d37 MB |
2227 | for (i = 0; i < MLX4_MAX_PORTS; i++) { |
2228 | if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) { | |
2229 | dev_err(&pdev->dev, | |
2230 | "Requested more VF's (%d) for port (%d) than allowed (%d)\n", | |
2231 | nvfs[i] + nvfs[2], i + 1, | |
2232 | MLX4_MAX_NUM_VF_P_PORT - 1); | |
2233 | return -EINVAL; | |
2234 | } | |
30e514a7 | 2235 | } |
1ab95d37 MB |
2236 | |
2237 | ||
225c7b1f | 2238 | /* |
ab9c17a0 | 2239 | * Check for BARs. |
225c7b1f | 2240 | */ |
839f1243 | 2241 | if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && |
ab9c17a0 | 2242 | !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { |
1a91de28 | 2243 | dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", |
839f1243 | 2244 | pci_dev_data, pci_resource_flags(pdev, 0)); |
225c7b1f RD |
2245 | err = -ENODEV; |
2246 | goto err_disable_pdev; | |
2247 | } | |
2248 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
1a91de28 | 2249 | dev_err(&pdev->dev, "Missing UAR, aborting\n"); |
225c7b1f RD |
2250 | err = -ENODEV; |
2251 | goto err_disable_pdev; | |
2252 | } | |
2253 | ||
a01df0fe | 2254 | err = pci_request_regions(pdev, DRV_NAME); |
225c7b1f | 2255 | if (err) { |
a01df0fe | 2256 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); |
225c7b1f RD |
2257 | goto err_disable_pdev; |
2258 | } | |
2259 | ||
225c7b1f RD |
2260 | pci_set_master(pdev); |
2261 | ||
6a35528a | 2262 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
225c7b1f | 2263 | if (err) { |
1a91de28 | 2264 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
284901a9 | 2265 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
225c7b1f | 2266 | if (err) { |
1a91de28 | 2267 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
a01df0fe | 2268 | goto err_release_regions; |
225c7b1f RD |
2269 | } |
2270 | } | |
6a35528a | 2271 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
225c7b1f | 2272 | if (err) { |
1a91de28 | 2273 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
284901a9 | 2274 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
225c7b1f | 2275 | if (err) { |
1a91de28 | 2276 | dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); |
a01df0fe | 2277 | goto err_release_regions; |
225c7b1f RD |
2278 | } |
2279 | } | |
2280 | ||
7f9e5c48 DD |
2281 | /* Allow large DMA segments, up to the firmware limit of 1 GB */ |
2282 | dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); | |
2283 | ||
befdf897 WY |
2284 | dev = pci_get_drvdata(pdev); |
2285 | priv = mlx4_priv(dev); | |
225c7b1f | 2286 | dev->pdev = pdev; |
b581401e RD |
2287 | INIT_LIST_HEAD(&priv->ctx_list); |
2288 | spin_lock_init(&priv->ctx_lock); | |
225c7b1f | 2289 | |
7ff93f8b YP |
2290 | mutex_init(&priv->port_mutex); |
2291 | ||
6296883c YP |
2292 | INIT_LIST_HEAD(&priv->pgdir_list); |
2293 | mutex_init(&priv->pgdir_mutex); | |
2294 | ||
c1b43dca EC |
2295 | INIT_LIST_HEAD(&priv->bf_list); |
2296 | mutex_init(&priv->bf_mutex); | |
2297 | ||
aca7a3ac | 2298 | dev->rev_id = pdev->revision; |
6e7136ed | 2299 | dev->numa_node = dev_to_node(&pdev->dev); |
ab9c17a0 | 2300 | /* Detect if this device is a virtual function */ |
839f1243 | 2301 | if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { |
ab9c17a0 JM |
2302 | /* When acting as pf, we normally skip vfs unless explicitly |
2303 | * requested to probe them. */ | |
1ab95d37 MB |
2304 | if (total_vfs) { |
2305 | unsigned vfs_offset = 0; | |
2306 | for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && | |
1a91de28 | 2307 | vfs_offset + nvfs[i] < extended_func_num(pdev); |
1ab95d37 MB |
2308 | vfs_offset += nvfs[i], i++) |
2309 | ; | |
2310 | if (i == sizeof(nvfs)/sizeof(nvfs[0])) { | |
2311 | err = -ENODEV; | |
2312 | goto err_free_dev; | |
2313 | } | |
2314 | if ((extended_func_num(pdev) - vfs_offset) | |
2315 | > prb_vf[i]) { | |
2316 | mlx4_warn(dev, "Skipping virtual function:%d\n", | |
2317 | extended_func_num(pdev)); | |
2318 | err = -ENODEV; | |
2319 | goto err_free_dev; | |
2320 | } | |
ab9c17a0 JM |
2321 | } |
2322 | mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); | |
2323 | dev->flags |= MLX4_FLAG_SLAVE; | |
2324 | } else { | |
2325 | /* We reset the device and enable SRIOV only for physical | |
2326 | * devices. Try to claim ownership on the device; | |
2327 | * if already taken, skip -- do not allow multiple PFs */ | |
2328 | err = mlx4_get_ownership(dev); | |
2329 | if (err) { | |
2330 | if (err < 0) | |
2331 | goto err_free_dev; | |
2332 | else { | |
1a91de28 | 2333 | mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); |
ab9c17a0 JM |
2334 | err = -EINVAL; |
2335 | goto err_free_dev; | |
2336 | } | |
2337 | } | |
aca7a3ac | 2338 | |
1ab95d37 MB |
2339 | if (total_vfs) { |
2340 | mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", | |
2341 | total_vfs); | |
2342 | dev->dev_vfs = kzalloc( | |
1a91de28 JP |
2343 | total_vfs * sizeof(*dev->dev_vfs), |
2344 | GFP_KERNEL); | |
1ab95d37 MB |
2345 | if (NULL == dev->dev_vfs) { |
2346 | mlx4_err(dev, "Failed to allocate memory for VFs\n"); | |
ab9c17a0 JM |
2347 | err = 0; |
2348 | } else { | |
1ab95d37 MB |
2349 | atomic_inc(&pf_loading); |
2350 | err = pci_enable_sriov(pdev, total_vfs); | |
1ab95d37 | 2351 | if (err) { |
1a91de28 | 2352 | mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", |
1ab95d37 | 2353 | err); |
e1a5ddc5 | 2354 | atomic_dec(&pf_loading); |
1ab95d37 MB |
2355 | err = 0; |
2356 | } else { | |
2357 | mlx4_warn(dev, "Running in master mode\n"); | |
2358 | dev->flags |= MLX4_FLAG_SRIOV | | |
1a91de28 | 2359 | MLX4_FLAG_MASTER; |
1ab95d37 MB |
2360 | dev->num_vfs = total_vfs; |
2361 | sriov_initialized = 1; | |
2362 | } | |
ab9c17a0 JM |
2363 | } |
2364 | } | |
2365 | ||
fe6f700d YP |
2366 | atomic_set(&priv->opreq_count, 0); |
2367 | INIT_WORK(&priv->opreq_task, mlx4_opreq_action); | |
2368 | ||
ab9c17a0 JM |
2369 | /* |
2370 | * Now reset the HCA before we touch the PCI capabilities or | |
2371 | * attempt a firmware command, since a boot ROM may have left | |
2372 | * the HCA in an undefined state. | |
2373 | */ | |
2374 | err = mlx4_reset(dev); | |
2375 | if (err) { | |
1a91de28 | 2376 | mlx4_err(dev, "Failed to reset HCA, aborting\n"); |
ab9c17a0 JM |
2377 | goto err_rel_own; |
2378 | } | |
225c7b1f RD |
2379 | } |
2380 | ||
ab9c17a0 | 2381 | slave_start: |
521130d1 EE |
2382 | err = mlx4_cmd_init(dev); |
2383 | if (err) { | |
1a91de28 | 2384 | mlx4_err(dev, "Failed to init command interface, aborting\n"); |
ab9c17a0 JM |
2385 | goto err_sriov; |
2386 | } | |
2387 | ||
2388 | /* In slave functions, the communication channel must be initialized | |
2389 | * before posting commands. Also, init num_slaves before calling | |
2390 | * mlx4_init_hca */ | |
2391 | if (mlx4_is_mfunc(dev)) { | |
2392 | if (mlx4_is_master(dev)) | |
2393 | dev->num_slaves = MLX4_MAX_NUM_SLAVES; | |
2394 | else { | |
2395 | dev->num_slaves = 0; | |
f356fcbe JM |
2396 | err = mlx4_multi_func_init(dev); |
2397 | if (err) { | |
1a91de28 | 2398 | mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); |
ab9c17a0 JM |
2399 | goto err_cmd; |
2400 | } | |
2401 | } | |
225c7b1f RD |
2402 | } |
2403 | ||
2404 | err = mlx4_init_hca(dev); | |
ab9c17a0 JM |
2405 | if (err) { |
2406 | if (err == -EACCES) { | |
2407 | /* Not primary Physical function | |
2408 | * Running in slave mode */ | |
2409 | mlx4_cmd_cleanup(dev); | |
2410 | dev->flags |= MLX4_FLAG_SLAVE; | |
2411 | dev->flags &= ~MLX4_FLAG_MASTER; | |
2412 | goto slave_start; | |
2413 | } else | |
2414 | goto err_mfunc; | |
2415 | } | |
2416 | ||
b912b2f8 EP |
2417 | /* check if the device is functioning at its maximum possible speed. |
2418 | * No return code for this call, just warn the user in case of PCI | |
2419 | * express device capabilities are under-satisfied by the bus. | |
2420 | */ | |
83d3459a EP |
2421 | if (!mlx4_is_slave(dev)) |
2422 | mlx4_check_pcie_caps(dev); | |
b912b2f8 | 2423 | |
ab9c17a0 JM |
2424 | /* In master functions, the communication channel must be initialized |
2425 | * after obtaining its address from fw */ | |
2426 | if (mlx4_is_master(dev)) { | |
1ab95d37 | 2427 | unsigned sum = 0; |
f356fcbe JM |
2428 | err = mlx4_multi_func_init(dev); |
2429 | if (err) { | |
1a91de28 | 2430 | mlx4_err(dev, "Failed to init master mfunc interface, aborting\n"); |
ab9c17a0 JM |
2431 | goto err_close; |
2432 | } | |
1ab95d37 | 2433 | if (sriov_initialized) { |
dd41cc3b MB |
2434 | int ib_ports = 0; |
2435 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) | |
2436 | ib_ports++; | |
2437 | ||
2438 | if (ib_ports && | |
2439 | (num_vfs_argc > 1 || probe_vfs_argc > 1)) { | |
2440 | mlx4_err(dev, | |
1a91de28 | 2441 | "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n"); |
960b1f45 OG |
2442 | err = -EINVAL; |
2443 | goto err_master_mfunc; | |
dd41cc3b | 2444 | } |
1ab95d37 MB |
2445 | for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]); i++) { |
2446 | unsigned j; | |
2447 | for (j = 0; j < nvfs[i]; ++sum, ++j) { | |
2448 | dev->dev_vfs[sum].min_port = | |
2449 | i < 2 ? i + 1 : 1; | |
2450 | dev->dev_vfs[sum].n_ports = i < 2 ? 1 : | |
2451 | dev->caps.num_ports; | |
2452 | } | |
2453 | } | |
2454 | } | |
ab9c17a0 | 2455 | } |
225c7b1f | 2456 | |
b8dd786f YP |
2457 | err = mlx4_alloc_eq_table(dev); |
2458 | if (err) | |
ab9c17a0 | 2459 | goto err_master_mfunc; |
b8dd786f | 2460 | |
0b7ca5a9 | 2461 | priv->msix_ctl.pool_bm = 0; |
730c41d5 | 2462 | mutex_init(&priv->msix_ctl.pool_lock); |
0b7ca5a9 | 2463 | |
08fb1055 | 2464 | mlx4_enable_msi_x(dev); |
ab9c17a0 JM |
2465 | if ((mlx4_is_mfunc(dev)) && |
2466 | !(dev->flags & MLX4_FLAG_MSI_X)) { | |
f356fcbe | 2467 | err = -ENOSYS; |
1a91de28 | 2468 | mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); |
b12d93d6 | 2469 | goto err_free_eq; |
ab9c17a0 JM |
2470 | } |
2471 | ||
2472 | if (!mlx4_is_slave(dev)) { | |
2473 | err = mlx4_init_steering(dev); | |
2474 | if (err) | |
2475 | goto err_free_eq; | |
2476 | } | |
b12d93d6 | 2477 | |
225c7b1f | 2478 | err = mlx4_setup_hca(dev); |
ab9c17a0 JM |
2479 | if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && |
2480 | !mlx4_is_mfunc(dev)) { | |
08fb1055 | 2481 | dev->flags &= ~MLX4_FLAG_MSI_X; |
9858d2d1 YP |
2482 | dev->caps.num_comp_vectors = 1; |
2483 | dev->caps.comp_pool = 0; | |
08fb1055 MT |
2484 | pci_disable_msix(pdev); |
2485 | err = mlx4_setup_hca(dev); | |
2486 | } | |
2487 | ||
225c7b1f | 2488 | if (err) |
b12d93d6 | 2489 | goto err_steer; |
225c7b1f | 2490 | |
5a0d0a61 JM |
2491 | mlx4_init_quotas(dev); |
2492 | ||
7ff93f8b YP |
2493 | for (port = 1; port <= dev->caps.num_ports; port++) { |
2494 | err = mlx4_init_port_info(dev, port); | |
2495 | if (err) | |
2496 | goto err_port; | |
2497 | } | |
2a2336f8 | 2498 | |
225c7b1f RD |
2499 | err = mlx4_register_device(dev); |
2500 | if (err) | |
7ff93f8b | 2501 | goto err_port; |
225c7b1f | 2502 | |
b046ffe5 EP |
2503 | mlx4_request_modules(dev); |
2504 | ||
27bf91d6 YP |
2505 | mlx4_sense_init(dev); |
2506 | mlx4_start_sense(dev); | |
2507 | ||
befdf897 | 2508 | priv->removed = 0; |
225c7b1f | 2509 | |
e1a5ddc5 AV |
2510 | if (mlx4_is_master(dev) && dev->num_vfs) |
2511 | atomic_dec(&pf_loading); | |
2512 | ||
225c7b1f RD |
2513 | return 0; |
2514 | ||
7ff93f8b | 2515 | err_port: |
b4f77264 | 2516 | for (--port; port >= 1; --port) |
7ff93f8b YP |
2517 | mlx4_cleanup_port_info(&priv->port[port]); |
2518 | ||
f2a3f6a3 | 2519 | mlx4_cleanup_counters_table(dev); |
225c7b1f RD |
2520 | mlx4_cleanup_qp_table(dev); |
2521 | mlx4_cleanup_srq_table(dev); | |
2522 | mlx4_cleanup_cq_table(dev); | |
2523 | mlx4_cmd_use_polling(dev); | |
2524 | mlx4_cleanup_eq_table(dev); | |
fe6f700d | 2525 | mlx4_cleanup_mcg_table(dev); |
225c7b1f | 2526 | mlx4_cleanup_mr_table(dev); |
012a8ff5 | 2527 | mlx4_cleanup_xrcd_table(dev); |
225c7b1f RD |
2528 | mlx4_cleanup_pd_table(dev); |
2529 | mlx4_cleanup_uar_table(dev); | |
2530 | ||
b12d93d6 | 2531 | err_steer: |
ab9c17a0 JM |
2532 | if (!mlx4_is_slave(dev)) |
2533 | mlx4_clear_steering(dev); | |
b12d93d6 | 2534 | |
b8dd786f YP |
2535 | err_free_eq: |
2536 | mlx4_free_eq_table(dev); | |
2537 | ||
ab9c17a0 JM |
2538 | err_master_mfunc: |
2539 | if (mlx4_is_master(dev)) | |
2540 | mlx4_multi_func_cleanup(dev); | |
2541 | ||
b38f2879 | 2542 | if (mlx4_is_slave(dev)) { |
99ec41d0 | 2543 | kfree(dev->caps.qp0_qkey); |
b38f2879 DB |
2544 | kfree(dev->caps.qp0_tunnel); |
2545 | kfree(dev->caps.qp0_proxy); | |
2546 | kfree(dev->caps.qp1_tunnel); | |
2547 | kfree(dev->caps.qp1_proxy); | |
2548 | } | |
2549 | ||
225c7b1f | 2550 | err_close: |
08fb1055 MT |
2551 | if (dev->flags & MLX4_FLAG_MSI_X) |
2552 | pci_disable_msix(pdev); | |
2553 | ||
225c7b1f RD |
2554 | mlx4_close_hca(dev); |
2555 | ||
ab9c17a0 JM |
2556 | err_mfunc: |
2557 | if (mlx4_is_slave(dev)) | |
2558 | mlx4_multi_func_cleanup(dev); | |
2559 | ||
225c7b1f RD |
2560 | err_cmd: |
2561 | mlx4_cmd_cleanup(dev); | |
2562 | ||
ab9c17a0 | 2563 | err_sriov: |
681372a7 | 2564 | if (dev->flags & MLX4_FLAG_SRIOV) |
ab9c17a0 JM |
2565 | pci_disable_sriov(pdev); |
2566 | ||
2567 | err_rel_own: | |
2568 | if (!mlx4_is_slave(dev)) | |
2569 | mlx4_free_ownership(dev); | |
2570 | ||
e1a5ddc5 AV |
2571 | if (mlx4_is_master(dev) && dev->num_vfs) |
2572 | atomic_dec(&pf_loading); | |
2573 | ||
1ab95d37 MB |
2574 | kfree(priv->dev.dev_vfs); |
2575 | ||
225c7b1f | 2576 | err_free_dev: |
225c7b1f RD |
2577 | kfree(priv); |
2578 | ||
a01df0fe RD |
2579 | err_release_regions: |
2580 | pci_release_regions(pdev); | |
225c7b1f RD |
2581 | |
2582 | err_disable_pdev: | |
2583 | pci_disable_device(pdev); | |
2584 | pci_set_drvdata(pdev, NULL); | |
2585 | return err; | |
2586 | } | |
2587 | ||
1dd06ae8 | 2588 | static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
3d73c288 | 2589 | { |
befdf897 WY |
2590 | struct mlx4_priv *priv; |
2591 | struct mlx4_dev *dev; | |
2592 | ||
0a645e80 | 2593 | printk_once(KERN_INFO "%s", mlx4_version); |
3d73c288 | 2594 | |
befdf897 WY |
2595 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
2596 | if (!priv) | |
2597 | return -ENOMEM; | |
2598 | ||
2599 | dev = &priv->dev; | |
2600 | pci_set_drvdata(pdev, dev); | |
2601 | priv->pci_dev_data = id->driver_data; | |
2602 | ||
839f1243 | 2603 | return __mlx4_init_one(pdev, id->driver_data); |
3d73c288 RD |
2604 | } |
2605 | ||
befdf897 | 2606 | static void __mlx4_remove_one(struct pci_dev *pdev) |
225c7b1f RD |
2607 | { |
2608 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
2609 | struct mlx4_priv *priv = mlx4_priv(dev); | |
befdf897 | 2610 | int pci_dev_data; |
225c7b1f RD |
2611 | int p; |
2612 | ||
befdf897 WY |
2613 | if (priv->removed) |
2614 | return; | |
225c7b1f | 2615 | |
befdf897 | 2616 | pci_dev_data = priv->pci_dev_data; |
225c7b1f | 2617 | |
befdf897 WY |
2618 | /* in SRIOV it is not allowed to unload the pf's |
2619 | * driver while there are alive vf's */ | |
2620 | if (mlx4_is_master(dev) && mlx4_how_many_lives_vf(dev)) | |
c20862c8 | 2621 | pr_warn("Removing PF when there are assigned VF's !!!\n"); |
befdf897 WY |
2622 | mlx4_stop_sense(dev); |
2623 | mlx4_unregister_device(dev); | |
225c7b1f | 2624 | |
befdf897 WY |
2625 | for (p = 1; p <= dev->caps.num_ports; p++) { |
2626 | mlx4_cleanup_port_info(&priv->port[p]); | |
2627 | mlx4_CLOSE_PORT(dev, p); | |
2628 | } | |
2629 | ||
2630 | if (mlx4_is_master(dev)) | |
2631 | mlx4_free_resource_tracker(dev, | |
2632 | RES_TR_FREE_SLAVES_ONLY); | |
2633 | ||
2634 | mlx4_cleanup_counters_table(dev); | |
2635 | mlx4_cleanup_qp_table(dev); | |
2636 | mlx4_cleanup_srq_table(dev); | |
2637 | mlx4_cleanup_cq_table(dev); | |
2638 | mlx4_cmd_use_polling(dev); | |
2639 | mlx4_cleanup_eq_table(dev); | |
2640 | mlx4_cleanup_mcg_table(dev); | |
2641 | mlx4_cleanup_mr_table(dev); | |
2642 | mlx4_cleanup_xrcd_table(dev); | |
2643 | mlx4_cleanup_pd_table(dev); | |
225c7b1f | 2644 | |
befdf897 WY |
2645 | if (mlx4_is_master(dev)) |
2646 | mlx4_free_resource_tracker(dev, | |
2647 | RES_TR_FREE_STRUCTS_ONLY); | |
47605df9 | 2648 | |
befdf897 WY |
2649 | iounmap(priv->kar); |
2650 | mlx4_uar_free(dev, &priv->driver_uar); | |
2651 | mlx4_cleanup_uar_table(dev); | |
2652 | if (!mlx4_is_slave(dev)) | |
2653 | mlx4_clear_steering(dev); | |
2654 | mlx4_free_eq_table(dev); | |
2655 | if (mlx4_is_master(dev)) | |
2656 | mlx4_multi_func_cleanup(dev); | |
2657 | mlx4_close_hca(dev); | |
2658 | if (mlx4_is_slave(dev)) | |
2659 | mlx4_multi_func_cleanup(dev); | |
2660 | mlx4_cmd_cleanup(dev); | |
47605df9 | 2661 | |
befdf897 WY |
2662 | if (dev->flags & MLX4_FLAG_MSI_X) |
2663 | pci_disable_msix(pdev); | |
2664 | if (dev->flags & MLX4_FLAG_SRIOV) { | |
2665 | mlx4_warn(dev, "Disabling SR-IOV\n"); | |
2666 | pci_disable_sriov(pdev); | |
e1a5ddc5 | 2667 | dev->num_vfs = 0; |
225c7b1f | 2668 | } |
befdf897 WY |
2669 | |
2670 | if (!mlx4_is_slave(dev)) | |
2671 | mlx4_free_ownership(dev); | |
2672 | ||
99ec41d0 | 2673 | kfree(dev->caps.qp0_qkey); |
befdf897 WY |
2674 | kfree(dev->caps.qp0_tunnel); |
2675 | kfree(dev->caps.qp0_proxy); | |
2676 | kfree(dev->caps.qp1_tunnel); | |
2677 | kfree(dev->caps.qp1_proxy); | |
2678 | kfree(dev->dev_vfs); | |
2679 | ||
2680 | pci_release_regions(pdev); | |
2681 | pci_disable_device(pdev); | |
2682 | memset(priv, 0, sizeof(*priv)); | |
2683 | priv->pci_dev_data = pci_dev_data; | |
2684 | priv->removed = 1; | |
2685 | } | |
2686 | ||
2687 | static void mlx4_remove_one(struct pci_dev *pdev) | |
2688 | { | |
2689 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
2690 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2691 | ||
2692 | __mlx4_remove_one(pdev); | |
2693 | kfree(priv); | |
2694 | pci_set_drvdata(pdev, NULL); | |
225c7b1f RD |
2695 | } |
2696 | ||
ee49bd93 JM |
2697 | int mlx4_restart_one(struct pci_dev *pdev) |
2698 | { | |
839f1243 RD |
2699 | struct mlx4_dev *dev = pci_get_drvdata(pdev); |
2700 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2701 | int pci_dev_data; | |
2702 | ||
2703 | pci_dev_data = priv->pci_dev_data; | |
befdf897 | 2704 | __mlx4_remove_one(pdev); |
839f1243 | 2705 | return __mlx4_init_one(pdev, pci_dev_data); |
ee49bd93 JM |
2706 | } |
2707 | ||
a3aa1884 | 2708 | static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { |
ab9c17a0 | 2709 | /* MT25408 "Hermon" SDR */ |
ca3e57a5 | 2710 | { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2711 | /* MT25408 "Hermon" DDR */ |
ca3e57a5 | 2712 | { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2713 | /* MT25408 "Hermon" QDR */ |
ca3e57a5 | 2714 | { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2715 | /* MT25408 "Hermon" DDR PCIe gen2 */ |
ca3e57a5 | 2716 | { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2717 | /* MT25408 "Hermon" QDR PCIe gen2 */ |
ca3e57a5 | 2718 | { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2719 | /* MT25408 "Hermon" EN 10GigE */ |
ca3e57a5 | 2720 | { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2721 | /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ |
ca3e57a5 | 2722 | { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2723 | /* MT25458 ConnectX EN 10GBASE-T 10GigE */ |
ca3e57a5 | 2724 | { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2725 | /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ |
ca3e57a5 | 2726 | { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2727 | /* MT26468 ConnectX EN 10GigE PCIe gen2*/ |
ca3e57a5 | 2728 | { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2729 | /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ |
ca3e57a5 | 2730 | { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2731 | /* MT26478 ConnectX2 40GigE PCIe gen2 */ |
ca3e57a5 | 2732 | { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2733 | /* MT25400 Family [ConnectX-2 Virtual Function] */ |
839f1243 | 2734 | { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, |
ab9c17a0 JM |
2735 | /* MT27500 Family [ConnectX-3] */ |
2736 | { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, | |
2737 | /* MT27500 Family [ConnectX-3 Virtual Function] */ | |
839f1243 | 2738 | { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, |
ab9c17a0 JM |
2739 | { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ |
2740 | { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ | |
2741 | { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ | |
2742 | { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ | |
2743 | { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ | |
2744 | { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ | |
2745 | { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ | |
2746 | { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ | |
2747 | { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ | |
2748 | { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ | |
2749 | { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ | |
2750 | { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ | |
225c7b1f RD |
2751 | { 0, } |
2752 | }; | |
2753 | ||
2754 | MODULE_DEVICE_TABLE(pci, mlx4_pci_table); | |
2755 | ||
57dbf29a KSS |
2756 | static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, |
2757 | pci_channel_state_t state) | |
2758 | { | |
befdf897 | 2759 | __mlx4_remove_one(pdev); |
57dbf29a KSS |
2760 | |
2761 | return state == pci_channel_io_perm_failure ? | |
2762 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
2763 | } | |
2764 | ||
2765 | static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) | |
2766 | { | |
befdf897 WY |
2767 | struct mlx4_dev *dev = pci_get_drvdata(pdev); |
2768 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2769 | int ret; | |
97a5221f | 2770 | |
befdf897 | 2771 | ret = __mlx4_init_one(pdev, priv->pci_dev_data); |
57dbf29a KSS |
2772 | |
2773 | return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
2774 | } | |
2775 | ||
3646f0e5 | 2776 | static const struct pci_error_handlers mlx4_err_handler = { |
57dbf29a KSS |
2777 | .error_detected = mlx4_pci_err_detected, |
2778 | .slot_reset = mlx4_pci_slot_reset, | |
2779 | }; | |
2780 | ||
225c7b1f RD |
2781 | static struct pci_driver mlx4_driver = { |
2782 | .name = DRV_NAME, | |
2783 | .id_table = mlx4_pci_table, | |
2784 | .probe = mlx4_init_one, | |
da1de8df | 2785 | .shutdown = __mlx4_remove_one, |
f57e6848 | 2786 | .remove = mlx4_remove_one, |
57dbf29a | 2787 | .err_handler = &mlx4_err_handler, |
225c7b1f RD |
2788 | }; |
2789 | ||
7ff93f8b YP |
2790 | static int __init mlx4_verify_params(void) |
2791 | { | |
2792 | if ((log_num_mac < 0) || (log_num_mac > 7)) { | |
c20862c8 | 2793 | pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); |
7ff93f8b YP |
2794 | return -1; |
2795 | } | |
2796 | ||
cb29688a | 2797 | if (log_num_vlan != 0) |
c20862c8 AV |
2798 | pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", |
2799 | MLX4_LOG_NUM_VLANS); | |
7ff93f8b | 2800 | |
ecc8fb11 AV |
2801 | if (use_prio != 0) |
2802 | pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); | |
7ff93f8b | 2803 | |
0498628f | 2804 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { |
c20862c8 AV |
2805 | pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", |
2806 | log_mtts_per_seg); | |
ab6bf42e EC |
2807 | return -1; |
2808 | } | |
2809 | ||
ab9c17a0 JM |
2810 | /* Check if module param for ports type has legal combination */ |
2811 | if (port_type_array[0] == false && port_type_array[1] == true) { | |
c20862c8 | 2812 | pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); |
ab9c17a0 JM |
2813 | port_type_array[0] = true; |
2814 | } | |
2815 | ||
3c439b55 JM |
2816 | if (mlx4_log_num_mgm_entry_size != -1 && |
2817 | (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || | |
2818 | mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { | |
1a91de28 JP |
2819 | pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n", |
2820 | mlx4_log_num_mgm_entry_size, | |
2821 | MLX4_MIN_MGM_LOG_ENTRY_SIZE, | |
2822 | MLX4_MAX_MGM_LOG_ENTRY_SIZE); | |
3c439b55 JM |
2823 | return -1; |
2824 | } | |
2825 | ||
7ff93f8b YP |
2826 | return 0; |
2827 | } | |
2828 | ||
225c7b1f RD |
2829 | static int __init mlx4_init(void) |
2830 | { | |
2831 | int ret; | |
2832 | ||
7ff93f8b YP |
2833 | if (mlx4_verify_params()) |
2834 | return -EINVAL; | |
2835 | ||
27bf91d6 YP |
2836 | mlx4_catas_init(); |
2837 | ||
2838 | mlx4_wq = create_singlethread_workqueue("mlx4"); | |
2839 | if (!mlx4_wq) | |
2840 | return -ENOMEM; | |
ee49bd93 | 2841 | |
225c7b1f | 2842 | ret = pci_register_driver(&mlx4_driver); |
1b85ee09 WY |
2843 | if (ret < 0) |
2844 | destroy_workqueue(mlx4_wq); | |
225c7b1f RD |
2845 | return ret < 0 ? ret : 0; |
2846 | } | |
2847 | ||
2848 | static void __exit mlx4_cleanup(void) | |
2849 | { | |
2850 | pci_unregister_driver(&mlx4_driver); | |
27bf91d6 | 2851 | destroy_workqueue(mlx4_wq); |
225c7b1f RD |
2852 | } |
2853 | ||
2854 | module_init(mlx4_init); | |
2855 | module_exit(mlx4_cleanup); |