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[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
691223ec 37#include <linux/kernel.h>
225c7b1f
RD		 38#include <linux/init.h>
39#include <linux/errno.h>
40#include <linux/pci.h>
41#include <linux/dma-mapping.h>
5a0e3ad6 42#include <linux/slab.h>
c1b43dca 43#include <linux/io-mapping.h>
ab9c17a0 44#include <linux/delay.h>
b046ffe5 45#include <linux/kmod.h>
10b1c04e 46#include <linux/etherdevice.h>
09d4d087 47#include <net/devlink.h>
225c7b1f
RD		 48
49#include <linux/mlx4/device.h>
50#include <linux/mlx4/doorbell.h>
51
52#include "mlx4.h"
53#include "fw.h"
54#include "icm.h"
55
56MODULE_AUTHOR("Roland Dreier");
57MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
58MODULE_LICENSE("Dual BSD/GPL");
59MODULE_VERSION(DRV_VERSION);
60
27bf91d6
YP		 61struct workqueue_struct *mlx4_wq;
62
225c7b1f
RD		 63#ifdef CONFIG_MLX4_DEBUG
64
65int mlx4_debug_level = 0;
66module_param_named(debug_level, mlx4_debug_level, int, 0644);
67MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
68
69#endif /* CONFIG_MLX4_DEBUG */
70
71#ifdef CONFIG_PCI_MSI
72
08fb1055 73static int msi_x = 1;
225c7b1f
RD		 74module_param(msi_x, int, 0444);
75MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
76
77#else /* CONFIG_PCI_MSI */
78
79#define msi_x (0)
80
81#endif /* CONFIG_PCI_MSI */
82
dd41cc3b 83static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 84static int num_vfs_argc;
dd41cc3b
MB		 85module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
86MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
87 "num_vfs=port1,port2,port1+2");
88
89static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 90static int probe_vfs_argc;
dd41cc3b
MB		 91module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
92MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
93 "probe_vf=port1,port2,port1+2");
ab9c17a0 94
3b68067b 95static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 96module_param_named(log_num_mgm_entry_size,
97 mlx4_log_num_mgm_entry_size, int, 0444);
98MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
99 " of qp per mcg, for example:"
3c439b55 100 " 10 gives 248.range: 7 <="
0ff1fb65 101 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 102 " To activate device managed"
103 " flow steering when available, set to -1");
0ec2c0f8 104
be902ab1 105static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 106module_param(enable_64b_cqe_eqe, bool, 0444);
107MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 108 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 109
76e39ccf
EC		 110static bool enable_4k_uar;
111module_param(enable_4k_uar, bool, 0444);
112MODULE_PARM_DESC(enable_4k_uar,
113 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
114
77507aa2 115#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 116 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
117 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 118
55ad3592
YH		 119#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
120
f57e6848 121static char mlx4_version[] =
225c7b1f 122 DRV_NAME ": Mellanox ConnectX core driver v"
cea2a6d8 123 DRV_VERSION "\n";
225c7b1f 124
3f2c5fb2 125static const struct mlx4_profile default_profile = {
ab9c17a0 126 .num_qp = 1 << 18,
225c7b1f 127 .num_srq = 1 << 16,
c9f2ba5e 128 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 129 .num_cq = 1 << 16,
130 .num_mcg = 1 << 13,
ab9c17a0 131 .num_mpt = 1 << 19,
9fd7a1e1 132 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 133};
134
3f2c5fb2 135static const struct mlx4_profile low_mem_profile = {
2599d858
AV		 136 .num_qp = 1 << 17,
137 .num_srq = 1 << 6,
138 .rdmarc_per_qp = 1 << 4,
139 .num_cq = 1 << 8,
140 .num_mcg = 1 << 8,
141 .num_mpt = 1 << 9,
142 .num_mtt = 1 << 7,
143};
144
ab9c17a0 145static int log_num_mac = 7;
93fc9e1b
YP		 146module_param_named(log_num_mac, log_num_mac, int, 0444);
147MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
148
149static int log_num_vlan;
150module_param_named(log_num_vlan, log_num_vlan, int, 0444);
151MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 152/* Log2 max number of VLANs per ETH port (0-7) */
153#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 154#define MLX4_MIN_LOG_NUM_VLANS 0
155#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 156
eb939922 157static bool use_prio;
93fc9e1b 158module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 159MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 160
2b8fb286 161int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 162module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 163MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 164
8d0fc7b6 165static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 166static int arr_argc = 2;
167module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 168MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
169 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 170
171struct mlx4_port_config {
172 struct list_head list;
173 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
174 struct pci_dev *pdev;
175};
176
97989356
AV		 177static atomic_t pf_loading = ATOMIC_INIT(0);
178
85743f1e
HN		 179static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
180 struct mlx4_dev_cap *dev_cap)
181{
182 /* The reserved_uars is calculated by system page size unit.
183 * Therefore, adjustment is added when the uar page size is less
184 * than the system page size
185 */
186 dev->caps.reserved_uars =
187 max_t(int,
188 mlx4_get_num_reserved_uar(dev),
189 dev_cap->reserved_uars /
190 (1 << (PAGE_SHIFT - dev->uar_page_shift)));
191}
192
27bf91d6
YP		 193int mlx4_check_port_params(struct mlx4_dev *dev,
194 enum mlx4_port_type *port_type)
7ff93f8b
YP		 195{
196 int i;
197
0b997657
YS		 198 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
199 for (i = 0; i < dev->caps.num_ports - 1; i++) {
200 if (port_type[i] != port_type[i + 1]) {
1a91de28 201 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 202 return -EINVAL;
203 }
7ff93f8b
YP		 204 }
205 }
7ff93f8b
YP		 206
207 for (i = 0; i < dev->caps.num_ports; i++) {
208 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 209 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
210 i + 1);
7ff93f8b
YP		 211 return -EINVAL;
212 }
213 }
214 return 0;
215}
216
217static void mlx4_set_port_mask(struct mlx4_dev *dev)
218{
219 int i;
220
7ff93f8b 221 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 222 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 223}
f2a3f6a3 224
7ae0e400
MB		 225enum {
226 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
227};
228
229static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
230{
231 int err = 0;
232 struct mlx4_func func;
233
234 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
235 err = mlx4_QUERY_FUNC(dev, &func, 0);
236 if (err) {
237 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
238 return err;
239 }
240 dev_cap->max_eqs = func.max_eq;
241 dev_cap->reserved_eqs = func.rsvd_eqs;
242 dev_cap->reserved_uars = func.rsvd_uars;
243 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
244 }
245 return err;
246}
247
77507aa2
IS		 248static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
249{
250 struct mlx4_caps *dev_cap = &dev->caps;
251
252 /* FW not supporting or cancelled by user */
253 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
254 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
255 return;
256
257 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
258 * When FW has NCSI it may decide not to report 64B CQE/EQEs
259 */
260 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
261 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
262 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
263 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
264 return;
265 }
266
267 if (cache_line_size() == 128 || cache_line_size() == 256) {
268 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
269 /* Changing the real data inside CQE size to 32B */
270 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
271 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
272
273 if (mlx4_is_master(dev))
274 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
275 } else {
0fab541a
OG		 276 if (cache_line_size() != 32 && cache_line_size() != 64)
277 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
77507aa2
IS		 278 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
279 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
280 }
281}
282
431df8c7
MB		 283static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
284 struct mlx4_port_cap *port_cap)
285{
286 dev->caps.vl_cap[port] = port_cap->max_vl;
287 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
288 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
289 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
290 /* set gid and pkey table operating lengths by default
291 * to non-sriov values
292 */
293 dev->caps.gid_table_len[port] = port_cap->max_gids;
294 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
295 dev->caps.port_width_cap[port] = port_cap->max_port_width;
296 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
af7d5185 297 dev->caps.max_tc_eth = port_cap->max_tc_eth;
431df8c7
MB		 298 dev->caps.def_mac[port] = port_cap->def_mac;
299 dev->caps.supported_type[port] = port_cap->supported_port_types;
300 dev->caps.suggested_type[port] = port_cap->suggested_type;
301 dev->caps.default_sense[port] = port_cap->default_sense;
302 dev->caps.trans_type[port] = port_cap->trans_type;
303 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
304 dev->caps.wavelength[port] = port_cap->wavelength;
305 dev->caps.trans_code[port] = port_cap->trans_code;
306
307 return 0;
308}
309
310static int mlx4_dev_port(struct mlx4_dev *dev, int port,
311 struct mlx4_port_cap *port_cap)
312{
313 int err = 0;
314
315 err = mlx4_QUERY_PORT(dev, port, port_cap);
316
317 if (err)
318 mlx4_err(dev, "QUERY_PORT command failed.\n");
319
320 return err;
321}
322
78500b8c
MM		 323static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
324{
325 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
326 return;
327
328 if (mlx4_is_mfunc(dev)) {
329 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
330 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
331 return;
332 }
333
334 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
335 mlx4_dbg(dev,
336 "Keep FCS is not supported - Disabling Ignore FCS");
337 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
338 return;
339 }
340}
341
431df8c7 342#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 343static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 344{
345 int err;
5ae2a7a8 346 int i;
225c7b1f
RD		 347
348 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
349 if (err) {
1a91de28 350 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 351 return err;
352 }
c78e25ed 353 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 354
355 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 356 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 357 dev_cap->min_page_sz, PAGE_SIZE);
358 return -ENODEV;
359 }
360 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 361 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 362 dev_cap->num_ports, MLX4_MAX_PORTS);
363 return -ENODEV;
364 }
365
872bf2fb 366 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
1a91de28 367 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f 368 dev_cap->uar_size,
872bf2fb
YH		 369 (unsigned long long)
370 pci_resource_len(dev->persist->pdev, 2));
225c7b1f
RD		 371 return -ENODEV;
372 }
373
374 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 375 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
376 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
377 dev->caps.num_sys_eqs :
378 MLX4_MAX_EQ_NUM;
5ae2a7a8 379 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 380 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
381 if (err) {
382 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
383 return err;
384 }
5ae2a7a8
RD		 385 }
386
ab9c17a0 387 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 388 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 389 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
390 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
391 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
392 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
393 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
394 dev->caps.max_wqes = dev_cap->max_qp_sz;
395 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 396 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
397 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
398 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
399 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
400 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 401 /*
402 * Subtract 1 from the limit because we need to allocate a
403 * spare CQE so the HCA HW can tell the difference between an
404 * empty CQ and a full CQ.
405 */
406 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
407 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
408 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 409 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 410 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0 411
225c7b1f 412 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 413 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
414 dev_cap->reserved_xrcds : 0;
415 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
416 dev_cap->max_xrcds : 0;
2b8fb286
MA		 417 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
418
149983af 419 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 420 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
421 dev->caps.flags = dev_cap->flags;
b3416f44 422 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 423 dev->caps.bmme_flags = dev_cap->bmme_flags;
424 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 425 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 426 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 427 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
c994f778
IK		 428 dev->caps.wol_port[1] = dev_cap->wol_port[1];
429 dev->caps.wol_port[2] = dev_cap->wol_port[2];
225c7b1f 430
85743f1e
HN		 431 /* Save uar page shift */
432 if (!mlx4_is_slave(dev)) {
433 /* Virtual PCI function needs to determine UAR page size from
434 * firmware. Only master PCI function can set the uar page size
435 */
ca3d89a3 436 if (enable_4k_uar || !dev->persist->num_vfs)
76e39ccf
EC		 437 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
438 else
439 dev->uar_page_shift = PAGE_SHIFT;
440
85743f1e
HN		 441 mlx4_set_num_reserved_uars(dev, dev_cap);
442 }
443
77fc29c4
HHZ		 444 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
445 struct mlx4_init_hca_param hca_param;
446
447 memset(&hca_param, 0, sizeof(hca_param));
448 err = mlx4_QUERY_HCA(dev, &hca_param);
449 /* Turn off PHV_EN flag in case phv_check_en is set.
450 * phv_check_en is a HW check that parse the packet and verify
451 * phv bit was reported correctly in the wqe. To allow QinQ
452 * PHV_EN flag should be set and phv_check_en must be cleared
453 * otherwise QinQ packets will be drop by the HW.
454 */
455 if (err || hca_param.phv_check_en)
456 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
457 }
458
ca3e57a5
RD		 459 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
460 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 461 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 462 /* Don't do sense port on multifunction devices (for now at least) */
463 if (mlx4_is_mfunc(dev))
464 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 465
2599d858
AV		 466 if (mlx4_low_memory_profile()) {
467 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
468 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
469 } else {
470 dev->caps.log_num_macs = log_num_mac;
471 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
472 }
93fc9e1b
YP		 473
474 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 475 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
476 if (dev->caps.supported_type[i]) {
477 /* if only ETH is supported - assign ETH */
478 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
479 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 480 /* if only IB is supported, assign IB */
ab9c17a0 481 else if (dev->caps.supported_type[i] ==
105c320f
JM		 482 MLX4_PORT_TYPE_IB)
483 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 484 else {
105c320f
JM		 485 /* if IB and ETH are supported, we set the port
486 * type according to user selection of port type;
487 * if user selected none, take the FW hint */
488 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 489 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
490 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 491 else
105c320f 492 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 493 }
494 }
8d0fc7b6
YP		 495 /*
496 * Link sensing is allowed on the port if 3 conditions are true:
497 * 1. Both protocols are supported on the port.
498 * 2. Different types are supported on the port
499 * 3. FW declared that it supports link sensing
500 */
27bf91d6 501 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 502 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 503 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 504 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 505
8d0fc7b6
YP		 506 /*
507 * If "default_sense" bit is set, we move the port to "AUTO" mode
508 * and perform sense_port FW command to try and set the correct
509 * port type from beginning
510 */
46c46747 511 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 512 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
513 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
514 mlx4_SENSE_PORT(dev, i, &sensed_port);
515 if (sensed_port != MLX4_PORT_TYPE_NONE)
516 dev->caps.port_type[i] = sensed_port;
517 } else {
518 dev->caps.possible_type[i] = dev->caps.port_type[i];
519 }
520
431df8c7
MB		 521 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
522 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 523 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 524 i, 1 << dev->caps.log_num_macs);
525 }
431df8c7
MB		 526 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
527 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 528 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 529 i, 1 << dev->caps.log_num_vlans);
530 }
531 }
532
ac0a72a3
OG		 533 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
534 (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
535 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
536 mlx4_warn(dev,
537 "Granular QoS per VF not supported with IB/Eth configuration\n");
538 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
539 }
540
47d8417f 541 dev->caps.max_counters = dev_cap->max_counters;
f2a3f6a3 542
93fc9e1b
YP		 543 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
544 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
545 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
546 (1 << dev->caps.log_num_macs) *
547 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 548 dev->caps.num_ports;
549 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 550
551 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
552 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
553 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
554 else
555 dev->caps.dmfs_high_rate_qpn_base =
556 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
557
558 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
559 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
560 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
561 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
562 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
563 } else {
564 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
565 dev->caps.dmfs_high_rate_qpn_base =
566 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
567 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
568 }
569
fc31e256
OG		 570 dev->caps.rl_caps = dev_cap->rl_caps;
571
d57febe1 572 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 573 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 574
575 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
576 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
577 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
578 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
579
e2c76824 580 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 581
b3051320 582 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 583 if (dev_cap->flags &
584 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
585 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
586 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
587 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
588 }
77507aa2
IS		 589
590 if (dev_cap->flags2 &
591 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
592 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
593 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
594 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
595 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
596 }
08ff3235
OG		 597 }
598
f97b4b5d 599 if ((dev->caps.flags &
08ff3235
OG		 600 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
601 mlx4_is_master(dev))
602 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
603
ddae0349 604 if (!mlx4_is_slave(dev)) {
77507aa2 605 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 606 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 607 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
608 MLX4_RESERVE_A0_QP;
3742cc65
IS		 609
610 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
611 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
612 mlx4_warn(dev, "Old device ETS support detected\n");
613 mlx4_warn(dev, "Consider upgrading device FW.\n");
614 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
615 }
616
ddae0349
EE		 617 } else {
618 dev->caps.alloc_res_qp_mask = 0;
619 }
77507aa2 620
78500b8c
MM		 621 mlx4_enable_ignore_fcs(dev);
622
225c7b1f
RD		 623 return 0;
624}
b912b2f8
EP		 625
626static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
627 enum pci_bus_speed *speed,
628 enum pcie_link_width *width)
629{
630 u32 lnkcap1, lnkcap2;
631 int err1, err2;
632
633#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
634
635 *speed = PCI_SPEED_UNKNOWN;
636 *width = PCIE_LNK_WIDTH_UNKNOWN;
637
872bf2fb
YH		 638 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
639 &lnkcap1);
640 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
641 &lnkcap2);
b912b2f8
EP		 642 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
643 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
644 *speed = PCIE_SPEED_8_0GT;
645 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
646 *speed = PCIE_SPEED_5_0GT;
647 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
648 *speed = PCIE_SPEED_2_5GT;
649 }
650 if (!err1) {
651 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
652 if (!lnkcap2) { /* pre-r3.0 */
653 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
654 *speed = PCIE_SPEED_5_0GT;
655 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
656 *speed = PCIE_SPEED_2_5GT;
657 }
658 }
659
660 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
661 return err1 ? err1 :
662 err2 ? err2 : -EINVAL;
663 }
664 return 0;
665}
666
667static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
668{
669 enum pcie_link_width width, width_cap;
670 enum pci_bus_speed speed, speed_cap;
671 int err;
672
673#define PCIE_SPEED_STR(speed) \
674 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
675 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
676 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
677 "Unknown")
678
679 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
680 if (err) {
681 mlx4_warn(dev,
682 "Unable to determine PCIe device BW capabilities\n");
683 return;
684 }
685
872bf2fb 686 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
b912b2f8
EP		 687 if (err || speed == PCI_SPEED_UNKNOWN ||
688 width == PCIE_LNK_WIDTH_UNKNOWN) {
689 mlx4_warn(dev,
690 "Unable to determine PCI device chain minimum BW\n");
691 return;
692 }
693
694 if (width != width_cap || speed != speed_cap)
695 mlx4_warn(dev,
696 "PCIe BW is different than device's capability\n");
697
698 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
699 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
700 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
701 width, width_cap);
702 return;
703}
704
ab9c17a0
JM		 705/*The function checks if there are live vf, return the num of them*/
706static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
707{
708 struct mlx4_priv *priv = mlx4_priv(dev);
709 struct mlx4_slave_state *s_state;
710 int i;
711 int ret = 0;
712
713 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
714 s_state = &priv->mfunc.master.slave_state[i];
715 if (s_state->active && s_state->last_cmd !=
716 MLX4_COMM_CMD_RESET) {
717 mlx4_warn(dev, "%s: slave: %d is still active\n",
718 __func__, i);
719 ret++;
720 }
721 }
722 return ret;
723}
724
396f2feb
JM		 725int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
726{
727 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 728
729 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
730 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 731 return -EINVAL;
732
47605df9 733 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 734 /* tunnel qp */
47605df9 735 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 736 else
47605df9 737 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 738 *qkey = qk;
739 return 0;
740}
741EXPORT_SYMBOL(mlx4_get_parav_qkey);
742
54679e14
JM		 743void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
744{
745 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
746
747 if (!mlx4_is_master(dev))
748 return;
749
750 priv->virt2phys_pkey[slave][port - 1][i] = val;
751}
752EXPORT_SYMBOL(mlx4_sync_pkey_table);
753
afa8fd1d
JM		 754void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
755{
756 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
757
758 if (!mlx4_is_master(dev))
759 return;
760
761 priv->slave_node_guids[slave] = guid;
762}
763EXPORT_SYMBOL(mlx4_put_slave_node_guid);
764
765__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
766{
767 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
768
769 if (!mlx4_is_master(dev))
770 return 0;
771
772 return priv->slave_node_guids[slave];
773}
774EXPORT_SYMBOL(mlx4_get_slave_node_guid);
775
e10903b0 776int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 777{
778 struct mlx4_priv *priv = mlx4_priv(dev);
779 struct mlx4_slave_state *s_slave;
780
781 if (!mlx4_is_master(dev))
782 return 0;
783
784 s_slave = &priv->mfunc.master.slave_state[slave];
785 return !!s_slave->active;
786}
787EXPORT_SYMBOL(mlx4_is_slave_active);
788
10b1c04e
JM		 789void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
790 struct _rule_hw *eth_header)
791{
792 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
793 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
794 struct mlx4_net_trans_rule_hw_eth *eth =
795 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
796 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
797 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
798 next_rule->rsvd == 0;
799
800 if (last_rule)
801 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
802 }
803}
804EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
805
7b8157be
JM		 806static void slave_adjust_steering_mode(struct mlx4_dev *dev,
807 struct mlx4_dev_cap *dev_cap,
808 struct mlx4_init_hca_param *hca_param)
809{
810 dev->caps.steering_mode = hca_param->steering_mode;
811 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
812 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
813 dev->caps.fs_log_max_ucast_qp_range_size =
814 dev_cap->fs_log_max_ucast_qp_range_size;
815 } else
816 dev->caps.num_qp_per_mgm =
817 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
818
819 mlx4_dbg(dev, "Steering mode is: %s\n",
820 mlx4_steering_mode_str(dev->caps.steering_mode));
821}
822
c73c8b1e
EBE		 823static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev)
824{
825 kfree(dev->caps.spec_qps);
826 dev->caps.spec_qps = NULL;
827}
828
829static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev)
830{
831 struct mlx4_func_cap *func_cap = NULL;
832 struct mlx4_caps *caps = &dev->caps;
833 int i, err = 0;
834
835 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
836 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
837
838 if (!func_cap || !caps->spec_qps) {
839 mlx4_err(dev, "Failed to allocate memory for special qps cap\n");
840 err = -ENOMEM;
841 goto err_mem;
842 }
843
844 for (i = 1; i <= caps->num_ports; ++i) {
845 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap);
846 if (err) {
847 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
848 i, err);
849 goto err_mem;
850 }
851 caps->spec_qps[i - 1] = func_cap->spec_qps;
852 caps->port_mask[i] = caps->port_type[i];
853 caps->phys_port_id[i] = func_cap->phys_port_id;
854 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
855 &caps->gid_table_len[i],
856 &caps->pkey_table_len[i]);
857 if (err) {
858 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n",
859 i, err);
860 goto err_mem;
861 }
862 }
863
864err_mem:
865 if (err)
866 mlx4_slave_destroy_special_qp_cap(dev);
867 kfree(func_cap);
868 return err;
869}
870
ab9c17a0
JM		 871static int mlx4_slave_cap(struct mlx4_dev *dev)
872{
873 int err;
874 u32 page_size;
c73c8b1e
EBE		 875 struct mlx4_dev_cap *dev_cap = NULL;
876 struct mlx4_func_cap *func_cap = NULL;
877 struct mlx4_init_hca_param *hca_param = NULL;
878
879 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL);
880 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
881 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
882 if (!hca_param || !func_cap || !dev_cap) {
883 mlx4_err(dev, "Failed to allocate memory for slave_cap\n");
884 err = -ENOMEM;
885 goto free_mem;
886 }
ab9c17a0 887
c73c8b1e 888 err = mlx4_QUERY_HCA(dev, hca_param);
ab9c17a0 889 if (err) {
1a91de28 890 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
c73c8b1e 891 goto free_mem;
ab9c17a0
JM		 892 }
893
483e0132
EP		 894 /* fail if the hca has an unknown global capability
895 * at this time global_caps should be always zeroed
896 */
c73c8b1e 897 if (hca_param->global_caps) {
ab9c17a0 898 mlx4_err(dev, "Unknown hca global capabilities\n");
c73c8b1e
EBE		 899 err = -EINVAL;
900 goto free_mem;
ab9c17a0
JM		 901 }
902
c73c8b1e 903 dev->caps.hca_core_clock = hca_param->hca_core_clock;
ddd8a6c1 904
c73c8b1e
EBE		 905 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
906 err = mlx4_dev_cap(dev, dev_cap);
ab9c17a0 907 if (err) {
1a91de28 908 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
c73c8b1e 909 goto free_mem;
ab9c17a0
JM		 910 }
911
b91cb3eb
JM		 912 err = mlx4_QUERY_FW(dev);
913 if (err)
1a91de28 914 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 915
ab9c17a0
JM		 916 page_size = ~dev->caps.page_size_cap + 1;
917 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
918 if (page_size > PAGE_SIZE) {
1a91de28 919 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0 920 page_size, PAGE_SIZE);
c73c8b1e
EBE		 921 err = -ENODEV;
922 goto free_mem;
ab9c17a0
JM		 923 }
924
85743f1e 925 /* Set uar_page_shift for VF */
c73c8b1e 926 dev->uar_page_shift = hca_param->uar_page_sz + 12;
ab9c17a0 927
85743f1e
HN		 928 /* Make sure the master uar page size is valid */
929 if (dev->uar_page_shift > PAGE_SHIFT) {
930 mlx4_err(dev,
931 "Invalid configuration: uar page size is larger than system page size\n");
c73c8b1e
EBE		 932 err = -ENODEV;
933 goto free_mem;
ab9c17a0
JM		 934 }
935
85743f1e 936 /* Set reserved_uars based on the uar_page_shift */
c73c8b1e 937 mlx4_set_num_reserved_uars(dev, dev_cap);
85743f1e
HN		 938
939 /* Although uar page size in FW differs from system page size,
940 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
941 * still works with assumption that uar page size == system page size
942 */
943 dev->caps.uar_page_size = PAGE_SIZE;
944
c73c8b1e 945 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap);
ab9c17a0 946 if (err) {
1a91de28
JP		 947 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
948 err);
c73c8b1e 949 goto free_mem;
ab9c17a0
JM		 950 }
951
c73c8b1e 952 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
ab9c17a0 953 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3 954 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
c73c8b1e
EBE		 955 func_cap->pf_context_behaviour,
956 PF_CONTEXT_BEHAVIOUR_MASK);
957 err = -EINVAL;
958 goto free_mem;
959 }
960
961 dev->caps.num_ports = func_cap->num_ports;
962 dev->quotas.qp = func_cap->qp_quota;
963 dev->quotas.srq = func_cap->srq_quota;
964 dev->quotas.cq = func_cap->cq_quota;
965 dev->quotas.mpt = func_cap->mpt_quota;
966 dev->quotas.mtt = func_cap->mtt_quota;
967 dev->caps.num_qps = 1 << hca_param->log_num_qps;
968 dev->caps.num_srqs = 1 << hca_param->log_num_srqs;
969 dev->caps.num_cqs = 1 << hca_param->log_num_cqs;
970 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz;
971 dev->caps.num_eqs = func_cap->max_eq;
972 dev->caps.reserved_eqs = func_cap->reserved_eq;
973 dev->caps.reserved_lkey = func_cap->reserved_lkey;
ab9c17a0
JM		 974 dev->caps.num_pds = MLX4_NUM_PDS;
975 dev->caps.num_mgms = 0;
976 dev->caps.num_amgms = 0;
977
ab9c17a0 978 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 979 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
980 dev->caps.num_ports, MLX4_MAX_PORTS);
542deb88
CIK		 981 err = -ENODEV;
982 goto free_mem;
ab9c17a0
JM		 983 }
984
2b3ddf27
JM		 985 mlx4_replace_zero_macs(dev);
986
c73c8b1e
EBE		 987 err = mlx4_slave_special_qp_cap(dev);
988 if (err) {
989 mlx4_err(dev, "Set special QP caps failed. aborting\n");
990 goto free_mem;
6634961c 991 }
6230bb23 992
ab9c17a0
JM		 993 if (dev->caps.uar_page_size * (dev->caps.num_uars -
994 dev->caps.reserved_uars) >
872bf2fb
YH		 995 pci_resource_len(dev->persist->pdev,
996 2)) {
1a91de28 997 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0 998 dev->caps.uar_page_size * dev->caps.num_uars,
872bf2fb
YH		 999 (unsigned long long)
1000 pci_resource_len(dev->persist->pdev, 2));
d49c2197 1001 err = -ENOMEM;
47605df9 1002 goto err_mem;
ab9c17a0
JM		 1003 }
1004
c73c8b1e 1005 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
08ff3235
OG		 1006 dev->caps.eqe_size = 64;
1007 dev->caps.eqe_factor = 1;
1008 } else {
1009 dev->caps.eqe_size = 32;
1010 dev->caps.eqe_factor = 0;
1011 }
1012
c73c8b1e 1013 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
08ff3235 1014 dev->caps.cqe_size = 64;
77507aa2 1015 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1016 } else {
1017 dev->caps.cqe_size = 32;
1018 }
1019
c73c8b1e
EBE		 1020 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
1021 dev->caps.eqe_size = hca_param->eqe_size;
77507aa2
IS		 1022 dev->caps.eqe_factor = 0;
1023 }
1024
c73c8b1e
EBE		 1025 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
1026 dev->caps.cqe_size = hca_param->cqe_size;
77507aa2
IS		 1027 /* User still need to know when CQE > 32B */
1028 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1029 }
1030
f9bd2d7f 1031 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1032 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 1033
be599603
MS		 1034 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
1035 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n");
1036
c73c8b1e 1037 slave_adjust_steering_mode(dev, dev_cap, hca_param);
802f42a8 1038 mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
c73c8b1e 1039 hca_param->rss_ip_frags ? "on" : "off");
7b8157be 1040
c73c8b1e 1041 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
ddae0349
EE		 1042 dev->caps.bf_reg_size)
1043 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1044
c73c8b1e 1045 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
d57febe1
MB		 1046 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
1047
47605df9 1048err_mem:
c73c8b1e
EBE		 1049 if (err)
1050 mlx4_slave_destroy_special_qp_cap(dev);
1051free_mem:
1052 kfree(hca_param);
1053 kfree(func_cap);
1054 kfree(dev_cap);
47605df9 1055 return err;
ab9c17a0 1056}
225c7b1f 1057
b046ffe5
EP		 1058static void mlx4_request_modules(struct mlx4_dev *dev)
1059{
1060 int port;
1061 int has_ib_port = false;
1062 int has_eth_port = false;
1063#define EN_DRV_NAME "mlx4_en"
1064#define IB_DRV_NAME "mlx4_ib"
1065
1066 for (port = 1; port <= dev->caps.num_ports; port++) {
1067 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1068 has_ib_port = true;
1069 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1070 has_eth_port = true;
1071 }
1072
b046ffe5
EP		 1073 if (has_eth_port)
1074 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 1075 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
1076 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 1077}
1078
7ff93f8b
YP		 1079/*
1080 * Change the port configuration of the device.
1081 * Every user of this function must hold the port mutex.
1082 */
27bf91d6
YP		 1083int mlx4_change_port_types(struct mlx4_dev *dev,
1084 enum mlx4_port_type *port_types)
7ff93f8b
YP		 1085{
1086 int err = 0;
1087 int change = 0;
1088 int port;
1089
1090 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 1091 /* Change the port type only if the new type is different
1092 * from the current, and not set to Auto */
3d8f9308 1093 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 1094 change = 1;
7ff93f8b
YP		 1095 }
1096 if (change) {
1097 mlx4_unregister_device(dev);
1098 for (port = 1; port <= dev->caps.num_ports; port++) {
1099 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 1100 dev->caps.port_type[port] = port_types[port - 1];
6634961c 1101 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 1102 if (err) {
1a91de28
JP		 1103 mlx4_err(dev, "Failed to set port %d, aborting\n",
1104 port);
7ff93f8b
YP		 1105 goto out;
1106 }
1107 }
1108 mlx4_set_port_mask(dev);
1109 err = mlx4_register_device(dev);
b046ffe5
EP		 1110 if (err) {
1111 mlx4_err(dev, "Failed to register device\n");
1112 goto out;
1113 }
1114 mlx4_request_modules(dev);
7ff93f8b
YP		 1115 }
1116
1117out:
1118 return err;
1119}
1120
1121static ssize_t show_port_type(struct device *dev,
1122 struct device_attribute *attr,
1123 char *buf)
1124{
1125 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1126 port_attr);
1127 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 1128 char type[8];
1129
1130 sprintf(type, "%s",
1131 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1132 "ib" : "eth");
1133 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1134 sprintf(buf, "auto (%s)\n", type);
1135 else
1136 sprintf(buf, "%s\n", type);
7ff93f8b 1137
27bf91d6 1138 return strlen(buf);
7ff93f8b
YP		 1139}
1140
b2facd95
JP		 1141static int __set_port_type(struct mlx4_port_info *info,
1142 enum mlx4_port_type port_type)
7ff93f8b 1143{
7ff93f8b
YP		 1144 struct mlx4_dev *mdev = info->dev;
1145 struct mlx4_priv *priv = mlx4_priv(mdev);
1146 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 1147 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 1148 int i;
1149 int err = 0;
1150
33a1f8b1
MG		 1151 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1152 mlx4_err(mdev,
1153 "Requested port type for port %d is not supported on this HCA\n",
1154 info->port);
1155 err = -EINVAL;
1156 goto err_sup;
1157 }
1158
27bf91d6 1159 mlx4_stop_sense(mdev);
7ff93f8b 1160 mutex_lock(&priv->port_mutex);
b2facd95
JP		 1161 info->tmp_type = port_type;
1162
27bf91d6
YP		 1163 /* Possible type is always the one that was delivered */
1164 mdev->caps.possible_type[info->port] = info->tmp_type;
1165
1166 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1167 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1168 mdev->caps.possible_type[i+1];
1169 if (types[i] == MLX4_PORT_TYPE_AUTO)
1170 types[i] = mdev->caps.port_type[i+1];
1171 }
7ff93f8b 1172
58a60168
YP		 1173 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1174 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1175 for (i = 1; i <= mdev->caps.num_ports; i++) {
1176 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1177 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1178 err = -EINVAL;
1179 }
1180 }
1181 }
1182 if (err) {
1a91de28 1183 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1184 goto out;
1185 }
1186
1187 mlx4_do_sense_ports(mdev, new_types, types);
1188
1189 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1190 if (err)
1191 goto out;
1192
27bf91d6
YP		 1193 /* We are about to apply the changes after the configuration
1194 * was verified, no need to remember the temporary types
1195 * any more */
1196 for (i = 0; i < mdev->caps.num_ports; i++)
1197 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1198
27bf91d6 1199 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1200
1201out:
27bf91d6 1202 mlx4_start_sense(mdev);
7ff93f8b 1203 mutex_unlock(&priv->port_mutex);
33a1f8b1 1204err_sup:
b2facd95
JP		 1205 return err;
1206}
1207
1208static ssize_t set_port_type(struct device *dev,
1209 struct device_attribute *attr,
1210 const char *buf, size_t count)
1211{
1212 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1213 port_attr);
1214 struct mlx4_dev *mdev = info->dev;
1215 enum mlx4_port_type port_type;
1216 static DEFINE_MUTEX(set_port_type_mutex);
1217 int err;
1218
1219 mutex_lock(&set_port_type_mutex);
1220
1221 if (!strcmp(buf, "ib\n")) {
1222 port_type = MLX4_PORT_TYPE_IB;
1223 } else if (!strcmp(buf, "eth\n")) {
1224 port_type = MLX4_PORT_TYPE_ETH;
1225 } else if (!strcmp(buf, "auto\n")) {
1226 port_type = MLX4_PORT_TYPE_AUTO;
1227 } else {
1228 mlx4_err(mdev, "%s is not supported port type\n", buf);
1229 err = -EINVAL;
1230 goto err_out;
1231 }
1232
1233 err = __set_port_type(info, port_type);
1234
0a984556
AV		 1235err_out:
1236 mutex_unlock(&set_port_type_mutex);
1237
7ff93f8b
YP		 1238 return err ? err : count;
1239}
1240
096335b3
OG		 1241enum ibta_mtu {
1242 IB_MTU_256 = 1,
1243 IB_MTU_512 = 2,
1244 IB_MTU_1024 = 3,
1245 IB_MTU_2048 = 4,
1246 IB_MTU_4096 = 5
1247};
1248
1249static inline int int_to_ibta_mtu(int mtu)
1250{
1251 switch (mtu) {
1252 case 256: return IB_MTU_256;
1253 case 512: return IB_MTU_512;
1254 case 1024: return IB_MTU_1024;
1255 case 2048: return IB_MTU_2048;
1256 case 4096: return IB_MTU_4096;
1257 default: return -1;
1258 }
1259}
1260
1261static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1262{
1263 switch (mtu) {
1264 case IB_MTU_256: return 256;
1265 case IB_MTU_512: return 512;
1266 case IB_MTU_1024: return 1024;
1267 case IB_MTU_2048: return 2048;
1268 case IB_MTU_4096: return 4096;
1269 default: return -1;
1270 }
1271}
1272
1273static ssize_t show_port_ib_mtu(struct device *dev,
1274 struct device_attribute *attr,
1275 char *buf)
1276{
1277 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1278 port_mtu_attr);
1279 struct mlx4_dev *mdev = info->dev;
1280
1281 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1282 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1283
1284 sprintf(buf, "%d\n",
1285 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1286 return strlen(buf);
1287}
1288
1289static ssize_t set_port_ib_mtu(struct device *dev,
1290 struct device_attribute *attr,
1291 const char *buf, size_t count)
1292{
1293 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1294 port_mtu_attr);
1295 struct mlx4_dev *mdev = info->dev;
1296 struct mlx4_priv *priv = mlx4_priv(mdev);
1297 int err, port, mtu, ibta_mtu = -1;
1298
1299 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1300 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1301 return -EINVAL;
1302 }
1303
618fad95
DB		 1304 err = kstrtoint(buf, 0, &mtu);
1305 if (!err)
096335b3
OG		 1306 ibta_mtu = int_to_ibta_mtu(mtu);
1307
618fad95 1308 if (err || ibta_mtu < 0) {
096335b3
OG		 1309 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1310 return -EINVAL;
1311 }
1312
1313 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1314
1315 mlx4_stop_sense(mdev);
1316 mutex_lock(&priv->port_mutex);
1317 mlx4_unregister_device(mdev);
1318 for (port = 1; port <= mdev->caps.num_ports; port++) {
1319 mlx4_CLOSE_PORT(mdev, port);
6634961c 1320 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1321 if (err) {
1a91de28
JP		 1322 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1323 port);
096335b3
OG		 1324 goto err_set_port;
1325 }
1326 }
1327 err = mlx4_register_device(mdev);
1328err_set_port:
1329 mutex_unlock(&priv->port_mutex);
1330 mlx4_start_sense(mdev);
1331 return err ? err : count;
1332}
1333
e57968a1
MS		 1334/* bond for multi-function device */
1335#define MAX_MF_BOND_ALLOWED_SLAVES 63
1336static int mlx4_mf_bond(struct mlx4_dev *dev)
1337{
1338 int err = 0;
00ada910 1339 int nvfs;
e57968a1
MS		 1340 struct mlx4_slaves_pport slaves_port1;
1341 struct mlx4_slaves_pport slaves_port2;
1342 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1343
1344 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1345 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1346 bitmap_and(slaves_port_1_2,
1347 slaves_port1.slaves, slaves_port2.slaves,
1348 dev->persist->num_vfs + 1);
1349
1350 /* only single port vfs are allowed */
1351 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1352 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1353 return -EINVAL;
1354 }
1355
00ada910
MS		 1356 /* number of virtual functions is number of total functions minus one
1357 * physical function for each port.
1358 */
1359 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1360 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1361
e57968a1 1362 /* limit on maximum allowed VFs */
00ada910
MS		 1363 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1364 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1365 nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
e57968a1 1366 return -EINVAL;
00ada910 1367 }
e57968a1
MS		 1368
1369 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1370 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1371 return -EINVAL;
1372 }
1373
1374 err = mlx4_bond_mac_table(dev);
1375 if (err)
1376 return err;
1377 err = mlx4_bond_vlan_table(dev);
1378 if (err)
1379 goto err1;
1380 err = mlx4_bond_fs_rules(dev);
1381 if (err)
1382 goto err2;
1383
1384 return 0;
1385err2:
1386 (void)mlx4_unbond_vlan_table(dev);
1387err1:
1388 (void)mlx4_unbond_mac_table(dev);
1389 return err;
1390}
1391
1392static int mlx4_mf_unbond(struct mlx4_dev *dev)
1393{
1394 int ret, ret1;
1395
1396 ret = mlx4_unbond_fs_rules(dev);
1397 if (ret)
1398 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret);
1399 ret1 = mlx4_unbond_mac_table(dev);
1400 if (ret1) {
1401 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1402 ret = ret1;
1403 }
1404 ret1 = mlx4_unbond_vlan_table(dev);
1405 if (ret1) {
1406 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1407 ret = ret1;
1408 }
1409 return ret;
1410}
1411
53f33ae2
MS		 1412int mlx4_bond(struct mlx4_dev *dev)
1413{
1414 int ret = 0;
1415 struct mlx4_priv *priv = mlx4_priv(dev);
1416
1417 mutex_lock(&priv->bond_mutex);
1418
e57968a1 1419 if (!mlx4_is_bonded(dev)) {
53f33ae2 1420 ret = mlx4_do_bond(dev, true);
e57968a1
MS		 1421 if (ret)
1422 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1423 if (!ret && mlx4_is_master(dev)) {
1424 ret = mlx4_mf_bond(dev);
1425 if (ret) {
1426 mlx4_err(dev, "bond for multifunction failed\n");
1427 mlx4_do_bond(dev, false);
1428 }
1429 }
1430 }
53f33ae2
MS		 1431
1432 mutex_unlock(&priv->bond_mutex);
e57968a1 1433 if (!ret)
53f33ae2 1434 mlx4_dbg(dev, "Device is bonded\n");
e57968a1 1435
53f33ae2
MS		 1436 return ret;
1437}
1438EXPORT_SYMBOL_GPL(mlx4_bond);
1439
1440int mlx4_unbond(struct mlx4_dev *dev)
1441{
1442 int ret = 0;
1443 struct mlx4_priv *priv = mlx4_priv(dev);
1444
1445 mutex_lock(&priv->bond_mutex);
1446
e57968a1
MS		 1447 if (mlx4_is_bonded(dev)) {
1448 int ret2 = 0;
1449
53f33ae2 1450 ret = mlx4_do_bond(dev, false);
e57968a1
MS		 1451 if (ret)
1452 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1453 if (mlx4_is_master(dev))
1454 ret2 = mlx4_mf_unbond(dev);
1455 if (ret2) {
1456 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1457 ret = ret2;
1458 }
1459 }
53f33ae2
MS		 1460
1461 mutex_unlock(&priv->bond_mutex);
e57968a1 1462 if (!ret)
53f33ae2 1463 mlx4_dbg(dev, "Device is unbonded\n");
e57968a1 1464
53f33ae2
MS		 1465 return ret;
1466}
1467EXPORT_SYMBOL_GPL(mlx4_unbond);
1468
1469
1470int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1471{
1472 u8 port1 = v2p->port1;
1473 u8 port2 = v2p->port2;
1474 struct mlx4_priv *priv = mlx4_priv(dev);
1475 int err;
1476
1477 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
423b3aec 1478 return -EOPNOTSUPP;
53f33ae2
MS		 1479
1480 mutex_lock(&priv->bond_mutex);
1481
1482 /* zero means keep current mapping for this port */
1483 if (port1 == 0)
1484 port1 = priv->v2p.port1;
1485 if (port2 == 0)
1486 port2 = priv->v2p.port2;
1487
1488 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1489 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1490 (port1 == 2 && port2 == 1)) {
1491 /* besides boundary checks cross mapping makes
1492 * no sense and therefore not allowed */
1493 err = -EINVAL;
1494 } else if ((port1 == priv->v2p.port1) &&
1495 (port2 == priv->v2p.port2)) {
1496 err = 0;
1497 } else {
1498 err = mlx4_virt2phy_port_map(dev, port1, port2);
1499 if (!err) {
1500 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1501 port1, port2);
1502 priv->v2p.port1 = port1;
1503 priv->v2p.port2 = port2;
1504 } else {
1505 mlx4_err(dev, "Failed to change port mape: %d\n", err);
1506 }
1507 }
1508
1509 mutex_unlock(&priv->bond_mutex);
1510 return err;
1511}
1512EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1513
e8f9b2ed 1514static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1515{
1516 struct mlx4_priv *priv = mlx4_priv(dev);
1517 int err;
1518
1519 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1520 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1521 if (!priv->fw.fw_icm) {
1a91de28 1522 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1523 return -ENOMEM;
1524 }
1525
1526 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1527 if (err) {
1a91de28 1528 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1529 goto err_free;
1530 }
1531
1532 err = mlx4_RUN_FW(dev);
1533 if (err) {
1a91de28 1534 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1535 goto err_unmap_fa;
1536 }
1537
1538 return 0;
1539
1540err_unmap_fa:
1541 mlx4_UNMAP_FA(dev);
1542
1543err_free:
5b0bf5e2 1544 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1545 return err;
1546}
1547
e8f9b2ed
RD		 1548static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1549 int cmpt_entry_sz)
225c7b1f
RD		 1550{
1551 struct mlx4_priv *priv = mlx4_priv(dev);
1552 int err;
ab9c17a0 1553 int num_eqs;
225c7b1f
RD		 1554
1555 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1556 cmpt_base +
1557 ((u64) (MLX4_CMPT_TYPE_QP *
1558 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1559 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1560 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1561 0, 0);
225c7b1f
RD		 1562 if (err)
1563 goto err;
1564
1565 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1566 cmpt_base +
1567 ((u64) (MLX4_CMPT_TYPE_SRQ *
1568 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1569 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1570 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1571 if (err)
1572 goto err_qp;
1573
1574 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1575 cmpt_base +
1576 ((u64) (MLX4_CMPT_TYPE_CQ *
1577 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1578 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1579 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1580 if (err)
1581 goto err_srq;
1582
7ae0e400 1583 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1584 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1585 cmpt_base +
1586 ((u64) (MLX4_CMPT_TYPE_EQ *
1587 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1588 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1589 if (err)
1590 goto err_cq;
1591
1592 return 0;
1593
1594err_cq:
1595 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1596
1597err_srq:
1598 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1599
1600err_qp:
1601 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1602
1603err:
1604 return err;
1605}
1606
3d73c288
RD		 1607static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1608 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1609{
1610 struct mlx4_priv *priv = mlx4_priv(dev);
1611 u64 aux_pages;
ab9c17a0 1612 int num_eqs;
225c7b1f
RD		 1613 int err;
1614
1615 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1616 if (err) {
1a91de28 1617 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1618 return err;
1619 }
1620
1a91de28 1621 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1622 (unsigned long long) icm_size >> 10,
1623 (unsigned long long) aux_pages << 2);
1624
1625 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1626 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1627 if (!priv->fw.aux_icm) {
1a91de28 1628 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1629 return -ENOMEM;
1630 }
1631
1632 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1633 if (err) {
1a91de28 1634 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1635 goto err_free_aux;
1636 }
1637
1638 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1639 if (err) {
1a91de28 1640 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1641 goto err_unmap_aux;
1642 }
1643
ab9c17a0 1644
7ae0e400 1645 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1646 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1647 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1648 num_eqs, num_eqs, 0, 0);
225c7b1f 1649 if (err) {
1a91de28 1650 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1651 goto err_unmap_cmpt;
1652 }
1653
d7bb58fb
JM		 1654 /*
1655 * Reserved MTT entries must be aligned up to a cacheline
1656 * boundary, since the FW will write to them, while the driver
1657 * writes to all other MTT entries. (The variable
1658 * dev->caps.mtt_entry_sz below is really the MTT segment
1659 * size, not the raw entry size)
1660 */
1661 dev->caps.reserved_mtts =
1662 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1663 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1664
225c7b1f
RD		 1665 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1666 init_hca->mtt_base,
1667 dev->caps.mtt_entry_sz,
2b8fb286 1668 dev->caps.num_mtts,
5b0bf5e2 1669 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1670 if (err) {
1a91de28 1671 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1672 goto err_unmap_eq;
1673 }
1674
1675 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1676 init_hca->dmpt_base,
1677 dev_cap->dmpt_entry_sz,
1678 dev->caps.num_mpts,
5b0bf5e2 1679 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1680 if (err) {
1a91de28 1681 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1682 goto err_unmap_mtt;
1683 }
1684
1685 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1686 init_hca->qpc_base,
1687 dev_cap->qpc_entry_sz,
1688 dev->caps.num_qps,
93fc9e1b
YP		 1689 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1690 0, 0);
225c7b1f 1691 if (err) {
1a91de28 1692 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1693 goto err_unmap_dmpt;
1694 }
1695
1696 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1697 init_hca->auxc_base,
1698 dev_cap->aux_entry_sz,
1699 dev->caps.num_qps,
93fc9e1b
YP		 1700 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1701 0, 0);
225c7b1f 1702 if (err) {
1a91de28 1703 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1704 goto err_unmap_qp;
1705 }
1706
1707 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1708 init_hca->altc_base,
1709 dev_cap->altc_entry_sz,
1710 dev->caps.num_qps,
93fc9e1b
YP		 1711 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1712 0, 0);
225c7b1f 1713 if (err) {
1a91de28 1714 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1715 goto err_unmap_auxc;
1716 }
1717
1718 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1719 init_hca->rdmarc_base,
1720 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1721 dev->caps.num_qps,
93fc9e1b
YP		 1722 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1723 0, 0);
225c7b1f
RD		 1724 if (err) {
1725 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1726 goto err_unmap_altc;
1727 }
1728
1729 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1730 init_hca->cqc_base,
1731 dev_cap->cqc_entry_sz,
1732 dev->caps.num_cqs,
5b0bf5e2 1733 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1734 if (err) {
1a91de28 1735 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1736 goto err_unmap_rdmarc;
1737 }
1738
1739 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1740 init_hca->srqc_base,
1741 dev_cap->srq_entry_sz,
1742 dev->caps.num_srqs,
5b0bf5e2 1743 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1744 if (err) {
1a91de28 1745 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1746 goto err_unmap_cq;
1747 }
1748
1749 /*
0ff1fb65
HHZ		 1750 * For flow steering device managed mode it is required to use
1751 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1752 * required, but for simplicity just map the whole multicast
1753 * group table now. The table isn't very big and it's a lot
1754 * easier than trying to track ref counts.
225c7b1f
RD		 1755 */
1756 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1757 init_hca->mc_base,
1758 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1759 dev->caps.num_mgms + dev->caps.num_amgms,
1760 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1761 0, 0);
225c7b1f 1762 if (err) {
1a91de28 1763 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1764 goto err_unmap_srq;
1765 }
1766
1767 return 0;
1768
1769err_unmap_srq:
1770 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1771
1772err_unmap_cq:
1773 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1774
1775err_unmap_rdmarc:
1776 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1777
1778err_unmap_altc:
1779 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1780
1781err_unmap_auxc:
1782 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1783
1784err_unmap_qp:
1785 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1786
1787err_unmap_dmpt:
1788 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1789
1790err_unmap_mtt:
1791 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1792
1793err_unmap_eq:
fa0681d2 1794 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1795
1796err_unmap_cmpt:
1797 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1798 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1799 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1800 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1801
1802err_unmap_aux:
1803 mlx4_UNMAP_ICM_AUX(dev);
1804
1805err_free_aux:
5b0bf5e2 1806 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1807
1808 return err;
1809}
1810
1811static void mlx4_free_icms(struct mlx4_dev *dev)
1812{
1813 struct mlx4_priv *priv = mlx4_priv(dev);
1814
1815 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1816 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1817 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1818 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1819 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1820 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1821 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1822 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1823 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1824 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1825 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1826 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1827 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1828 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1829
1830 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1831 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1832}
1833
ab9c17a0
JM		 1834static void mlx4_slave_exit(struct mlx4_dev *dev)
1835{
1836 struct mlx4_priv *priv = mlx4_priv(dev);
1837
f3d4c89e 1838 mutex_lock(&priv->cmd.slave_cmd_mutex);
0cd93027
YH		 1839 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1840 MLX4_COMM_TIME))
1a91de28 1841 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1842 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1843}
1844
c1b43dca
EC		 1845static int map_bf_area(struct mlx4_dev *dev)
1846{
1847 struct mlx4_priv *priv = mlx4_priv(dev);
1848 resource_size_t bf_start;
1849 resource_size_t bf_len;
1850 int err = 0;
1851
3d747473
JM		 1852 if (!dev->caps.bf_reg_size)
1853 return -ENXIO;
1854
872bf2fb 1855 bf_start = pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0 1856 (dev->caps.num_uars << PAGE_SHIFT);
872bf2fb 1857 bf_len = pci_resource_len(dev->persist->pdev, 2) -
ab9c17a0 1858 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1859 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1860 if (!priv->bf_mapping)
1861 err = -ENOMEM;
1862
1863 return err;
1864}
1865
1866static void unmap_bf_area(struct mlx4_dev *dev)
1867{
1868 if (mlx4_priv(dev)->bf_mapping)
1869 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1870}
1871
a5a1d1c2 1872u64 mlx4_read_clock(struct mlx4_dev *dev)
ec693d47
AV		 1873{
1874 u32 clockhi, clocklo, clockhi1;
a5a1d1c2 1875 u64 cycles;
ec693d47
AV		 1876 int i;
1877 struct mlx4_priv *priv = mlx4_priv(dev);
1878
1879 for (i = 0; i < 10; i++) {
1880 clockhi = swab32(readl(priv->clock_mapping));
1881 clocklo = swab32(readl(priv->clock_mapping + 4));
1882 clockhi1 = swab32(readl(priv->clock_mapping));
1883 if (clockhi == clockhi1)
1884 break;
1885 }
1886
1887 cycles = (u64) clockhi << 32 | (u64) clocklo;
1888
1889 return cycles;
1890}
1891EXPORT_SYMBOL_GPL(mlx4_read_clock);
1892
1893
ddd8a6c1
EE		 1894static int map_internal_clock(struct mlx4_dev *dev)
1895{
1896 struct mlx4_priv *priv = mlx4_priv(dev);
1897
1898 priv->clock_mapping =
872bf2fb
YH		 1899 ioremap(pci_resource_start(dev->persist->pdev,
1900 priv->fw.clock_bar) +
ddd8a6c1
EE		 1901 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1902
1903 if (!priv->clock_mapping)
1904 return -ENOMEM;
1905
1906 return 0;
1907}
1908
52033cfb
MB		 1909int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1910 struct mlx4_clock_params *params)
1911{
1912 struct mlx4_priv *priv = mlx4_priv(dev);
1913
1914 if (mlx4_is_slave(dev))
423b3aec 1915 return -EOPNOTSUPP;
52033cfb
MB		 1916
1917 if (!params)
1918 return -EINVAL;
1919
1920 params->bar = priv->fw.clock_bar;
1921 params->offset = priv->fw.clock_offset;
1922 params->size = MLX4_CLOCK_SIZE;
1923
1924 return 0;
1925}
1926EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1927
ddd8a6c1
EE		 1928static void unmap_internal_clock(struct mlx4_dev *dev)
1929{
1930 struct mlx4_priv *priv = mlx4_priv(dev);
1931
1932 if (priv->clock_mapping)
1933 iounmap(priv->clock_mapping);
1934}
1935
225c7b1f
RD		 1936static void mlx4_close_hca(struct mlx4_dev *dev)
1937{
ddd8a6c1 1938 unmap_internal_clock(dev);
c1b43dca 1939 unmap_bf_area(dev);
ab9c17a0
JM		 1940 if (mlx4_is_slave(dev))
1941 mlx4_slave_exit(dev);
1942 else {
1943 mlx4_CLOSE_HCA(dev, 0);
1944 mlx4_free_icms(dev);
a0eacca9
MB		 1945 }
1946}
1947
1948static void mlx4_close_fw(struct mlx4_dev *dev)
1949{
1950 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1951 mlx4_UNMAP_FA(dev);
1952 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1953 }
1954}
1955
55ad3592
YH		 1956static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1957{
1958#define COMM_CHAN_OFFLINE_OFFSET 0x09
1959
1960 u32 comm_flags;
1961 u32 offline_bit;
1962 unsigned long end;
1963 struct mlx4_priv *priv = mlx4_priv(dev);
1964
1965 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1966 while (time_before(jiffies, end)) {
1967 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1968 MLX4_COMM_CHAN_FLAGS));
1969 offline_bit = (comm_flags &
1970 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1971 if (!offline_bit)
1972 return 0;
4cbe4dac
JM		 1973
1974 /* If device removal has been requested,
1975 * do not continue retrying.
1976 */
1977 if (dev->persist->interface_state &
1978 MLX4_INTERFACE_STATE_NOWAIT)
1979 break;
1980
55ad3592
YH		 1981 /* There are cases as part of AER/Reset flow that PF needs
1982 * around 100 msec to load. We therefore sleep for 100 msec
1983 * to allow other tasks to make use of that CPU during this
1984 * time interval.
1985 */
1986 msleep(100);
1987 }
1988 mlx4_err(dev, "Communication channel is offline.\n");
1989 return -EIO;
1990}
1991
1992static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1993{
1994#define COMM_CHAN_RST_OFFSET 0x1e
1995
1996 struct mlx4_priv *priv = mlx4_priv(dev);
1997 u32 comm_rst;
1998 u32 comm_caps;
1999
2000 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
2001 MLX4_COMM_CHAN_CAPS));
2002 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
2003
2004 if (comm_rst)
2005 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
2006}
2007
ab9c17a0
JM		 2008static int mlx4_init_slave(struct mlx4_dev *dev)
2009{
2010 struct mlx4_priv *priv = mlx4_priv(dev);
2011 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 2012 int ret_from_reset = 0;
2013 u32 slave_read;
2014 u32 cmd_channel_ver;
2015
97989356 2016 if (atomic_read(&pf_loading)) {
1a91de28 2017 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 2018 return -EPROBE_DEFER;
2019 }
2020
f3d4c89e 2021 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 2022 priv->cmd.max_cmds = 1;
55ad3592
YH		 2023 if (mlx4_comm_check_offline(dev)) {
2024 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
2025 goto err_offline;
2026 }
2027
2028 mlx4_reset_vf_support(dev);
ab9c17a0
JM		 2029 mlx4_warn(dev, "Sending reset\n");
2030 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
0cd93027 2031 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
ab9c17a0
JM		 2032 /* if we are in the middle of flr the slave will try
2033 * NUM_OF_RESET_RETRIES times before leaving.*/
2034 if (ret_from_reset) {
2035 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 2036 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 2037 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2038 return -EPROBE_DEFER;
ab9c17a0
JM		 2039 } else
2040 goto err;
2041 }
2042
2043 /* check the driver version - the slave I/F revision
2044 * must match the master's */
2045 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
2046 cmd_channel_ver = mlx4_comm_get_version();
2047
2048 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
2049 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 2050 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 2051 goto err;
2052 }
2053
2054 mlx4_warn(dev, "Sending vhcr0\n");
2055 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
0cd93027 2056 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 2057 goto err;
2058 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
0cd93027 2059 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 2060 goto err;
2061 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
0cd93027 2062 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 2063 goto err;
0cd93027
YH		 2064 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
2065 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 2066 goto err;
f3d4c89e
RD		 2067
2068 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 2069 return 0;
2070
2071err:
0cd93027 2072 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
55ad3592 2073err_offline:
f3d4c89e 2074 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 2075 return -EIO;
225c7b1f
RD		 2076}
2077
6634961c
JM		 2078static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2079{
2080 int i;
2081
2082 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 2083 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2084 dev->caps.gid_table_len[i] =
449fc488 2085 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 2086 else
2087 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 2088 dev->caps.pkey_table_len[i] =
2089 dev->phys_caps.pkey_phys_table_len[i] - 1;
2090 }
2091}
2092
3c439b55
JM		 2093static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2094{
2095 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2096
2097 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2098 i++) {
2099 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2100 break;
2101 }
2102
2103 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2104}
2105
7d077cd3
MB		 2106static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2107{
2108 switch (dmfs_high_steer_mode) {
2109 case MLX4_STEERING_DMFS_A0_DEFAULT:
2110 return "default performance";
2111
2112 case MLX4_STEERING_DMFS_A0_DYNAMIC:
2113 return "dynamic hybrid mode";
2114
2115 case MLX4_STEERING_DMFS_A0_STATIC:
2116 return "performance optimized for limited rule configuration (static)";
2117
2118 case MLX4_STEERING_DMFS_A0_DISABLE:
2119 return "disabled performance optimized steering";
2120
2121 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2122 return "performance optimized steering not supported";
2123
2124 default:
2125 return "Unrecognized mode";
2126 }
2127}
2128
2129#define MLX4_DMFS_A0_STEERING (1UL << 2)
2130
7b8157be
JM		 2131static void choose_steering_mode(struct mlx4_dev *dev,
2132 struct mlx4_dev_cap *dev_cap)
2133{
7d077cd3
MB		 2134 if (mlx4_log_num_mgm_entry_size <= 0) {
2135 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2136 if (dev->caps.dmfs_high_steer_mode ==
2137 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2138 mlx4_err(dev, "DMFS high rate mode not supported\n");
2139 else
2140 dev->caps.dmfs_high_steer_mode =
2141 MLX4_STEERING_DMFS_A0_STATIC;
2142 }
2143 }
2144
2145 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 2146 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 2147 (!mlx4_is_mfunc(dev) ||
872bf2fb
YH		 2148 (dev_cap->fs_max_num_qp_per_entry >=
2149 (dev->persist->num_vfs + 1))) &&
3c439b55
JM		 2150 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2151 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2152 dev->oper_log_mgm_entry_size =
2153 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 2154 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2155 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2156 dev->caps.fs_log_max_ucast_qp_range_size =
2157 dev_cap->fs_log_max_ucast_qp_range_size;
2158 } else {
7d077cd3
MB		 2159 if (dev->caps.dmfs_high_steer_mode !=
2160 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2161 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 2162 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2163 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2164 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2165 else {
2166 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2167
2168 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2169 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 2170 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 2171 }
3c439b55
JM		 2172 dev->oper_log_mgm_entry_size =
2173 mlx4_log_num_mgm_entry_size > 0 ?
2174 mlx4_log_num_mgm_entry_size :
2175 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 2176 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2177 }
1a91de28 2178 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 2179 mlx4_steering_mode_str(dev->caps.steering_mode),
2180 dev->oper_log_mgm_entry_size,
2181 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 2182}
2183
7ffdf726
OG		 2184static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2185 struct mlx4_dev_cap *dev_cap)
2186{
2187 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
5eff6dad 2188 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
7ffdf726
OG		 2189 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2190 else
2191 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2192
2193 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2194 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2195}
2196
7d077cd3
MB		 2197static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2198{
2199 int i;
2200 struct mlx4_port_cap port_cap;
2201
2202 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2203 return -EINVAL;
2204
2205 for (i = 1; i <= dev->caps.num_ports; i++) {
2206 if (mlx4_dev_port(dev, i, &port_cap)) {
2207 mlx4_err(dev,
2208 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2209 } else if ((dev->caps.dmfs_high_steer_mode !=
2210 MLX4_STEERING_DMFS_A0_DEFAULT) &&
2211 (port_cap.dmfs_optimized_state ==
2212 !!(dev->caps.dmfs_high_steer_mode ==
2213 MLX4_STEERING_DMFS_A0_DISABLE))) {
2214 mlx4_err(dev,
2215 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2216 dmfs_high_rate_steering_mode_str(
2217 dev->caps.dmfs_high_steer_mode),
2218 (port_cap.dmfs_optimized_state ?
2219 "enabled" : "disabled"));
2220 }
2221 }
2222
2223 return 0;
2224}
2225
a0eacca9 2226static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 2227{
2d928651 2228 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 2229 int err = 0;
225c7b1f 2230
ab9c17a0
JM		 2231 if (!mlx4_is_slave(dev)) {
2232 err = mlx4_QUERY_FW(dev);
2233 if (err) {
2234 if (err == -EACCES)
1a91de28 2235 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 2236 else
1a91de28 2237 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 2238 return err;
ab9c17a0 2239 }
225c7b1f 2240
ab9c17a0
JM		 2241 err = mlx4_load_fw(dev);
2242 if (err) {
1a91de28 2243 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 2244 return err;
ab9c17a0 2245 }
225c7b1f 2246
ab9c17a0
JM		 2247 mlx4_cfg.log_pg_sz_m = 1;
2248 mlx4_cfg.log_pg_sz = 0;
2249 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2250 if (err)
2251 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 2252 }
2d928651 2253
a0eacca9
MB		 2254 return err;
2255}
2256
2257static int mlx4_init_hca(struct mlx4_dev *dev)
2258{
2259 struct mlx4_priv *priv = mlx4_priv(dev);
2260 struct mlx4_adapter adapter;
2261 struct mlx4_dev_cap dev_cap;
2262 struct mlx4_profile profile;
2263 struct mlx4_init_hca_param init_hca;
2264 u64 icm_size;
2265 struct mlx4_config_dev_params params;
2266 int err;
2267
2268 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2269 err = mlx4_dev_cap(dev, &dev_cap);
2270 if (err) {
1a91de28 2271 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
d0d01250 2272 return err;
ab9c17a0 2273 }
225c7b1f 2274
7b8157be 2275 choose_steering_mode(dev, &dev_cap);
7ffdf726 2276 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 2277
7d077cd3
MB		 2278 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2279 mlx4_is_master(dev))
2280 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2281
8e1a28e8
HHZ		 2282 err = mlx4_get_phys_port_id(dev);
2283 if (err)
2284 mlx4_err(dev, "Fail to get physical port id\n");
2285
6634961c
JM		 2286 if (mlx4_is_master(dev))
2287 mlx4_parav_master_pf_caps(dev);
2288
2599d858
AV		 2289 if (mlx4_low_memory_profile()) {
2290 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2291 profile = low_mem_profile;
2292 } else {
2293 profile = default_profile;
2294 }
0ff1fb65
HHZ		 2295 if (dev->caps.steering_mode ==
2296 MLX4_STEERING_MODE_DEVICE_MANAGED)
2297 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 2298
ab9c17a0
JM		 2299 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2300 &init_hca);
2301 if ((long long) icm_size < 0) {
2302 err = icm_size;
d0d01250 2303 return err;
ab9c17a0 2304 }
225c7b1f 2305
a5bbe892
EC		 2306 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2307
ca3d89a3 2308 if (enable_4k_uar || !dev->persist->num_vfs) {
76e39ccf
EC		 2309 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2310 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
2311 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2312 } else {
2313 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2314 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2315 }
85743f1e 2316
e448834e
SM		 2317 init_hca.mw_enabled = 0;
2318 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2319 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2320 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 2321
ab9c17a0
JM		 2322 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2323 if (err)
d0d01250 2324 return err;
225c7b1f 2325
ab9c17a0
JM		 2326 err = mlx4_INIT_HCA(dev, &init_hca);
2327 if (err) {
1a91de28 2328 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 2329 goto err_free_icm;
2330 }
7ae0e400
MB		 2331
2332 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2333 err = mlx4_query_func(dev, &dev_cap);
2334 if (err < 0) {
2335 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 2336 goto err_close;
7ae0e400
MB		 2337 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2338 dev->caps.num_eqs = dev_cap.max_eqs;
2339 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2340 dev->caps.reserved_uars = dev_cap.reserved_uars;
2341 }
2342 }
2343
ddd8a6c1
EE		 2344 /*
2345 * If TS is supported by FW
2346 * read HCA frequency by QUERY_HCA command
2347 */
2348 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2349 memset(&init_hca, 0, sizeof(init_hca));
2350 err = mlx4_QUERY_HCA(dev, &init_hca);
2351 if (err) {
1a91de28 2352 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 2353 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2354 } else {
2355 dev->caps.hca_core_clock =
2356 init_hca.hca_core_clock;
2357 }
2358
2359 /* In case we got HCA frequency 0 - disable timestamping
2360 * to avoid dividing by zero
2361 */
2362 if (!dev->caps.hca_core_clock) {
2363 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2364 mlx4_err(dev,
1a91de28 2365 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 2366 } else if (map_internal_clock(dev)) {
2367 /*
2368 * Map internal clock,
2369 * in case of failure disable timestamping
2370 */
2371 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 2372 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 2373 }
2374 }
7d077cd3
MB		 2375
2376 if (dev->caps.dmfs_high_steer_mode !=
2377 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2378 if (mlx4_validate_optimized_steering(dev))
2379 mlx4_warn(dev, "Optimized steering validation failed\n");
2380
2381 if (dev->caps.dmfs_high_steer_mode ==
2382 MLX4_STEERING_DMFS_A0_DISABLE) {
2383 dev->caps.dmfs_high_rate_qpn_base =
2384 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2385 dev->caps.dmfs_high_rate_qpn_range =
2386 MLX4_A0_STEERING_TABLE_SIZE;
2387 }
2388
4931c6ef
SM		 2389 mlx4_info(dev, "DMFS high rate steer mode is: %s\n",
2390 dmfs_high_rate_steering_mode_str(
7d077cd3
MB		 2391 dev->caps.dmfs_high_steer_mode));
2392 }
ab9c17a0
JM		 2393 } else {
2394 err = mlx4_init_slave(dev);
2395 if (err) {
5efe5355
JM		 2396 if (err != -EPROBE_DEFER)
2397 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 2398 return err;
ab9c17a0 2399 }
225c7b1f 2400
ab9c17a0
JM		 2401 err = mlx4_slave_cap(dev);
2402 if (err) {
2403 mlx4_err(dev, "Failed to obtain slave caps\n");
2404 goto err_close;
2405 }
225c7b1f
RD		 2406 }
2407
ab9c17a0
JM		 2408 if (map_bf_area(dev))
2409 mlx4_dbg(dev, "Failed to map blue flame area\n");
2410
2411 /*Only the master set the ports, all the rest got it from it.*/
2412 if (!mlx4_is_slave(dev))
2413 mlx4_set_port_mask(dev);
2414
225c7b1f
RD		 2415 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2416 if (err) {
1a91de28 2417 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 2418 goto unmap_bf;
225c7b1f
RD		 2419 }
2420
f8c6455b
SM		 2421 /* Query CONFIG_DEV parameters */
2422 err = mlx4_config_dev_retrieval(dev, &params);
423b3aec 2423 if (err && err != -EOPNOTSUPP) {
f8c6455b
SM		 2424 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2425 } else if (!err) {
2426 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2427 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2428 }
225c7b1f 2429 priv->eq_table.inta_pin = adapter.inta_pin;
31975e27 2430 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id));
225c7b1f
RD		 2431
2432 return 0;
2433
bef772eb 2434unmap_bf:
ddd8a6c1 2435 unmap_internal_clock(dev);
bef772eb
AY		 2436 unmap_bf_area(dev);
2437
c73c8b1e
EBE		 2438 if (mlx4_is_slave(dev))
2439 mlx4_slave_destroy_special_qp_cap(dev);
b38f2879 2440
225c7b1f 2441err_close:
41929ed2
DB		 2442 if (mlx4_is_slave(dev))
2443 mlx4_slave_exit(dev);
2444 else
2445 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2446
2447err_free_icm:
ab9c17a0
JM		 2448 if (!mlx4_is_slave(dev))
2449 mlx4_free_icms(dev);
225c7b1f 2450
225c7b1f
RD		 2451 return err;
2452}
2453
f2a3f6a3
OG		 2454static int mlx4_init_counters_table(struct mlx4_dev *dev)
2455{
2456 struct mlx4_priv *priv = mlx4_priv(dev);
47d8417f 2457 int nent_pow2;
f2a3f6a3
OG		 2458
2459 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2460 return -ENOENT;
2461
2632d18d
EBE		 2462 if (!dev->caps.max_counters)
2463 return -ENOSPC;
2464
47d8417f
EBE		 2465 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2466 /* reserve last counter index for sink counter */
2467 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2468 nent_pow2 - 1, 0,
2469 nent_pow2 - dev->caps.max_counters + 1);
f2a3f6a3
OG		 2470}
2471
2472static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2473{
efa6bc91
EBE		 2474 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2475 return;
2476
2632d18d
EBE		 2477 if (!dev->caps.max_counters)
2478 return;
2479
f2a3f6a3
OG		 2480 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2481}
2482
6de5f7f6
EBE		 2483static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2484{
2485 struct mlx4_priv *priv = mlx4_priv(dev);
2486 int port;
2487
2488 for (port = 0; port < dev->caps.num_ports; port++)
2489 if (priv->def_counter[port] != -1)
2490 mlx4_counter_free(dev, priv->def_counter[port]);
2491}
2492
2493static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2494{
2495 struct mlx4_priv *priv = mlx4_priv(dev);
2496 int port, err = 0;
2497 u32 idx;
2498
2499 for (port = 0; port < dev->caps.num_ports; port++)
2500 priv->def_counter[port] = -1;
2501
2502 for (port = 0; port < dev->caps.num_ports; port++) {
f3301870 2503 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER);
6de5f7f6
EBE		 2504
2505 if (!err || err == -ENOSPC) {
2506 priv->def_counter[port] = idx;
2507 } else if (err == -ENOENT) {
2508 err = 0;
2509 continue;
178d23e3
OG		 2510 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2511 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2512 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2513 MLX4_SINK_COUNTER_INDEX(dev));
2514 err = 0;
6de5f7f6
EBE		 2515 } else {
2516 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2517 __func__, port + 1, err);
2518 mlx4_cleanup_default_counters(dev);
2519 return err;
2520 }
2521
2522 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2523 __func__, priv->def_counter[port], port + 1);
2524 }
2525
2526 return err;
2527}
2528
ba062d52 2529int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2530{
2531 struct mlx4_priv *priv = mlx4_priv(dev);
2532
2533 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2534 return -ENOENT;
2535
2536 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
6de5f7f6
EBE		 2537 if (*idx == -1) {
2538 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2539 return -ENOSPC;
2540 }
f2a3f6a3
OG		 2541
2542 return 0;
2543}
ba062d52 2544
f3301870 2545int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage)
ba062d52 2546{
f3301870 2547 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30);
ba062d52
JM		 2548 u64 out_param;
2549 int err;
2550
2551 if (mlx4_is_mfunc(dev)) {
f3301870 2552 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier,
ba062d52
JM		 2553 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2554 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2555 if (!err)
2556 *idx = get_param_l(&out_param);
2557
2558 return err;
2559 }
2560 return __mlx4_counter_alloc(dev, idx);
2561}
f2a3f6a3
OG		 2562EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2563
b72ca7e9
EBE		 2564static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2565 u8 counter_index)
2566{
2567 struct mlx4_cmd_mailbox *if_stat_mailbox;
2568 int err;
2569 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2570
2571 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2572 if (IS_ERR(if_stat_mailbox))
2573 return PTR_ERR(if_stat_mailbox);
2574
2575 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2576 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2577 MLX4_CMD_NATIVE);
2578
2579 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2580 return err;
2581}
2582
ba062d52 2583void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2584{
efa6bc91
EBE		 2585 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2586 return;
2587
6de5f7f6
EBE		 2588 if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2589 return;
2590
b72ca7e9
EBE		 2591 __mlx4_clear_if_stat(dev, idx);
2592
7c6d74d2 2593 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2594 return;
2595}
ba062d52
JM		 2596
2597void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2598{
e7dbeba8 2599 u64 in_param = 0;
ba062d52
JM		 2600
2601 if (mlx4_is_mfunc(dev)) {
2602 set_param_l(&in_param, idx);
2603 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2604 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2605 MLX4_CMD_WRAPPED);
2606 return;
2607 }
2608 __mlx4_counter_free(dev, idx);
2609}
f2a3f6a3
OG		 2610EXPORT_SYMBOL_GPL(mlx4_counter_free);
2611
6de5f7f6
EBE		 2612int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2613{
2614 struct mlx4_priv *priv = mlx4_priv(dev);
2615
2616 return priv->def_counter[port - 1];
2617}
2618EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2619
773af94e
YH		 2620void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2621{
2622 struct mlx4_priv *priv = mlx4_priv(dev);
2623
2624 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2625}
2626EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2627
2628__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2629{
2630 struct mlx4_priv *priv = mlx4_priv(dev);
2631
2632 return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2633}
2634EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2635
fb517a4f
YH		 2636void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2637{
2638 struct mlx4_priv *priv = mlx4_priv(dev);
2639 __be64 guid;
2640
2641 /* hw GUID */
2642 if (entry == 0)
2643 return;
2644
2645 get_random_bytes((char *)&guid, sizeof(guid));
2646 guid &= ~(cpu_to_be64(1ULL << 56));
2647 guid |= cpu_to_be64(1ULL << 57);
2648 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2649}
2650
3d73c288 2651static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2652{
2653 struct mlx4_priv *priv = mlx4_priv(dev);
2654 int err;
7ff93f8b 2655 int port;
9a5aa622 2656 __be32 ib_port_default_caps;
225c7b1f 2657
225c7b1f
RD		 2658 err = mlx4_init_uar_table(dev);
2659 if (err) {
1a91de28 2660 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
5d4de16c 2661 return err;
225c7b1f
RD		 2662 }
2663
2664 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2665 if (err) {
1a91de28 2666 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2667 goto err_uar_table_free;
2668 }
2669
4979d18f 2670 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2671 if (!priv->kar) {
1a91de28 2672 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2673 err = -ENOMEM;
2674 goto err_uar_free;
2675 }
2676
2677 err = mlx4_init_pd_table(dev);
2678 if (err) {
1a91de28 2679 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2680 goto err_kar_unmap;
2681 }
2682
012a8ff5
SH		 2683 err = mlx4_init_xrcd_table(dev);
2684 if (err) {
1a91de28 2685 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2686 goto err_pd_table_free;
2687 }
2688
225c7b1f
RD		 2689 err = mlx4_init_mr_table(dev);
2690 if (err) {
1a91de28 2691 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2692 goto err_xrcd_table_free;
225c7b1f
RD		 2693 }
2694
fe6f700d
YP		 2695 if (!mlx4_is_slave(dev)) {
2696 err = mlx4_init_mcg_table(dev);
2697 if (err) {
1a91de28 2698 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2699 goto err_mr_table_free;
2700 }
114840c3
JM		 2701 err = mlx4_config_mad_demux(dev);
2702 if (err) {
2703 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2704 goto err_mcg_table_free;
2705 }
fe6f700d
YP		 2706 }
2707
225c7b1f
RD		 2708 err = mlx4_init_eq_table(dev);
2709 if (err) {
1a91de28 2710 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2711 goto err_mcg_table_free;
225c7b1f
RD		 2712 }
2713
2714 err = mlx4_cmd_use_events(dev);
2715 if (err) {
1a91de28 2716 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2717 goto err_eq_table_free;
2718 }
2719
2720 err = mlx4_NOP(dev);
2721 if (err) {
08fb1055 2722 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2723 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
c66fa19c 2724 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
1a91de28 2725 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2726 } else {
1a91de28 2727 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
c66fa19c 2728 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 2729 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2730 }
225c7b1f
RD		 2731
2732 goto err_cmd_poll;
2733 }
2734
2735 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2736
2737 err = mlx4_init_cq_table(dev);
2738 if (err) {
1a91de28 2739 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2740 goto err_cmd_poll;
2741 }
2742
2743 err = mlx4_init_srq_table(dev);
2744 if (err) {
1a91de28 2745 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2746 goto err_cq_table_free;
2747 }
2748
2749 err = mlx4_init_qp_table(dev);
2750 if (err) {
1a91de28 2751 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2752 goto err_srq_table_free;
2753 }
2754
2632d18d
EBE		 2755 if (!mlx4_is_slave(dev)) {
2756 err = mlx4_init_counters_table(dev);
2757 if (err && err != -ENOENT) {
2758 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2759 goto err_qp_table_free;
2760 }
f2a3f6a3
OG		 2761 }
2762
6de5f7f6
EBE		 2763 err = mlx4_allocate_default_counters(dev);
2764 if (err) {
2765 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2766 goto err_counters_table_free;
f2a3f6a3
OG		 2767 }
2768
ab9c17a0
JM		 2769 if (!mlx4_is_slave(dev)) {
2770 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2771 ib_port_default_caps = 0;
2772 err = mlx4_get_port_ib_caps(dev, port,
2773 &ib_port_default_caps);
2774 if (err)
1a91de28
JP		 2775 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2776 port, err);
ab9c17a0
JM		 2777 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2778
2aca1172
JM		 2779 /* initialize per-slave default ib port capabilities */
2780 if (mlx4_is_master(dev)) {
2781 int i;
2782 for (i = 0; i < dev->num_slaves; i++) {
2783 if (i == mlx4_master_func_num(dev))
2784 continue;
2785 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2786 ib_port_default_caps;
2aca1172
JM		 2787 }
2788 }
2789
096335b3
OG		 2790 if (mlx4_is_mfunc(dev))
2791 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2792 else
2793 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2794
6634961c
JM		 2795 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2796 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2797 if (err) {
2798 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2799 port);
6de5f7f6 2800 goto err_default_countes_free;
ab9c17a0 2801 }
7ff93f8b
YP		 2802 }
2803 }
2804
225c7b1f
RD		 2805 return 0;
2806
6de5f7f6
EBE		 2807err_default_countes_free:
2808 mlx4_cleanup_default_counters(dev);
2809
f2a3f6a3 2810err_counters_table_free:
2632d18d
EBE		 2811 if (!mlx4_is_slave(dev))
2812 mlx4_cleanup_counters_table(dev);
f2a3f6a3 2813
225c7b1f
RD		 2814err_qp_table_free:
2815 mlx4_cleanup_qp_table(dev);
2816
2817err_srq_table_free:
2818 mlx4_cleanup_srq_table(dev);
2819
2820err_cq_table_free:
2821 mlx4_cleanup_cq_table(dev);
2822
2823err_cmd_poll:
2824 mlx4_cmd_use_polling(dev);
2825
2826err_eq_table_free:
2827 mlx4_cleanup_eq_table(dev);
2828
fe6f700d
YP		 2829err_mcg_table_free:
2830 if (!mlx4_is_slave(dev))
2831 mlx4_cleanup_mcg_table(dev);
2832
ee49bd93 2833err_mr_table_free:
225c7b1f
RD		 2834 mlx4_cleanup_mr_table(dev);
2835
012a8ff5
SH		 2836err_xrcd_table_free:
2837 mlx4_cleanup_xrcd_table(dev);
2838
225c7b1f
RD		 2839err_pd_table_free:
2840 mlx4_cleanup_pd_table(dev);
2841
2842err_kar_unmap:
2843 iounmap(priv->kar);
2844
2845err_uar_free:
2846 mlx4_uar_free(dev, &priv->driver_uar);
2847
2848err_uar_table_free:
2849 mlx4_cleanup_uar_table(dev);
2850 return err;
2851}
2852
de161803
IS		 2853static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2854{
2855 int requested_cpu = 0;
2856 struct mlx4_priv *priv = mlx4_priv(dev);
2857 struct mlx4_eq *eq;
2858 int off = 0;
2859 int i;
2860
2861 if (eqn > dev->caps.num_comp_vectors)
2862 return -EINVAL;
2863
2864 for (i = 1; i < port; i++)
2865 off += mlx4_get_eqs_per_port(dev, i);
2866
2867 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2868
2869 /* Meaning EQs are shared, and this call comes from the second port */
2870 if (requested_cpu < 0)
2871 return 0;
2872
2873 eq = &priv->eq_table.eq[eqn];
2874
2875 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2876 return -ENOMEM;
2877
2878 cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2879
2880 return 0;
2881}
2882
e8f9b2ed 2883static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2884{
2885 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2886 struct msix_entry *entries;
225c7b1f 2887 int i;
c66fa19c 2888 int port = 0;
225c7b1f
RD		 2889
2890 if (msi_x) {
4762010f 2891 int nreq = min3(dev->caps.num_ports *
2892 (int)num_online_cpus() + 1,
2893 dev->caps.num_eqs - dev->caps.reserved_eqs,
2894 MAX_MSIX);
ab9c17a0 2895
31975e27 2896 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
b8dd786f
YP		 2897 if (!entries)
2898 goto no_msi;
2899
2900 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2901 entries[i].entry = i;
2902
872bf2fb
YH		 2903 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2904 nreq);
66e2f9c1 2905
c66fa19c 2906 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
5bf0da7d 2907 kfree(entries);
225c7b1f 2908 goto no_msi;
0b7ca5a9 2909 }
c66fa19c
MB		 2910 /* 1 is reserved for events (asyncrounous EQ) */
2911 dev->caps.num_comp_vectors = nreq - 1;
2912
2913 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2914 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2915 dev->caps.num_ports);
2916
2917 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2918 if (i == MLX4_EQ_ASYNC)
2919 continue;
2920
2921 priv->eq_table.eq[i].irq =
2922 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2923
85121d6e 2924 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
c66fa19c
MB		 2925 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2926 dev->caps.num_ports);
de161803
IS		 2927 /* We don't set affinity hint when there
2928 * aren't enough EQs
2929 */
c66fa19c
MB		 2930 } else {
2931 set_bit(port,
2932 priv->eq_table.eq[i].actv_ports.ports);
de161803
IS		 2933 if (mlx4_init_affinity_hint(dev, port + 1, i))
2934 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2935 i);
c66fa19c
MB		 2936 }
2937 /* We divide the Eqs evenly between the two ports.
2938 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2939 * refers to the number of Eqs per port
2940 * (i.e eqs_per_port). Theoretically, we would like to
2941 * write something like (i + 1) % eqs_per_port == 0.
2942 * However, since there's an asynchronous Eq, we have
2943 * to skip over it by comparing this condition to
2944 * !!((i + 1) > MLX4_EQ_ASYNC).
2945 */
2946 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2947 ((i + 1) %
2948 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2949 !!((i + 1) > MLX4_EQ_ASYNC))
2950 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2951 * everything is shared anyway.
2952 */
2953 port++;
2954 }
225c7b1f
RD		 2955
2956 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2957
2958 kfree(entries);
225c7b1f
RD		 2959 return;
2960 }
2961
2962no_msi:
b8dd786f
YP		 2963 dev->caps.num_comp_vectors = 1;
2964
c66fa19c
MB		 2965 BUG_ON(MLX4_EQ_ASYNC >= 2);
2966 for (i = 0; i < 2; ++i) {
872bf2fb 2967 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
c66fa19c
MB		 2968 if (i != MLX4_EQ_ASYNC) {
2969 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2970 dev->caps.num_ports);
2971 }
2972 }
225c7b1f
RD		 2973}
2974
7ff93f8b 2975static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8 2976{
09d4d087 2977 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2a2336f8 2978 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
09d4d087
JP		 2979 int err;
2980
2981 err = devlink_port_register(devlink, &info->devlink_port, port);
2982 if (err)
2983 return err;
2a2336f8
YP		 2984
2985 info->dev = dev;
2986 info->port = port;
ab9c17a0 2987 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2988 mlx4_init_mac_table(dev, &info->mac_table);
2989 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2990 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2991 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2992 }
7ff93f8b
YP		 2993
2994 sprintf(info->dev_name, "mlx4_port%d", port);
2995 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2996 if (mlx4_is_mfunc(dev))
2997 info->port_attr.attr.mode = S_IRUGO;
2998 else {
2999 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
3000 info->port_attr.store = set_port_type;
3001 }
7ff93f8b 3002 info->port_attr.show = show_port_type;
3691c964 3003 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b 3004
872bf2fb 3005 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
7ff93f8b
YP		 3006 if (err) {
3007 mlx4_err(dev, "Failed to create file for port %d\n", port);
09d4d087 3008 devlink_port_unregister(&info->devlink_port);
7ff93f8b
YP		 3009 info->port = -1;
3010 }
3011
096335b3
OG		 3012 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
3013 info->port_mtu_attr.attr.name = info->dev_mtu_name;
3014 if (mlx4_is_mfunc(dev))
3015 info->port_mtu_attr.attr.mode = S_IRUGO;
3016 else {
3017 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
3018 info->port_mtu_attr.store = set_port_ib_mtu;
3019 }
3020 info->port_mtu_attr.show = show_port_ib_mtu;
3021 sysfs_attr_init(&info->port_mtu_attr.attr);
3022
872bf2fb
YH		 3023 err = device_create_file(&dev->persist->pdev->dev,
3024 &info->port_mtu_attr);
096335b3
OG		 3025 if (err) {
3026 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
872bf2fb
YH		 3027 device_remove_file(&info->dev->persist->pdev->dev,
3028 &info->port_attr);
fba12966 3029 devlink_port_unregister(&info->devlink_port);
096335b3
OG		 3030 info->port = -1;
3031 }
3032
7ff93f8b
YP		 3033 return err;
3034}
3035
3036static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
3037{
3038 if (info->port < 0)
3039 return;
3040
872bf2fb
YH		 3041 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
3042 device_remove_file(&info->dev->persist->pdev->dev,
3043 &info->port_mtu_attr);
fba12966
KH		 3044 devlink_port_unregister(&info->devlink_port);
3045
c66fa19c
MB		 3046#ifdef CONFIG_RFS_ACCEL
3047 free_irq_cpu_rmap(info->rmap);
3048 info->rmap = NULL;
3049#endif
2a2336f8
YP		 3050}
3051
b12d93d6
YP		 3052static int mlx4_init_steering(struct mlx4_dev *dev)
3053{
3054 struct mlx4_priv *priv = mlx4_priv(dev);
3055 int num_entries = dev->caps.num_ports;
3056 int i, j;
3057
3058 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
3059 if (!priv->steer)
3060 return -ENOMEM;
3061
45b51365 3062 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 3063 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3064 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3065 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3066 }
b12d93d6
YP		 3067 return 0;
3068}
3069
3070static void mlx4_clear_steering(struct mlx4_dev *dev)
3071{
3072 struct mlx4_priv *priv = mlx4_priv(dev);
3073 struct mlx4_steer_index *entry, *tmp_entry;
3074 struct mlx4_promisc_qp *pqp, *tmp_pqp;
3075 int num_entries = dev->caps.num_ports;
3076 int i, j;
3077
3078 for (i = 0; i < num_entries; i++) {
3079 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3080 list_for_each_entry_safe(pqp, tmp_pqp,
3081 &priv->steer[i].promisc_qps[j],
3082 list) {
3083 list_del(&pqp->list);
3084 kfree(pqp);
3085 }
3086 list_for_each_entry_safe(entry, tmp_entry,
3087 &priv->steer[i].steer_entries[j],
3088 list) {
3089 list_del(&entry->list);
3090 list_for_each_entry_safe(pqp, tmp_pqp,
3091 &entry->duplicates,
3092 list) {
3093 list_del(&pqp->list);
3094 kfree(pqp);
3095 }
3096 kfree(entry);
3097 }
3098 }
3099 }
3100 kfree(priv->steer);
3101}
3102
ab9c17a0
JM		 3103static int extended_func_num(struct pci_dev *pdev)
3104{
3105 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3106}
3107
3108#define MLX4_OWNER_BASE 0x8069c
3109#define MLX4_OWNER_SIZE 4
3110
3111static int mlx4_get_ownership(struct mlx4_dev *dev)
3112{
3113 void __iomem *owner;
3114 u32 ret;
3115
872bf2fb 3116 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3117 return -EIO;
3118
872bf2fb
YH		 3119 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3120 MLX4_OWNER_BASE,
ab9c17a0
JM		 3121 MLX4_OWNER_SIZE);
3122 if (!owner) {
3123 mlx4_err(dev, "Failed to obtain ownership bit\n");
3124 return -ENOMEM;
3125 }
3126
3127 ret = readl(owner);
3128 iounmap(owner);
3129 return (int) !!ret;
3130}
3131
3132static void mlx4_free_ownership(struct mlx4_dev *dev)
3133{
3134 void __iomem *owner;
3135
872bf2fb 3136 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3137 return;
3138
872bf2fb
YH		 3139 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3140 MLX4_OWNER_BASE,
ab9c17a0
JM		 3141 MLX4_OWNER_SIZE);
3142 if (!owner) {
3143 mlx4_err(dev, "Failed to obtain ownership bit\n");
3144 return;
3145 }
3146 writel(0, owner);
3147 msleep(1000);
3148 iounmap(owner);
3149}
3150
a0eacca9
MB		 3151#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3152 !!((flags) & MLX4_FLAG_MASTER))
3153
3154static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
55ad3592 3155 u8 total_vfs, int existing_vfs, int reset_flow)
a0eacca9
MB		 3156{
3157 u64 dev_flags = dev->flags;
da315679 3158 int err = 0;
0beb44b0
CS		 3159 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3160 MLX4_MAX_NUM_VF);
a0eacca9 3161
55ad3592
YH		 3162 if (reset_flow) {
3163 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3164 GFP_KERNEL);
3165 if (!dev->dev_vfs)
3166 goto free_mem;
3167 return dev_flags;
3168 }
3169
da315679
MB		 3170 atomic_inc(&pf_loading);
3171 if (dev->flags & MLX4_FLAG_SRIOV) {
3172 if (existing_vfs != total_vfs) {
3173 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3174 existing_vfs, total_vfs);
3175 total_vfs = existing_vfs;
3176 }
3177 }
3178
3179 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 3180 if (NULL == dev->dev_vfs) {
3181 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3182 goto disable_sriov;
da315679
MB		 3183 }
3184
3185 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
0beb44b0
CS		 3186 if (total_vfs > fw_enabled_sriov_vfs) {
3187 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3188 total_vfs, fw_enabled_sriov_vfs);
3189 err = -ENOMEM;
3190 goto disable_sriov;
3191 }
da315679
MB		 3192 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3193 err = pci_enable_sriov(pdev, total_vfs);
3194 }
3195 if (err) {
3196 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3197 err);
3198 goto disable_sriov;
3199 } else {
3200 mlx4_warn(dev, "Running in master mode\n");
3201 dev_flags |= MLX4_FLAG_SRIOV |
3202 MLX4_FLAG_MASTER;
3203 dev_flags &= ~MLX4_FLAG_SLAVE;
872bf2fb 3204 dev->persist->num_vfs = total_vfs;
a0eacca9
MB		 3205 }
3206 return dev_flags;
3207
3208disable_sriov:
da315679 3209 atomic_dec(&pf_loading);
55ad3592 3210free_mem:
872bf2fb 3211 dev->persist->num_vfs = 0;
a0eacca9 3212 kfree(dev->dev_vfs);
5114a04e 3213 dev->dev_vfs = NULL;
a0eacca9
MB		 3214 return dev_flags & ~MLX4_FLAG_MASTER;
3215}
3216
de966c59
MB		 3217enum {
3218 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3219};
3220
3221static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3222 int *nvfs)
3223{
3224 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3225 /* Checking for 64 VFs as a limitation of CX2 */
3226 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3227 requested_vfs >= 64) {
3228 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3229 requested_vfs);
3230 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3231 }
3232 return 0;
3233}
3234
4bfd2e6e
DJ		 3235static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3236{
3237 struct pci_dev *pdev = dev->persist->pdev;
3238 int err = 0;
3239
3240 mutex_lock(&dev->persist->pci_status_mutex);
3241 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3242 err = pci_enable_device(pdev);
3243 if (!err)
3244 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3245 }
3246 mutex_unlock(&dev->persist->pci_status_mutex);
3247
3248 return err;
3249}
3250
3251static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3252{
3253 struct pci_dev *pdev = dev->persist->pdev;
3254
3255 mutex_lock(&dev->persist->pci_status_mutex);
3256 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3257 pci_disable_device(pdev);
3258 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3259 }
3260 mutex_unlock(&dev->persist->pci_status_mutex);
3261}
3262
e1c00e10 3263static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
55ad3592
YH		 3264 int total_vfs, int *nvfs, struct mlx4_priv *priv,
3265 int reset_flow)
225c7b1f 3266{
225c7b1f 3267 struct mlx4_dev *dev;
e1c00e10 3268 unsigned sum = 0;
225c7b1f 3269 int err;
2a2336f8 3270 int port;
e1c00e10 3271 int i;
7ae0e400 3272 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 3273 int existing_vfs = 0;
225c7b1f 3274
e1c00e10 3275 dev = &priv->dev;
225c7b1f 3276
b581401e
RD		 3277 INIT_LIST_HEAD(&priv->ctx_list);
3278 spin_lock_init(&priv->ctx_lock);
225c7b1f 3279
7ff93f8b 3280 mutex_init(&priv->port_mutex);
53f33ae2 3281 mutex_init(&priv->bond_mutex);
7ff93f8b 3282
6296883c
YP		 3283 INIT_LIST_HEAD(&priv->pgdir_list);
3284 mutex_init(&priv->pgdir_mutex);
0c5ddb51 3285 spin_lock_init(&priv->cmd.context_lock);
6296883c 3286
c1b43dca
EC		 3287 INIT_LIST_HEAD(&priv->bf_list);
3288 mutex_init(&priv->bf_mutex);
3289
aca7a3ac 3290 dev->rev_id = pdev->revision;
6e7136ed 3291 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 3292
ab9c17a0 3293 /* Detect if this device is a virtual function */
839f1243 3294 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 3295 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3296 dev->flags |= MLX4_FLAG_SLAVE;
3297 } else {
3298 /* We reset the device and enable SRIOV only for physical
3299 * devices. Try to claim ownership on the device;
3300 * if already taken, skip -- do not allow multiple PFs */
3301 err = mlx4_get_ownership(dev);
3302 if (err) {
3303 if (err < 0)
e1c00e10 3304 return err;
ab9c17a0 3305 else {
1a91de28 3306 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 3307 return -EINVAL;
ab9c17a0
JM		 3308 }
3309 }
aca7a3ac 3310
fe6f700d
YP		 3311 atomic_set(&priv->opreq_count, 0);
3312 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3313
ab9c17a0
JM		 3314 /*
3315 * Now reset the HCA before we touch the PCI capabilities or
3316 * attempt a firmware command, since a boot ROM may have left
3317 * the HCA in an undefined state.
3318 */
3319 err = mlx4_reset(dev);
3320 if (err) {
1a91de28 3321 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 3322 goto err_sriov;
ab9c17a0 3323 }
7ae0e400
MB		 3324
3325 if (total_vfs) {
7ae0e400 3326 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 3327 existing_vfs = pci_num_vf(pdev);
3328 if (existing_vfs)
3329 dev->flags |= MLX4_FLAG_SRIOV;
872bf2fb 3330 dev->persist->num_vfs = total_vfs;
7ae0e400 3331 }
225c7b1f
RD		 3332 }
3333
f6bc11e4
YH		 3334 /* on load remove any previous indication of internal error,
3335 * device is up.
3336 */
3337 dev->persist->state = MLX4_DEVICE_STATE_UP;
3338
ab9c17a0 3339slave_start:
521130d1
EE		 3340 err = mlx4_cmd_init(dev);
3341 if (err) {
1a91de28 3342 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 3343 goto err_sriov;
3344 }
3345
3346 /* In slave functions, the communication channel must be initialized
3347 * before posting commands. Also, init num_slaves before calling
3348 * mlx4_init_hca */
3349 if (mlx4_is_mfunc(dev)) {
7ae0e400 3350 if (mlx4_is_master(dev)) {
ab9c17a0 3351 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 3352
3353 } else {
ab9c17a0 3354 dev->num_slaves = 0;
f356fcbe
JM		 3355 err = mlx4_multi_func_init(dev);
3356 if (err) {
1a91de28 3357 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 3358 goto err_cmd;
3359 }
3360 }
225c7b1f
RD		 3361 }
3362
a0eacca9
MB		 3363 err = mlx4_init_fw(dev);
3364 if (err) {
3365 mlx4_err(dev, "Failed to init fw, aborting.\n");
3366 goto err_mfunc;
3367 }
3368
7ae0e400 3369 if (mlx4_is_master(dev)) {
da315679 3370 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 3371 if (!dev_cap) {
3372 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3373
3374 if (!dev_cap) {
3375 err = -ENOMEM;
3376 goto err_fw;
3377 }
3378
3379 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3380 if (err) {
3381 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3382 goto err_fw;
3383 }
3384
de966c59
MB		 3385 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3386 goto err_fw;
3387
7ae0e400 3388 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3389 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3390 total_vfs,
3391 existing_vfs,
3392 reset_flow);
7ae0e400 3393
ed3d2276 3394 mlx4_close_fw(dev);
7ae0e400
MB		 3395 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3396 dev->flags = dev_flags;
3397 if (!SRIOV_VALID_STATE(dev->flags)) {
3398 mlx4_err(dev, "Invalid SRIOV state\n");
3399 goto err_sriov;
3400 }
3401 err = mlx4_reset(dev);
3402 if (err) {
3403 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3404 goto err_sriov;
3405 }
3406 goto slave_start;
3407 }
3408 } else {
3409 /* Legacy mode FW requires SRIOV to be enabled before
3410 * doing QUERY_DEV_CAP, since max_eq's value is different if
3411 * SRIOV is enabled.
3412 */
3413 memset(dev_cap, 0, sizeof(*dev_cap));
3414 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3415 if (err) {
3416 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3417 goto err_fw;
3418 }
de966c59
MB		 3419
3420 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3421 goto err_fw;
7ae0e400
MB		 3422 }
3423 }
3424
225c7b1f 3425 err = mlx4_init_hca(dev);
ab9c17a0
JM		 3426 if (err) {
3427 if (err == -EACCES) {
3428 /* Not primary Physical function
3429 * Running in slave mode */
ffc39f6d 3430 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 3431 /* We're not a PF */
3432 if (dev->flags & MLX4_FLAG_SRIOV) {
3433 if (!existing_vfs)
3434 pci_disable_sriov(pdev);
55ad3592 3435 if (mlx4_is_master(dev) && !reset_flow)
a0eacca9
MB		 3436 atomic_dec(&pf_loading);
3437 dev->flags &= ~MLX4_FLAG_SRIOV;
3438 }
3439 if (!mlx4_is_slave(dev))
3440 mlx4_free_ownership(dev);
ab9c17a0
JM		 3441 dev->flags |= MLX4_FLAG_SLAVE;
3442 dev->flags &= ~MLX4_FLAG_MASTER;
3443 goto slave_start;
3444 } else
a0eacca9 3445 goto err_fw;
ab9c17a0
JM		 3446 }
3447
7ae0e400 3448 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3449 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3450 existing_vfs, reset_flow);
7ae0e400
MB		 3451
3452 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3453 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3454 dev->flags = dev_flags;
3455 err = mlx4_cmd_init(dev);
3456 if (err) {
3457 /* Only VHCR is cleaned up, so could still
3458 * send FW commands
3459 */
3460 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3461 goto err_close;
3462 }
3463 } else {
3464 dev->flags = dev_flags;
3465 }
3466
3467 if (!SRIOV_VALID_STATE(dev->flags)) {
3468 mlx4_err(dev, "Invalid SRIOV state\n");
3469 goto err_close;
3470 }
3471 }
3472
b912b2f8
EP		 3473 /* check if the device is functioning at its maximum possible speed.
3474 * No return code for this call, just warn the user in case of PCI
3475 * express device capabilities are under-satisfied by the bus.
3476 */
83d3459a
EP		 3477 if (!mlx4_is_slave(dev))
3478 mlx4_check_pcie_caps(dev);
b912b2f8 3479
ab9c17a0
JM		 3480 /* In master functions, the communication channel must be initialized
3481 * after obtaining its address from fw */
3482 if (mlx4_is_master(dev)) {
e1c00e10
MD		 3483 if (dev->caps.num_ports < 2 &&
3484 num_vfs_argc > 1) {
3485 err = -EINVAL;
3486 mlx4_err(dev,
3487 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3488 dev->caps.num_ports);
ab9c17a0
JM		 3489 goto err_close;
3490 }
872bf2fb 3491 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
dd41cc3b 3492
872bf2fb
YH		 3493 for (i = 0;
3494 i < sizeof(dev->persist->nvfs)/
3495 sizeof(dev->persist->nvfs[0]); i++) {
e1c00e10
MD		 3496 unsigned j;
3497
872bf2fb 3498 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
e1c00e10
MD		 3499 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3500 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3501 dev->caps.num_ports;
1ab95d37
MB		 3502 }
3503 }
e1c00e10
MD		 3504
3505 /* In master functions, the communication channel
3506 * must be initialized after obtaining its address from fw
3507 */
3508 err = mlx4_multi_func_init(dev);
3509 if (err) {
3510 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3511 goto err_close;
3512 }
ab9c17a0 3513 }
225c7b1f 3514
b8dd786f
YP		 3515 err = mlx4_alloc_eq_table(dev);
3516 if (err)
ab9c17a0 3517 goto err_master_mfunc;
b8dd786f 3518
c66fa19c 3519 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
730c41d5 3520 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 3521
08fb1055 3522 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 3523 if ((mlx4_is_mfunc(dev)) &&
3524 !(dev->flags & MLX4_FLAG_MSI_X)) {
72b8eaab 3525 err = -EOPNOTSUPP;
1a91de28 3526 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 3527 goto err_free_eq;
ab9c17a0
JM		 3528 }
3529
3530 if (!mlx4_is_slave(dev)) {
3531 err = mlx4_init_steering(dev);
3532 if (err)
e1c00e10 3533 goto err_disable_msix;
ab9c17a0 3534 }
b12d93d6 3535
6ed63d84
JM		 3536 mlx4_init_quotas(dev);
3537
225c7b1f 3538 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 3539 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3540 !mlx4_is_mfunc(dev)) {
08fb1055 3541 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1 3542 dev->caps.num_comp_vectors = 1;
08fb1055
MT		 3543 pci_disable_msix(pdev);
3544 err = mlx4_setup_hca(dev);
3545 }
3546
225c7b1f 3547 if (err)
b12d93d6 3548 goto err_steer;
225c7b1f 3549
55ad3592
YH		 3550 /* When PF resources are ready arm its comm channel to enable
3551 * getting commands
3552 */
3553 if (mlx4_is_master(dev)) {
3554 err = mlx4_ARM_COMM_CHANNEL(dev);
3555 if (err) {
3556 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3557 err);
3558 goto err_steer;
3559 }
3560 }
5a0d0a61 3561
7ff93f8b
YP		 3562 for (port = 1; port <= dev->caps.num_ports; port++) {
3563 err = mlx4_init_port_info(dev, port);
3564 if (err)
3565 goto err_port;
3566 }
2a2336f8 3567
53f33ae2
MS		 3568 priv->v2p.port1 = 1;
3569 priv->v2p.port2 = 2;
3570
225c7b1f
RD		 3571 err = mlx4_register_device(dev);
3572 if (err)
7ff93f8b 3573 goto err_port;
225c7b1f 3574
b046ffe5
EP		 3575 mlx4_request_modules(dev);
3576
27bf91d6
YP		 3577 mlx4_sense_init(dev);
3578 mlx4_start_sense(dev);
3579
befdf897 3580 priv->removed = 0;
225c7b1f 3581
55ad3592 3582 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3583 atomic_dec(&pf_loading);
3584
da315679 3585 kfree(dev_cap);
225c7b1f
RD		 3586 return 0;
3587
7ff93f8b 3588err_port:
b4f77264 3589 for (--port; port >= 1; --port)
7ff93f8b
YP		 3590 mlx4_cleanup_port_info(&priv->port[port]);
3591
6de5f7f6 3592 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3593 if (!mlx4_is_slave(dev))
3594 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 3595 mlx4_cleanup_qp_table(dev);
3596 mlx4_cleanup_srq_table(dev);
3597 mlx4_cleanup_cq_table(dev);
3598 mlx4_cmd_use_polling(dev);
3599 mlx4_cleanup_eq_table(dev);
fe6f700d 3600 mlx4_cleanup_mcg_table(dev);
225c7b1f 3601 mlx4_cleanup_mr_table(dev);
012a8ff5 3602 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 3603 mlx4_cleanup_pd_table(dev);
3604 mlx4_cleanup_uar_table(dev);
3605
b12d93d6 3606err_steer:
ab9c17a0
JM		 3607 if (!mlx4_is_slave(dev))
3608 mlx4_clear_steering(dev);
b12d93d6 3609
e1c00e10
MD		 3610err_disable_msix:
3611 if (dev->flags & MLX4_FLAG_MSI_X)
3612 pci_disable_msix(pdev);
3613
b8dd786f
YP		 3614err_free_eq:
3615 mlx4_free_eq_table(dev);
3616
ab9c17a0 3617err_master_mfunc:
772103e6
JM		 3618 if (mlx4_is_master(dev)) {
3619 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 3620 mlx4_multi_func_cleanup(dev);
772103e6 3621 }
ab9c17a0 3622
c73c8b1e
EBE		 3623 if (mlx4_is_slave(dev))
3624 mlx4_slave_destroy_special_qp_cap(dev);
b38f2879 3625
225c7b1f
RD		 3626err_close:
3627 mlx4_close_hca(dev);
3628
a0eacca9
MB		 3629err_fw:
3630 mlx4_close_fw(dev);
3631
ab9c17a0
JM		 3632err_mfunc:
3633 if (mlx4_is_slave(dev))
3634 mlx4_multi_func_cleanup(dev);
3635
225c7b1f 3636err_cmd:
ffc39f6d 3637 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 3638
ab9c17a0 3639err_sriov:
55ad3592 3640 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
ab9c17a0 3641 pci_disable_sriov(pdev);
55ad3592
YH		 3642 dev->flags &= ~MLX4_FLAG_SRIOV;
3643 }
ab9c17a0 3644
55ad3592 3645 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3646 atomic_dec(&pf_loading);
3647
1ab95d37
MB		 3648 kfree(priv->dev.dev_vfs);
3649
e1c00e10
MD		 3650 if (!mlx4_is_slave(dev))
3651 mlx4_free_ownership(dev);
3652
7ae0e400 3653 kfree(dev_cap);
e1c00e10
MD		 3654 return err;
3655}
3656
3657static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3658 struct mlx4_priv *priv)
3659{
3660 int err;
3661 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3662 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3663 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3664 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3665 unsigned total_vfs = 0;
3666 unsigned int i;
3667
3668 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3669
4bfd2e6e 3670 err = mlx4_pci_enable_device(&priv->dev);
e1c00e10
MD		 3671 if (err) {
3672 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3673 return err;
3674 }
3675
3676 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3677 * per port, we must limit the number of VFs to 63 (since their are
3678 * 128 MACs)
3679 */
691223ec 3680 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc;
e1c00e10
MD		 3681 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3682 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3683 if (nvfs[i] < 0) {
3684 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3685 err = -EINVAL;
3686 goto err_disable_pdev;
3687 }
3688 }
691223ec 3689 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc;
e1c00e10
MD		 3690 i++) {
3691 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3692 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3693 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3694 err = -EINVAL;
3695 goto err_disable_pdev;
3696 }
3697 }
0beb44b0 3698 if (total_vfs > MLX4_MAX_NUM_VF) {
e1c00e10 3699 dev_err(&pdev->dev,
0beb44b0
CS		 3700 "Requested more VF's (%d) than allowed by hw (%d)\n",
3701 total_vfs, MLX4_MAX_NUM_VF);
e1c00e10
MD		 3702 err = -EINVAL;
3703 goto err_disable_pdev;
3704 }
3705
3706 for (i = 0; i < MLX4_MAX_PORTS; i++) {
0beb44b0 3707 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
e1c00e10 3708 dev_err(&pdev->dev,
0beb44b0 3709 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
e1c00e10 3710 nvfs[i] + nvfs[2], i + 1,
0beb44b0 3711 MLX4_MAX_NUM_VF_P_PORT);
e1c00e10
MD		 3712 err = -EINVAL;
3713 goto err_disable_pdev;
3714 }
3715 }
3716
3717 /* Check for BARs. */
3718 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3719 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3720 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3721 pci_dev_data, pci_resource_flags(pdev, 0));
3722 err = -ENODEV;
3723 goto err_disable_pdev;
3724 }
3725 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3726 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3727 err = -ENODEV;
3728 goto err_disable_pdev;
3729 }
3730
3731 err = pci_request_regions(pdev, DRV_NAME);
3732 if (err) {
3733 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3734 goto err_disable_pdev;
3735 }
3736
3737 pci_set_master(pdev);
3738
3739 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3740 if (err) {
3741 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3742 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3743 if (err) {
3744 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3745 goto err_release_regions;
3746 }
3747 }
3748 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3749 if (err) {
3750 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3751 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3752 if (err) {
3753 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3754 goto err_release_regions;
3755 }
3756 }
3757
3758 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3759 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3760 /* Detect if this device is a virtual function */
3761 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3762 /* When acting as pf, we normally skip vfs unless explicitly
3763 * requested to probe them.
3764 */
3765 if (total_vfs) {
3766 unsigned vfs_offset = 0;
3767
691223ec 3768 for (i = 0; i < ARRAY_SIZE(nvfs) &&
e1c00e10
MD		 3769 vfs_offset + nvfs[i] < extended_func_num(pdev);
3770 vfs_offset += nvfs[i], i++)
3771 ;
691223ec 3772 if (i == ARRAY_SIZE(nvfs)) {
e1c00e10
MD		 3773 err = -ENODEV;
3774 goto err_release_regions;
3775 }
3776 if ((extended_func_num(pdev) - vfs_offset)
3777 > prb_vf[i]) {
3778 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3779 extended_func_num(pdev));
3780 err = -ENODEV;
3781 goto err_release_regions;
3782 }
3783 }
3784 }
3785
ad9a0bf0 3786 err = mlx4_catas_init(&priv->dev);
e1c00e10
MD		 3787 if (err)
3788 goto err_release_regions;
ad9a0bf0 3789
55ad3592 3790 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
ad9a0bf0
YH		 3791 if (err)
3792 goto err_catas;
3793
e1c00e10 3794 return 0;
225c7b1f 3795
ad9a0bf0
YH		 3796err_catas:
3797 mlx4_catas_end(&priv->dev);
3798
a01df0fe
RD		 3799err_release_regions:
3800 pci_release_regions(pdev);
225c7b1f
RD		 3801
3802err_disable_pdev:
4bfd2e6e 3803 mlx4_pci_disable_device(&priv->dev);
225c7b1f
RD		 3804 return err;
3805}
3806
b2facd95
JP		 3807static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3808 enum devlink_port_type port_type)
3809{
3810 struct mlx4_port_info *info = container_of(devlink_port,
3811 struct mlx4_port_info,
3812 devlink_port);
3813 enum mlx4_port_type mlx4_port_type;
3814
3815 switch (port_type) {
3816 case DEVLINK_PORT_TYPE_AUTO:
3817 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3818 break;
3819 case DEVLINK_PORT_TYPE_ETH:
3820 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3821 break;
3822 case DEVLINK_PORT_TYPE_IB:
3823 mlx4_port_type = MLX4_PORT_TYPE_IB;
3824 break;
3825 default:
3826 return -EOPNOTSUPP;
3827 }
3828
3829 return __set_port_type(info, mlx4_port_type);
3830}
3831
3832static const struct devlink_ops mlx4_devlink_ops = {
3833 .port_type_set = mlx4_devlink_port_type_set,
3834};
3835
1dd06ae8 3836static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 3837{
09d4d087 3838 struct devlink *devlink;
befdf897
WY		 3839 struct mlx4_priv *priv;
3840 struct mlx4_dev *dev;
e1c00e10 3841 int ret;
befdf897 3842
0a645e80 3843 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 3844
b2facd95 3845 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv));
09d4d087 3846 if (!devlink)
befdf897 3847 return -ENOMEM;
09d4d087 3848 priv = devlink_priv(devlink);
befdf897
WY		 3849
3850 dev = &priv->dev;
872bf2fb
YH		 3851 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3852 if (!dev->persist) {
09d4d087
JP		 3853 ret = -ENOMEM;
3854 goto err_devlink_free;
872bf2fb
YH		 3855 }
3856 dev->persist->pdev = pdev;
3857 dev->persist->dev = dev;
3858 pci_set_drvdata(pdev, dev->persist);
befdf897 3859 priv->pci_dev_data = id->driver_data;
f6bc11e4 3860 mutex_init(&dev->persist->device_state_mutex);
c69453e2 3861 mutex_init(&dev->persist->interface_state_mutex);
4bfd2e6e 3862 mutex_init(&dev->persist->pci_status_mutex);
befdf897 3863
09d4d087
JP		 3864 ret = devlink_register(devlink, &pdev->dev);
3865 if (ret)
3866 goto err_persist_free;
3867
e1c00e10 3868 ret = __mlx4_init_one(pdev, id->driver_data, priv);
09d4d087
JP		 3869 if (ret)
3870 goto err_devlink_unregister;
2ba5fbd6 3871
09d4d087
JP		 3872 pci_save_state(pdev);
3873 return 0;
3874
3875err_devlink_unregister:
3876 devlink_unregister(devlink);
3877err_persist_free:
3878 kfree(dev->persist);
3879err_devlink_free:
3880 devlink_free(devlink);
e1c00e10 3881 return ret;
3d73c288
RD		 3882}
3883
dd0eefe3
YH		 3884static void mlx4_clean_dev(struct mlx4_dev *dev)
3885{
3886 struct mlx4_dev_persistent *persist = dev->persist;
3887 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3888 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
dd0eefe3
YH		 3889
3890 memset(priv, 0, sizeof(*priv));
3891 priv->dev.persist = persist;
55ad3592 3892 priv->dev.flags = flags;
dd0eefe3
YH		 3893}
3894
e1c00e10 3895static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f 3896{
872bf2fb
YH		 3897 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3898 struct mlx4_dev *dev = persist->dev;
225c7b1f 3899 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 3900 int pci_dev_data;
dd0eefe3 3901 int p, i;
225c7b1f 3902
befdf897
WY		 3903 if (priv->removed)
3904 return;
225c7b1f 3905
dd0eefe3
YH		 3906 /* saving current ports type for further use */
3907 for (i = 0; i < dev->caps.num_ports; i++) {
3908 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3909 dev->persist->curr_port_poss_type[i] = dev->caps.
3910 possible_type[i + 1];
3911 }
3912
befdf897 3913 pci_dev_data = priv->pci_dev_data;
225c7b1f 3914
befdf897
WY		 3915 mlx4_stop_sense(dev);
3916 mlx4_unregister_device(dev);
225c7b1f 3917
befdf897
WY		 3918 for (p = 1; p <= dev->caps.num_ports; p++) {
3919 mlx4_cleanup_port_info(&priv->port[p]);
3920 mlx4_CLOSE_PORT(dev, p);
3921 }
3922
3923 if (mlx4_is_master(dev))
3924 mlx4_free_resource_tracker(dev,
3925 RES_TR_FREE_SLAVES_ONLY);
3926
6de5f7f6 3927 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3928 if (!mlx4_is_slave(dev))
3929 mlx4_cleanup_counters_table(dev);
befdf897
WY		 3930 mlx4_cleanup_qp_table(dev);
3931 mlx4_cleanup_srq_table(dev);
3932 mlx4_cleanup_cq_table(dev);
3933 mlx4_cmd_use_polling(dev);
3934 mlx4_cleanup_eq_table(dev);
3935 mlx4_cleanup_mcg_table(dev);
3936 mlx4_cleanup_mr_table(dev);
3937 mlx4_cleanup_xrcd_table(dev);
3938 mlx4_cleanup_pd_table(dev);
225c7b1f 3939
befdf897
WY		 3940 if (mlx4_is_master(dev))
3941 mlx4_free_resource_tracker(dev,
3942 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3943
befdf897
WY		 3944 iounmap(priv->kar);
3945 mlx4_uar_free(dev, &priv->driver_uar);
3946 mlx4_cleanup_uar_table(dev);
3947 if (!mlx4_is_slave(dev))
3948 mlx4_clear_steering(dev);
3949 mlx4_free_eq_table(dev);
3950 if (mlx4_is_master(dev))
3951 mlx4_multi_func_cleanup(dev);
3952 mlx4_close_hca(dev);
a0eacca9 3953 mlx4_close_fw(dev);
befdf897
WY		 3954 if (mlx4_is_slave(dev))
3955 mlx4_multi_func_cleanup(dev);
ffc39f6d 3956 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3957
befdf897
WY		 3958 if (dev->flags & MLX4_FLAG_MSI_X)
3959 pci_disable_msix(pdev);
befdf897
WY		 3960
3961 if (!mlx4_is_slave(dev))
3962 mlx4_free_ownership(dev);
3963
c73c8b1e 3964 mlx4_slave_destroy_special_qp_cap(dev);
befdf897
WY		 3965 kfree(dev->dev_vfs);
3966
dd0eefe3 3967 mlx4_clean_dev(dev);
befdf897
WY		 3968 priv->pci_dev_data = pci_dev_data;
3969 priv->removed = 1;
3970}
3971
3972static void mlx4_remove_one(struct pci_dev *pdev)
3973{
872bf2fb
YH		 3974 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3975 struct mlx4_dev *dev = persist->dev;
befdf897 3976 struct mlx4_priv *priv = mlx4_priv(dev);
09d4d087 3977 struct devlink *devlink = priv_to_devlink(priv);
55ad3592 3978 int active_vfs = 0;
befdf897 3979
4cbe4dac
JM		 3980 if (mlx4_is_slave(dev))
3981 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
3982
c69453e2
YH		 3983 mutex_lock(&persist->interface_state_mutex);
3984 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3985 mutex_unlock(&persist->interface_state_mutex);
3986
55ad3592
YH		 3987 /* Disabling SR-IOV is not allowed while there are active vf's */
3988 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3989 active_vfs = mlx4_how_many_lives_vf(dev);
3990 if (active_vfs) {
3991 pr_warn("Removing PF when there are active VF's !!\n");
3992 pr_warn("Will not disable SR-IOV.\n");
3993 }
3994 }
3995
c69453e2
YH		 3996 /* device marked to be under deletion running now without the lock
3997 * letting other tasks to be terminated
3998 */
3999 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4000 mlx4_unload_one(pdev);
4001 else
4002 mlx4_info(dev, "%s: interface is down\n", __func__);
ad9a0bf0 4003 mlx4_catas_end(dev);
55ad3592
YH		 4004 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
4005 mlx4_warn(dev, "Disabling SR-IOV\n");
4006 pci_disable_sriov(pdev);
4007 }
4008
e1c00e10 4009 pci_release_regions(pdev);
4bfd2e6e 4010 mlx4_pci_disable_device(dev);
09d4d087 4011 devlink_unregister(devlink);
872bf2fb 4012 kfree(dev->persist);
09d4d087 4013 devlink_free(devlink);
225c7b1f
RD		 4014}
4015
dd0eefe3
YH		 4016static int restore_current_port_types(struct mlx4_dev *dev,
4017 enum mlx4_port_type *types,
4018 enum mlx4_port_type *poss_types)
4019{
4020 struct mlx4_priv *priv = mlx4_priv(dev);
4021 int err, i;
4022
4023 mlx4_stop_sense(dev);
4024
4025 mutex_lock(&priv->port_mutex);
4026 for (i = 0; i < dev->caps.num_ports; i++)
4027 dev->caps.possible_type[i + 1] = poss_types[i];
4028 err = mlx4_change_port_types(dev, types);
4029 mlx4_start_sense(dev);
4030 mutex_unlock(&priv->port_mutex);
4031
4032 return err;
4033}
4034
ee49bd93
JM		 4035int mlx4_restart_one(struct pci_dev *pdev)
4036{
872bf2fb
YH		 4037 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4038 struct mlx4_dev *dev = persist->dev;
839f1243 4039 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 4040 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4041 int pci_dev_data, err, total_vfs;
839f1243
RD		 4042
4043 pci_dev_data = priv->pci_dev_data;
872bf2fb
YH		 4044 total_vfs = dev->persist->num_vfs;
4045 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
e1c00e10
MD		 4046
4047 mlx4_unload_one(pdev);
55ad3592 4048 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
e1c00e10
MD		 4049 if (err) {
4050 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
4051 __func__, pci_name(pdev), err);
4052 return err;
4053 }
4054
dd0eefe3
YH		 4055 err = restore_current_port_types(dev, dev->persist->curr_port_type,
4056 dev->persist->curr_port_poss_type);
4057 if (err)
4058 mlx4_err(dev, "could not restore original port types (%d)\n",
4059 err);
4060
e1c00e10 4061 return err;
ee49bd93
JM		 4062}
4063
c19e4b90
BH		 4064#define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
4065#define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
4066#define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
4067
9baa3c34 4068static const struct pci_device_id mlx4_pci_table[] = {
a1b87145 4069#ifdef CONFIG_MLX4_CORE_GEN2
c19e4b90
BH		 4070 /* MT25408 "Hermon" */
4071 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */
4072 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */
4073 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */
4074 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */
4075 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */
4076 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */
4077 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */
4078 /* MT25458 ConnectX EN 10GBASE-T */
4079 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
4080 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */
4081 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/
4082 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
4083 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */
4084 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
4085 /* MT26478 ConnectX2 40GigE PCIe Gen2 */
4086 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
4087 /* MT25400 Family [ConnectX-2] */
4088 MLX_VF(0x1002), /* Virtual Function */
a1b87145 4089#endif /* CONFIG_MLX4_CORE_GEN2 */
ab9c17a0 4090 /* MT27500 Family [ConnectX-3] */
c19e4b90
BH		 4091 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
4092 MLX_VF(0x1004), /* Virtual Function */
4093 MLX_GN(0x1005), /* MT27510 Family */
4094 MLX_GN(0x1006), /* MT27511 Family */
4095 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */
4096 MLX_GN(0x1008), /* MT27521 Family */
4097 MLX_GN(0x1009), /* MT27530 Family */
4098 MLX_GN(0x100a), /* MT27531 Family */
4099 MLX_GN(0x100b), /* MT27540 Family */
4100 MLX_GN(0x100c), /* MT27541 Family */
4101 MLX_GN(0x100d), /* MT27550 Family */
4102 MLX_GN(0x100e), /* MT27551 Family */
4103 MLX_GN(0x100f), /* MT27560 Family */
4104 MLX_GN(0x1010), /* MT27561 Family */
4105
4106 /*
4107 * See the mellanox_check_broken_intx_masking() quirk when
4108 * adding devices
4109 */
4110
225c7b1f
RD		 4111 { 0, }
4112};
4113
4114MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4115
57dbf29a
KSS		 4116static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4117 pci_channel_state_t state)
4118{
2ba5fbd6
YH		 4119 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4120
4121 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4122 mlx4_enter_error_state(persist);
57dbf29a 4123
2ba5fbd6
YH		 4124 mutex_lock(&persist->interface_state_mutex);
4125 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4126 mlx4_unload_one(pdev);
4127
4128 mutex_unlock(&persist->interface_state_mutex);
4129 if (state == pci_channel_io_perm_failure)
4130 return PCI_ERS_RESULT_DISCONNECT;
4131
4bfd2e6e 4132 mlx4_pci_disable_device(persist->dev);
2ba5fbd6 4133 return PCI_ERS_RESULT_NEED_RESET;
57dbf29a
KSS		 4134}
4135
4136static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4137{
2ba5fbd6
YH		 4138 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4139 struct mlx4_dev *dev = persist->dev;
c12833ac 4140 int err;
97a5221f 4141
2ba5fbd6 4142 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4bfd2e6e 4143 err = mlx4_pci_enable_device(dev);
c12833ac
DJ		 4144 if (err) {
4145 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
2ba5fbd6
YH		 4146 return PCI_ERS_RESULT_DISCONNECT;
4147 }
4148
4149 pci_set_master(pdev);
4150 pci_restore_state(pdev);
4151 pci_save_state(pdev);
c12833ac
DJ		 4152 return PCI_ERS_RESULT_RECOVERED;
4153}
4154
4155static void mlx4_pci_resume(struct pci_dev *pdev)
4156{
4157 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4158 struct mlx4_dev *dev = persist->dev;
4159 struct mlx4_priv *priv = mlx4_priv(dev);
4160 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4161 int total_vfs;
4162 int err;
2ba5fbd6 4163
c12833ac 4164 mlx4_err(dev, "%s was called\n", __func__);
2ba5fbd6
YH		 4165 total_vfs = dev->persist->num_vfs;
4166 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4167
4168 mutex_lock(&persist->interface_state_mutex);
4169 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
c12833ac 4170 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
55ad3592 4171 priv, 1);
c12833ac
DJ		 4172 if (err) {
4173 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4174 __func__, err);
2ba5fbd6
YH		 4175 goto end;
4176 }
4177
c12833ac 4178 err = restore_current_port_types(dev, dev->persist->
2ba5fbd6
YH		 4179 curr_port_type, dev->persist->
4180 curr_port_poss_type);
c12833ac
DJ		 4181 if (err)
4182 mlx4_err(dev, "could not restore original port types (%d)\n", err);
2ba5fbd6
YH		 4183 }
4184end:
4185 mutex_unlock(&persist->interface_state_mutex);
57dbf29a 4186
57dbf29a
KSS		 4187}
4188
2ba5fbd6
YH		 4189static void mlx4_shutdown(struct pci_dev *pdev)
4190{
4191 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4192
4193 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4194 mutex_lock(&persist->interface_state_mutex);
b4353708 4195 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
2ba5fbd6
YH		 4196 mlx4_unload_one(pdev);
4197 mutex_unlock(&persist->interface_state_mutex);
4198}
4199
3646f0e5 4200static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 4201 .error_detected = mlx4_pci_err_detected,
4202 .slot_reset = mlx4_pci_slot_reset,
c12833ac 4203 .resume = mlx4_pci_resume,
57dbf29a
KSS		 4204};
4205
225c7b1f
RD		 4206static struct pci_driver mlx4_driver = {
4207 .name = DRV_NAME,
4208 .id_table = mlx4_pci_table,
4209 .probe = mlx4_init_one,
2ba5fbd6 4210 .shutdown = mlx4_shutdown,
f57e6848 4211 .remove = mlx4_remove_one,
57dbf29a 4212 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 4213};
4214
7ff93f8b
YP		 4215static int __init mlx4_verify_params(void)
4216{
4217 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 4218 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 4219 return -1;
4220 }
4221
cb29688a 4222 if (log_num_vlan != 0)
c20862c8
AV		 4223 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4224 MLX4_LOG_NUM_VLANS);
7ff93f8b 4225
ecc8fb11
AV		 4226 if (use_prio != 0)
4227 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 4228
0498628f 4229 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 4230 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4231 log_mtts_per_seg);
ab6bf42e
EC		 4232 return -1;
4233 }
4234
ab9c17a0
JM		 4235 /* Check if module param for ports type has legal combination */
4236 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 4237 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 4238 port_type_array[0] = true;
4239 }
4240
7d077cd3
MB		 4241 if (mlx4_log_num_mgm_entry_size < -7 ||
4242 (mlx4_log_num_mgm_entry_size > 0 &&
4243 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4244 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4245 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 4246 mlx4_log_num_mgm_entry_size,
4247 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4248 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 4249 return -1;
4250 }
4251
7ff93f8b
YP		 4252 return 0;
4253}
4254
225c7b1f
RD		 4255static int __init mlx4_init(void)
4256{
4257 int ret;
4258
7ff93f8b
YP		 4259 if (mlx4_verify_params())
4260 return -EINVAL;
4261
27bf91d6
YP		 4262
4263 mlx4_wq = create_singlethread_workqueue("mlx4");
4264 if (!mlx4_wq)
4265 return -ENOMEM;
ee49bd93 4266
225c7b1f 4267 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 4268 if (ret < 0)
4269 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4270 return ret < 0 ? ret : 0;
4271}
4272
4273static void __exit mlx4_cleanup(void)
4274{
4275 pci_unregister_driver(&mlx4_driver);
27bf91d6 4276 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4277}
4278
4279module_init(mlx4_init);
4280module_exit(mlx4_cleanup);
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