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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
51a379d0 | 4 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
5 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/errno.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 41 | #include <linux/slab.h> |
c1b43dca | 42 | #include <linux/io-mapping.h> |
ab9c17a0 | 43 | #include <linux/delay.h> |
90b1ebe7 | 44 | #include <linux/netdevice.h> |
b046ffe5 | 45 | #include <linux/kmod.h> |
225c7b1f RD |
46 | |
47 | #include <linux/mlx4/device.h> | |
48 | #include <linux/mlx4/doorbell.h> | |
49 | ||
50 | #include "mlx4.h" | |
51 | #include "fw.h" | |
52 | #include "icm.h" | |
53 | ||
54 | MODULE_AUTHOR("Roland Dreier"); | |
55 | MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); | |
56 | MODULE_LICENSE("Dual BSD/GPL"); | |
57 | MODULE_VERSION(DRV_VERSION); | |
58 | ||
27bf91d6 YP |
59 | struct workqueue_struct *mlx4_wq; |
60 | ||
225c7b1f RD |
61 | #ifdef CONFIG_MLX4_DEBUG |
62 | ||
63 | int mlx4_debug_level = 0; | |
64 | module_param_named(debug_level, mlx4_debug_level, int, 0644); | |
65 | MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); | |
66 | ||
67 | #endif /* CONFIG_MLX4_DEBUG */ | |
68 | ||
69 | #ifdef CONFIG_PCI_MSI | |
70 | ||
08fb1055 | 71 | static int msi_x = 1; |
225c7b1f RD |
72 | module_param(msi_x, int, 0444); |
73 | MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); | |
74 | ||
75 | #else /* CONFIG_PCI_MSI */ | |
76 | ||
77 | #define msi_x (0) | |
78 | ||
79 | #endif /* CONFIG_PCI_MSI */ | |
80 | ||
ab9c17a0 JM |
81 | static int num_vfs; |
82 | module_param(num_vfs, int, 0444); | |
83 | MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0"); | |
84 | ||
85 | static int probe_vf; | |
86 | module_param(probe_vf, int, 0644); | |
87 | MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)"); | |
88 | ||
3c439b55 | 89 | int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; |
0ec2c0f8 EE |
90 | module_param_named(log_num_mgm_entry_size, |
91 | mlx4_log_num_mgm_entry_size, int, 0444); | |
92 | MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" | |
93 | " of qp per mcg, for example:" | |
3c439b55 | 94 | " 10 gives 248.range: 7 <=" |
0ff1fb65 | 95 | " log_num_mgm_entry_size <= 12." |
3c439b55 JM |
96 | " To activate device managed" |
97 | " flow steering when available, set to -1"); | |
0ec2c0f8 | 98 | |
08ff3235 OG |
99 | static bool enable_64b_cqe_eqe; |
100 | module_param(enable_64b_cqe_eqe, bool, 0444); | |
101 | MODULE_PARM_DESC(enable_64b_cqe_eqe, | |
278cee05 | 102 | "Enable 64 byte CQEs/EQEs when the FW supports this"); |
08ff3235 | 103 | |
ab9c17a0 | 104 | #define HCA_GLOBAL_CAP_MASK 0 |
08ff3235 OG |
105 | |
106 | #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE | |
ab9c17a0 | 107 | |
f57e6848 | 108 | static char mlx4_version[] = |
225c7b1f RD |
109 | DRV_NAME ": Mellanox ConnectX core driver v" |
110 | DRV_VERSION " (" DRV_RELDATE ")\n"; | |
111 | ||
112 | static struct mlx4_profile default_profile = { | |
ab9c17a0 | 113 | .num_qp = 1 << 18, |
225c7b1f | 114 | .num_srq = 1 << 16, |
c9f2ba5e | 115 | .rdmarc_per_qp = 1 << 4, |
225c7b1f RD |
116 | .num_cq = 1 << 16, |
117 | .num_mcg = 1 << 13, | |
ab9c17a0 | 118 | .num_mpt = 1 << 19, |
9fd7a1e1 | 119 | .num_mtt = 1 << 20, /* It is really num mtt segements */ |
225c7b1f RD |
120 | }; |
121 | ||
ab9c17a0 | 122 | static int log_num_mac = 7; |
93fc9e1b YP |
123 | module_param_named(log_num_mac, log_num_mac, int, 0444); |
124 | MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); | |
125 | ||
126 | static int log_num_vlan; | |
127 | module_param_named(log_num_vlan, log_num_vlan, int, 0444); | |
128 | MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); | |
cb29688a OG |
129 | /* Log2 max number of VLANs per ETH port (0-7) */ |
130 | #define MLX4_LOG_NUM_VLANS 7 | |
93fc9e1b | 131 | |
eb939922 | 132 | static bool use_prio; |
93fc9e1b YP |
133 | module_param_named(use_prio, use_prio, bool, 0444); |
134 | MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " | |
135 | "(0/1, default 0)"); | |
136 | ||
2b8fb286 | 137 | int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); |
ab6bf42e | 138 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); |
0498628f | 139 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); |
ab6bf42e | 140 | |
8d0fc7b6 | 141 | static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; |
ab9c17a0 JM |
142 | static int arr_argc = 2; |
143 | module_param_array(port_type_array, int, &arr_argc, 0444); | |
8d0fc7b6 YP |
144 | MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " |
145 | "1 for IB, 2 for Ethernet"); | |
ab9c17a0 JM |
146 | |
147 | struct mlx4_port_config { | |
148 | struct list_head list; | |
149 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; | |
150 | struct pci_dev *pdev; | |
151 | }; | |
152 | ||
27bf91d6 YP |
153 | int mlx4_check_port_params(struct mlx4_dev *dev, |
154 | enum mlx4_port_type *port_type) | |
7ff93f8b YP |
155 | { |
156 | int i; | |
157 | ||
158 | for (i = 0; i < dev->caps.num_ports - 1; i++) { | |
27bf91d6 YP |
159 | if (port_type[i] != port_type[i + 1]) { |
160 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { | |
161 | mlx4_err(dev, "Only same port types supported " | |
162 | "on this HCA, aborting.\n"); | |
163 | return -EINVAL; | |
164 | } | |
7ff93f8b YP |
165 | } |
166 | } | |
7ff93f8b YP |
167 | |
168 | for (i = 0; i < dev->caps.num_ports; i++) { | |
169 | if (!(port_type[i] & dev->caps.supported_type[i+1])) { | |
170 | mlx4_err(dev, "Requested port type for port %d is not " | |
171 | "supported on this HCA\n", i + 1); | |
172 | return -EINVAL; | |
173 | } | |
174 | } | |
175 | return 0; | |
176 | } | |
177 | ||
178 | static void mlx4_set_port_mask(struct mlx4_dev *dev) | |
179 | { | |
180 | int i; | |
181 | ||
7ff93f8b | 182 | for (i = 1; i <= dev->caps.num_ports; ++i) |
65dab25d | 183 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
7ff93f8b | 184 | } |
f2a3f6a3 | 185 | |
3d73c288 | 186 | static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
225c7b1f RD |
187 | { |
188 | int err; | |
5ae2a7a8 | 189 | int i; |
225c7b1f RD |
190 | |
191 | err = mlx4_QUERY_DEV_CAP(dev, dev_cap); | |
192 | if (err) { | |
193 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
194 | return err; | |
195 | } | |
196 | ||
197 | if (dev_cap->min_page_sz > PAGE_SIZE) { | |
198 | mlx4_err(dev, "HCA minimum page size of %d bigger than " | |
199 | "kernel PAGE_SIZE of %ld, aborting.\n", | |
200 | dev_cap->min_page_sz, PAGE_SIZE); | |
201 | return -ENODEV; | |
202 | } | |
203 | if (dev_cap->num_ports > MLX4_MAX_PORTS) { | |
204 | mlx4_err(dev, "HCA has %d ports, but we only support %d, " | |
205 | "aborting.\n", | |
206 | dev_cap->num_ports, MLX4_MAX_PORTS); | |
207 | return -ENODEV; | |
208 | } | |
209 | ||
210 | if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { | |
211 | mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than " | |
212 | "PCI resource 2 size of 0x%llx, aborting.\n", | |
213 | dev_cap->uar_size, | |
214 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
215 | return -ENODEV; | |
216 | } | |
217 | ||
218 | dev->caps.num_ports = dev_cap->num_ports; | |
3fc929e2 | 219 | dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM; |
5ae2a7a8 RD |
220 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
221 | dev->caps.vl_cap[i] = dev_cap->max_vl[i]; | |
b79acb49 | 222 | dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; |
6634961c JM |
223 | dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; |
224 | dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; | |
225 | /* set gid and pkey table operating lengths by default | |
226 | * to non-sriov values */ | |
5ae2a7a8 RD |
227 | dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; |
228 | dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; | |
229 | dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; | |
b79acb49 YP |
230 | dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; |
231 | dev->caps.def_mac[i] = dev_cap->def_mac[i]; | |
7ff93f8b | 232 | dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; |
8d0fc7b6 YP |
233 | dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; |
234 | dev->caps.default_sense[i] = dev_cap->default_sense[i]; | |
7699517d YP |
235 | dev->caps.trans_type[i] = dev_cap->trans_type[i]; |
236 | dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; | |
237 | dev->caps.wavelength[i] = dev_cap->wavelength[i]; | |
238 | dev->caps.trans_code[i] = dev_cap->trans_code[i]; | |
5ae2a7a8 RD |
239 | } |
240 | ||
ab9c17a0 | 241 | dev->caps.uar_page_size = PAGE_SIZE; |
225c7b1f | 242 | dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; |
225c7b1f RD |
243 | dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; |
244 | dev->caps.bf_reg_size = dev_cap->bf_reg_size; | |
245 | dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; | |
246 | dev->caps.max_sq_sg = dev_cap->max_sq_sg; | |
247 | dev->caps.max_rq_sg = dev_cap->max_rq_sg; | |
248 | dev->caps.max_wqes = dev_cap->max_qp_sz; | |
249 | dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; | |
225c7b1f RD |
250 | dev->caps.max_srq_wqes = dev_cap->max_srq_sz; |
251 | dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; | |
252 | dev->caps.reserved_srqs = dev_cap->reserved_srqs; | |
253 | dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; | |
254 | dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; | |
225c7b1f RD |
255 | /* |
256 | * Subtract 1 from the limit because we need to allocate a | |
257 | * spare CQE so the HCA HW can tell the difference between an | |
258 | * empty CQ and a full CQ. | |
259 | */ | |
260 | dev->caps.max_cqes = dev_cap->max_cq_sz - 1; | |
261 | dev->caps.reserved_cqs = dev_cap->reserved_cqs; | |
262 | dev->caps.reserved_eqs = dev_cap->reserved_eqs; | |
2b8fb286 | 263 | dev->caps.reserved_mtts = dev_cap->reserved_mtts; |
225c7b1f | 264 | dev->caps.reserved_mrws = dev_cap->reserved_mrws; |
ab9c17a0 JM |
265 | |
266 | /* The first 128 UARs are used for EQ doorbells */ | |
267 | dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); | |
225c7b1f | 268 | dev->caps.reserved_pds = dev_cap->reserved_pds; |
012a8ff5 SH |
269 | dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? |
270 | dev_cap->reserved_xrcds : 0; | |
271 | dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? | |
272 | dev_cap->max_xrcds : 0; | |
2b8fb286 MA |
273 | dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; |
274 | ||
149983af | 275 | dev->caps.max_msg_sz = dev_cap->max_msg_sz; |
225c7b1f RD |
276 | dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); |
277 | dev->caps.flags = dev_cap->flags; | |
b3416f44 | 278 | dev->caps.flags2 = dev_cap->flags2; |
95d04f07 RD |
279 | dev->caps.bmme_flags = dev_cap->bmme_flags; |
280 | dev->caps.reserved_lkey = dev_cap->reserved_lkey; | |
225c7b1f | 281 | dev->caps.stat_rate_support = dev_cap->stat_rate_support; |
b832be1e | 282 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; |
b3416f44 | 283 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; |
225c7b1f | 284 | |
ca3e57a5 RD |
285 | /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ |
286 | if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) | |
58a60168 | 287 | dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; |
aadf4f3f RD |
288 | /* Don't do sense port on multifunction devices (for now at least) */ |
289 | if (mlx4_is_mfunc(dev)) | |
290 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; | |
58a60168 | 291 | |
93fc9e1b | 292 | dev->caps.log_num_macs = log_num_mac; |
cb29688a | 293 | dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; |
93fc9e1b YP |
294 | dev->caps.log_num_prios = use_prio ? 3 : 0; |
295 | ||
296 | for (i = 1; i <= dev->caps.num_ports; ++i) { | |
ab9c17a0 JM |
297 | dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; |
298 | if (dev->caps.supported_type[i]) { | |
299 | /* if only ETH is supported - assign ETH */ | |
300 | if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) | |
301 | dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; | |
105c320f | 302 | /* if only IB is supported, assign IB */ |
ab9c17a0 | 303 | else if (dev->caps.supported_type[i] == |
105c320f JM |
304 | MLX4_PORT_TYPE_IB) |
305 | dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 306 | else { |
105c320f JM |
307 | /* if IB and ETH are supported, we set the port |
308 | * type according to user selection of port type; | |
309 | * if user selected none, take the FW hint */ | |
310 | if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) | |
8d0fc7b6 YP |
311 | dev->caps.port_type[i] = dev->caps.suggested_type[i] ? |
312 | MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 313 | else |
105c320f | 314 | dev->caps.port_type[i] = port_type_array[i - 1]; |
ab9c17a0 JM |
315 | } |
316 | } | |
8d0fc7b6 YP |
317 | /* |
318 | * Link sensing is allowed on the port if 3 conditions are true: | |
319 | * 1. Both protocols are supported on the port. | |
320 | * 2. Different types are supported on the port | |
321 | * 3. FW declared that it supports link sensing | |
322 | */ | |
27bf91d6 | 323 | mlx4_priv(dev)->sense.sense_allowed[i] = |
58a60168 | 324 | ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && |
8d0fc7b6 | 325 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
58a60168 | 326 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); |
7ff93f8b | 327 | |
8d0fc7b6 YP |
328 | /* |
329 | * If "default_sense" bit is set, we move the port to "AUTO" mode | |
330 | * and perform sense_port FW command to try and set the correct | |
331 | * port type from beginning | |
332 | */ | |
46c46747 | 333 | if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { |
8d0fc7b6 YP |
334 | enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; |
335 | dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; | |
336 | mlx4_SENSE_PORT(dev, i, &sensed_port); | |
337 | if (sensed_port != MLX4_PORT_TYPE_NONE) | |
338 | dev->caps.port_type[i] = sensed_port; | |
339 | } else { | |
340 | dev->caps.possible_type[i] = dev->caps.port_type[i]; | |
341 | } | |
342 | ||
93fc9e1b YP |
343 | if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { |
344 | dev->caps.log_num_macs = dev_cap->log_max_macs[i]; | |
345 | mlx4_warn(dev, "Requested number of MACs is too much " | |
346 | "for port %d, reducing to %d.\n", | |
347 | i, 1 << dev->caps.log_num_macs); | |
348 | } | |
349 | if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { | |
350 | dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; | |
351 | mlx4_warn(dev, "Requested number of VLANs is too much " | |
352 | "for port %d, reducing to %d.\n", | |
353 | i, 1 << dev->caps.log_num_vlans); | |
354 | } | |
355 | } | |
356 | ||
f2a3f6a3 OG |
357 | dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); |
358 | ||
93fc9e1b YP |
359 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; |
360 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = | |
361 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = | |
362 | (1 << dev->caps.log_num_macs) * | |
363 | (1 << dev->caps.log_num_vlans) * | |
364 | (1 << dev->caps.log_num_prios) * | |
365 | dev->caps.num_ports; | |
366 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; | |
367 | ||
368 | dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + | |
369 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + | |
370 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + | |
371 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; | |
372 | ||
e2c76824 | 373 | dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; |
08ff3235 | 374 | |
b3051320 | 375 | if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { |
08ff3235 OG |
376 | if (dev_cap->flags & |
377 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { | |
378 | mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); | |
379 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; | |
380 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; | |
381 | } | |
382 | } | |
383 | ||
f97b4b5d | 384 | if ((dev->caps.flags & |
08ff3235 OG |
385 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && |
386 | mlx4_is_master(dev)) | |
387 | dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; | |
388 | ||
225c7b1f RD |
389 | return 0; |
390 | } | |
ab9c17a0 JM |
391 | /*The function checks if there are live vf, return the num of them*/ |
392 | static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) | |
393 | { | |
394 | struct mlx4_priv *priv = mlx4_priv(dev); | |
395 | struct mlx4_slave_state *s_state; | |
396 | int i; | |
397 | int ret = 0; | |
398 | ||
399 | for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { | |
400 | s_state = &priv->mfunc.master.slave_state[i]; | |
401 | if (s_state->active && s_state->last_cmd != | |
402 | MLX4_COMM_CMD_RESET) { | |
403 | mlx4_warn(dev, "%s: slave: %d is still active\n", | |
404 | __func__, i); | |
405 | ret++; | |
406 | } | |
407 | } | |
408 | return ret; | |
409 | } | |
410 | ||
396f2feb JM |
411 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) |
412 | { | |
413 | u32 qk = MLX4_RESERVED_QKEY_BASE; | |
47605df9 JM |
414 | |
415 | if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || | |
416 | qpn < dev->phys_caps.base_proxy_sqpn) | |
396f2feb JM |
417 | return -EINVAL; |
418 | ||
47605df9 | 419 | if (qpn >= dev->phys_caps.base_tunnel_sqpn) |
396f2feb | 420 | /* tunnel qp */ |
47605df9 | 421 | qk += qpn - dev->phys_caps.base_tunnel_sqpn; |
396f2feb | 422 | else |
47605df9 | 423 | qk += qpn - dev->phys_caps.base_proxy_sqpn; |
396f2feb JM |
424 | *qkey = qk; |
425 | return 0; | |
426 | } | |
427 | EXPORT_SYMBOL(mlx4_get_parav_qkey); | |
428 | ||
54679e14 JM |
429 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) |
430 | { | |
431 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
432 | ||
433 | if (!mlx4_is_master(dev)) | |
434 | return; | |
435 | ||
436 | priv->virt2phys_pkey[slave][port - 1][i] = val; | |
437 | } | |
438 | EXPORT_SYMBOL(mlx4_sync_pkey_table); | |
439 | ||
afa8fd1d JM |
440 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) |
441 | { | |
442 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
443 | ||
444 | if (!mlx4_is_master(dev)) | |
445 | return; | |
446 | ||
447 | priv->slave_node_guids[slave] = guid; | |
448 | } | |
449 | EXPORT_SYMBOL(mlx4_put_slave_node_guid); | |
450 | ||
451 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) | |
452 | { | |
453 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
454 | ||
455 | if (!mlx4_is_master(dev)) | |
456 | return 0; | |
457 | ||
458 | return priv->slave_node_guids[slave]; | |
459 | } | |
460 | EXPORT_SYMBOL(mlx4_get_slave_node_guid); | |
461 | ||
e10903b0 | 462 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) |
ab9c17a0 JM |
463 | { |
464 | struct mlx4_priv *priv = mlx4_priv(dev); | |
465 | struct mlx4_slave_state *s_slave; | |
466 | ||
467 | if (!mlx4_is_master(dev)) | |
468 | return 0; | |
469 | ||
470 | s_slave = &priv->mfunc.master.slave_state[slave]; | |
471 | return !!s_slave->active; | |
472 | } | |
473 | EXPORT_SYMBOL(mlx4_is_slave_active); | |
474 | ||
7b8157be JM |
475 | static void slave_adjust_steering_mode(struct mlx4_dev *dev, |
476 | struct mlx4_dev_cap *dev_cap, | |
477 | struct mlx4_init_hca_param *hca_param) | |
478 | { | |
479 | dev->caps.steering_mode = hca_param->steering_mode; | |
480 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
481 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | |
482 | dev->caps.fs_log_max_ucast_qp_range_size = | |
483 | dev_cap->fs_log_max_ucast_qp_range_size; | |
484 | } else | |
485 | dev->caps.num_qp_per_mgm = | |
486 | 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); | |
487 | ||
488 | mlx4_dbg(dev, "Steering mode is: %s\n", | |
489 | mlx4_steering_mode_str(dev->caps.steering_mode)); | |
490 | } | |
491 | ||
ab9c17a0 JM |
492 | static int mlx4_slave_cap(struct mlx4_dev *dev) |
493 | { | |
494 | int err; | |
495 | u32 page_size; | |
496 | struct mlx4_dev_cap dev_cap; | |
497 | struct mlx4_func_cap func_cap; | |
498 | struct mlx4_init_hca_param hca_param; | |
499 | int i; | |
500 | ||
501 | memset(&hca_param, 0, sizeof(hca_param)); | |
502 | err = mlx4_QUERY_HCA(dev, &hca_param); | |
503 | if (err) { | |
504 | mlx4_err(dev, "QUERY_HCA command failed, aborting.\n"); | |
505 | return err; | |
506 | } | |
507 | ||
508 | /*fail if the hca has an unknown capability */ | |
509 | if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) != | |
510 | HCA_GLOBAL_CAP_MASK) { | |
511 | mlx4_err(dev, "Unknown hca global capabilities\n"); | |
512 | return -ENOSYS; | |
513 | } | |
514 | ||
515 | mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; | |
516 | ||
ddd8a6c1 EE |
517 | dev->caps.hca_core_clock = hca_param.hca_core_clock; |
518 | ||
ab9c17a0 | 519 | memset(&dev_cap, 0, sizeof(dev_cap)); |
b91cb3eb | 520 | dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; |
ab9c17a0 JM |
521 | err = mlx4_dev_cap(dev, &dev_cap); |
522 | if (err) { | |
523 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
524 | return err; | |
525 | } | |
526 | ||
b91cb3eb JM |
527 | err = mlx4_QUERY_FW(dev); |
528 | if (err) | |
529 | mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n"); | |
530 | ||
ab9c17a0 JM |
531 | page_size = ~dev->caps.page_size_cap + 1; |
532 | mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); | |
533 | if (page_size > PAGE_SIZE) { | |
534 | mlx4_err(dev, "HCA minimum page size of %d bigger than " | |
535 | "kernel PAGE_SIZE of %ld, aborting.\n", | |
536 | page_size, PAGE_SIZE); | |
537 | return -ENODEV; | |
538 | } | |
539 | ||
540 | /* slave gets uar page size from QUERY_HCA fw command */ | |
541 | dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); | |
542 | ||
543 | /* TODO: relax this assumption */ | |
544 | if (dev->caps.uar_page_size != PAGE_SIZE) { | |
545 | mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", | |
546 | dev->caps.uar_page_size, PAGE_SIZE); | |
547 | return -ENODEV; | |
548 | } | |
549 | ||
550 | memset(&func_cap, 0, sizeof(func_cap)); | |
47605df9 | 551 | err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); |
ab9c17a0 | 552 | if (err) { |
47605df9 JM |
553 | mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n", |
554 | err); | |
ab9c17a0 JM |
555 | return err; |
556 | } | |
557 | ||
558 | if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != | |
559 | PF_CONTEXT_BEHAVIOUR_MASK) { | |
560 | mlx4_err(dev, "Unknown pf context behaviour\n"); | |
561 | return -ENOSYS; | |
562 | } | |
563 | ||
ab9c17a0 JM |
564 | dev->caps.num_ports = func_cap.num_ports; |
565 | dev->caps.num_qps = func_cap.qp_quota; | |
566 | dev->caps.num_srqs = func_cap.srq_quota; | |
567 | dev->caps.num_cqs = func_cap.cq_quota; | |
568 | dev->caps.num_eqs = func_cap.max_eq; | |
569 | dev->caps.reserved_eqs = func_cap.reserved_eq; | |
570 | dev->caps.num_mpts = func_cap.mpt_quota; | |
571 | dev->caps.num_mtts = func_cap.mtt_quota; | |
572 | dev->caps.num_pds = MLX4_NUM_PDS; | |
573 | dev->caps.num_mgms = 0; | |
574 | dev->caps.num_amgms = 0; | |
575 | ||
ab9c17a0 JM |
576 | if (dev->caps.num_ports > MLX4_MAX_PORTS) { |
577 | mlx4_err(dev, "HCA has %d ports, but we only support %d, " | |
578 | "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS); | |
579 | return -ENODEV; | |
580 | } | |
581 | ||
47605df9 JM |
582 | dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); |
583 | dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
584 | dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
585 | dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
586 | ||
587 | if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || | |
588 | !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) { | |
589 | err = -ENOMEM; | |
590 | goto err_mem; | |
591 | } | |
592 | ||
6634961c | 593 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
47605df9 JM |
594 | err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap); |
595 | if (err) { | |
596 | mlx4_err(dev, "QUERY_FUNC_CAP port command failed for" | |
597 | " port %d, aborting (%d).\n", i, err); | |
598 | goto err_mem; | |
599 | } | |
600 | dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; | |
601 | dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; | |
602 | dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; | |
603 | dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; | |
6230bb23 | 604 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
6634961c JM |
605 | if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, |
606 | &dev->caps.gid_table_len[i], | |
607 | &dev->caps.pkey_table_len[i])) | |
47605df9 | 608 | goto err_mem; |
6634961c | 609 | } |
6230bb23 | 610 | |
ab9c17a0 JM |
611 | if (dev->caps.uar_page_size * (dev->caps.num_uars - |
612 | dev->caps.reserved_uars) > | |
613 | pci_resource_len(dev->pdev, 2)) { | |
614 | mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than " | |
615 | "PCI resource 2 size of 0x%llx, aborting.\n", | |
616 | dev->caps.uar_page_size * dev->caps.num_uars, | |
617 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
47605df9 | 618 | goto err_mem; |
ab9c17a0 JM |
619 | } |
620 | ||
08ff3235 OG |
621 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { |
622 | dev->caps.eqe_size = 64; | |
623 | dev->caps.eqe_factor = 1; | |
624 | } else { | |
625 | dev->caps.eqe_size = 32; | |
626 | dev->caps.eqe_factor = 0; | |
627 | } | |
628 | ||
629 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { | |
630 | dev->caps.cqe_size = 64; | |
631 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; | |
632 | } else { | |
633 | dev->caps.cqe_size = 32; | |
634 | } | |
635 | ||
f9bd2d7f AV |
636 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; |
637 | mlx4_warn(dev, "Timestamping is not supported in slave mode.\n"); | |
638 | ||
7b8157be JM |
639 | slave_adjust_steering_mode(dev, &dev_cap, &hca_param); |
640 | ||
ab9c17a0 | 641 | return 0; |
47605df9 JM |
642 | |
643 | err_mem: | |
644 | kfree(dev->caps.qp0_tunnel); | |
645 | kfree(dev->caps.qp0_proxy); | |
646 | kfree(dev->caps.qp1_tunnel); | |
647 | kfree(dev->caps.qp1_proxy); | |
648 | dev->caps.qp0_tunnel = dev->caps.qp0_proxy = | |
649 | dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL; | |
650 | ||
651 | return err; | |
ab9c17a0 | 652 | } |
225c7b1f | 653 | |
b046ffe5 EP |
654 | static void mlx4_request_modules(struct mlx4_dev *dev) |
655 | { | |
656 | int port; | |
657 | int has_ib_port = false; | |
658 | int has_eth_port = false; | |
659 | #define EN_DRV_NAME "mlx4_en" | |
660 | #define IB_DRV_NAME "mlx4_ib" | |
661 | ||
662 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
663 | if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) | |
664 | has_ib_port = true; | |
665 | else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) | |
666 | has_eth_port = true; | |
667 | } | |
668 | ||
669 | if (has_ib_port) | |
670 | request_module_nowait(IB_DRV_NAME); | |
671 | if (has_eth_port) | |
672 | request_module_nowait(EN_DRV_NAME); | |
673 | } | |
674 | ||
7ff93f8b YP |
675 | /* |
676 | * Change the port configuration of the device. | |
677 | * Every user of this function must hold the port mutex. | |
678 | */ | |
27bf91d6 YP |
679 | int mlx4_change_port_types(struct mlx4_dev *dev, |
680 | enum mlx4_port_type *port_types) | |
7ff93f8b YP |
681 | { |
682 | int err = 0; | |
683 | int change = 0; | |
684 | int port; | |
685 | ||
686 | for (port = 0; port < dev->caps.num_ports; port++) { | |
27bf91d6 YP |
687 | /* Change the port type only if the new type is different |
688 | * from the current, and not set to Auto */ | |
3d8f9308 | 689 | if (port_types[port] != dev->caps.port_type[port + 1]) |
7ff93f8b | 690 | change = 1; |
7ff93f8b YP |
691 | } |
692 | if (change) { | |
693 | mlx4_unregister_device(dev); | |
694 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
695 | mlx4_CLOSE_PORT(dev, port); | |
1e0f03d5 | 696 | dev->caps.port_type[port] = port_types[port - 1]; |
6634961c | 697 | err = mlx4_SET_PORT(dev, port, -1); |
7ff93f8b YP |
698 | if (err) { |
699 | mlx4_err(dev, "Failed to set port %d, " | |
700 | "aborting\n", port); | |
701 | goto out; | |
702 | } | |
703 | } | |
704 | mlx4_set_port_mask(dev); | |
705 | err = mlx4_register_device(dev); | |
b046ffe5 EP |
706 | if (err) { |
707 | mlx4_err(dev, "Failed to register device\n"); | |
708 | goto out; | |
709 | } | |
710 | mlx4_request_modules(dev); | |
7ff93f8b YP |
711 | } |
712 | ||
713 | out: | |
714 | return err; | |
715 | } | |
716 | ||
717 | static ssize_t show_port_type(struct device *dev, | |
718 | struct device_attribute *attr, | |
719 | char *buf) | |
720 | { | |
721 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
722 | port_attr); | |
723 | struct mlx4_dev *mdev = info->dev; | |
27bf91d6 YP |
724 | char type[8]; |
725 | ||
726 | sprintf(type, "%s", | |
727 | (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? | |
728 | "ib" : "eth"); | |
729 | if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) | |
730 | sprintf(buf, "auto (%s)\n", type); | |
731 | else | |
732 | sprintf(buf, "%s\n", type); | |
7ff93f8b | 733 | |
27bf91d6 | 734 | return strlen(buf); |
7ff93f8b YP |
735 | } |
736 | ||
737 | static ssize_t set_port_type(struct device *dev, | |
738 | struct device_attribute *attr, | |
739 | const char *buf, size_t count) | |
740 | { | |
741 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
742 | port_attr); | |
743 | struct mlx4_dev *mdev = info->dev; | |
744 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
745 | enum mlx4_port_type types[MLX4_MAX_PORTS]; | |
27bf91d6 | 746 | enum mlx4_port_type new_types[MLX4_MAX_PORTS]; |
7ff93f8b YP |
747 | int i; |
748 | int err = 0; | |
749 | ||
750 | if (!strcmp(buf, "ib\n")) | |
751 | info->tmp_type = MLX4_PORT_TYPE_IB; | |
752 | else if (!strcmp(buf, "eth\n")) | |
753 | info->tmp_type = MLX4_PORT_TYPE_ETH; | |
27bf91d6 YP |
754 | else if (!strcmp(buf, "auto\n")) |
755 | info->tmp_type = MLX4_PORT_TYPE_AUTO; | |
7ff93f8b YP |
756 | else { |
757 | mlx4_err(mdev, "%s is not supported port type\n", buf); | |
758 | return -EINVAL; | |
759 | } | |
760 | ||
27bf91d6 | 761 | mlx4_stop_sense(mdev); |
7ff93f8b | 762 | mutex_lock(&priv->port_mutex); |
27bf91d6 YP |
763 | /* Possible type is always the one that was delivered */ |
764 | mdev->caps.possible_type[info->port] = info->tmp_type; | |
765 | ||
766 | for (i = 0; i < mdev->caps.num_ports; i++) { | |
7ff93f8b | 767 | types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : |
27bf91d6 YP |
768 | mdev->caps.possible_type[i+1]; |
769 | if (types[i] == MLX4_PORT_TYPE_AUTO) | |
770 | types[i] = mdev->caps.port_type[i+1]; | |
771 | } | |
7ff93f8b | 772 | |
58a60168 YP |
773 | if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
774 | !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { | |
27bf91d6 YP |
775 | for (i = 1; i <= mdev->caps.num_ports; i++) { |
776 | if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { | |
777 | mdev->caps.possible_type[i] = mdev->caps.port_type[i]; | |
778 | err = -EINVAL; | |
779 | } | |
780 | } | |
781 | } | |
782 | if (err) { | |
783 | mlx4_err(mdev, "Auto sensing is not supported on this HCA. " | |
784 | "Set only 'eth' or 'ib' for both ports " | |
785 | "(should be the same)\n"); | |
786 | goto out; | |
787 | } | |
788 | ||
789 | mlx4_do_sense_ports(mdev, new_types, types); | |
790 | ||
791 | err = mlx4_check_port_params(mdev, new_types); | |
7ff93f8b YP |
792 | if (err) |
793 | goto out; | |
794 | ||
27bf91d6 YP |
795 | /* We are about to apply the changes after the configuration |
796 | * was verified, no need to remember the temporary types | |
797 | * any more */ | |
798 | for (i = 0; i < mdev->caps.num_ports; i++) | |
799 | priv->port[i + 1].tmp_type = 0; | |
7ff93f8b | 800 | |
27bf91d6 | 801 | err = mlx4_change_port_types(mdev, new_types); |
7ff93f8b YP |
802 | |
803 | out: | |
27bf91d6 | 804 | mlx4_start_sense(mdev); |
7ff93f8b YP |
805 | mutex_unlock(&priv->port_mutex); |
806 | return err ? err : count; | |
807 | } | |
808 | ||
096335b3 OG |
809 | enum ibta_mtu { |
810 | IB_MTU_256 = 1, | |
811 | IB_MTU_512 = 2, | |
812 | IB_MTU_1024 = 3, | |
813 | IB_MTU_2048 = 4, | |
814 | IB_MTU_4096 = 5 | |
815 | }; | |
816 | ||
817 | static inline int int_to_ibta_mtu(int mtu) | |
818 | { | |
819 | switch (mtu) { | |
820 | case 256: return IB_MTU_256; | |
821 | case 512: return IB_MTU_512; | |
822 | case 1024: return IB_MTU_1024; | |
823 | case 2048: return IB_MTU_2048; | |
824 | case 4096: return IB_MTU_4096; | |
825 | default: return -1; | |
826 | } | |
827 | } | |
828 | ||
829 | static inline int ibta_mtu_to_int(enum ibta_mtu mtu) | |
830 | { | |
831 | switch (mtu) { | |
832 | case IB_MTU_256: return 256; | |
833 | case IB_MTU_512: return 512; | |
834 | case IB_MTU_1024: return 1024; | |
835 | case IB_MTU_2048: return 2048; | |
836 | case IB_MTU_4096: return 4096; | |
837 | default: return -1; | |
838 | } | |
839 | } | |
840 | ||
841 | static ssize_t show_port_ib_mtu(struct device *dev, | |
842 | struct device_attribute *attr, | |
843 | char *buf) | |
844 | { | |
845 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
846 | port_mtu_attr); | |
847 | struct mlx4_dev *mdev = info->dev; | |
848 | ||
849 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) | |
850 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
851 | ||
852 | sprintf(buf, "%d\n", | |
853 | ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); | |
854 | return strlen(buf); | |
855 | } | |
856 | ||
857 | static ssize_t set_port_ib_mtu(struct device *dev, | |
858 | struct device_attribute *attr, | |
859 | const char *buf, size_t count) | |
860 | { | |
861 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
862 | port_mtu_attr); | |
863 | struct mlx4_dev *mdev = info->dev; | |
864 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
865 | int err, port, mtu, ibta_mtu = -1; | |
866 | ||
867 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { | |
868 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
869 | return -EINVAL; | |
870 | } | |
871 | ||
618fad95 DB |
872 | err = kstrtoint(buf, 0, &mtu); |
873 | if (!err) | |
096335b3 OG |
874 | ibta_mtu = int_to_ibta_mtu(mtu); |
875 | ||
618fad95 | 876 | if (err || ibta_mtu < 0) { |
096335b3 OG |
877 | mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); |
878 | return -EINVAL; | |
879 | } | |
880 | ||
881 | mdev->caps.port_ib_mtu[info->port] = ibta_mtu; | |
882 | ||
883 | mlx4_stop_sense(mdev); | |
884 | mutex_lock(&priv->port_mutex); | |
885 | mlx4_unregister_device(mdev); | |
886 | for (port = 1; port <= mdev->caps.num_ports; port++) { | |
887 | mlx4_CLOSE_PORT(mdev, port); | |
6634961c | 888 | err = mlx4_SET_PORT(mdev, port, -1); |
096335b3 OG |
889 | if (err) { |
890 | mlx4_err(mdev, "Failed to set port %d, " | |
891 | "aborting\n", port); | |
892 | goto err_set_port; | |
893 | } | |
894 | } | |
895 | err = mlx4_register_device(mdev); | |
896 | err_set_port: | |
897 | mutex_unlock(&priv->port_mutex); | |
898 | mlx4_start_sense(mdev); | |
899 | return err ? err : count; | |
900 | } | |
901 | ||
e8f9b2ed | 902 | static int mlx4_load_fw(struct mlx4_dev *dev) |
225c7b1f RD |
903 | { |
904 | struct mlx4_priv *priv = mlx4_priv(dev); | |
905 | int err; | |
906 | ||
907 | priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, | |
5b0bf5e2 | 908 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f RD |
909 | if (!priv->fw.fw_icm) { |
910 | mlx4_err(dev, "Couldn't allocate FW area, aborting.\n"); | |
911 | return -ENOMEM; | |
912 | } | |
913 | ||
914 | err = mlx4_MAP_FA(dev, priv->fw.fw_icm); | |
915 | if (err) { | |
916 | mlx4_err(dev, "MAP_FA command failed, aborting.\n"); | |
917 | goto err_free; | |
918 | } | |
919 | ||
920 | err = mlx4_RUN_FW(dev); | |
921 | if (err) { | |
922 | mlx4_err(dev, "RUN_FW command failed, aborting.\n"); | |
923 | goto err_unmap_fa; | |
924 | } | |
925 | ||
926 | return 0; | |
927 | ||
928 | err_unmap_fa: | |
929 | mlx4_UNMAP_FA(dev); | |
930 | ||
931 | err_free: | |
5b0bf5e2 | 932 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); |
225c7b1f RD |
933 | return err; |
934 | } | |
935 | ||
e8f9b2ed RD |
936 | static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, |
937 | int cmpt_entry_sz) | |
225c7b1f RD |
938 | { |
939 | struct mlx4_priv *priv = mlx4_priv(dev); | |
940 | int err; | |
ab9c17a0 | 941 | int num_eqs; |
225c7b1f RD |
942 | |
943 | err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, | |
944 | cmpt_base + | |
945 | ((u64) (MLX4_CMPT_TYPE_QP * | |
946 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
947 | cmpt_entry_sz, dev->caps.num_qps, | |
93fc9e1b YP |
948 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
949 | 0, 0); | |
225c7b1f RD |
950 | if (err) |
951 | goto err; | |
952 | ||
953 | err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, | |
954 | cmpt_base + | |
955 | ((u64) (MLX4_CMPT_TYPE_SRQ * | |
956 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
957 | cmpt_entry_sz, dev->caps.num_srqs, | |
5b0bf5e2 | 958 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
959 | if (err) |
960 | goto err_qp; | |
961 | ||
962 | err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, | |
963 | cmpt_base + | |
964 | ((u64) (MLX4_CMPT_TYPE_CQ * | |
965 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
966 | cmpt_entry_sz, dev->caps.num_cqs, | |
5b0bf5e2 | 967 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
968 | if (err) |
969 | goto err_srq; | |
970 | ||
3fc929e2 MA |
971 | num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : |
972 | dev->caps.num_eqs; | |
225c7b1f RD |
973 | err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, |
974 | cmpt_base + | |
975 | ((u64) (MLX4_CMPT_TYPE_EQ * | |
976 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
ab9c17a0 | 977 | cmpt_entry_sz, num_eqs, num_eqs, 0, 0); |
225c7b1f RD |
978 | if (err) |
979 | goto err_cq; | |
980 | ||
981 | return 0; | |
982 | ||
983 | err_cq: | |
984 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
985 | ||
986 | err_srq: | |
987 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
988 | ||
989 | err_qp: | |
990 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
991 | ||
992 | err: | |
993 | return err; | |
994 | } | |
995 | ||
3d73c288 RD |
996 | static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, |
997 | struct mlx4_init_hca_param *init_hca, u64 icm_size) | |
225c7b1f RD |
998 | { |
999 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1000 | u64 aux_pages; | |
ab9c17a0 | 1001 | int num_eqs; |
225c7b1f RD |
1002 | int err; |
1003 | ||
1004 | err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); | |
1005 | if (err) { | |
1006 | mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n"); | |
1007 | return err; | |
1008 | } | |
1009 | ||
1010 | mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n", | |
1011 | (unsigned long long) icm_size >> 10, | |
1012 | (unsigned long long) aux_pages << 2); | |
1013 | ||
1014 | priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, | |
5b0bf5e2 | 1015 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f RD |
1016 | if (!priv->fw.aux_icm) { |
1017 | mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n"); | |
1018 | return -ENOMEM; | |
1019 | } | |
1020 | ||
1021 | err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); | |
1022 | if (err) { | |
1023 | mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n"); | |
1024 | goto err_free_aux; | |
1025 | } | |
1026 | ||
1027 | err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); | |
1028 | if (err) { | |
1029 | mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n"); | |
1030 | goto err_unmap_aux; | |
1031 | } | |
1032 | ||
ab9c17a0 | 1033 | |
3fc929e2 MA |
1034 | num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : |
1035 | dev->caps.num_eqs; | |
fa0681d2 RD |
1036 | err = mlx4_init_icm_table(dev, &priv->eq_table.table, |
1037 | init_hca->eqc_base, dev_cap->eqc_entry_sz, | |
ab9c17a0 | 1038 | num_eqs, num_eqs, 0, 0); |
225c7b1f RD |
1039 | if (err) { |
1040 | mlx4_err(dev, "Failed to map EQ context memory, aborting.\n"); | |
1041 | goto err_unmap_cmpt; | |
1042 | } | |
1043 | ||
d7bb58fb JM |
1044 | /* |
1045 | * Reserved MTT entries must be aligned up to a cacheline | |
1046 | * boundary, since the FW will write to them, while the driver | |
1047 | * writes to all other MTT entries. (The variable | |
1048 | * dev->caps.mtt_entry_sz below is really the MTT segment | |
1049 | * size, not the raw entry size) | |
1050 | */ | |
1051 | dev->caps.reserved_mtts = | |
1052 | ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, | |
1053 | dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; | |
1054 | ||
225c7b1f RD |
1055 | err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, |
1056 | init_hca->mtt_base, | |
1057 | dev->caps.mtt_entry_sz, | |
2b8fb286 | 1058 | dev->caps.num_mtts, |
5b0bf5e2 | 1059 | dev->caps.reserved_mtts, 1, 0); |
225c7b1f RD |
1060 | if (err) { |
1061 | mlx4_err(dev, "Failed to map MTT context memory, aborting.\n"); | |
1062 | goto err_unmap_eq; | |
1063 | } | |
1064 | ||
1065 | err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, | |
1066 | init_hca->dmpt_base, | |
1067 | dev_cap->dmpt_entry_sz, | |
1068 | dev->caps.num_mpts, | |
5b0bf5e2 | 1069 | dev->caps.reserved_mrws, 1, 1); |
225c7b1f RD |
1070 | if (err) { |
1071 | mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n"); | |
1072 | goto err_unmap_mtt; | |
1073 | } | |
1074 | ||
1075 | err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, | |
1076 | init_hca->qpc_base, | |
1077 | dev_cap->qpc_entry_sz, | |
1078 | dev->caps.num_qps, | |
93fc9e1b YP |
1079 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1080 | 0, 0); | |
225c7b1f RD |
1081 | if (err) { |
1082 | mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); | |
1083 | goto err_unmap_dmpt; | |
1084 | } | |
1085 | ||
1086 | err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, | |
1087 | init_hca->auxc_base, | |
1088 | dev_cap->aux_entry_sz, | |
1089 | dev->caps.num_qps, | |
93fc9e1b YP |
1090 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1091 | 0, 0); | |
225c7b1f RD |
1092 | if (err) { |
1093 | mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); | |
1094 | goto err_unmap_qp; | |
1095 | } | |
1096 | ||
1097 | err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, | |
1098 | init_hca->altc_base, | |
1099 | dev_cap->altc_entry_sz, | |
1100 | dev->caps.num_qps, | |
93fc9e1b YP |
1101 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1102 | 0, 0); | |
225c7b1f RD |
1103 | if (err) { |
1104 | mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); | |
1105 | goto err_unmap_auxc; | |
1106 | } | |
1107 | ||
1108 | err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, | |
1109 | init_hca->rdmarc_base, | |
1110 | dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, | |
1111 | dev->caps.num_qps, | |
93fc9e1b YP |
1112 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1113 | 0, 0); | |
225c7b1f RD |
1114 | if (err) { |
1115 | mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); | |
1116 | goto err_unmap_altc; | |
1117 | } | |
1118 | ||
1119 | err = mlx4_init_icm_table(dev, &priv->cq_table.table, | |
1120 | init_hca->cqc_base, | |
1121 | dev_cap->cqc_entry_sz, | |
1122 | dev->caps.num_cqs, | |
5b0bf5e2 | 1123 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
1124 | if (err) { |
1125 | mlx4_err(dev, "Failed to map CQ context memory, aborting.\n"); | |
1126 | goto err_unmap_rdmarc; | |
1127 | } | |
1128 | ||
1129 | err = mlx4_init_icm_table(dev, &priv->srq_table.table, | |
1130 | init_hca->srqc_base, | |
1131 | dev_cap->srq_entry_sz, | |
1132 | dev->caps.num_srqs, | |
5b0bf5e2 | 1133 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
1134 | if (err) { |
1135 | mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n"); | |
1136 | goto err_unmap_cq; | |
1137 | } | |
1138 | ||
1139 | /* | |
0ff1fb65 HHZ |
1140 | * For flow steering device managed mode it is required to use |
1141 | * mlx4_init_icm_table. For B0 steering mode it's not strictly | |
1142 | * required, but for simplicity just map the whole multicast | |
1143 | * group table now. The table isn't very big and it's a lot | |
1144 | * easier than trying to track ref counts. | |
225c7b1f RD |
1145 | */ |
1146 | err = mlx4_init_icm_table(dev, &priv->mcg_table.table, | |
0ec2c0f8 EE |
1147 | init_hca->mc_base, |
1148 | mlx4_get_mgm_entry_size(dev), | |
225c7b1f RD |
1149 | dev->caps.num_mgms + dev->caps.num_amgms, |
1150 | dev->caps.num_mgms + dev->caps.num_amgms, | |
5b0bf5e2 | 1151 | 0, 0); |
225c7b1f RD |
1152 | if (err) { |
1153 | mlx4_err(dev, "Failed to map MCG context memory, aborting.\n"); | |
1154 | goto err_unmap_srq; | |
1155 | } | |
1156 | ||
1157 | return 0; | |
1158 | ||
1159 | err_unmap_srq: | |
1160 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1161 | ||
1162 | err_unmap_cq: | |
1163 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1164 | ||
1165 | err_unmap_rdmarc: | |
1166 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1167 | ||
1168 | err_unmap_altc: | |
1169 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1170 | ||
1171 | err_unmap_auxc: | |
1172 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1173 | ||
1174 | err_unmap_qp: | |
1175 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1176 | ||
1177 | err_unmap_dmpt: | |
1178 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1179 | ||
1180 | err_unmap_mtt: | |
1181 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
1182 | ||
1183 | err_unmap_eq: | |
fa0681d2 | 1184 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1185 | |
1186 | err_unmap_cmpt: | |
1187 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); | |
1188 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1189 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1190 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
1191 | ||
1192 | err_unmap_aux: | |
1193 | mlx4_UNMAP_ICM_AUX(dev); | |
1194 | ||
1195 | err_free_aux: | |
5b0bf5e2 | 1196 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1197 | |
1198 | return err; | |
1199 | } | |
1200 | ||
1201 | static void mlx4_free_icms(struct mlx4_dev *dev) | |
1202 | { | |
1203 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1204 | ||
1205 | mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); | |
1206 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1207 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1208 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1209 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1210 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1211 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1212 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1213 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
fa0681d2 | 1214 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1215 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); |
1216 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1217 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1218 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
225c7b1f RD |
1219 | |
1220 | mlx4_UNMAP_ICM_AUX(dev); | |
5b0bf5e2 | 1221 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1222 | } |
1223 | ||
ab9c17a0 JM |
1224 | static void mlx4_slave_exit(struct mlx4_dev *dev) |
1225 | { | |
1226 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1227 | ||
f3d4c89e | 1228 | mutex_lock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1229 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) |
1230 | mlx4_warn(dev, "Failed to close slave function.\n"); | |
f3d4c89e | 1231 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1232 | } |
1233 | ||
c1b43dca EC |
1234 | static int map_bf_area(struct mlx4_dev *dev) |
1235 | { | |
1236 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1237 | resource_size_t bf_start; | |
1238 | resource_size_t bf_len; | |
1239 | int err = 0; | |
1240 | ||
3d747473 JM |
1241 | if (!dev->caps.bf_reg_size) |
1242 | return -ENXIO; | |
1243 | ||
ab9c17a0 JM |
1244 | bf_start = pci_resource_start(dev->pdev, 2) + |
1245 | (dev->caps.num_uars << PAGE_SHIFT); | |
1246 | bf_len = pci_resource_len(dev->pdev, 2) - | |
1247 | (dev->caps.num_uars << PAGE_SHIFT); | |
c1b43dca EC |
1248 | priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); |
1249 | if (!priv->bf_mapping) | |
1250 | err = -ENOMEM; | |
1251 | ||
1252 | return err; | |
1253 | } | |
1254 | ||
1255 | static void unmap_bf_area(struct mlx4_dev *dev) | |
1256 | { | |
1257 | if (mlx4_priv(dev)->bf_mapping) | |
1258 | io_mapping_free(mlx4_priv(dev)->bf_mapping); | |
1259 | } | |
1260 | ||
ec693d47 AV |
1261 | cycle_t mlx4_read_clock(struct mlx4_dev *dev) |
1262 | { | |
1263 | u32 clockhi, clocklo, clockhi1; | |
1264 | cycle_t cycles; | |
1265 | int i; | |
1266 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1267 | ||
1268 | for (i = 0; i < 10; i++) { | |
1269 | clockhi = swab32(readl(priv->clock_mapping)); | |
1270 | clocklo = swab32(readl(priv->clock_mapping + 4)); | |
1271 | clockhi1 = swab32(readl(priv->clock_mapping)); | |
1272 | if (clockhi == clockhi1) | |
1273 | break; | |
1274 | } | |
1275 | ||
1276 | cycles = (u64) clockhi << 32 | (u64) clocklo; | |
1277 | ||
1278 | return cycles; | |
1279 | } | |
1280 | EXPORT_SYMBOL_GPL(mlx4_read_clock); | |
1281 | ||
1282 | ||
ddd8a6c1 EE |
1283 | static int map_internal_clock(struct mlx4_dev *dev) |
1284 | { | |
1285 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1286 | ||
1287 | priv->clock_mapping = | |
1288 | ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) + | |
1289 | priv->fw.clock_offset, MLX4_CLOCK_SIZE); | |
1290 | ||
1291 | if (!priv->clock_mapping) | |
1292 | return -ENOMEM; | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static void unmap_internal_clock(struct mlx4_dev *dev) | |
1298 | { | |
1299 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1300 | ||
1301 | if (priv->clock_mapping) | |
1302 | iounmap(priv->clock_mapping); | |
1303 | } | |
1304 | ||
225c7b1f RD |
1305 | static void mlx4_close_hca(struct mlx4_dev *dev) |
1306 | { | |
ddd8a6c1 | 1307 | unmap_internal_clock(dev); |
c1b43dca | 1308 | unmap_bf_area(dev); |
ab9c17a0 JM |
1309 | if (mlx4_is_slave(dev)) |
1310 | mlx4_slave_exit(dev); | |
1311 | else { | |
1312 | mlx4_CLOSE_HCA(dev, 0); | |
1313 | mlx4_free_icms(dev); | |
1314 | mlx4_UNMAP_FA(dev); | |
1315 | mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | static int mlx4_init_slave(struct mlx4_dev *dev) | |
1320 | { | |
1321 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1322 | u64 dma = (u64) priv->mfunc.vhcr_dma; | |
ab9c17a0 JM |
1323 | int ret_from_reset = 0; |
1324 | u32 slave_read; | |
1325 | u32 cmd_channel_ver; | |
1326 | ||
f3d4c89e | 1327 | mutex_lock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1328 | priv->cmd.max_cmds = 1; |
1329 | mlx4_warn(dev, "Sending reset\n"); | |
1330 | ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, | |
1331 | MLX4_COMM_TIME); | |
1332 | /* if we are in the middle of flr the slave will try | |
1333 | * NUM_OF_RESET_RETRIES times before leaving.*/ | |
1334 | if (ret_from_reset) { | |
1335 | if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { | |
5efe5355 JM |
1336 | mlx4_warn(dev, "slave is currently in the " |
1337 | "middle of FLR. Deferring probe.\n"); | |
1338 | mutex_unlock(&priv->cmd.slave_cmd_mutex); | |
1339 | return -EPROBE_DEFER; | |
ab9c17a0 JM |
1340 | } else |
1341 | goto err; | |
1342 | } | |
1343 | ||
1344 | /* check the driver version - the slave I/F revision | |
1345 | * must match the master's */ | |
1346 | slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); | |
1347 | cmd_channel_ver = mlx4_comm_get_version(); | |
1348 | ||
1349 | if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != | |
1350 | MLX4_COMM_GET_IF_REV(slave_read)) { | |
1351 | mlx4_err(dev, "slave driver version is not supported" | |
1352 | " by the master\n"); | |
1353 | goto err; | |
1354 | } | |
1355 | ||
1356 | mlx4_warn(dev, "Sending vhcr0\n"); | |
1357 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, | |
1358 | MLX4_COMM_TIME)) | |
1359 | goto err; | |
1360 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, | |
1361 | MLX4_COMM_TIME)) | |
1362 | goto err; | |
1363 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, | |
1364 | MLX4_COMM_TIME)) | |
1365 | goto err; | |
1366 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) | |
1367 | goto err; | |
f3d4c89e RD |
1368 | |
1369 | mutex_unlock(&priv->cmd.slave_cmd_mutex); | |
ab9c17a0 JM |
1370 | return 0; |
1371 | ||
1372 | err: | |
1373 | mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); | |
f3d4c89e | 1374 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 | 1375 | return -EIO; |
225c7b1f RD |
1376 | } |
1377 | ||
6634961c JM |
1378 | static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) |
1379 | { | |
1380 | int i; | |
1381 | ||
1382 | for (i = 1; i <= dev->caps.num_ports; i++) { | |
1383 | dev->caps.gid_table_len[i] = 1; | |
1384 | dev->caps.pkey_table_len[i] = | |
1385 | dev->phys_caps.pkey_phys_table_len[i] - 1; | |
1386 | } | |
1387 | } | |
1388 | ||
3c439b55 JM |
1389 | static int choose_log_fs_mgm_entry_size(int qp_per_entry) |
1390 | { | |
1391 | int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; | |
1392 | ||
1393 | for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; | |
1394 | i++) { | |
1395 | if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) | |
1396 | break; | |
1397 | } | |
1398 | ||
1399 | return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; | |
1400 | } | |
1401 | ||
7b8157be JM |
1402 | static void choose_steering_mode(struct mlx4_dev *dev, |
1403 | struct mlx4_dev_cap *dev_cap) | |
1404 | { | |
3c439b55 JM |
1405 | if (mlx4_log_num_mgm_entry_size == -1 && |
1406 | dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && | |
7b8157be | 1407 | (!mlx4_is_mfunc(dev) || |
3c439b55 JM |
1408 | (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) && |
1409 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= | |
1410 | MLX4_MIN_MGM_LOG_ENTRY_SIZE) { | |
1411 | dev->oper_log_mgm_entry_size = | |
1412 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); | |
7b8157be JM |
1413 | dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
1414 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | |
1415 | dev->caps.fs_log_max_ucast_qp_range_size = | |
1416 | dev_cap->fs_log_max_ucast_qp_range_size; | |
1417 | } else { | |
1418 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && | |
1419 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | |
1420 | dev->caps.steering_mode = MLX4_STEERING_MODE_B0; | |
1421 | else { | |
1422 | dev->caps.steering_mode = MLX4_STEERING_MODE_A0; | |
1423 | ||
1424 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || | |
1425 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | |
1426 | mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags " | |
1427 | "set to use B0 steering. Falling back to A0 steering mode.\n"); | |
1428 | } | |
3c439b55 JM |
1429 | dev->oper_log_mgm_entry_size = |
1430 | mlx4_log_num_mgm_entry_size > 0 ? | |
1431 | mlx4_log_num_mgm_entry_size : | |
1432 | MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; | |
7b8157be JM |
1433 | dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); |
1434 | } | |
3c439b55 JM |
1435 | mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, " |
1436 | "modparam log_num_mgm_entry_size = %d\n", | |
1437 | mlx4_steering_mode_str(dev->caps.steering_mode), | |
1438 | dev->oper_log_mgm_entry_size, | |
1439 | mlx4_log_num_mgm_entry_size); | |
7b8157be JM |
1440 | } |
1441 | ||
3d73c288 | 1442 | static int mlx4_init_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1443 | { |
1444 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1445 | struct mlx4_adapter adapter; | |
1446 | struct mlx4_dev_cap dev_cap; | |
2d928651 | 1447 | struct mlx4_mod_stat_cfg mlx4_cfg; |
225c7b1f RD |
1448 | struct mlx4_profile profile; |
1449 | struct mlx4_init_hca_param init_hca; | |
1450 | u64 icm_size; | |
1451 | int err; | |
1452 | ||
ab9c17a0 JM |
1453 | if (!mlx4_is_slave(dev)) { |
1454 | err = mlx4_QUERY_FW(dev); | |
1455 | if (err) { | |
1456 | if (err == -EACCES) | |
1457 | mlx4_info(dev, "non-primary physical function, skipping.\n"); | |
1458 | else | |
1459 | mlx4_err(dev, "QUERY_FW command failed, aborting.\n"); | |
bef772eb | 1460 | return err; |
ab9c17a0 | 1461 | } |
225c7b1f | 1462 | |
ab9c17a0 JM |
1463 | err = mlx4_load_fw(dev); |
1464 | if (err) { | |
1465 | mlx4_err(dev, "Failed to start FW, aborting.\n"); | |
bef772eb | 1466 | return err; |
ab9c17a0 | 1467 | } |
225c7b1f | 1468 | |
ab9c17a0 JM |
1469 | mlx4_cfg.log_pg_sz_m = 1; |
1470 | mlx4_cfg.log_pg_sz = 0; | |
1471 | err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); | |
1472 | if (err) | |
1473 | mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); | |
2d928651 | 1474 | |
ab9c17a0 JM |
1475 | err = mlx4_dev_cap(dev, &dev_cap); |
1476 | if (err) { | |
1477 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
1478 | goto err_stop_fw; | |
1479 | } | |
225c7b1f | 1480 | |
7b8157be JM |
1481 | choose_steering_mode(dev, &dev_cap); |
1482 | ||
6634961c JM |
1483 | if (mlx4_is_master(dev)) |
1484 | mlx4_parav_master_pf_caps(dev); | |
1485 | ||
ab9c17a0 | 1486 | profile = default_profile; |
0ff1fb65 HHZ |
1487 | if (dev->caps.steering_mode == |
1488 | MLX4_STEERING_MODE_DEVICE_MANAGED) | |
1489 | profile.num_mcg = MLX4_FS_NUM_MCG; | |
225c7b1f | 1490 | |
ab9c17a0 JM |
1491 | icm_size = mlx4_make_profile(dev, &profile, &dev_cap, |
1492 | &init_hca); | |
1493 | if ((long long) icm_size < 0) { | |
1494 | err = icm_size; | |
1495 | goto err_stop_fw; | |
1496 | } | |
225c7b1f | 1497 | |
a5bbe892 EC |
1498 | dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; |
1499 | ||
ab9c17a0 JM |
1500 | init_hca.log_uar_sz = ilog2(dev->caps.num_uars); |
1501 | init_hca.uar_page_sz = PAGE_SHIFT - 12; | |
e448834e SM |
1502 | init_hca.mw_enabled = 0; |
1503 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || | |
1504 | dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) | |
1505 | init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; | |
c1b43dca | 1506 | |
ab9c17a0 JM |
1507 | err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); |
1508 | if (err) | |
1509 | goto err_stop_fw; | |
225c7b1f | 1510 | |
ab9c17a0 JM |
1511 | err = mlx4_INIT_HCA(dev, &init_hca); |
1512 | if (err) { | |
1513 | mlx4_err(dev, "INIT_HCA command failed, aborting.\n"); | |
1514 | goto err_free_icm; | |
1515 | } | |
ddd8a6c1 EE |
1516 | /* |
1517 | * If TS is supported by FW | |
1518 | * read HCA frequency by QUERY_HCA command | |
1519 | */ | |
1520 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { | |
1521 | memset(&init_hca, 0, sizeof(init_hca)); | |
1522 | err = mlx4_QUERY_HCA(dev, &init_hca); | |
1523 | if (err) { | |
1524 | mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n"); | |
1525 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1526 | } else { | |
1527 | dev->caps.hca_core_clock = | |
1528 | init_hca.hca_core_clock; | |
1529 | } | |
1530 | ||
1531 | /* In case we got HCA frequency 0 - disable timestamping | |
1532 | * to avoid dividing by zero | |
1533 | */ | |
1534 | if (!dev->caps.hca_core_clock) { | |
1535 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1536 | mlx4_err(dev, | |
1537 | "HCA frequency is 0. Timestamping is not supported."); | |
1538 | } else if (map_internal_clock(dev)) { | |
1539 | /* | |
1540 | * Map internal clock, | |
1541 | * in case of failure disable timestamping | |
1542 | */ | |
1543 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1544 | mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n"); | |
1545 | } | |
1546 | } | |
ab9c17a0 JM |
1547 | } else { |
1548 | err = mlx4_init_slave(dev); | |
1549 | if (err) { | |
5efe5355 JM |
1550 | if (err != -EPROBE_DEFER) |
1551 | mlx4_err(dev, "Failed to initialize slave\n"); | |
bef772eb | 1552 | return err; |
ab9c17a0 | 1553 | } |
225c7b1f | 1554 | |
ab9c17a0 JM |
1555 | err = mlx4_slave_cap(dev); |
1556 | if (err) { | |
1557 | mlx4_err(dev, "Failed to obtain slave caps\n"); | |
1558 | goto err_close; | |
1559 | } | |
225c7b1f RD |
1560 | } |
1561 | ||
ab9c17a0 JM |
1562 | if (map_bf_area(dev)) |
1563 | mlx4_dbg(dev, "Failed to map blue flame area\n"); | |
1564 | ||
1565 | /*Only the master set the ports, all the rest got it from it.*/ | |
1566 | if (!mlx4_is_slave(dev)) | |
1567 | mlx4_set_port_mask(dev); | |
1568 | ||
225c7b1f RD |
1569 | err = mlx4_QUERY_ADAPTER(dev, &adapter); |
1570 | if (err) { | |
1571 | mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n"); | |
bef772eb | 1572 | goto unmap_bf; |
225c7b1f RD |
1573 | } |
1574 | ||
1575 | priv->eq_table.inta_pin = adapter.inta_pin; | |
cd9281d8 | 1576 | memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); |
225c7b1f RD |
1577 | |
1578 | return 0; | |
1579 | ||
bef772eb | 1580 | unmap_bf: |
ddd8a6c1 | 1581 | unmap_internal_clock(dev); |
bef772eb AY |
1582 | unmap_bf_area(dev); |
1583 | ||
225c7b1f | 1584 | err_close: |
41929ed2 DB |
1585 | if (mlx4_is_slave(dev)) |
1586 | mlx4_slave_exit(dev); | |
1587 | else | |
1588 | mlx4_CLOSE_HCA(dev, 0); | |
225c7b1f RD |
1589 | |
1590 | err_free_icm: | |
ab9c17a0 JM |
1591 | if (!mlx4_is_slave(dev)) |
1592 | mlx4_free_icms(dev); | |
225c7b1f RD |
1593 | |
1594 | err_stop_fw: | |
ab9c17a0 JM |
1595 | if (!mlx4_is_slave(dev)) { |
1596 | mlx4_UNMAP_FA(dev); | |
1597 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); | |
1598 | } | |
225c7b1f RD |
1599 | return err; |
1600 | } | |
1601 | ||
f2a3f6a3 OG |
1602 | static int mlx4_init_counters_table(struct mlx4_dev *dev) |
1603 | { | |
1604 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1605 | int nent; | |
1606 | ||
1607 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1608 | return -ENOENT; | |
1609 | ||
1610 | nent = dev->caps.max_counters; | |
1611 | return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); | |
1612 | } | |
1613 | ||
1614 | static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) | |
1615 | { | |
1616 | mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); | |
1617 | } | |
1618 | ||
ba062d52 | 1619 | int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) |
f2a3f6a3 OG |
1620 | { |
1621 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1622 | ||
1623 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1624 | return -ENOENT; | |
1625 | ||
1626 | *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); | |
1627 | if (*idx == -1) | |
1628 | return -ENOMEM; | |
1629 | ||
1630 | return 0; | |
1631 | } | |
ba062d52 JM |
1632 | |
1633 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) | |
1634 | { | |
1635 | u64 out_param; | |
1636 | int err; | |
1637 | ||
1638 | if (mlx4_is_mfunc(dev)) { | |
1639 | err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, | |
1640 | RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, | |
1641 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
1642 | if (!err) | |
1643 | *idx = get_param_l(&out_param); | |
1644 | ||
1645 | return err; | |
1646 | } | |
1647 | return __mlx4_counter_alloc(dev, idx); | |
1648 | } | |
f2a3f6a3 OG |
1649 | EXPORT_SYMBOL_GPL(mlx4_counter_alloc); |
1650 | ||
ba062d52 | 1651 | void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) |
f2a3f6a3 OG |
1652 | { |
1653 | mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx); | |
1654 | return; | |
1655 | } | |
ba062d52 JM |
1656 | |
1657 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) | |
1658 | { | |
e7dbeba8 | 1659 | u64 in_param = 0; |
ba062d52 JM |
1660 | |
1661 | if (mlx4_is_mfunc(dev)) { | |
1662 | set_param_l(&in_param, idx); | |
1663 | mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, | |
1664 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
1665 | MLX4_CMD_WRAPPED); | |
1666 | return; | |
1667 | } | |
1668 | __mlx4_counter_free(dev, idx); | |
1669 | } | |
f2a3f6a3 OG |
1670 | EXPORT_SYMBOL_GPL(mlx4_counter_free); |
1671 | ||
3d73c288 | 1672 | static int mlx4_setup_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1673 | { |
1674 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1675 | int err; | |
7ff93f8b | 1676 | int port; |
9a5aa622 | 1677 | __be32 ib_port_default_caps; |
225c7b1f | 1678 | |
225c7b1f RD |
1679 | err = mlx4_init_uar_table(dev); |
1680 | if (err) { | |
1681 | mlx4_err(dev, "Failed to initialize " | |
1682 | "user access region table, aborting.\n"); | |
1683 | return err; | |
1684 | } | |
1685 | ||
1686 | err = mlx4_uar_alloc(dev, &priv->driver_uar); | |
1687 | if (err) { | |
1688 | mlx4_err(dev, "Failed to allocate driver access region, " | |
1689 | "aborting.\n"); | |
1690 | goto err_uar_table_free; | |
1691 | } | |
1692 | ||
4979d18f | 1693 | priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); |
225c7b1f RD |
1694 | if (!priv->kar) { |
1695 | mlx4_err(dev, "Couldn't map kernel access region, " | |
1696 | "aborting.\n"); | |
1697 | err = -ENOMEM; | |
1698 | goto err_uar_free; | |
1699 | } | |
1700 | ||
1701 | err = mlx4_init_pd_table(dev); | |
1702 | if (err) { | |
1703 | mlx4_err(dev, "Failed to initialize " | |
1704 | "protection domain table, aborting.\n"); | |
1705 | goto err_kar_unmap; | |
1706 | } | |
1707 | ||
012a8ff5 SH |
1708 | err = mlx4_init_xrcd_table(dev); |
1709 | if (err) { | |
1710 | mlx4_err(dev, "Failed to initialize " | |
1711 | "reliable connection domain table, aborting.\n"); | |
1712 | goto err_pd_table_free; | |
1713 | } | |
1714 | ||
225c7b1f RD |
1715 | err = mlx4_init_mr_table(dev); |
1716 | if (err) { | |
1717 | mlx4_err(dev, "Failed to initialize " | |
1718 | "memory region table, aborting.\n"); | |
012a8ff5 | 1719 | goto err_xrcd_table_free; |
225c7b1f RD |
1720 | } |
1721 | ||
fe6f700d YP |
1722 | if (!mlx4_is_slave(dev)) { |
1723 | err = mlx4_init_mcg_table(dev); | |
1724 | if (err) { | |
1725 | mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n"); | |
1726 | goto err_mr_table_free; | |
1727 | } | |
1728 | } | |
1729 | ||
225c7b1f RD |
1730 | err = mlx4_init_eq_table(dev); |
1731 | if (err) { | |
1732 | mlx4_err(dev, "Failed to initialize " | |
1733 | "event queue table, aborting.\n"); | |
fe6f700d | 1734 | goto err_mcg_table_free; |
225c7b1f RD |
1735 | } |
1736 | ||
1737 | err = mlx4_cmd_use_events(dev); | |
1738 | if (err) { | |
1739 | mlx4_err(dev, "Failed to switch to event-driven " | |
1740 | "firmware commands, aborting.\n"); | |
1741 | goto err_eq_table_free; | |
1742 | } | |
1743 | ||
1744 | err = mlx4_NOP(dev); | |
1745 | if (err) { | |
08fb1055 MT |
1746 | if (dev->flags & MLX4_FLAG_MSI_X) { |
1747 | mlx4_warn(dev, "NOP command failed to generate MSI-X " | |
1748 | "interrupt IRQ %d).\n", | |
b8dd786f | 1749 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
08fb1055 MT |
1750 | mlx4_warn(dev, "Trying again without MSI-X.\n"); |
1751 | } else { | |
1752 | mlx4_err(dev, "NOP command failed to generate interrupt " | |
1753 | "(IRQ %d), aborting.\n", | |
b8dd786f | 1754 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
225c7b1f | 1755 | mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); |
08fb1055 | 1756 | } |
225c7b1f RD |
1757 | |
1758 | goto err_cmd_poll; | |
1759 | } | |
1760 | ||
1761 | mlx4_dbg(dev, "NOP command IRQ test passed\n"); | |
1762 | ||
1763 | err = mlx4_init_cq_table(dev); | |
1764 | if (err) { | |
1765 | mlx4_err(dev, "Failed to initialize " | |
1766 | "completion queue table, aborting.\n"); | |
1767 | goto err_cmd_poll; | |
1768 | } | |
1769 | ||
1770 | err = mlx4_init_srq_table(dev); | |
1771 | if (err) { | |
1772 | mlx4_err(dev, "Failed to initialize " | |
1773 | "shared receive queue table, aborting.\n"); | |
1774 | goto err_cq_table_free; | |
1775 | } | |
1776 | ||
1777 | err = mlx4_init_qp_table(dev); | |
1778 | if (err) { | |
1779 | mlx4_err(dev, "Failed to initialize " | |
1780 | "queue pair table, aborting.\n"); | |
1781 | goto err_srq_table_free; | |
1782 | } | |
1783 | ||
f2a3f6a3 OG |
1784 | err = mlx4_init_counters_table(dev); |
1785 | if (err && err != -ENOENT) { | |
1786 | mlx4_err(dev, "Failed to initialize counters table, aborting.\n"); | |
fe6f700d | 1787 | goto err_qp_table_free; |
f2a3f6a3 OG |
1788 | } |
1789 | ||
ab9c17a0 JM |
1790 | if (!mlx4_is_slave(dev)) { |
1791 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
ab9c17a0 JM |
1792 | ib_port_default_caps = 0; |
1793 | err = mlx4_get_port_ib_caps(dev, port, | |
1794 | &ib_port_default_caps); | |
1795 | if (err) | |
1796 | mlx4_warn(dev, "failed to get port %d default " | |
1797 | "ib capabilities (%d). Continuing " | |
1798 | "with caps = 0\n", port, err); | |
1799 | dev->caps.ib_port_def_cap[port] = ib_port_default_caps; | |
1800 | ||
2aca1172 JM |
1801 | /* initialize per-slave default ib port capabilities */ |
1802 | if (mlx4_is_master(dev)) { | |
1803 | int i; | |
1804 | for (i = 0; i < dev->num_slaves; i++) { | |
1805 | if (i == mlx4_master_func_num(dev)) | |
1806 | continue; | |
1807 | priv->mfunc.master.slave_state[i].ib_cap_mask[port] = | |
1808 | ib_port_default_caps; | |
1809 | } | |
1810 | } | |
1811 | ||
096335b3 OG |
1812 | if (mlx4_is_mfunc(dev)) |
1813 | dev->caps.port_ib_mtu[port] = IB_MTU_2048; | |
1814 | else | |
1815 | dev->caps.port_ib_mtu[port] = IB_MTU_4096; | |
97285b78 | 1816 | |
6634961c JM |
1817 | err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? |
1818 | dev->caps.pkey_table_len[port] : -1); | |
ab9c17a0 JM |
1819 | if (err) { |
1820 | mlx4_err(dev, "Failed to set port %d, aborting\n", | |
1821 | port); | |
1822 | goto err_counters_table_free; | |
1823 | } | |
7ff93f8b YP |
1824 | } |
1825 | } | |
1826 | ||
225c7b1f RD |
1827 | return 0; |
1828 | ||
f2a3f6a3 OG |
1829 | err_counters_table_free: |
1830 | mlx4_cleanup_counters_table(dev); | |
1831 | ||
225c7b1f RD |
1832 | err_qp_table_free: |
1833 | mlx4_cleanup_qp_table(dev); | |
1834 | ||
1835 | err_srq_table_free: | |
1836 | mlx4_cleanup_srq_table(dev); | |
1837 | ||
1838 | err_cq_table_free: | |
1839 | mlx4_cleanup_cq_table(dev); | |
1840 | ||
1841 | err_cmd_poll: | |
1842 | mlx4_cmd_use_polling(dev); | |
1843 | ||
1844 | err_eq_table_free: | |
1845 | mlx4_cleanup_eq_table(dev); | |
1846 | ||
fe6f700d YP |
1847 | err_mcg_table_free: |
1848 | if (!mlx4_is_slave(dev)) | |
1849 | mlx4_cleanup_mcg_table(dev); | |
1850 | ||
ee49bd93 | 1851 | err_mr_table_free: |
225c7b1f RD |
1852 | mlx4_cleanup_mr_table(dev); |
1853 | ||
012a8ff5 SH |
1854 | err_xrcd_table_free: |
1855 | mlx4_cleanup_xrcd_table(dev); | |
1856 | ||
225c7b1f RD |
1857 | err_pd_table_free: |
1858 | mlx4_cleanup_pd_table(dev); | |
1859 | ||
1860 | err_kar_unmap: | |
1861 | iounmap(priv->kar); | |
1862 | ||
1863 | err_uar_free: | |
1864 | mlx4_uar_free(dev, &priv->driver_uar); | |
1865 | ||
1866 | err_uar_table_free: | |
1867 | mlx4_cleanup_uar_table(dev); | |
1868 | return err; | |
1869 | } | |
1870 | ||
e8f9b2ed | 1871 | static void mlx4_enable_msi_x(struct mlx4_dev *dev) |
225c7b1f RD |
1872 | { |
1873 | struct mlx4_priv *priv = mlx4_priv(dev); | |
b8dd786f | 1874 | struct msix_entry *entries; |
0b7ca5a9 | 1875 | int nreq = min_t(int, dev->caps.num_ports * |
90b1ebe7 YM |
1876 | min_t(int, netif_get_num_default_rss_queues() + 1, |
1877 | MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX); | |
225c7b1f RD |
1878 | int err; |
1879 | int i; | |
1880 | ||
1881 | if (msi_x) { | |
ca4c7b35 OG |
1882 | nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, |
1883 | nreq); | |
ab9c17a0 | 1884 | |
b8dd786f YP |
1885 | entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); |
1886 | if (!entries) | |
1887 | goto no_msi; | |
1888 | ||
1889 | for (i = 0; i < nreq; ++i) | |
225c7b1f RD |
1890 | entries[i].entry = i; |
1891 | ||
b8dd786f YP |
1892 | retry: |
1893 | err = pci_enable_msix(dev->pdev, entries, nreq); | |
225c7b1f | 1894 | if (err) { |
b8dd786f YP |
1895 | /* Try again if at least 2 vectors are available */ |
1896 | if (err > 1) { | |
1897 | mlx4_info(dev, "Requested %d vectors, " | |
1898 | "but only %d MSI-X vectors available, " | |
1899 | "trying again\n", nreq, err); | |
1900 | nreq = err; | |
1901 | goto retry; | |
1902 | } | |
5bf0da7d | 1903 | kfree(entries); |
225c7b1f RD |
1904 | goto no_msi; |
1905 | } | |
1906 | ||
0b7ca5a9 YP |
1907 | if (nreq < |
1908 | MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) { | |
1909 | /*Working in legacy mode , all EQ's shared*/ | |
1910 | dev->caps.comp_pool = 0; | |
1911 | dev->caps.num_comp_vectors = nreq - 1; | |
1912 | } else { | |
1913 | dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; | |
1914 | dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; | |
1915 | } | |
b8dd786f | 1916 | for (i = 0; i < nreq; ++i) |
225c7b1f RD |
1917 | priv->eq_table.eq[i].irq = entries[i].vector; |
1918 | ||
1919 | dev->flags |= MLX4_FLAG_MSI_X; | |
b8dd786f YP |
1920 | |
1921 | kfree(entries); | |
225c7b1f RD |
1922 | return; |
1923 | } | |
1924 | ||
1925 | no_msi: | |
b8dd786f | 1926 | dev->caps.num_comp_vectors = 1; |
0b7ca5a9 | 1927 | dev->caps.comp_pool = 0; |
b8dd786f YP |
1928 | |
1929 | for (i = 0; i < 2; ++i) | |
225c7b1f RD |
1930 | priv->eq_table.eq[i].irq = dev->pdev->irq; |
1931 | } | |
1932 | ||
7ff93f8b | 1933 | static int mlx4_init_port_info(struct mlx4_dev *dev, int port) |
2a2336f8 YP |
1934 | { |
1935 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
7ff93f8b | 1936 | int err = 0; |
2a2336f8 YP |
1937 | |
1938 | info->dev = dev; | |
1939 | info->port = port; | |
ab9c17a0 | 1940 | if (!mlx4_is_slave(dev)) { |
ab9c17a0 JM |
1941 | mlx4_init_mac_table(dev, &info->mac_table); |
1942 | mlx4_init_vlan_table(dev, &info->vlan_table); | |
16a10ffd | 1943 | info->base_qpn = mlx4_get_base_qpn(dev, port); |
ab9c17a0 | 1944 | } |
7ff93f8b YP |
1945 | |
1946 | sprintf(info->dev_name, "mlx4_port%d", port); | |
1947 | info->port_attr.attr.name = info->dev_name; | |
ab9c17a0 JM |
1948 | if (mlx4_is_mfunc(dev)) |
1949 | info->port_attr.attr.mode = S_IRUGO; | |
1950 | else { | |
1951 | info->port_attr.attr.mode = S_IRUGO | S_IWUSR; | |
1952 | info->port_attr.store = set_port_type; | |
1953 | } | |
7ff93f8b | 1954 | info->port_attr.show = show_port_type; |
3691c964 | 1955 | sysfs_attr_init(&info->port_attr.attr); |
7ff93f8b YP |
1956 | |
1957 | err = device_create_file(&dev->pdev->dev, &info->port_attr); | |
1958 | if (err) { | |
1959 | mlx4_err(dev, "Failed to create file for port %d\n", port); | |
1960 | info->port = -1; | |
1961 | } | |
1962 | ||
096335b3 OG |
1963 | sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); |
1964 | info->port_mtu_attr.attr.name = info->dev_mtu_name; | |
1965 | if (mlx4_is_mfunc(dev)) | |
1966 | info->port_mtu_attr.attr.mode = S_IRUGO; | |
1967 | else { | |
1968 | info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; | |
1969 | info->port_mtu_attr.store = set_port_ib_mtu; | |
1970 | } | |
1971 | info->port_mtu_attr.show = show_port_ib_mtu; | |
1972 | sysfs_attr_init(&info->port_mtu_attr.attr); | |
1973 | ||
1974 | err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); | |
1975 | if (err) { | |
1976 | mlx4_err(dev, "Failed to create mtu file for port %d\n", port); | |
1977 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
1978 | info->port = -1; | |
1979 | } | |
1980 | ||
7ff93f8b YP |
1981 | return err; |
1982 | } | |
1983 | ||
1984 | static void mlx4_cleanup_port_info(struct mlx4_port_info *info) | |
1985 | { | |
1986 | if (info->port < 0) | |
1987 | return; | |
1988 | ||
1989 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
096335b3 | 1990 | device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); |
2a2336f8 YP |
1991 | } |
1992 | ||
b12d93d6 YP |
1993 | static int mlx4_init_steering(struct mlx4_dev *dev) |
1994 | { | |
1995 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1996 | int num_entries = dev->caps.num_ports; | |
1997 | int i, j; | |
1998 | ||
1999 | priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); | |
2000 | if (!priv->steer) | |
2001 | return -ENOMEM; | |
2002 | ||
45b51365 | 2003 | for (i = 0; i < num_entries; i++) |
b12d93d6 YP |
2004 | for (j = 0; j < MLX4_NUM_STEERS; j++) { |
2005 | INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); | |
2006 | INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); | |
2007 | } | |
b12d93d6 YP |
2008 | return 0; |
2009 | } | |
2010 | ||
2011 | static void mlx4_clear_steering(struct mlx4_dev *dev) | |
2012 | { | |
2013 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2014 | struct mlx4_steer_index *entry, *tmp_entry; | |
2015 | struct mlx4_promisc_qp *pqp, *tmp_pqp; | |
2016 | int num_entries = dev->caps.num_ports; | |
2017 | int i, j; | |
2018 | ||
2019 | for (i = 0; i < num_entries; i++) { | |
2020 | for (j = 0; j < MLX4_NUM_STEERS; j++) { | |
2021 | list_for_each_entry_safe(pqp, tmp_pqp, | |
2022 | &priv->steer[i].promisc_qps[j], | |
2023 | list) { | |
2024 | list_del(&pqp->list); | |
2025 | kfree(pqp); | |
2026 | } | |
2027 | list_for_each_entry_safe(entry, tmp_entry, | |
2028 | &priv->steer[i].steer_entries[j], | |
2029 | list) { | |
2030 | list_del(&entry->list); | |
2031 | list_for_each_entry_safe(pqp, tmp_pqp, | |
2032 | &entry->duplicates, | |
2033 | list) { | |
2034 | list_del(&pqp->list); | |
2035 | kfree(pqp); | |
2036 | } | |
2037 | kfree(entry); | |
2038 | } | |
2039 | } | |
2040 | } | |
2041 | kfree(priv->steer); | |
2042 | } | |
2043 | ||
ab9c17a0 JM |
2044 | static int extended_func_num(struct pci_dev *pdev) |
2045 | { | |
2046 | return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); | |
2047 | } | |
2048 | ||
2049 | #define MLX4_OWNER_BASE 0x8069c | |
2050 | #define MLX4_OWNER_SIZE 4 | |
2051 | ||
2052 | static int mlx4_get_ownership(struct mlx4_dev *dev) | |
2053 | { | |
2054 | void __iomem *owner; | |
2055 | u32 ret; | |
2056 | ||
57dbf29a KSS |
2057 | if (pci_channel_offline(dev->pdev)) |
2058 | return -EIO; | |
2059 | ||
ab9c17a0 JM |
2060 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, |
2061 | MLX4_OWNER_SIZE); | |
2062 | if (!owner) { | |
2063 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
2064 | return -ENOMEM; | |
2065 | } | |
2066 | ||
2067 | ret = readl(owner); | |
2068 | iounmap(owner); | |
2069 | return (int) !!ret; | |
2070 | } | |
2071 | ||
2072 | static void mlx4_free_ownership(struct mlx4_dev *dev) | |
2073 | { | |
2074 | void __iomem *owner; | |
2075 | ||
57dbf29a KSS |
2076 | if (pci_channel_offline(dev->pdev)) |
2077 | return; | |
2078 | ||
ab9c17a0 JM |
2079 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, |
2080 | MLX4_OWNER_SIZE); | |
2081 | if (!owner) { | |
2082 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
2083 | return; | |
2084 | } | |
2085 | writel(0, owner); | |
2086 | msleep(1000); | |
2087 | iounmap(owner); | |
2088 | } | |
2089 | ||
839f1243 | 2090 | static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data) |
225c7b1f | 2091 | { |
225c7b1f RD |
2092 | struct mlx4_priv *priv; |
2093 | struct mlx4_dev *dev; | |
2094 | int err; | |
2a2336f8 | 2095 | int port; |
225c7b1f | 2096 | |
0a645e80 | 2097 | pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); |
225c7b1f RD |
2098 | |
2099 | err = pci_enable_device(pdev); | |
2100 | if (err) { | |
2101 | dev_err(&pdev->dev, "Cannot enable PCI device, " | |
2102 | "aborting.\n"); | |
2103 | return err; | |
2104 | } | |
ab9c17a0 JM |
2105 | if (num_vfs > MLX4_MAX_NUM_VF) { |
2106 | printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n", | |
2107 | num_vfs, MLX4_MAX_NUM_VF); | |
2108 | return -EINVAL; | |
2109 | } | |
30e514a7 JM |
2110 | |
2111 | if (num_vfs < 0) { | |
2112 | pr_err("num_vfs module parameter cannot be negative\n"); | |
2113 | return -EINVAL; | |
2114 | } | |
225c7b1f | 2115 | /* |
ab9c17a0 | 2116 | * Check for BARs. |
225c7b1f | 2117 | */ |
839f1243 | 2118 | if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && |
ab9c17a0 JM |
2119 | !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { |
2120 | dev_err(&pdev->dev, "Missing DCS, aborting." | |
839f1243 RD |
2121 | "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", |
2122 | pci_dev_data, pci_resource_flags(pdev, 0)); | |
225c7b1f RD |
2123 | err = -ENODEV; |
2124 | goto err_disable_pdev; | |
2125 | } | |
2126 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
2127 | dev_err(&pdev->dev, "Missing UAR, aborting.\n"); | |
2128 | err = -ENODEV; | |
2129 | goto err_disable_pdev; | |
2130 | } | |
2131 | ||
a01df0fe | 2132 | err = pci_request_regions(pdev, DRV_NAME); |
225c7b1f | 2133 | if (err) { |
a01df0fe | 2134 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); |
225c7b1f RD |
2135 | goto err_disable_pdev; |
2136 | } | |
2137 | ||
225c7b1f RD |
2138 | pci_set_master(pdev); |
2139 | ||
6a35528a | 2140 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
225c7b1f RD |
2141 | if (err) { |
2142 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); | |
284901a9 | 2143 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
225c7b1f RD |
2144 | if (err) { |
2145 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); | |
a01df0fe | 2146 | goto err_release_regions; |
225c7b1f RD |
2147 | } |
2148 | } | |
6a35528a | 2149 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
225c7b1f RD |
2150 | if (err) { |
2151 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " | |
2152 | "consistent PCI DMA mask.\n"); | |
284901a9 | 2153 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
225c7b1f RD |
2154 | if (err) { |
2155 | dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " | |
2156 | "aborting.\n"); | |
a01df0fe | 2157 | goto err_release_regions; |
225c7b1f RD |
2158 | } |
2159 | } | |
2160 | ||
7f9e5c48 DD |
2161 | /* Allow large DMA segments, up to the firmware limit of 1 GB */ |
2162 | dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); | |
2163 | ||
b2adaca9 | 2164 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
225c7b1f | 2165 | if (!priv) { |
225c7b1f | 2166 | err = -ENOMEM; |
a01df0fe | 2167 | goto err_release_regions; |
225c7b1f RD |
2168 | } |
2169 | ||
2170 | dev = &priv->dev; | |
2171 | dev->pdev = pdev; | |
b581401e RD |
2172 | INIT_LIST_HEAD(&priv->ctx_list); |
2173 | spin_lock_init(&priv->ctx_lock); | |
225c7b1f | 2174 | |
7ff93f8b YP |
2175 | mutex_init(&priv->port_mutex); |
2176 | ||
6296883c YP |
2177 | INIT_LIST_HEAD(&priv->pgdir_list); |
2178 | mutex_init(&priv->pgdir_mutex); | |
2179 | ||
c1b43dca EC |
2180 | INIT_LIST_HEAD(&priv->bf_list); |
2181 | mutex_init(&priv->bf_mutex); | |
2182 | ||
aca7a3ac | 2183 | dev->rev_id = pdev->revision; |
ab9c17a0 | 2184 | /* Detect if this device is a virtual function */ |
839f1243 | 2185 | if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { |
ab9c17a0 JM |
2186 | /* When acting as pf, we normally skip vfs unless explicitly |
2187 | * requested to probe them. */ | |
2188 | if (num_vfs && extended_func_num(pdev) > probe_vf) { | |
2189 | mlx4_warn(dev, "Skipping virtual function:%d\n", | |
2190 | extended_func_num(pdev)); | |
2191 | err = -ENODEV; | |
2192 | goto err_free_dev; | |
2193 | } | |
2194 | mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); | |
2195 | dev->flags |= MLX4_FLAG_SLAVE; | |
2196 | } else { | |
2197 | /* We reset the device and enable SRIOV only for physical | |
2198 | * devices. Try to claim ownership on the device; | |
2199 | * if already taken, skip -- do not allow multiple PFs */ | |
2200 | err = mlx4_get_ownership(dev); | |
2201 | if (err) { | |
2202 | if (err < 0) | |
2203 | goto err_free_dev; | |
2204 | else { | |
2205 | mlx4_warn(dev, "Multiple PFs not yet supported." | |
2206 | " Skipping PF.\n"); | |
2207 | err = -EINVAL; | |
2208 | goto err_free_dev; | |
2209 | } | |
2210 | } | |
aca7a3ac | 2211 | |
ab9c17a0 | 2212 | if (num_vfs) { |
84b1f153 | 2213 | mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs); |
ab9c17a0 JM |
2214 | err = pci_enable_sriov(pdev, num_vfs); |
2215 | if (err) { | |
84b1f153 RD |
2216 | mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n", |
2217 | err); | |
ab9c17a0 JM |
2218 | err = 0; |
2219 | } else { | |
2220 | mlx4_warn(dev, "Running in master mode\n"); | |
2221 | dev->flags |= MLX4_FLAG_SRIOV | | |
2222 | MLX4_FLAG_MASTER; | |
2223 | dev->num_vfs = num_vfs; | |
2224 | } | |
2225 | } | |
2226 | ||
fe6f700d YP |
2227 | atomic_set(&priv->opreq_count, 0); |
2228 | INIT_WORK(&priv->opreq_task, mlx4_opreq_action); | |
2229 | ||
ab9c17a0 JM |
2230 | /* |
2231 | * Now reset the HCA before we touch the PCI capabilities or | |
2232 | * attempt a firmware command, since a boot ROM may have left | |
2233 | * the HCA in an undefined state. | |
2234 | */ | |
2235 | err = mlx4_reset(dev); | |
2236 | if (err) { | |
2237 | mlx4_err(dev, "Failed to reset HCA, aborting.\n"); | |
2238 | goto err_rel_own; | |
2239 | } | |
225c7b1f RD |
2240 | } |
2241 | ||
ab9c17a0 | 2242 | slave_start: |
521130d1 EE |
2243 | err = mlx4_cmd_init(dev); |
2244 | if (err) { | |
225c7b1f | 2245 | mlx4_err(dev, "Failed to init command interface, aborting.\n"); |
ab9c17a0 JM |
2246 | goto err_sriov; |
2247 | } | |
2248 | ||
2249 | /* In slave functions, the communication channel must be initialized | |
2250 | * before posting commands. Also, init num_slaves before calling | |
2251 | * mlx4_init_hca */ | |
2252 | if (mlx4_is_mfunc(dev)) { | |
2253 | if (mlx4_is_master(dev)) | |
2254 | dev->num_slaves = MLX4_MAX_NUM_SLAVES; | |
2255 | else { | |
2256 | dev->num_slaves = 0; | |
f356fcbe JM |
2257 | err = mlx4_multi_func_init(dev); |
2258 | if (err) { | |
ab9c17a0 JM |
2259 | mlx4_err(dev, "Failed to init slave mfunc" |
2260 | " interface, aborting.\n"); | |
2261 | goto err_cmd; | |
2262 | } | |
2263 | } | |
225c7b1f RD |
2264 | } |
2265 | ||
2266 | err = mlx4_init_hca(dev); | |
ab9c17a0 JM |
2267 | if (err) { |
2268 | if (err == -EACCES) { | |
2269 | /* Not primary Physical function | |
2270 | * Running in slave mode */ | |
2271 | mlx4_cmd_cleanup(dev); | |
2272 | dev->flags |= MLX4_FLAG_SLAVE; | |
2273 | dev->flags &= ~MLX4_FLAG_MASTER; | |
2274 | goto slave_start; | |
2275 | } else | |
2276 | goto err_mfunc; | |
2277 | } | |
2278 | ||
2279 | /* In master functions, the communication channel must be initialized | |
2280 | * after obtaining its address from fw */ | |
2281 | if (mlx4_is_master(dev)) { | |
f356fcbe JM |
2282 | err = mlx4_multi_func_init(dev); |
2283 | if (err) { | |
ab9c17a0 JM |
2284 | mlx4_err(dev, "Failed to init master mfunc" |
2285 | "interface, aborting.\n"); | |
2286 | goto err_close; | |
2287 | } | |
2288 | } | |
225c7b1f | 2289 | |
b8dd786f YP |
2290 | err = mlx4_alloc_eq_table(dev); |
2291 | if (err) | |
ab9c17a0 | 2292 | goto err_master_mfunc; |
b8dd786f | 2293 | |
0b7ca5a9 | 2294 | priv->msix_ctl.pool_bm = 0; |
730c41d5 | 2295 | mutex_init(&priv->msix_ctl.pool_lock); |
0b7ca5a9 | 2296 | |
08fb1055 | 2297 | mlx4_enable_msi_x(dev); |
ab9c17a0 JM |
2298 | if ((mlx4_is_mfunc(dev)) && |
2299 | !(dev->flags & MLX4_FLAG_MSI_X)) { | |
f356fcbe | 2300 | err = -ENOSYS; |
ab9c17a0 JM |
2301 | mlx4_err(dev, "INTx is not supported in multi-function mode." |
2302 | " aborting.\n"); | |
b12d93d6 | 2303 | goto err_free_eq; |
ab9c17a0 JM |
2304 | } |
2305 | ||
2306 | if (!mlx4_is_slave(dev)) { | |
2307 | err = mlx4_init_steering(dev); | |
2308 | if (err) | |
2309 | goto err_free_eq; | |
2310 | } | |
b12d93d6 | 2311 | |
225c7b1f | 2312 | err = mlx4_setup_hca(dev); |
ab9c17a0 JM |
2313 | if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && |
2314 | !mlx4_is_mfunc(dev)) { | |
08fb1055 | 2315 | dev->flags &= ~MLX4_FLAG_MSI_X; |
9858d2d1 YP |
2316 | dev->caps.num_comp_vectors = 1; |
2317 | dev->caps.comp_pool = 0; | |
08fb1055 MT |
2318 | pci_disable_msix(pdev); |
2319 | err = mlx4_setup_hca(dev); | |
2320 | } | |
2321 | ||
225c7b1f | 2322 | if (err) |
b12d93d6 | 2323 | goto err_steer; |
225c7b1f | 2324 | |
7ff93f8b YP |
2325 | for (port = 1; port <= dev->caps.num_ports; port++) { |
2326 | err = mlx4_init_port_info(dev, port); | |
2327 | if (err) | |
2328 | goto err_port; | |
2329 | } | |
2a2336f8 | 2330 | |
225c7b1f RD |
2331 | err = mlx4_register_device(dev); |
2332 | if (err) | |
7ff93f8b | 2333 | goto err_port; |
225c7b1f | 2334 | |
b046ffe5 EP |
2335 | mlx4_request_modules(dev); |
2336 | ||
27bf91d6 YP |
2337 | mlx4_sense_init(dev); |
2338 | mlx4_start_sense(dev); | |
2339 | ||
839f1243 | 2340 | priv->pci_dev_data = pci_dev_data; |
225c7b1f RD |
2341 | pci_set_drvdata(pdev, dev); |
2342 | ||
2343 | return 0; | |
2344 | ||
7ff93f8b | 2345 | err_port: |
b4f77264 | 2346 | for (--port; port >= 1; --port) |
7ff93f8b YP |
2347 | mlx4_cleanup_port_info(&priv->port[port]); |
2348 | ||
f2a3f6a3 | 2349 | mlx4_cleanup_counters_table(dev); |
225c7b1f RD |
2350 | mlx4_cleanup_qp_table(dev); |
2351 | mlx4_cleanup_srq_table(dev); | |
2352 | mlx4_cleanup_cq_table(dev); | |
2353 | mlx4_cmd_use_polling(dev); | |
2354 | mlx4_cleanup_eq_table(dev); | |
fe6f700d | 2355 | mlx4_cleanup_mcg_table(dev); |
225c7b1f | 2356 | mlx4_cleanup_mr_table(dev); |
012a8ff5 | 2357 | mlx4_cleanup_xrcd_table(dev); |
225c7b1f RD |
2358 | mlx4_cleanup_pd_table(dev); |
2359 | mlx4_cleanup_uar_table(dev); | |
2360 | ||
b12d93d6 | 2361 | err_steer: |
ab9c17a0 JM |
2362 | if (!mlx4_is_slave(dev)) |
2363 | mlx4_clear_steering(dev); | |
b12d93d6 | 2364 | |
b8dd786f YP |
2365 | err_free_eq: |
2366 | mlx4_free_eq_table(dev); | |
2367 | ||
ab9c17a0 JM |
2368 | err_master_mfunc: |
2369 | if (mlx4_is_master(dev)) | |
2370 | mlx4_multi_func_cleanup(dev); | |
2371 | ||
225c7b1f | 2372 | err_close: |
08fb1055 MT |
2373 | if (dev->flags & MLX4_FLAG_MSI_X) |
2374 | pci_disable_msix(pdev); | |
2375 | ||
225c7b1f RD |
2376 | mlx4_close_hca(dev); |
2377 | ||
ab9c17a0 JM |
2378 | err_mfunc: |
2379 | if (mlx4_is_slave(dev)) | |
2380 | mlx4_multi_func_cleanup(dev); | |
2381 | ||
225c7b1f RD |
2382 | err_cmd: |
2383 | mlx4_cmd_cleanup(dev); | |
2384 | ||
ab9c17a0 | 2385 | err_sriov: |
681372a7 | 2386 | if (dev->flags & MLX4_FLAG_SRIOV) |
ab9c17a0 JM |
2387 | pci_disable_sriov(pdev); |
2388 | ||
2389 | err_rel_own: | |
2390 | if (!mlx4_is_slave(dev)) | |
2391 | mlx4_free_ownership(dev); | |
2392 | ||
225c7b1f | 2393 | err_free_dev: |
225c7b1f RD |
2394 | kfree(priv); |
2395 | ||
a01df0fe RD |
2396 | err_release_regions: |
2397 | pci_release_regions(pdev); | |
225c7b1f RD |
2398 | |
2399 | err_disable_pdev: | |
2400 | pci_disable_device(pdev); | |
2401 | pci_set_drvdata(pdev, NULL); | |
2402 | return err; | |
2403 | } | |
2404 | ||
1dd06ae8 | 2405 | static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
3d73c288 | 2406 | { |
0a645e80 | 2407 | printk_once(KERN_INFO "%s", mlx4_version); |
3d73c288 | 2408 | |
839f1243 | 2409 | return __mlx4_init_one(pdev, id->driver_data); |
3d73c288 RD |
2410 | } |
2411 | ||
2412 | static void mlx4_remove_one(struct pci_dev *pdev) | |
225c7b1f RD |
2413 | { |
2414 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
2415 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2416 | int p; | |
2417 | ||
2418 | if (dev) { | |
ab9c17a0 JM |
2419 | /* in SRIOV it is not allowed to unload the pf's |
2420 | * driver while there are alive vf's */ | |
2421 | if (mlx4_is_master(dev)) { | |
2422 | if (mlx4_how_many_lives_vf(dev)) | |
2423 | printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n"); | |
2424 | } | |
27bf91d6 | 2425 | mlx4_stop_sense(dev); |
225c7b1f RD |
2426 | mlx4_unregister_device(dev); |
2427 | ||
7ff93f8b YP |
2428 | for (p = 1; p <= dev->caps.num_ports; p++) { |
2429 | mlx4_cleanup_port_info(&priv->port[p]); | |
225c7b1f | 2430 | mlx4_CLOSE_PORT(dev, p); |
7ff93f8b | 2431 | } |
225c7b1f | 2432 | |
b8924951 JM |
2433 | if (mlx4_is_master(dev)) |
2434 | mlx4_free_resource_tracker(dev, | |
2435 | RES_TR_FREE_SLAVES_ONLY); | |
2436 | ||
f2a3f6a3 | 2437 | mlx4_cleanup_counters_table(dev); |
225c7b1f RD |
2438 | mlx4_cleanup_qp_table(dev); |
2439 | mlx4_cleanup_srq_table(dev); | |
2440 | mlx4_cleanup_cq_table(dev); | |
2441 | mlx4_cmd_use_polling(dev); | |
2442 | mlx4_cleanup_eq_table(dev); | |
fe6f700d | 2443 | mlx4_cleanup_mcg_table(dev); |
225c7b1f | 2444 | mlx4_cleanup_mr_table(dev); |
012a8ff5 | 2445 | mlx4_cleanup_xrcd_table(dev); |
225c7b1f RD |
2446 | mlx4_cleanup_pd_table(dev); |
2447 | ||
ab9c17a0 | 2448 | if (mlx4_is_master(dev)) |
b8924951 JM |
2449 | mlx4_free_resource_tracker(dev, |
2450 | RES_TR_FREE_STRUCTS_ONLY); | |
ab9c17a0 | 2451 | |
225c7b1f RD |
2452 | iounmap(priv->kar); |
2453 | mlx4_uar_free(dev, &priv->driver_uar); | |
2454 | mlx4_cleanup_uar_table(dev); | |
ab9c17a0 JM |
2455 | if (!mlx4_is_slave(dev)) |
2456 | mlx4_clear_steering(dev); | |
b8dd786f | 2457 | mlx4_free_eq_table(dev); |
ab9c17a0 JM |
2458 | if (mlx4_is_master(dev)) |
2459 | mlx4_multi_func_cleanup(dev); | |
225c7b1f | 2460 | mlx4_close_hca(dev); |
ab9c17a0 JM |
2461 | if (mlx4_is_slave(dev)) |
2462 | mlx4_multi_func_cleanup(dev); | |
225c7b1f RD |
2463 | mlx4_cmd_cleanup(dev); |
2464 | ||
2465 | if (dev->flags & MLX4_FLAG_MSI_X) | |
2466 | pci_disable_msix(pdev); | |
681372a7 | 2467 | if (dev->flags & MLX4_FLAG_SRIOV) { |
84b1f153 | 2468 | mlx4_warn(dev, "Disabling SR-IOV\n"); |
ab9c17a0 JM |
2469 | pci_disable_sriov(pdev); |
2470 | } | |
225c7b1f | 2471 | |
ab9c17a0 JM |
2472 | if (!mlx4_is_slave(dev)) |
2473 | mlx4_free_ownership(dev); | |
47605df9 JM |
2474 | |
2475 | kfree(dev->caps.qp0_tunnel); | |
2476 | kfree(dev->caps.qp0_proxy); | |
2477 | kfree(dev->caps.qp1_tunnel); | |
2478 | kfree(dev->caps.qp1_proxy); | |
2479 | ||
225c7b1f | 2480 | kfree(priv); |
a01df0fe | 2481 | pci_release_regions(pdev); |
225c7b1f RD |
2482 | pci_disable_device(pdev); |
2483 | pci_set_drvdata(pdev, NULL); | |
2484 | } | |
2485 | } | |
2486 | ||
ee49bd93 JM |
2487 | int mlx4_restart_one(struct pci_dev *pdev) |
2488 | { | |
839f1243 RD |
2489 | struct mlx4_dev *dev = pci_get_drvdata(pdev); |
2490 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2491 | int pci_dev_data; | |
2492 | ||
2493 | pci_dev_data = priv->pci_dev_data; | |
ee49bd93 | 2494 | mlx4_remove_one(pdev); |
839f1243 | 2495 | return __mlx4_init_one(pdev, pci_dev_data); |
ee49bd93 JM |
2496 | } |
2497 | ||
a3aa1884 | 2498 | static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { |
ab9c17a0 | 2499 | /* MT25408 "Hermon" SDR */ |
ca3e57a5 | 2500 | { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2501 | /* MT25408 "Hermon" DDR */ |
ca3e57a5 | 2502 | { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2503 | /* MT25408 "Hermon" QDR */ |
ca3e57a5 | 2504 | { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2505 | /* MT25408 "Hermon" DDR PCIe gen2 */ |
ca3e57a5 | 2506 | { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2507 | /* MT25408 "Hermon" QDR PCIe gen2 */ |
ca3e57a5 | 2508 | { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2509 | /* MT25408 "Hermon" EN 10GigE */ |
ca3e57a5 | 2510 | { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2511 | /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ |
ca3e57a5 | 2512 | { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2513 | /* MT25458 ConnectX EN 10GBASE-T 10GigE */ |
ca3e57a5 | 2514 | { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2515 | /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ |
ca3e57a5 | 2516 | { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2517 | /* MT26468 ConnectX EN 10GigE PCIe gen2*/ |
ca3e57a5 | 2518 | { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2519 | /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ |
ca3e57a5 | 2520 | { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2521 | /* MT26478 ConnectX2 40GigE PCIe gen2 */ |
ca3e57a5 | 2522 | { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2523 | /* MT25400 Family [ConnectX-2 Virtual Function] */ |
839f1243 | 2524 | { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, |
ab9c17a0 JM |
2525 | /* MT27500 Family [ConnectX-3] */ |
2526 | { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, | |
2527 | /* MT27500 Family [ConnectX-3 Virtual Function] */ | |
839f1243 | 2528 | { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, |
ab9c17a0 JM |
2529 | { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ |
2530 | { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ | |
2531 | { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ | |
2532 | { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ | |
2533 | { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ | |
2534 | { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ | |
2535 | { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ | |
2536 | { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ | |
2537 | { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ | |
2538 | { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ | |
2539 | { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ | |
2540 | { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ | |
225c7b1f RD |
2541 | { 0, } |
2542 | }; | |
2543 | ||
2544 | MODULE_DEVICE_TABLE(pci, mlx4_pci_table); | |
2545 | ||
57dbf29a KSS |
2546 | static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, |
2547 | pci_channel_state_t state) | |
2548 | { | |
2549 | mlx4_remove_one(pdev); | |
2550 | ||
2551 | return state == pci_channel_io_perm_failure ? | |
2552 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
2553 | } | |
2554 | ||
2555 | static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) | |
2556 | { | |
839f1243 | 2557 | int ret = __mlx4_init_one(pdev, 0); |
57dbf29a KSS |
2558 | |
2559 | return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
2560 | } | |
2561 | ||
3646f0e5 | 2562 | static const struct pci_error_handlers mlx4_err_handler = { |
57dbf29a KSS |
2563 | .error_detected = mlx4_pci_err_detected, |
2564 | .slot_reset = mlx4_pci_slot_reset, | |
2565 | }; | |
2566 | ||
225c7b1f RD |
2567 | static struct pci_driver mlx4_driver = { |
2568 | .name = DRV_NAME, | |
2569 | .id_table = mlx4_pci_table, | |
2570 | .probe = mlx4_init_one, | |
f57e6848 | 2571 | .remove = mlx4_remove_one, |
57dbf29a | 2572 | .err_handler = &mlx4_err_handler, |
225c7b1f RD |
2573 | }; |
2574 | ||
7ff93f8b YP |
2575 | static int __init mlx4_verify_params(void) |
2576 | { | |
2577 | if ((log_num_mac < 0) || (log_num_mac > 7)) { | |
0a645e80 | 2578 | pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac); |
7ff93f8b YP |
2579 | return -1; |
2580 | } | |
2581 | ||
cb29688a OG |
2582 | if (log_num_vlan != 0) |
2583 | pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n", | |
2584 | MLX4_LOG_NUM_VLANS); | |
7ff93f8b | 2585 | |
0498628f | 2586 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { |
0a645e80 | 2587 | pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); |
ab6bf42e EC |
2588 | return -1; |
2589 | } | |
2590 | ||
ab9c17a0 JM |
2591 | /* Check if module param for ports type has legal combination */ |
2592 | if (port_type_array[0] == false && port_type_array[1] == true) { | |
2593 | printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); | |
2594 | port_type_array[0] = true; | |
2595 | } | |
2596 | ||
3c439b55 JM |
2597 | if (mlx4_log_num_mgm_entry_size != -1 && |
2598 | (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || | |
2599 | mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { | |
2600 | pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not " | |
2601 | "in legal range (-1 or %d..%d)\n", | |
2602 | mlx4_log_num_mgm_entry_size, | |
2603 | MLX4_MIN_MGM_LOG_ENTRY_SIZE, | |
2604 | MLX4_MAX_MGM_LOG_ENTRY_SIZE); | |
2605 | return -1; | |
2606 | } | |
2607 | ||
7ff93f8b YP |
2608 | return 0; |
2609 | } | |
2610 | ||
225c7b1f RD |
2611 | static int __init mlx4_init(void) |
2612 | { | |
2613 | int ret; | |
2614 | ||
7ff93f8b YP |
2615 | if (mlx4_verify_params()) |
2616 | return -EINVAL; | |
2617 | ||
27bf91d6 YP |
2618 | mlx4_catas_init(); |
2619 | ||
2620 | mlx4_wq = create_singlethread_workqueue("mlx4"); | |
2621 | if (!mlx4_wq) | |
2622 | return -ENOMEM; | |
ee49bd93 | 2623 | |
225c7b1f RD |
2624 | ret = pci_register_driver(&mlx4_driver); |
2625 | return ret < 0 ? ret : 0; | |
2626 | } | |
2627 | ||
2628 | static void __exit mlx4_cleanup(void) | |
2629 | { | |
2630 | pci_unregister_driver(&mlx4_driver); | |
27bf91d6 | 2631 | destroy_workqueue(mlx4_wq); |
225c7b1f RD |
2632 | } |
2633 | ||
2634 | module_init(mlx4_init); | |
2635 | module_exit(mlx4_cleanup); |