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net/mlx4_core: Deprecate use_prio module parameter
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
dd41cc3b
MB		 80static uint8_t num_vfs[3] = {0, 0, 0};
81static int num_vfs_argc = 3;
82module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86static uint8_t probe_vf[3] = {0, 0, 0};
87static int probe_vfs_argc = 3;
88module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
ab9c17a0 91
3c439b55 92int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 93module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
3c439b55 97 " 10 gives 248.range: 7 <="
0ff1fb65 98 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 99 " To activate device managed"
100 " flow steering when available, set to -1");
0ec2c0f8 101
be902ab1 102static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 103module_param(enable_64b_cqe_eqe, bool, 0444);
104MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 106
08ff3235 107#define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
ab9c17a0 108
f57e6848 109static char mlx4_version[] =
225c7b1f
RD		 110 DRV_NAME ": Mellanox ConnectX core driver v"
111 DRV_VERSION " (" DRV_RELDATE ")\n";
112
113static struct mlx4_profile default_profile = {
ab9c17a0 114 .num_qp = 1 << 18,
225c7b1f 115 .num_srq = 1 << 16,
c9f2ba5e 116 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 117 .num_cq = 1 << 16,
118 .num_mcg = 1 << 13,
ab9c17a0 119 .num_mpt = 1 << 19,
9fd7a1e1 120 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 121};
122
ab9c17a0 123static int log_num_mac = 7;
93fc9e1b
YP		 124module_param_named(log_num_mac, log_num_mac, int, 0444);
125MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
126
127static int log_num_vlan;
128module_param_named(log_num_vlan, log_num_vlan, int, 0444);
129MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 130/* Log2 max number of VLANs per ETH port (0-7) */
131#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 132
eb939922 133static bool use_prio;
93fc9e1b 134module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 135MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 136
2b8fb286 137int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 138module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 139MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 140
8d0fc7b6 141static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 142static int arr_argc = 2;
143module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 144MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
145 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 146
147struct mlx4_port_config {
148 struct list_head list;
149 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
150 struct pci_dev *pdev;
151};
152
97989356
AV		 153static atomic_t pf_loading = ATOMIC_INIT(0);
154
27bf91d6
YP		 155int mlx4_check_port_params(struct mlx4_dev *dev,
156 enum mlx4_port_type *port_type)
7ff93f8b
YP		 157{
158 int i;
159
160 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 161 if (port_type[i] != port_type[i + 1]) {
162 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
1a91de28 163 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 164 return -EINVAL;
165 }
7ff93f8b
YP		 166 }
167 }
7ff93f8b
YP		 168
169 for (i = 0; i < dev->caps.num_ports; i++) {
170 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 171 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
172 i + 1);
7ff93f8b
YP		 173 return -EINVAL;
174 }
175 }
176 return 0;
177}
178
179static void mlx4_set_port_mask(struct mlx4_dev *dev)
180{
181 int i;
182
7ff93f8b 183 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 184 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 185}
f2a3f6a3 186
3d73c288 187static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 188{
189 int err;
5ae2a7a8 190 int i;
225c7b1f
RD		 191
192 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
193 if (err) {
1a91de28 194 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 195 return err;
196 }
197
198 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 199 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 200 dev_cap->min_page_sz, PAGE_SIZE);
201 return -ENODEV;
202 }
203 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 204 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 205 dev_cap->num_ports, MLX4_MAX_PORTS);
206 return -ENODEV;
207 }
208
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
1a91de28 210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f
RD		 211 dev_cap->uar_size,
212 (unsigned long long) pci_resource_len(dev->pdev, 2));
213 return -ENODEV;
214 }
215
216 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 217 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 218 for (i = 1; i <= dev->caps.num_ports; ++i) {
219 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 220 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 221 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
222 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
223 /* set gid and pkey table operating lengths by default
224 * to non-sriov values */
5ae2a7a8
RD		 225 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
226 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
227 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 228 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
229 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 230 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 231 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
232 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 233 dev->caps.trans_type[i] = dev_cap->trans_type[i];
234 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
235 dev->caps.wavelength[i] = dev_cap->wavelength[i];
236 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 237 }
238
ab9c17a0 239 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 240 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 241 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
242 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
243 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
244 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
245 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
246 dev->caps.max_wqes = dev_cap->max_qp_sz;
247 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 248 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
249 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
250 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
251 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
252 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 253 /*
254 * Subtract 1 from the limit because we need to allocate a
255 * spare CQE so the HCA HW can tell the difference between an
256 * empty CQ and a full CQ.
257 */
258 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
259 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
260 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 261 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 262 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 263
264 /* The first 128 UARs are used for EQ doorbells */
265 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 266 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 267 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
268 dev_cap->reserved_xrcds : 0;
269 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
270 dev_cap->max_xrcds : 0;
2b8fb286
MA		 271 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
272
149983af 273 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 274 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
275 dev->caps.flags = dev_cap->flags;
b3416f44 276 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 277 dev->caps.bmme_flags = dev_cap->bmme_flags;
278 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 279 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 280 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 281 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 282
ca3e57a5
RD		 283 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
284 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 285 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 286 /* Don't do sense port on multifunction devices (for now at least) */
287 if (mlx4_is_mfunc(dev))
288 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 289
93fc9e1b 290 dev->caps.log_num_macs = log_num_mac;
cb29688a 291 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 292
293 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 294 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
295 if (dev->caps.supported_type[i]) {
296 /* if only ETH is supported - assign ETH */
297 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
298 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 299 /* if only IB is supported, assign IB */
ab9c17a0 300 else if (dev->caps.supported_type[i] ==
105c320f
JM		 301 MLX4_PORT_TYPE_IB)
302 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 303 else {
105c320f
JM		 304 /* if IB and ETH are supported, we set the port
305 * type according to user selection of port type;
306 * if user selected none, take the FW hint */
307 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 308 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
309 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 310 else
105c320f 311 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 312 }
313 }
8d0fc7b6
YP		 314 /*
315 * Link sensing is allowed on the port if 3 conditions are true:
316 * 1. Both protocols are supported on the port.
317 * 2. Different types are supported on the port
318 * 3. FW declared that it supports link sensing
319 */
27bf91d6 320 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 321 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 322 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 323 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 324
8d0fc7b6
YP		 325 /*
326 * If "default_sense" bit is set, we move the port to "AUTO" mode
327 * and perform sense_port FW command to try and set the correct
328 * port type from beginning
329 */
46c46747 330 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 331 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
332 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
333 mlx4_SENSE_PORT(dev, i, &sensed_port);
334 if (sensed_port != MLX4_PORT_TYPE_NONE)
335 dev->caps.port_type[i] = sensed_port;
336 } else {
337 dev->caps.possible_type[i] = dev->caps.port_type[i];
338 }
339
93fc9e1b
YP		 340 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
341 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
1a91de28 342 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 343 i, 1 << dev->caps.log_num_macs);
344 }
345 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
346 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
1a91de28 347 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 348 i, 1 << dev->caps.log_num_vlans);
349 }
350 }
351
f2a3f6a3
OG		 352 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
353
93fc9e1b
YP		 354 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
355 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
356 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
357 (1 << dev->caps.log_num_macs) *
358 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 359 dev->caps.num_ports;
360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
361
362 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
363 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
364 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
366
e2c76824 367 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 368
b3051320 369 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 370 if (dev_cap->flags &
371 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
372 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
373 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
374 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
375 }
376 }
377
f97b4b5d 378 if ((dev->caps.flags &
08ff3235
OG		 379 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
380 mlx4_is_master(dev))
381 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
382
225c7b1f
RD		 383 return 0;
384}
b912b2f8
EP		 385
386static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
387 enum pci_bus_speed *speed,
388 enum pcie_link_width *width)
389{
390 u32 lnkcap1, lnkcap2;
391 int err1, err2;
392
393#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
394
395 *speed = PCI_SPEED_UNKNOWN;
396 *width = PCIE_LNK_WIDTH_UNKNOWN;
397
398 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
399 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
400 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
401 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
402 *speed = PCIE_SPEED_8_0GT;
403 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
404 *speed = PCIE_SPEED_5_0GT;
405 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
406 *speed = PCIE_SPEED_2_5GT;
407 }
408 if (!err1) {
409 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
410 if (!lnkcap2) { /* pre-r3.0 */
411 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
412 *speed = PCIE_SPEED_5_0GT;
413 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
414 *speed = PCIE_SPEED_2_5GT;
415 }
416 }
417
418 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
419 return err1 ? err1 :
420 err2 ? err2 : -EINVAL;
421 }
422 return 0;
423}
424
425static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
426{
427 enum pcie_link_width width, width_cap;
428 enum pci_bus_speed speed, speed_cap;
429 int err;
430
431#define PCIE_SPEED_STR(speed) \
432 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
433 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
434 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
435 "Unknown")
436
437 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
438 if (err) {
439 mlx4_warn(dev,
440 "Unable to determine PCIe device BW capabilities\n");
441 return;
442 }
443
444 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
445 if (err || speed == PCI_SPEED_UNKNOWN ||
446 width == PCIE_LNK_WIDTH_UNKNOWN) {
447 mlx4_warn(dev,
448 "Unable to determine PCI device chain minimum BW\n");
449 return;
450 }
451
452 if (width != width_cap || speed != speed_cap)
453 mlx4_warn(dev,
454 "PCIe BW is different than device's capability\n");
455
456 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
457 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
458 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
459 width, width_cap);
460 return;
461}
462
ab9c17a0
JM		 463/*The function checks if there are live vf, return the num of them*/
464static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
465{
466 struct mlx4_priv *priv = mlx4_priv(dev);
467 struct mlx4_slave_state *s_state;
468 int i;
469 int ret = 0;
470
471 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
472 s_state = &priv->mfunc.master.slave_state[i];
473 if (s_state->active && s_state->last_cmd !=
474 MLX4_COMM_CMD_RESET) {
475 mlx4_warn(dev, "%s: slave: %d is still active\n",
476 __func__, i);
477 ret++;
478 }
479 }
480 return ret;
481}
482
396f2feb
JM		 483int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
484{
485 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 486
487 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
488 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 489 return -EINVAL;
490
47605df9 491 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 492 /* tunnel qp */
47605df9 493 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 494 else
47605df9 495 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 496 *qkey = qk;
497 return 0;
498}
499EXPORT_SYMBOL(mlx4_get_parav_qkey);
500
54679e14
JM		 501void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
502{
503 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
504
505 if (!mlx4_is_master(dev))
506 return;
507
508 priv->virt2phys_pkey[slave][port - 1][i] = val;
509}
510EXPORT_SYMBOL(mlx4_sync_pkey_table);
511
afa8fd1d
JM		 512void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
513{
514 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
515
516 if (!mlx4_is_master(dev))
517 return;
518
519 priv->slave_node_guids[slave] = guid;
520}
521EXPORT_SYMBOL(mlx4_put_slave_node_guid);
522
523__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
524{
525 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
526
527 if (!mlx4_is_master(dev))
528 return 0;
529
530 return priv->slave_node_guids[slave];
531}
532EXPORT_SYMBOL(mlx4_get_slave_node_guid);
533
e10903b0 534int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 535{
536 struct mlx4_priv *priv = mlx4_priv(dev);
537 struct mlx4_slave_state *s_slave;
538
539 if (!mlx4_is_master(dev))
540 return 0;
541
542 s_slave = &priv->mfunc.master.slave_state[slave];
543 return !!s_slave->active;
544}
545EXPORT_SYMBOL(mlx4_is_slave_active);
546
7b8157be
JM		 547static void slave_adjust_steering_mode(struct mlx4_dev *dev,
548 struct mlx4_dev_cap *dev_cap,
549 struct mlx4_init_hca_param *hca_param)
550{
551 dev->caps.steering_mode = hca_param->steering_mode;
552 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
553 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
554 dev->caps.fs_log_max_ucast_qp_range_size =
555 dev_cap->fs_log_max_ucast_qp_range_size;
556 } else
557 dev->caps.num_qp_per_mgm =
558 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
559
560 mlx4_dbg(dev, "Steering mode is: %s\n",
561 mlx4_steering_mode_str(dev->caps.steering_mode));
562}
563
ab9c17a0
JM		 564static int mlx4_slave_cap(struct mlx4_dev *dev)
565{
566 int err;
567 u32 page_size;
568 struct mlx4_dev_cap dev_cap;
569 struct mlx4_func_cap func_cap;
570 struct mlx4_init_hca_param hca_param;
571 int i;
572
573 memset(&hca_param, 0, sizeof(hca_param));
574 err = mlx4_QUERY_HCA(dev, &hca_param);
575 if (err) {
1a91de28 576 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
ab9c17a0
JM		 577 return err;
578 }
579
483e0132
EP		 580 /* fail if the hca has an unknown global capability
581 * at this time global_caps should be always zeroed
582 */
583 if (hca_param.global_caps) {
ab9c17a0
JM		 584 mlx4_err(dev, "Unknown hca global capabilities\n");
585 return -ENOSYS;
586 }
587
588 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
589
ddd8a6c1
EE		 590 dev->caps.hca_core_clock = hca_param.hca_core_clock;
591
ab9c17a0 592 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 593 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 594 err = mlx4_dev_cap(dev, &dev_cap);
595 if (err) {
1a91de28 596 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 597 return err;
598 }
599
b91cb3eb
JM		 600 err = mlx4_QUERY_FW(dev);
601 if (err)
1a91de28 602 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 603
ab9c17a0
JM		 604 page_size = ~dev->caps.page_size_cap + 1;
605 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
606 if (page_size > PAGE_SIZE) {
1a91de28 607 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0
JM		 608 page_size, PAGE_SIZE);
609 return -ENODEV;
610 }
611
612 /* slave gets uar page size from QUERY_HCA fw command */
613 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
614
615 /* TODO: relax this assumption */
616 if (dev->caps.uar_page_size != PAGE_SIZE) {
617 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
618 dev->caps.uar_page_size, PAGE_SIZE);
619 return -ENODEV;
620 }
621
622 memset(&func_cap, 0, sizeof(func_cap));
47605df9 623 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 624 if (err) {
1a91de28
JP		 625 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
626 err);
ab9c17a0
JM		 627 return err;
628 }
629
630 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
631 PF_CONTEXT_BEHAVIOUR_MASK) {
632 mlx4_err(dev, "Unknown pf context behaviour\n");
633 return -ENOSYS;
634 }
635
ab9c17a0 636 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 637 dev->quotas.qp = func_cap.qp_quota;
638 dev->quotas.srq = func_cap.srq_quota;
639 dev->quotas.cq = func_cap.cq_quota;
640 dev->quotas.mpt = func_cap.mpt_quota;
641 dev->quotas.mtt = func_cap.mtt_quota;
642 dev->caps.num_qps = 1 << hca_param.log_num_qps;
643 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
644 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
645 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
646 dev->caps.num_eqs = func_cap.max_eq;
647 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 648 dev->caps.num_pds = MLX4_NUM_PDS;
649 dev->caps.num_mgms = 0;
650 dev->caps.num_amgms = 0;
651
ab9c17a0 652 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 653 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
654 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 655 return -ENODEV;
656 }
657
47605df9
JM		 658 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
659 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
660 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
661 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
662
663 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
664 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
665 err = -ENOMEM;
666 goto err_mem;
667 }
668
6634961c 669 for (i = 1; i <= dev->caps.num_ports; ++i) {
47605df9
JM		 670 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
671 if (err) {
1a91de28
JP		 672 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
673 i, err);
47605df9
JM		 674 goto err_mem;
675 }
676 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
677 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
678 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
679 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 680 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 681 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 682 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
683 &dev->caps.gid_table_len[i],
684 &dev->caps.pkey_table_len[i]))
47605df9 685 goto err_mem;
6634961c 686 }
6230bb23 687
ab9c17a0
JM		 688 if (dev->caps.uar_page_size * (dev->caps.num_uars -
689 dev->caps.reserved_uars) >
690 pci_resource_len(dev->pdev, 2)) {
1a91de28 691 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0
JM		 692 dev->caps.uar_page_size * dev->caps.num_uars,
693 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 694 goto err_mem;
ab9c17a0
JM		 695 }
696
08ff3235
OG		 697 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
698 dev->caps.eqe_size = 64;
699 dev->caps.eqe_factor = 1;
700 } else {
701 dev->caps.eqe_size = 32;
702 dev->caps.eqe_factor = 0;
703 }
704
705 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
706 dev->caps.cqe_size = 64;
707 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
708 } else {
709 dev->caps.cqe_size = 32;
710 }
711
f9bd2d7f 712 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 713 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 714
7b8157be
JM		 715 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
716
ab9c17a0 717 return 0;
47605df9
JM		 718
719err_mem:
720 kfree(dev->caps.qp0_tunnel);
721 kfree(dev->caps.qp0_proxy);
722 kfree(dev->caps.qp1_tunnel);
723 kfree(dev->caps.qp1_proxy);
724 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
725 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
726
727 return err;
ab9c17a0 728}
225c7b1f 729
b046ffe5
EP		 730static void mlx4_request_modules(struct mlx4_dev *dev)
731{
732 int port;
733 int has_ib_port = false;
734 int has_eth_port = false;
735#define EN_DRV_NAME "mlx4_en"
736#define IB_DRV_NAME "mlx4_ib"
737
738 for (port = 1; port <= dev->caps.num_ports; port++) {
739 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
740 has_ib_port = true;
741 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
742 has_eth_port = true;
743 }
744
b046ffe5
EP		 745 if (has_eth_port)
746 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 747 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
748 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 749}
750
7ff93f8b
YP		 751/*
752 * Change the port configuration of the device.
753 * Every user of this function must hold the port mutex.
754 */
27bf91d6
YP		 755int mlx4_change_port_types(struct mlx4_dev *dev,
756 enum mlx4_port_type *port_types)
7ff93f8b
YP		 757{
758 int err = 0;
759 int change = 0;
760 int port;
761
762 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 763 /* Change the port type only if the new type is different
764 * from the current, and not set to Auto */
3d8f9308 765 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 766 change = 1;
7ff93f8b
YP		 767 }
768 if (change) {
769 mlx4_unregister_device(dev);
770 for (port = 1; port <= dev->caps.num_ports; port++) {
771 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 772 dev->caps.port_type[port] = port_types[port - 1];
6634961c 773 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 774 if (err) {
1a91de28
JP		 775 mlx4_err(dev, "Failed to set port %d, aborting\n",
776 port);
7ff93f8b
YP		 777 goto out;
778 }
779 }
780 mlx4_set_port_mask(dev);
781 err = mlx4_register_device(dev);
b046ffe5
EP		 782 if (err) {
783 mlx4_err(dev, "Failed to register device\n");
784 goto out;
785 }
786 mlx4_request_modules(dev);
7ff93f8b
YP		 787 }
788
789out:
790 return err;
791}
792
793static ssize_t show_port_type(struct device *dev,
794 struct device_attribute *attr,
795 char *buf)
796{
797 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
798 port_attr);
799 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 800 char type[8];
801
802 sprintf(type, "%s",
803 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
804 "ib" : "eth");
805 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
806 sprintf(buf, "auto (%s)\n", type);
807 else
808 sprintf(buf, "%s\n", type);
7ff93f8b 809
27bf91d6 810 return strlen(buf);
7ff93f8b
YP		 811}
812
813static ssize_t set_port_type(struct device *dev,
814 struct device_attribute *attr,
815 const char *buf, size_t count)
816{
817 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
818 port_attr);
819 struct mlx4_dev *mdev = info->dev;
820 struct mlx4_priv *priv = mlx4_priv(mdev);
821 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 822 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 823 int i;
824 int err = 0;
825
826 if (!strcmp(buf, "ib\n"))
827 info->tmp_type = MLX4_PORT_TYPE_IB;
828 else if (!strcmp(buf, "eth\n"))
829 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 830 else if (!strcmp(buf, "auto\n"))
831 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 832 else {
833 mlx4_err(mdev, "%s is not supported port type\n", buf);
834 return -EINVAL;
835 }
836
27bf91d6 837 mlx4_stop_sense(mdev);
7ff93f8b 838 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 839 /* Possible type is always the one that was delivered */
840 mdev->caps.possible_type[info->port] = info->tmp_type;
841
842 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 843 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 844 mdev->caps.possible_type[i+1];
845 if (types[i] == MLX4_PORT_TYPE_AUTO)
846 types[i] = mdev->caps.port_type[i+1];
847 }
7ff93f8b 848
58a60168
YP		 849 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
850 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 851 for (i = 1; i <= mdev->caps.num_ports; i++) {
852 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
853 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
854 err = -EINVAL;
855 }
856 }
857 }
858 if (err) {
1a91de28 859 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 860 goto out;
861 }
862
863 mlx4_do_sense_ports(mdev, new_types, types);
864
865 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 866 if (err)
867 goto out;
868
27bf91d6
YP		 869 /* We are about to apply the changes after the configuration
870 * was verified, no need to remember the temporary types
871 * any more */
872 for (i = 0; i < mdev->caps.num_ports; i++)
873 priv->port[i + 1].tmp_type = 0;
7ff93f8b 874
27bf91d6 875 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 876
877out:
27bf91d6 878 mlx4_start_sense(mdev);
7ff93f8b
YP		 879 mutex_unlock(&priv->port_mutex);
880 return err ? err : count;
881}
882
096335b3
OG		 883enum ibta_mtu {
884 IB_MTU_256 = 1,
885 IB_MTU_512 = 2,
886 IB_MTU_1024 = 3,
887 IB_MTU_2048 = 4,
888 IB_MTU_4096 = 5
889};
890
891static inline int int_to_ibta_mtu(int mtu)
892{
893 switch (mtu) {
894 case 256: return IB_MTU_256;
895 case 512: return IB_MTU_512;
896 case 1024: return IB_MTU_1024;
897 case 2048: return IB_MTU_2048;
898 case 4096: return IB_MTU_4096;
899 default: return -1;
900 }
901}
902
903static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
904{
905 switch (mtu) {
906 case IB_MTU_256: return 256;
907 case IB_MTU_512: return 512;
908 case IB_MTU_1024: return 1024;
909 case IB_MTU_2048: return 2048;
910 case IB_MTU_4096: return 4096;
911 default: return -1;
912 }
913}
914
915static ssize_t show_port_ib_mtu(struct device *dev,
916 struct device_attribute *attr,
917 char *buf)
918{
919 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
920 port_mtu_attr);
921 struct mlx4_dev *mdev = info->dev;
922
923 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
924 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
925
926 sprintf(buf, "%d\n",
927 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
928 return strlen(buf);
929}
930
931static ssize_t set_port_ib_mtu(struct device *dev,
932 struct device_attribute *attr,
933 const char *buf, size_t count)
934{
935 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
936 port_mtu_attr);
937 struct mlx4_dev *mdev = info->dev;
938 struct mlx4_priv *priv = mlx4_priv(mdev);
939 int err, port, mtu, ibta_mtu = -1;
940
941 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
942 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
943 return -EINVAL;
944 }
945
618fad95
DB		 946 err = kstrtoint(buf, 0, &mtu);
947 if (!err)
096335b3
OG		 948 ibta_mtu = int_to_ibta_mtu(mtu);
949
618fad95 950 if (err || ibta_mtu < 0) {
096335b3
OG		 951 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
952 return -EINVAL;
953 }
954
955 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
956
957 mlx4_stop_sense(mdev);
958 mutex_lock(&priv->port_mutex);
959 mlx4_unregister_device(mdev);
960 for (port = 1; port <= mdev->caps.num_ports; port++) {
961 mlx4_CLOSE_PORT(mdev, port);
6634961c 962 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 963 if (err) {
1a91de28
JP		 964 mlx4_err(mdev, "Failed to set port %d, aborting\n",
965 port);
096335b3
OG		 966 goto err_set_port;
967 }
968 }
969 err = mlx4_register_device(mdev);
970err_set_port:
971 mutex_unlock(&priv->port_mutex);
972 mlx4_start_sense(mdev);
973 return err ? err : count;
974}
975
e8f9b2ed 976static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 977{
978 struct mlx4_priv *priv = mlx4_priv(dev);
979 int err;
980
981 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 982 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 983 if (!priv->fw.fw_icm) {
1a91de28 984 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 985 return -ENOMEM;
986 }
987
988 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
989 if (err) {
1a91de28 990 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 991 goto err_free;
992 }
993
994 err = mlx4_RUN_FW(dev);
995 if (err) {
1a91de28 996 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 997 goto err_unmap_fa;
998 }
999
1000 return 0;
1001
1002err_unmap_fa:
1003 mlx4_UNMAP_FA(dev);
1004
1005err_free:
5b0bf5e2 1006 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1007 return err;
1008}
1009
e8f9b2ed
RD		 1010static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1011 int cmpt_entry_sz)
225c7b1f
RD		 1012{
1013 struct mlx4_priv *priv = mlx4_priv(dev);
1014 int err;
ab9c17a0 1015 int num_eqs;
225c7b1f
RD		 1016
1017 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1018 cmpt_base +
1019 ((u64) (MLX4_CMPT_TYPE_QP *
1020 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1021 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1022 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1023 0, 0);
225c7b1f
RD		 1024 if (err)
1025 goto err;
1026
1027 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1028 cmpt_base +
1029 ((u64) (MLX4_CMPT_TYPE_SRQ *
1030 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1031 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1032 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1033 if (err)
1034 goto err_qp;
1035
1036 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1037 cmpt_base +
1038 ((u64) (MLX4_CMPT_TYPE_CQ *
1039 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1040 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1041 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1042 if (err)
1043 goto err_srq;
1044
3fc929e2
MA		 1045 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1046 dev->caps.num_eqs;
225c7b1f
RD		 1047 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1048 cmpt_base +
1049 ((u64) (MLX4_CMPT_TYPE_EQ *
1050 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1051 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1052 if (err)
1053 goto err_cq;
1054
1055 return 0;
1056
1057err_cq:
1058 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1059
1060err_srq:
1061 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1062
1063err_qp:
1064 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1065
1066err:
1067 return err;
1068}
1069
3d73c288
RD		 1070static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1071 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1072{
1073 struct mlx4_priv *priv = mlx4_priv(dev);
1074 u64 aux_pages;
ab9c17a0 1075 int num_eqs;
225c7b1f
RD		 1076 int err;
1077
1078 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1079 if (err) {
1a91de28 1080 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1081 return err;
1082 }
1083
1a91de28 1084 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1085 (unsigned long long) icm_size >> 10,
1086 (unsigned long long) aux_pages << 2);
1087
1088 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1089 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1090 if (!priv->fw.aux_icm) {
1a91de28 1091 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1092 return -ENOMEM;
1093 }
1094
1095 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1096 if (err) {
1a91de28 1097 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1098 goto err_free_aux;
1099 }
1100
1101 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1102 if (err) {
1a91de28 1103 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1104 goto err_unmap_aux;
1105 }
1106
ab9c17a0 1107
3fc929e2
MA		 1108 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1109 dev->caps.num_eqs;
fa0681d2
RD		 1110 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1111 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1112 num_eqs, num_eqs, 0, 0);
225c7b1f 1113 if (err) {
1a91de28 1114 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1115 goto err_unmap_cmpt;
1116 }
1117
d7bb58fb
JM		 1118 /*
1119 * Reserved MTT entries must be aligned up to a cacheline
1120 * boundary, since the FW will write to them, while the driver
1121 * writes to all other MTT entries. (The variable
1122 * dev->caps.mtt_entry_sz below is really the MTT segment
1123 * size, not the raw entry size)
1124 */
1125 dev->caps.reserved_mtts =
1126 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1127 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1128
225c7b1f
RD		 1129 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1130 init_hca->mtt_base,
1131 dev->caps.mtt_entry_sz,
2b8fb286 1132 dev->caps.num_mtts,
5b0bf5e2 1133 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1134 if (err) {
1a91de28 1135 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1136 goto err_unmap_eq;
1137 }
1138
1139 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1140 init_hca->dmpt_base,
1141 dev_cap->dmpt_entry_sz,
1142 dev->caps.num_mpts,
5b0bf5e2 1143 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1144 if (err) {
1a91de28 1145 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1146 goto err_unmap_mtt;
1147 }
1148
1149 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1150 init_hca->qpc_base,
1151 dev_cap->qpc_entry_sz,
1152 dev->caps.num_qps,
93fc9e1b
YP		 1153 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1154 0, 0);
225c7b1f 1155 if (err) {
1a91de28 1156 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1157 goto err_unmap_dmpt;
1158 }
1159
1160 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1161 init_hca->auxc_base,
1162 dev_cap->aux_entry_sz,
1163 dev->caps.num_qps,
93fc9e1b
YP		 1164 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1165 0, 0);
225c7b1f 1166 if (err) {
1a91de28 1167 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1168 goto err_unmap_qp;
1169 }
1170
1171 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1172 init_hca->altc_base,
1173 dev_cap->altc_entry_sz,
1174 dev->caps.num_qps,
93fc9e1b
YP		 1175 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1176 0, 0);
225c7b1f 1177 if (err) {
1a91de28 1178 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1179 goto err_unmap_auxc;
1180 }
1181
1182 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1183 init_hca->rdmarc_base,
1184 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1185 dev->caps.num_qps,
93fc9e1b
YP		 1186 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1187 0, 0);
225c7b1f
RD		 1188 if (err) {
1189 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1190 goto err_unmap_altc;
1191 }
1192
1193 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1194 init_hca->cqc_base,
1195 dev_cap->cqc_entry_sz,
1196 dev->caps.num_cqs,
5b0bf5e2 1197 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1198 if (err) {
1a91de28 1199 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1200 goto err_unmap_rdmarc;
1201 }
1202
1203 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1204 init_hca->srqc_base,
1205 dev_cap->srq_entry_sz,
1206 dev->caps.num_srqs,
5b0bf5e2 1207 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1208 if (err) {
1a91de28 1209 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1210 goto err_unmap_cq;
1211 }
1212
1213 /*
0ff1fb65
HHZ		 1214 * For flow steering device managed mode it is required to use
1215 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1216 * required, but for simplicity just map the whole multicast
1217 * group table now. The table isn't very big and it's a lot
1218 * easier than trying to track ref counts.
225c7b1f
RD		 1219 */
1220 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1221 init_hca->mc_base,
1222 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1223 dev->caps.num_mgms + dev->caps.num_amgms,
1224 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1225 0, 0);
225c7b1f 1226 if (err) {
1a91de28 1227 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1228 goto err_unmap_srq;
1229 }
1230
1231 return 0;
1232
1233err_unmap_srq:
1234 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1235
1236err_unmap_cq:
1237 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1238
1239err_unmap_rdmarc:
1240 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1241
1242err_unmap_altc:
1243 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1244
1245err_unmap_auxc:
1246 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1247
1248err_unmap_qp:
1249 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1250
1251err_unmap_dmpt:
1252 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1253
1254err_unmap_mtt:
1255 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1256
1257err_unmap_eq:
fa0681d2 1258 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1259
1260err_unmap_cmpt:
1261 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1262 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1263 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1264 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1265
1266err_unmap_aux:
1267 mlx4_UNMAP_ICM_AUX(dev);
1268
1269err_free_aux:
5b0bf5e2 1270 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1271
1272 return err;
1273}
1274
1275static void mlx4_free_icms(struct mlx4_dev *dev)
1276{
1277 struct mlx4_priv *priv = mlx4_priv(dev);
1278
1279 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1280 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1281 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1282 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1283 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1284 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1285 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1286 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1287 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1288 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1289 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1290 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1291 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1292 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1293
1294 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1295 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1296}
1297
ab9c17a0
JM		 1298static void mlx4_slave_exit(struct mlx4_dev *dev)
1299{
1300 struct mlx4_priv *priv = mlx4_priv(dev);
1301
f3d4c89e 1302 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1303 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1a91de28 1304 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1305 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1306}
1307
c1b43dca
EC		 1308static int map_bf_area(struct mlx4_dev *dev)
1309{
1310 struct mlx4_priv *priv = mlx4_priv(dev);
1311 resource_size_t bf_start;
1312 resource_size_t bf_len;
1313 int err = 0;
1314
3d747473
JM		 1315 if (!dev->caps.bf_reg_size)
1316 return -ENXIO;
1317
ab9c17a0
JM		 1318 bf_start = pci_resource_start(dev->pdev, 2) +
1319 (dev->caps.num_uars << PAGE_SHIFT);
1320 bf_len = pci_resource_len(dev->pdev, 2) -
1321 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1322 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1323 if (!priv->bf_mapping)
1324 err = -ENOMEM;
1325
1326 return err;
1327}
1328
1329static void unmap_bf_area(struct mlx4_dev *dev)
1330{
1331 if (mlx4_priv(dev)->bf_mapping)
1332 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1333}
1334
ec693d47
AV		 1335cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1336{
1337 u32 clockhi, clocklo, clockhi1;
1338 cycle_t cycles;
1339 int i;
1340 struct mlx4_priv *priv = mlx4_priv(dev);
1341
1342 for (i = 0; i < 10; i++) {
1343 clockhi = swab32(readl(priv->clock_mapping));
1344 clocklo = swab32(readl(priv->clock_mapping + 4));
1345 clockhi1 = swab32(readl(priv->clock_mapping));
1346 if (clockhi == clockhi1)
1347 break;
1348 }
1349
1350 cycles = (u64) clockhi << 32 | (u64) clocklo;
1351
1352 return cycles;
1353}
1354EXPORT_SYMBOL_GPL(mlx4_read_clock);
1355
1356
ddd8a6c1
EE		 1357static int map_internal_clock(struct mlx4_dev *dev)
1358{
1359 struct mlx4_priv *priv = mlx4_priv(dev);
1360
1361 priv->clock_mapping =
1362 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1363 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1364
1365 if (!priv->clock_mapping)
1366 return -ENOMEM;
1367
1368 return 0;
1369}
1370
1371static void unmap_internal_clock(struct mlx4_dev *dev)
1372{
1373 struct mlx4_priv *priv = mlx4_priv(dev);
1374
1375 if (priv->clock_mapping)
1376 iounmap(priv->clock_mapping);
1377}
1378
225c7b1f
RD		 1379static void mlx4_close_hca(struct mlx4_dev *dev)
1380{
ddd8a6c1 1381 unmap_internal_clock(dev);
c1b43dca 1382 unmap_bf_area(dev);
ab9c17a0
JM		 1383 if (mlx4_is_slave(dev))
1384 mlx4_slave_exit(dev);
1385 else {
1386 mlx4_CLOSE_HCA(dev, 0);
1387 mlx4_free_icms(dev);
1388 mlx4_UNMAP_FA(dev);
1389 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1390 }
1391}
1392
1393static int mlx4_init_slave(struct mlx4_dev *dev)
1394{
1395 struct mlx4_priv *priv = mlx4_priv(dev);
1396 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1397 int ret_from_reset = 0;
1398 u32 slave_read;
1399 u32 cmd_channel_ver;
1400
97989356 1401 if (atomic_read(&pf_loading)) {
1a91de28 1402 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 1403 return -EPROBE_DEFER;
1404 }
1405
f3d4c89e 1406 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1407 priv->cmd.max_cmds = 1;
1408 mlx4_warn(dev, "Sending reset\n");
1409 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1410 MLX4_COMM_TIME);
1411 /* if we are in the middle of flr the slave will try
1412 * NUM_OF_RESET_RETRIES times before leaving.*/
1413 if (ret_from_reset) {
1414 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 1415 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 1416 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1417 return -EPROBE_DEFER;
ab9c17a0
JM		 1418 } else
1419 goto err;
1420 }
1421
1422 /* check the driver version - the slave I/F revision
1423 * must match the master's */
1424 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1425 cmd_channel_ver = mlx4_comm_get_version();
1426
1427 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1428 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 1429 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 1430 goto err;
1431 }
1432
1433 mlx4_warn(dev, "Sending vhcr0\n");
1434 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1435 MLX4_COMM_TIME))
1436 goto err;
1437 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1438 MLX4_COMM_TIME))
1439 goto err;
1440 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1441 MLX4_COMM_TIME))
1442 goto err;
1443 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1444 goto err;
f3d4c89e
RD		 1445
1446 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1447 return 0;
1448
1449err:
1450 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1451 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1452 return -EIO;
225c7b1f
RD		 1453}
1454
6634961c
JM		 1455static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1456{
1457 int i;
1458
1459 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1460 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1461 dev->caps.gid_table_len[i] =
449fc488 1462 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 1463 else
1464 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1465 dev->caps.pkey_table_len[i] =
1466 dev->phys_caps.pkey_phys_table_len[i] - 1;
1467 }
1468}
1469
3c439b55
JM		 1470static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1471{
1472 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1473
1474 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1475 i++) {
1476 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1477 break;
1478 }
1479
1480 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1481}
1482
7b8157be
JM		 1483static void choose_steering_mode(struct mlx4_dev *dev,
1484 struct mlx4_dev_cap *dev_cap)
1485{
3c439b55
JM		 1486 if (mlx4_log_num_mgm_entry_size == -1 &&
1487 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1488 (!mlx4_is_mfunc(dev) ||
449fc488 1489 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
3c439b55
JM		 1490 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1491 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1492 dev->oper_log_mgm_entry_size =
1493 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1494 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1495 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1496 dev->caps.fs_log_max_ucast_qp_range_size =
1497 dev_cap->fs_log_max_ucast_qp_range_size;
1498 } else {
1499 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1500 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1501 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1502 else {
1503 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1504
1505 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1506 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 1507 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 1508 }
3c439b55
JM		 1509 dev->oper_log_mgm_entry_size =
1510 mlx4_log_num_mgm_entry_size > 0 ?
1511 mlx4_log_num_mgm_entry_size :
1512 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1513 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1514 }
1a91de28 1515 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 1516 mlx4_steering_mode_str(dev->caps.steering_mode),
1517 dev->oper_log_mgm_entry_size,
1518 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1519}
1520
7ffdf726
OG		 1521static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1522 struct mlx4_dev_cap *dev_cap)
1523{
1524 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1525 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1526 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1527 else
1528 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1529
1530 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1531 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1532}
1533
3d73c288 1534static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1535{
1536 struct mlx4_priv *priv = mlx4_priv(dev);
1537 struct mlx4_adapter adapter;
1538 struct mlx4_dev_cap dev_cap;
2d928651 1539 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1540 struct mlx4_profile profile;
1541 struct mlx4_init_hca_param init_hca;
1542 u64 icm_size;
1543 int err;
1544
ab9c17a0
JM		 1545 if (!mlx4_is_slave(dev)) {
1546 err = mlx4_QUERY_FW(dev);
1547 if (err) {
1548 if (err == -EACCES)
1a91de28 1549 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 1550 else
1a91de28 1551 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 1552 return err;
ab9c17a0 1553 }
225c7b1f 1554
ab9c17a0
JM		 1555 err = mlx4_load_fw(dev);
1556 if (err) {
1a91de28 1557 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 1558 return err;
ab9c17a0 1559 }
225c7b1f 1560
ab9c17a0
JM		 1561 mlx4_cfg.log_pg_sz_m = 1;
1562 mlx4_cfg.log_pg_sz = 0;
1563 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1564 if (err)
1565 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1566
ab9c17a0
JM		 1567 err = mlx4_dev_cap(dev, &dev_cap);
1568 if (err) {
1a91de28 1569 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
ab9c17a0
JM		 1570 goto err_stop_fw;
1571 }
225c7b1f 1572
7b8157be 1573 choose_steering_mode(dev, &dev_cap);
7ffdf726 1574 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1575
8e1a28e8
HHZ		 1576 err = mlx4_get_phys_port_id(dev);
1577 if (err)
1578 mlx4_err(dev, "Fail to get physical port id\n");
1579
6634961c
JM		 1580 if (mlx4_is_master(dev))
1581 mlx4_parav_master_pf_caps(dev);
1582
ab9c17a0 1583 profile = default_profile;
0ff1fb65
HHZ		 1584 if (dev->caps.steering_mode ==
1585 MLX4_STEERING_MODE_DEVICE_MANAGED)
1586 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1587
ab9c17a0
JM		 1588 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1589 &init_hca);
1590 if ((long long) icm_size < 0) {
1591 err = icm_size;
1592 goto err_stop_fw;
1593 }
225c7b1f 1594
a5bbe892
EC		 1595 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1596
ab9c17a0
JM		 1597 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1598 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1599 init_hca.mw_enabled = 0;
1600 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1601 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1602 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1603
ab9c17a0
JM		 1604 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1605 if (err)
1606 goto err_stop_fw;
225c7b1f 1607
ab9c17a0
JM		 1608 err = mlx4_INIT_HCA(dev, &init_hca);
1609 if (err) {
1a91de28 1610 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 1611 goto err_free_icm;
1612 }
ddd8a6c1
EE		 1613 /*
1614 * If TS is supported by FW
1615 * read HCA frequency by QUERY_HCA command
1616 */
1617 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1618 memset(&init_hca, 0, sizeof(init_hca));
1619 err = mlx4_QUERY_HCA(dev, &init_hca);
1620 if (err) {
1a91de28 1621 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 1622 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1623 } else {
1624 dev->caps.hca_core_clock =
1625 init_hca.hca_core_clock;
1626 }
1627
1628 /* In case we got HCA frequency 0 - disable timestamping
1629 * to avoid dividing by zero
1630 */
1631 if (!dev->caps.hca_core_clock) {
1632 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1633 mlx4_err(dev,
1a91de28 1634 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 1635 } else if (map_internal_clock(dev)) {
1636 /*
1637 * Map internal clock,
1638 * in case of failure disable timestamping
1639 */
1640 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1641 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 1642 }
1643 }
ab9c17a0
JM		 1644 } else {
1645 err = mlx4_init_slave(dev);
1646 if (err) {
5efe5355
JM		 1647 if (err != -EPROBE_DEFER)
1648 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1649 return err;
ab9c17a0 1650 }
225c7b1f 1651
ab9c17a0
JM		 1652 err = mlx4_slave_cap(dev);
1653 if (err) {
1654 mlx4_err(dev, "Failed to obtain slave caps\n");
1655 goto err_close;
1656 }
225c7b1f
RD		 1657 }
1658
ab9c17a0
JM		 1659 if (map_bf_area(dev))
1660 mlx4_dbg(dev, "Failed to map blue flame area\n");
1661
1662 /*Only the master set the ports, all the rest got it from it.*/
1663 if (!mlx4_is_slave(dev))
1664 mlx4_set_port_mask(dev);
1665
225c7b1f
RD		 1666 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1667 if (err) {
1a91de28 1668 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 1669 goto unmap_bf;
225c7b1f
RD		 1670 }
1671
1672 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1673 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1674
1675 return 0;
1676
bef772eb 1677unmap_bf:
ddd8a6c1 1678 unmap_internal_clock(dev);
bef772eb
AY		 1679 unmap_bf_area(dev);
1680
225c7b1f 1681err_close:
41929ed2
DB		 1682 if (mlx4_is_slave(dev))
1683 mlx4_slave_exit(dev);
1684 else
1685 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1686
1687err_free_icm:
ab9c17a0
JM		 1688 if (!mlx4_is_slave(dev))
1689 mlx4_free_icms(dev);
225c7b1f
RD		 1690
1691err_stop_fw:
ab9c17a0
JM		 1692 if (!mlx4_is_slave(dev)) {
1693 mlx4_UNMAP_FA(dev);
1694 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1695 }
225c7b1f
RD		 1696 return err;
1697}
1698
f2a3f6a3
OG		 1699static int mlx4_init_counters_table(struct mlx4_dev *dev)
1700{
1701 struct mlx4_priv *priv = mlx4_priv(dev);
1702 int nent;
1703
1704 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1705 return -ENOENT;
1706
1707 nent = dev->caps.max_counters;
1708 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1709}
1710
1711static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1712{
1713 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1714}
1715
ba062d52 1716int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1717{
1718 struct mlx4_priv *priv = mlx4_priv(dev);
1719
1720 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1721 return -ENOENT;
1722
1723 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1724 if (*idx == -1)
1725 return -ENOMEM;
1726
1727 return 0;
1728}
ba062d52
JM		 1729
1730int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1731{
1732 u64 out_param;
1733 int err;
1734
1735 if (mlx4_is_mfunc(dev)) {
1736 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1737 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1738 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1739 if (!err)
1740 *idx = get_param_l(&out_param);
1741
1742 return err;
1743 }
1744 return __mlx4_counter_alloc(dev, idx);
1745}
f2a3f6a3
OG		 1746EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1747
ba062d52 1748void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 1749{
7c6d74d2 1750 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 1751 return;
1752}
ba062d52
JM		 1753
1754void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1755{
e7dbeba8 1756 u64 in_param = 0;
ba062d52
JM		 1757
1758 if (mlx4_is_mfunc(dev)) {
1759 set_param_l(&in_param, idx);
1760 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1761 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1762 MLX4_CMD_WRAPPED);
1763 return;
1764 }
1765 __mlx4_counter_free(dev, idx);
1766}
f2a3f6a3
OG		 1767EXPORT_SYMBOL_GPL(mlx4_counter_free);
1768
3d73c288 1769static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1770{
1771 struct mlx4_priv *priv = mlx4_priv(dev);
1772 int err;
7ff93f8b 1773 int port;
9a5aa622 1774 __be32 ib_port_default_caps;
225c7b1f 1775
225c7b1f
RD		 1776 err = mlx4_init_uar_table(dev);
1777 if (err) {
1a91de28
JP		 1778 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
1779 return err;
225c7b1f
RD		 1780 }
1781
1782 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1783 if (err) {
1a91de28 1784 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 1785 goto err_uar_table_free;
1786 }
1787
4979d18f 1788 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 1789 if (!priv->kar) {
1a91de28 1790 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 1791 err = -ENOMEM;
1792 goto err_uar_free;
1793 }
1794
1795 err = mlx4_init_pd_table(dev);
1796 if (err) {
1a91de28 1797 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 1798 goto err_kar_unmap;
1799 }
1800
012a8ff5
SH		 1801 err = mlx4_init_xrcd_table(dev);
1802 if (err) {
1a91de28 1803 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 1804 goto err_pd_table_free;
1805 }
1806
225c7b1f
RD		 1807 err = mlx4_init_mr_table(dev);
1808 if (err) {
1a91de28 1809 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 1810 goto err_xrcd_table_free;
225c7b1f
RD		 1811 }
1812
fe6f700d
YP		 1813 if (!mlx4_is_slave(dev)) {
1814 err = mlx4_init_mcg_table(dev);
1815 if (err) {
1a91de28 1816 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 1817 goto err_mr_table_free;
1818 }
1819 }
1820
225c7b1f
RD		 1821 err = mlx4_init_eq_table(dev);
1822 if (err) {
1a91de28 1823 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 1824 goto err_mcg_table_free;
225c7b1f
RD		 1825 }
1826
1827 err = mlx4_cmd_use_events(dev);
1828 if (err) {
1a91de28 1829 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 1830 goto err_eq_table_free;
1831 }
1832
1833 err = mlx4_NOP(dev);
1834 if (err) {
08fb1055 1835 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 1836 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
b8dd786f 1837 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1a91de28 1838 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 1839 } else {
1a91de28 1840 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
b8dd786f 1841 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1842 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1843 }
225c7b1f
RD		 1844
1845 goto err_cmd_poll;
1846 }
1847
1848 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1849
1850 err = mlx4_init_cq_table(dev);
1851 if (err) {
1a91de28 1852 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 1853 goto err_cmd_poll;
1854 }
1855
1856 err = mlx4_init_srq_table(dev);
1857 if (err) {
1a91de28 1858 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 1859 goto err_cq_table_free;
1860 }
1861
1862 err = mlx4_init_qp_table(dev);
1863 if (err) {
1a91de28 1864 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 1865 goto err_srq_table_free;
1866 }
1867
f2a3f6a3
OG		 1868 err = mlx4_init_counters_table(dev);
1869 if (err && err != -ENOENT) {
1a91de28 1870 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
fe6f700d 1871 goto err_qp_table_free;
f2a3f6a3
OG		 1872 }
1873
ab9c17a0
JM		 1874 if (!mlx4_is_slave(dev)) {
1875 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1876 ib_port_default_caps = 0;
1877 err = mlx4_get_port_ib_caps(dev, port,
1878 &ib_port_default_caps);
1879 if (err)
1a91de28
JP		 1880 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
1881 port, err);
ab9c17a0
JM		 1882 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1883
2aca1172
JM		 1884 /* initialize per-slave default ib port capabilities */
1885 if (mlx4_is_master(dev)) {
1886 int i;
1887 for (i = 0; i < dev->num_slaves; i++) {
1888 if (i == mlx4_master_func_num(dev))
1889 continue;
1890 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 1891 ib_port_default_caps;
2aca1172
JM		 1892 }
1893 }
1894
096335b3
OG		 1895 if (mlx4_is_mfunc(dev))
1896 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1897 else
1898 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 1899
6634961c
JM		 1900 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1901 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 1902 if (err) {
1903 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 1904 port);
ab9c17a0
JM		 1905 goto err_counters_table_free;
1906 }
7ff93f8b
YP		 1907 }
1908 }
1909
225c7b1f
RD		 1910 return 0;
1911
f2a3f6a3
OG		 1912err_counters_table_free:
1913 mlx4_cleanup_counters_table(dev);
1914
225c7b1f
RD		 1915err_qp_table_free:
1916 mlx4_cleanup_qp_table(dev);
1917
1918err_srq_table_free:
1919 mlx4_cleanup_srq_table(dev);
1920
1921err_cq_table_free:
1922 mlx4_cleanup_cq_table(dev);
1923
1924err_cmd_poll:
1925 mlx4_cmd_use_polling(dev);
1926
1927err_eq_table_free:
1928 mlx4_cleanup_eq_table(dev);
1929
fe6f700d
YP		 1930err_mcg_table_free:
1931 if (!mlx4_is_slave(dev))
1932 mlx4_cleanup_mcg_table(dev);
1933
ee49bd93 1934err_mr_table_free:
225c7b1f
RD		 1935 mlx4_cleanup_mr_table(dev);
1936
012a8ff5
SH		 1937err_xrcd_table_free:
1938 mlx4_cleanup_xrcd_table(dev);
1939
225c7b1f
RD		 1940err_pd_table_free:
1941 mlx4_cleanup_pd_table(dev);
1942
1943err_kar_unmap:
1944 iounmap(priv->kar);
1945
1946err_uar_free:
1947 mlx4_uar_free(dev, &priv->driver_uar);
1948
1949err_uar_table_free:
1950 mlx4_cleanup_uar_table(dev);
1951 return err;
1952}
1953
e8f9b2ed 1954static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1955{
1956 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1957 struct msix_entry *entries;
0b7ca5a9 1958 int nreq = min_t(int, dev->caps.num_ports *
bb2146bc 1959 min_t(int, num_online_cpus() + 1,
90b1ebe7 1960 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1961 int i;
1962
1963 if (msi_x) {
ca4c7b35
OG		 1964 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1965 nreq);
ab9c17a0 1966
b8dd786f
YP		 1967 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1968 if (!entries)
1969 goto no_msi;
1970
1971 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1972 entries[i].entry = i;
1973
66e2f9c1
AG		 1974 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
1975
1976 if (nreq < 0) {
5bf0da7d 1977 kfree(entries);
225c7b1f 1978 goto no_msi;
66e2f9c1 1979 } else if (nreq < MSIX_LEGACY_SZ +
1a91de28 1980 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 1981 /*Working in legacy mode , all EQ's shared*/
1982 dev->caps.comp_pool = 0;
1983 dev->caps.num_comp_vectors = nreq - 1;
1984 } else {
1985 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1986 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1987 }
b8dd786f 1988 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1989 priv->eq_table.eq[i].irq = entries[i].vector;
1990
1991 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 1992
1993 kfree(entries);
225c7b1f
RD		 1994 return;
1995 }
1996
1997no_msi:
b8dd786f 1998 dev->caps.num_comp_vectors = 1;
0b7ca5a9 1999 dev->caps.comp_pool = 0;
b8dd786f
YP		 2000
2001 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2002 priv->eq_table.eq[i].irq = dev->pdev->irq;
2003}
2004
7ff93f8b 2005static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2006{
2007 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2008 int err = 0;
2a2336f8
YP		 2009
2010 info->dev = dev;
2011 info->port = port;
ab9c17a0 2012 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2013 mlx4_init_mac_table(dev, &info->mac_table);
2014 mlx4_init_vlan_table(dev, &info->vlan_table);
16a10ffd 2015 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2016 }
7ff93f8b
YP		 2017
2018 sprintf(info->dev_name, "mlx4_port%d", port);
2019 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2020 if (mlx4_is_mfunc(dev))
2021 info->port_attr.attr.mode = S_IRUGO;
2022 else {
2023 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2024 info->port_attr.store = set_port_type;
2025 }
7ff93f8b 2026 info->port_attr.show = show_port_type;
3691c964 2027 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2028
2029 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2030 if (err) {
2031 mlx4_err(dev, "Failed to create file for port %d\n", port);
2032 info->port = -1;
2033 }
2034
096335b3
OG		 2035 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2036 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2037 if (mlx4_is_mfunc(dev))
2038 info->port_mtu_attr.attr.mode = S_IRUGO;
2039 else {
2040 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2041 info->port_mtu_attr.store = set_port_ib_mtu;
2042 }
2043 info->port_mtu_attr.show = show_port_ib_mtu;
2044 sysfs_attr_init(&info->port_mtu_attr.attr);
2045
2046 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2047 if (err) {
2048 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2049 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2050 info->port = -1;
2051 }
2052
7ff93f8b
YP		 2053 return err;
2054}
2055
2056static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2057{
2058 if (info->port < 0)
2059 return;
2060
2061 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2062 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2063}
2064
b12d93d6
YP		 2065static int mlx4_init_steering(struct mlx4_dev *dev)
2066{
2067 struct mlx4_priv *priv = mlx4_priv(dev);
2068 int num_entries = dev->caps.num_ports;
2069 int i, j;
2070
2071 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2072 if (!priv->steer)
2073 return -ENOMEM;
2074
45b51365 2075 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2076 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2077 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2078 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2079 }
b12d93d6
YP		 2080 return 0;
2081}
2082
2083static void mlx4_clear_steering(struct mlx4_dev *dev)
2084{
2085 struct mlx4_priv *priv = mlx4_priv(dev);
2086 struct mlx4_steer_index *entry, *tmp_entry;
2087 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2088 int num_entries = dev->caps.num_ports;
2089 int i, j;
2090
2091 for (i = 0; i < num_entries; i++) {
2092 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2093 list_for_each_entry_safe(pqp, tmp_pqp,
2094 &priv->steer[i].promisc_qps[j],
2095 list) {
2096 list_del(&pqp->list);
2097 kfree(pqp);
2098 }
2099 list_for_each_entry_safe(entry, tmp_entry,
2100 &priv->steer[i].steer_entries[j],
2101 list) {
2102 list_del(&entry->list);
2103 list_for_each_entry_safe(pqp, tmp_pqp,
2104 &entry->duplicates,
2105 list) {
2106 list_del(&pqp->list);
2107 kfree(pqp);
2108 }
2109 kfree(entry);
2110 }
2111 }
2112 }
2113 kfree(priv->steer);
2114}
2115
ab9c17a0
JM		 2116static int extended_func_num(struct pci_dev *pdev)
2117{
2118 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2119}
2120
2121#define MLX4_OWNER_BASE 0x8069c
2122#define MLX4_OWNER_SIZE 4
2123
2124static int mlx4_get_ownership(struct mlx4_dev *dev)
2125{
2126 void __iomem *owner;
2127 u32 ret;
2128
57dbf29a
KSS		 2129 if (pci_channel_offline(dev->pdev))
2130 return -EIO;
2131
ab9c17a0
JM		 2132 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2133 MLX4_OWNER_SIZE);
2134 if (!owner) {
2135 mlx4_err(dev, "Failed to obtain ownership bit\n");
2136 return -ENOMEM;
2137 }
2138
2139 ret = readl(owner);
2140 iounmap(owner);
2141 return (int) !!ret;
2142}
2143
2144static void mlx4_free_ownership(struct mlx4_dev *dev)
2145{
2146 void __iomem *owner;
2147
57dbf29a
KSS		 2148 if (pci_channel_offline(dev->pdev))
2149 return;
2150
ab9c17a0
JM		 2151 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2152 MLX4_OWNER_SIZE);
2153 if (!owner) {
2154 mlx4_err(dev, "Failed to obtain ownership bit\n");
2155 return;
2156 }
2157 writel(0, owner);
2158 msleep(1000);
2159 iounmap(owner);
2160}
2161
839f1243 2162static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
225c7b1f 2163{
225c7b1f
RD		 2164 struct mlx4_priv *priv;
2165 struct mlx4_dev *dev;
2166 int err;
2a2336f8 2167 int port;
dd41cc3b
MB		 2168 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2169 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2170 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2171 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
1ab95d37
MB		 2172 unsigned total_vfs = 0;
2173 int sriov_initialized = 0;
2174 unsigned int i;
225c7b1f 2175
0a645e80 2176 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 2177
2178 err = pci_enable_device(pdev);
2179 if (err) {
1a91de28 2180 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
225c7b1f
RD		 2181 return err;
2182 }
5a0d0a61
JM		 2183
2184 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2185 * per port, we must limit the number of VFs to 63 (since their are
2186 * 128 MACs)
2187 */
dd41cc3b
MB		 2188 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2189 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2190 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
1ab95d37
MB		 2191 if (nvfs[i] < 0) {
2192 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2193 return -EINVAL;
2194 }
2195 }
dd41cc3b
MB		 2196 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2197 i++) {
2198 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
1ab95d37
MB		 2199 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2200 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2201 return -EINVAL;
2202 }
2203 }
2204 if (total_vfs >= MLX4_MAX_NUM_VF) {
5a0d0a61
JM		 2205 dev_err(&pdev->dev,
2206 "Requested more VF's (%d) than allowed (%d)\n",
1ab95d37 2207 total_vfs, MLX4_MAX_NUM_VF - 1);
ab9c17a0
JM		 2208 return -EINVAL;
2209 }
30e514a7 2210
1ab95d37
MB		 2211 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2212 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2213 dev_err(&pdev->dev,
2214 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2215 nvfs[i] + nvfs[2], i + 1,
2216 MLX4_MAX_NUM_VF_P_PORT - 1);
2217 return -EINVAL;
2218 }
30e514a7 2219 }
1ab95d37
MB		 2220
2221
225c7b1f 2222 /*
ab9c17a0 2223 * Check for BARs.
225c7b1f 2224 */
839f1243 2225 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
ab9c17a0 2226 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 2227 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
839f1243 2228 pci_dev_data, pci_resource_flags(pdev, 0));
225c7b1f
RD		 2229 err = -ENODEV;
2230 goto err_disable_pdev;
2231 }
2232 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1a91de28 2233 dev_err(&pdev->dev, "Missing UAR, aborting\n");
225c7b1f
RD		 2234 err = -ENODEV;
2235 goto err_disable_pdev;
2236 }
2237
a01df0fe 2238 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 2239 if (err) {
a01df0fe 2240 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 2241 goto err_disable_pdev;
2242 }
2243
225c7b1f
RD		 2244 pci_set_master(pdev);
2245
6a35528a 2246 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f 2247 if (err) {
1a91de28 2248 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
284901a9 2249 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f 2250 if (err) {
1a91de28 2251 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
a01df0fe 2252 goto err_release_regions;
225c7b1f
RD		 2253 }
2254 }
6a35528a 2255 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f 2256 if (err) {
1a91de28 2257 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
284901a9 2258 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f 2259 if (err) {
1a91de28 2260 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
a01df0fe 2261 goto err_release_regions;
225c7b1f
RD		 2262 }
2263 }
2264
7f9e5c48
DD		 2265 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2266 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2267
befdf897
WY		 2268 dev = pci_get_drvdata(pdev);
2269 priv = mlx4_priv(dev);
225c7b1f 2270 dev->pdev = pdev;
b581401e
RD		 2271 INIT_LIST_HEAD(&priv->ctx_list);
2272 spin_lock_init(&priv->ctx_lock);
225c7b1f 2273
7ff93f8b
YP		 2274 mutex_init(&priv->port_mutex);
2275
6296883c
YP		 2276 INIT_LIST_HEAD(&priv->pgdir_list);
2277 mutex_init(&priv->pgdir_mutex);
2278
c1b43dca
EC		 2279 INIT_LIST_HEAD(&priv->bf_list);
2280 mutex_init(&priv->bf_mutex);
2281
aca7a3ac 2282 dev->rev_id = pdev->revision;
6e7136ed 2283 dev->numa_node = dev_to_node(&pdev->dev);
ab9c17a0 2284 /* Detect if this device is a virtual function */
839f1243 2285 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2286 /* When acting as pf, we normally skip vfs unless explicitly
2287 * requested to probe them. */
1ab95d37
MB		 2288 if (total_vfs) {
2289 unsigned vfs_offset = 0;
2290 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
1a91de28 2291 vfs_offset + nvfs[i] < extended_func_num(pdev);
1ab95d37
MB		 2292 vfs_offset += nvfs[i], i++)
2293 ;
2294 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
2295 err = -ENODEV;
2296 goto err_free_dev;
2297 }
2298 if ((extended_func_num(pdev) - vfs_offset)
2299 > prb_vf[i]) {
2300 mlx4_warn(dev, "Skipping virtual function:%d\n",
2301 extended_func_num(pdev));
2302 err = -ENODEV;
2303 goto err_free_dev;
2304 }
ab9c17a0
JM		 2305 }
2306 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2307 dev->flags |= MLX4_FLAG_SLAVE;
2308 } else {
2309 /* We reset the device and enable SRIOV only for physical
2310 * devices. Try to claim ownership on the device;
2311 * if already taken, skip -- do not allow multiple PFs */
2312 err = mlx4_get_ownership(dev);
2313 if (err) {
2314 if (err < 0)
2315 goto err_free_dev;
2316 else {
1a91de28 2317 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
ab9c17a0
JM		 2318 err = -EINVAL;
2319 goto err_free_dev;
2320 }
2321 }
aca7a3ac 2322
1ab95d37
MB		 2323 if (total_vfs) {
2324 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n",
2325 total_vfs);
2326 dev->dev_vfs = kzalloc(
1a91de28
JP		 2327 total_vfs * sizeof(*dev->dev_vfs),
2328 GFP_KERNEL);
1ab95d37
MB		 2329 if (NULL == dev->dev_vfs) {
2330 mlx4_err(dev, "Failed to allocate memory for VFs\n");
ab9c17a0
JM		 2331 err = 0;
2332 } else {
1ab95d37
MB		 2333 atomic_inc(&pf_loading);
2334 err = pci_enable_sriov(pdev, total_vfs);
1ab95d37 2335 if (err) {
1a91de28 2336 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
1ab95d37 2337 err);
e1a5ddc5 2338 atomic_dec(&pf_loading);
1ab95d37
MB		 2339 err = 0;
2340 } else {
2341 mlx4_warn(dev, "Running in master mode\n");
2342 dev->flags |= MLX4_FLAG_SRIOV |
1a91de28 2343 MLX4_FLAG_MASTER;
1ab95d37
MB		 2344 dev->num_vfs = total_vfs;
2345 sriov_initialized = 1;
2346 }
ab9c17a0
JM		 2347 }
2348 }
2349
fe6f700d
YP		 2350 atomic_set(&priv->opreq_count, 0);
2351 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2352
ab9c17a0
JM		 2353 /*
2354 * Now reset the HCA before we touch the PCI capabilities or
2355 * attempt a firmware command, since a boot ROM may have left
2356 * the HCA in an undefined state.
2357 */
2358 err = mlx4_reset(dev);
2359 if (err) {
1a91de28 2360 mlx4_err(dev, "Failed to reset HCA, aborting\n");
ab9c17a0
JM		 2361 goto err_rel_own;
2362 }
225c7b1f
RD		 2363 }
2364
ab9c17a0 2365slave_start:
521130d1
EE		 2366 err = mlx4_cmd_init(dev);
2367 if (err) {
1a91de28 2368 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 2369 goto err_sriov;
2370 }
2371
2372 /* In slave functions, the communication channel must be initialized
2373 * before posting commands. Also, init num_slaves before calling
2374 * mlx4_init_hca */
2375 if (mlx4_is_mfunc(dev)) {
2376 if (mlx4_is_master(dev))
2377 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2378 else {
2379 dev->num_slaves = 0;
f356fcbe
JM		 2380 err = mlx4_multi_func_init(dev);
2381 if (err) {
1a91de28 2382 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 2383 goto err_cmd;
2384 }
2385 }
225c7b1f
RD		 2386 }
2387
2388 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2389 if (err) {
2390 if (err == -EACCES) {
2391 /* Not primary Physical function
2392 * Running in slave mode */
2393 mlx4_cmd_cleanup(dev);
2394 dev->flags |= MLX4_FLAG_SLAVE;
2395 dev->flags &= ~MLX4_FLAG_MASTER;
2396 goto slave_start;
2397 } else
2398 goto err_mfunc;
2399 }
2400
b912b2f8
EP		 2401 /* check if the device is functioning at its maximum possible speed.
2402 * No return code for this call, just warn the user in case of PCI
2403 * express device capabilities are under-satisfied by the bus.
2404 */
83d3459a
EP		 2405 if (!mlx4_is_slave(dev))
2406 mlx4_check_pcie_caps(dev);
b912b2f8 2407
ab9c17a0
JM		 2408 /* In master functions, the communication channel must be initialized
2409 * after obtaining its address from fw */
2410 if (mlx4_is_master(dev)) {
1ab95d37 2411 unsigned sum = 0;
f356fcbe
JM		 2412 err = mlx4_multi_func_init(dev);
2413 if (err) {
1a91de28 2414 mlx4_err(dev, "Failed to init master mfunc interface, aborting\n");
ab9c17a0
JM		 2415 goto err_close;
2416 }
1ab95d37 2417 if (sriov_initialized) {
dd41cc3b
MB		 2418 int ib_ports = 0;
2419 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2420 ib_ports++;
2421
2422 if (ib_ports &&
2423 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2424 mlx4_err(dev,
1a91de28 2425 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
dd41cc3b
MB		 2426 goto err_close;
2427 }
1ab95d37
MB		 2428 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]); i++) {
2429 unsigned j;
2430 for (j = 0; j < nvfs[i]; ++sum, ++j) {
2431 dev->dev_vfs[sum].min_port =
2432 i < 2 ? i + 1 : 1;
2433 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2434 dev->caps.num_ports;
2435 }
2436 }
2437 }
ab9c17a0 2438 }
225c7b1f 2439
b8dd786f
YP		 2440 err = mlx4_alloc_eq_table(dev);
2441 if (err)
ab9c17a0 2442 goto err_master_mfunc;
b8dd786f 2443
0b7ca5a9 2444 priv->msix_ctl.pool_bm = 0;
730c41d5 2445 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2446
08fb1055 2447 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2448 if ((mlx4_is_mfunc(dev)) &&
2449 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2450 err = -ENOSYS;
1a91de28 2451 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 2452 goto err_free_eq;
ab9c17a0
JM		 2453 }
2454
2455 if (!mlx4_is_slave(dev)) {
2456 err = mlx4_init_steering(dev);
2457 if (err)
2458 goto err_free_eq;
2459 }
b12d93d6 2460
225c7b1f 2461 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2462 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2463 !mlx4_is_mfunc(dev)) {
08fb1055 2464 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2465 dev->caps.num_comp_vectors = 1;
2466 dev->caps.comp_pool = 0;
08fb1055
MT		 2467 pci_disable_msix(pdev);
2468 err = mlx4_setup_hca(dev);
2469 }
2470
225c7b1f 2471 if (err)
b12d93d6 2472 goto err_steer;
225c7b1f 2473
5a0d0a61
JM		 2474 mlx4_init_quotas(dev);
2475
7ff93f8b
YP		 2476 for (port = 1; port <= dev->caps.num_ports; port++) {
2477 err = mlx4_init_port_info(dev, port);
2478 if (err)
2479 goto err_port;
2480 }
2a2336f8 2481
225c7b1f
RD		 2482 err = mlx4_register_device(dev);
2483 if (err)
7ff93f8b 2484 goto err_port;
225c7b1f 2485
b046ffe5
EP		 2486 mlx4_request_modules(dev);
2487
27bf91d6
YP		 2488 mlx4_sense_init(dev);
2489 mlx4_start_sense(dev);
2490
befdf897 2491 priv->removed = 0;
225c7b1f 2492
e1a5ddc5
AV		 2493 if (mlx4_is_master(dev) && dev->num_vfs)
2494 atomic_dec(&pf_loading);
2495
225c7b1f
RD		 2496 return 0;
2497
7ff93f8b 2498err_port:
b4f77264 2499 for (--port; port >= 1; --port)
7ff93f8b
YP		 2500 mlx4_cleanup_port_info(&priv->port[port]);
2501
f2a3f6a3 2502 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2503 mlx4_cleanup_qp_table(dev);
2504 mlx4_cleanup_srq_table(dev);
2505 mlx4_cleanup_cq_table(dev);
2506 mlx4_cmd_use_polling(dev);
2507 mlx4_cleanup_eq_table(dev);
fe6f700d 2508 mlx4_cleanup_mcg_table(dev);
225c7b1f 2509 mlx4_cleanup_mr_table(dev);
012a8ff5 2510 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2511 mlx4_cleanup_pd_table(dev);
2512 mlx4_cleanup_uar_table(dev);
2513
b12d93d6 2514err_steer:
ab9c17a0
JM		 2515 if (!mlx4_is_slave(dev))
2516 mlx4_clear_steering(dev);
b12d93d6 2517
b8dd786f
YP		 2518err_free_eq:
2519 mlx4_free_eq_table(dev);
2520
ab9c17a0
JM		 2521err_master_mfunc:
2522 if (mlx4_is_master(dev))
2523 mlx4_multi_func_cleanup(dev);
2524
225c7b1f 2525err_close:
08fb1055
MT		 2526 if (dev->flags & MLX4_FLAG_MSI_X)
2527 pci_disable_msix(pdev);
2528
225c7b1f
RD		 2529 mlx4_close_hca(dev);
2530
ab9c17a0
JM		 2531err_mfunc:
2532 if (mlx4_is_slave(dev))
2533 mlx4_multi_func_cleanup(dev);
2534
225c7b1f
RD		 2535err_cmd:
2536 mlx4_cmd_cleanup(dev);
2537
ab9c17a0 2538err_sriov:
681372a7 2539 if (dev->flags & MLX4_FLAG_SRIOV)
ab9c17a0
JM		 2540 pci_disable_sriov(pdev);
2541
2542err_rel_own:
2543 if (!mlx4_is_slave(dev))
2544 mlx4_free_ownership(dev);
2545
e1a5ddc5
AV		 2546 if (mlx4_is_master(dev) && dev->num_vfs)
2547 atomic_dec(&pf_loading);
2548
1ab95d37
MB		 2549 kfree(priv->dev.dev_vfs);
2550
225c7b1f 2551err_free_dev:
225c7b1f
RD		 2552 kfree(priv);
2553
a01df0fe
RD		 2554err_release_regions:
2555 pci_release_regions(pdev);
225c7b1f
RD		 2556
2557err_disable_pdev:
2558 pci_disable_device(pdev);
2559 pci_set_drvdata(pdev, NULL);
2560 return err;
2561}
2562
1dd06ae8 2563static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2564{
befdf897
WY		 2565 struct mlx4_priv *priv;
2566 struct mlx4_dev *dev;
2567
0a645e80 2568 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2569
befdf897
WY		 2570 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2571 if (!priv)
2572 return -ENOMEM;
2573
2574 dev = &priv->dev;
2575 pci_set_drvdata(pdev, dev);
2576 priv->pci_dev_data = id->driver_data;
2577
839f1243 2578 return __mlx4_init_one(pdev, id->driver_data);
3d73c288
RD		 2579}
2580
befdf897 2581static void __mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 2582{
2583 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2584 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 2585 int pci_dev_data;
225c7b1f
RD		 2586 int p;
2587
befdf897
WY		 2588 if (priv->removed)
2589 return;
225c7b1f 2590
befdf897 2591 pci_dev_data = priv->pci_dev_data;
225c7b1f 2592
befdf897
WY		 2593 /* in SRIOV it is not allowed to unload the pf's
2594 * driver while there are alive vf's */
2595 if (mlx4_is_master(dev) && mlx4_how_many_lives_vf(dev))
2596 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2597 mlx4_stop_sense(dev);
2598 mlx4_unregister_device(dev);
225c7b1f 2599
befdf897
WY		 2600 for (p = 1; p <= dev->caps.num_ports; p++) {
2601 mlx4_cleanup_port_info(&priv->port[p]);
2602 mlx4_CLOSE_PORT(dev, p);
2603 }
2604
2605 if (mlx4_is_master(dev))
2606 mlx4_free_resource_tracker(dev,
2607 RES_TR_FREE_SLAVES_ONLY);
2608
2609 mlx4_cleanup_counters_table(dev);
2610 mlx4_cleanup_qp_table(dev);
2611 mlx4_cleanup_srq_table(dev);
2612 mlx4_cleanup_cq_table(dev);
2613 mlx4_cmd_use_polling(dev);
2614 mlx4_cleanup_eq_table(dev);
2615 mlx4_cleanup_mcg_table(dev);
2616 mlx4_cleanup_mr_table(dev);
2617 mlx4_cleanup_xrcd_table(dev);
2618 mlx4_cleanup_pd_table(dev);
225c7b1f 2619
befdf897
WY		 2620 if (mlx4_is_master(dev))
2621 mlx4_free_resource_tracker(dev,
2622 RES_TR_FREE_STRUCTS_ONLY);
47605df9 2623
befdf897
WY		 2624 iounmap(priv->kar);
2625 mlx4_uar_free(dev, &priv->driver_uar);
2626 mlx4_cleanup_uar_table(dev);
2627 if (!mlx4_is_slave(dev))
2628 mlx4_clear_steering(dev);
2629 mlx4_free_eq_table(dev);
2630 if (mlx4_is_master(dev))
2631 mlx4_multi_func_cleanup(dev);
2632 mlx4_close_hca(dev);
2633 if (mlx4_is_slave(dev))
2634 mlx4_multi_func_cleanup(dev);
2635 mlx4_cmd_cleanup(dev);
47605df9 2636
befdf897
WY		 2637 if (dev->flags & MLX4_FLAG_MSI_X)
2638 pci_disable_msix(pdev);
2639 if (dev->flags & MLX4_FLAG_SRIOV) {
2640 mlx4_warn(dev, "Disabling SR-IOV\n");
2641 pci_disable_sriov(pdev);
e1a5ddc5 2642 dev->num_vfs = 0;
225c7b1f 2643 }
befdf897
WY		 2644
2645 if (!mlx4_is_slave(dev))
2646 mlx4_free_ownership(dev);
2647
2648 kfree(dev->caps.qp0_tunnel);
2649 kfree(dev->caps.qp0_proxy);
2650 kfree(dev->caps.qp1_tunnel);
2651 kfree(dev->caps.qp1_proxy);
2652 kfree(dev->dev_vfs);
2653
2654 pci_release_regions(pdev);
2655 pci_disable_device(pdev);
2656 memset(priv, 0, sizeof(*priv));
2657 priv->pci_dev_data = pci_dev_data;
2658 priv->removed = 1;
2659}
2660
2661static void mlx4_remove_one(struct pci_dev *pdev)
2662{
2663 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2664 struct mlx4_priv *priv = mlx4_priv(dev);
2665
2666 __mlx4_remove_one(pdev);
2667 kfree(priv);
2668 pci_set_drvdata(pdev, NULL);
225c7b1f
RD		 2669}
2670
ee49bd93
JM		 2671int mlx4_restart_one(struct pci_dev *pdev)
2672{
839f1243
RD		 2673 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2674 struct mlx4_priv *priv = mlx4_priv(dev);
2675 int pci_dev_data;
2676
2677 pci_dev_data = priv->pci_dev_data;
befdf897 2678 __mlx4_remove_one(pdev);
839f1243 2679 return __mlx4_init_one(pdev, pci_dev_data);
ee49bd93
JM		 2680}
2681
a3aa1884 2682static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0 2683 /* MT25408 "Hermon" SDR */
ca3e57a5 2684 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2685 /* MT25408 "Hermon" DDR */
ca3e57a5 2686 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2687 /* MT25408 "Hermon" QDR */
ca3e57a5 2688 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2689 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 2690 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2691 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 2692 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2693 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 2694 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2695 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 2696 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2697 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 2698 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2699 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 2700 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2701 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 2702 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2703 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 2704 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2705 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 2706 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2707 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 2708 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2709 /* MT27500 Family [ConnectX-3] */
2710 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2711 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 2712 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2713 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2714 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2715 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2716 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2717 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2718 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2719 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2720 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2721 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2722 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2723 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2724 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2725 { 0, }
2726};
2727
2728MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2729
57dbf29a
KSS		 2730static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2731 pci_channel_state_t state)
2732{
befdf897 2733 __mlx4_remove_one(pdev);
57dbf29a
KSS		 2734
2735 return state == pci_channel_io_perm_failure ?
2736 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2737}
2738
2739static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2740{
befdf897
WY		 2741 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2742 struct mlx4_priv *priv = mlx4_priv(dev);
2743 int ret;
97a5221f 2744
befdf897 2745 ret = __mlx4_init_one(pdev, priv->pci_dev_data);
57dbf29a
KSS		 2746
2747 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2748}
2749
3646f0e5 2750static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 2751 .error_detected = mlx4_pci_err_detected,
2752 .slot_reset = mlx4_pci_slot_reset,
2753};
2754
225c7b1f
RD		 2755static struct pci_driver mlx4_driver = {
2756 .name = DRV_NAME,
2757 .id_table = mlx4_pci_table,
2758 .probe = mlx4_init_one,
367d56f7 2759 .shutdown = mlx4_remove_one,
f57e6848 2760 .remove = mlx4_remove_one,
57dbf29a 2761 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 2762};
2763
7ff93f8b
YP		 2764static int __init mlx4_verify_params(void)
2765{
2766 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2767 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2768 return -1;
2769 }
2770
cb29688a
OG		 2771 if (log_num_vlan != 0)
2772 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2773 MLX4_LOG_NUM_VLANS);
7ff93f8b 2774
ecc8fb11
AV		 2775 if (use_prio != 0)
2776 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
2777
0498628f 2778 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2779 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2780 return -1;
2781 }
2782
ab9c17a0
JM		 2783 /* Check if module param for ports type has legal combination */
2784 if (port_type_array[0] == false && port_type_array[1] == true) {
2785 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2786 port_type_array[0] = true;
2787 }
2788
3c439b55
JM		 2789 if (mlx4_log_num_mgm_entry_size != -1 &&
2790 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2791 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
1a91de28
JP		 2792 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
2793 mlx4_log_num_mgm_entry_size,
2794 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2795 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 2796 return -1;
2797 }
2798
7ff93f8b
YP		 2799 return 0;
2800}
2801
225c7b1f
RD		 2802static int __init mlx4_init(void)
2803{
2804 int ret;
2805
7ff93f8b
YP		 2806 if (mlx4_verify_params())
2807 return -EINVAL;
2808
27bf91d6
YP		 2809 mlx4_catas_init();
2810
2811 mlx4_wq = create_singlethread_workqueue("mlx4");
2812 if (!mlx4_wq)
2813 return -ENOMEM;
ee49bd93 2814
225c7b1f 2815 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 2816 if (ret < 0)
2817 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2818 return ret < 0 ? ret : 0;
2819}
2820
2821static void __exit mlx4_cleanup(void)
2822{
2823 pci_unregister_driver(&mlx4_driver);
27bf91d6 2824 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2825}
2826
2827module_init(mlx4_init);
2828module_exit(mlx4_cleanup);
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