]>
Commit | Line | Data |
---|---|---|
225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
225c7b1f | 34 | #include <linux/string.h> |
0345584e | 35 | #include <linux/etherdevice.h> |
225c7b1f RD |
36 | |
37 | #include <linux/mlx4/cmd.h> | |
ee40fa06 | 38 | #include <linux/export.h> |
225c7b1f RD |
39 | |
40 | #include "mlx4.h" | |
41 | ||
225c7b1f RD |
42 | static const u8 zero_gid[16]; /* automatically initialized to 0 */ |
43 | ||
0ec2c0f8 EE |
44 | int mlx4_get_mgm_entry_size(struct mlx4_dev *dev) |
45 | { | |
3c439b55 | 46 | return 1 << dev->oper_log_mgm_entry_size; |
0ec2c0f8 EE |
47 | } |
48 | ||
49 | int mlx4_get_qp_per_mgm(struct mlx4_dev *dev) | |
50 | { | |
51 | return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2); | |
52 | } | |
53 | ||
8fcfb4db HHZ |
54 | static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev, |
55 | struct mlx4_cmd_mailbox *mailbox, | |
56 | u32 size, | |
57 | u64 *reg_id) | |
58 | { | |
59 | u64 imm; | |
60 | int err = 0; | |
61 | ||
62 | err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0, | |
63 | MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, | |
64 | MLX4_CMD_NATIVE); | |
65 | if (err) | |
66 | return err; | |
67 | *reg_id = imm; | |
68 | ||
69 | return err; | |
70 | } | |
71 | ||
72 | static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid) | |
73 | { | |
74 | int err = 0; | |
75 | ||
76 | err = mlx4_cmd(dev, regid, 0, 0, | |
77 | MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, | |
78 | MLX4_CMD_NATIVE); | |
79 | ||
80 | return err; | |
81 | } | |
82 | ||
0345584e YP |
83 | static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index, |
84 | struct mlx4_cmd_mailbox *mailbox) | |
225c7b1f RD |
85 | { |
86 | return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG, | |
f9baff50 | 87 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
88 | } |
89 | ||
0345584e YP |
90 | static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index, |
91 | struct mlx4_cmd_mailbox *mailbox) | |
225c7b1f RD |
92 | { |
93 | return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG, | |
f9baff50 | 94 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
95 | } |
96 | ||
0ec2c0f8 | 97 | static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer, |
b12d93d6 YP |
98 | struct mlx4_cmd_mailbox *mailbox) |
99 | { | |
100 | u32 in_mod; | |
101 | ||
0ec2c0f8 | 102 | in_mod = (u32) port << 16 | steer << 1; |
b12d93d6 | 103 | return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1, |
f9baff50 JM |
104 | MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A, |
105 | MLX4_CMD_NATIVE); | |
b12d93d6 YP |
106 | } |
107 | ||
0345584e YP |
108 | static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, |
109 | u16 *hash, u8 op_mod) | |
225c7b1f RD |
110 | { |
111 | u64 imm; | |
112 | int err; | |
113 | ||
0345584e | 114 | err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod, |
f9baff50 JM |
115 | MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A, |
116 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
117 | |
118 | if (!err) | |
119 | *hash = imm; | |
120 | ||
121 | return err; | |
122 | } | |
123 | ||
60d31c14 | 124 | static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port, |
b12d93d6 YP |
125 | enum mlx4_steer_type steer, |
126 | u32 qpn) | |
127 | { | |
982290a7 | 128 | struct mlx4_steer *s_steer; |
b12d93d6 YP |
129 | struct mlx4_promisc_qp *pqp; |
130 | ||
982290a7 MB |
131 | if (port < 1 || port > dev->caps.num_ports) |
132 | return NULL; | |
133 | ||
134 | s_steer = &mlx4_priv(dev)->steer[port - 1]; | |
135 | ||
b12d93d6 YP |
136 | list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) { |
137 | if (pqp->qpn == qpn) | |
138 | return pqp; | |
139 | } | |
140 | /* not found */ | |
141 | return NULL; | |
142 | } | |
143 | ||
144 | /* | |
145 | * Add new entry to steering data structure. | |
146 | * All promisc QPs should be added as well | |
147 | */ | |
0ec2c0f8 | 148 | static int new_steering_entry(struct mlx4_dev *dev, u8 port, |
b12d93d6 YP |
149 | enum mlx4_steer_type steer, |
150 | unsigned int index, u32 qpn) | |
151 | { | |
152 | struct mlx4_steer *s_steer; | |
153 | struct mlx4_cmd_mailbox *mailbox; | |
154 | struct mlx4_mgm *mgm; | |
155 | u32 members_count; | |
156 | struct mlx4_steer_index *new_entry; | |
157 | struct mlx4_promisc_qp *pqp; | |
a14b289d | 158 | struct mlx4_promisc_qp *dqp = NULL; |
b12d93d6 YP |
159 | u32 prot; |
160 | int err; | |
b12d93d6 | 161 | |
982290a7 MB |
162 | if (port < 1 || port > dev->caps.num_ports) |
163 | return -EINVAL; | |
164 | ||
4c41b367 | 165 | s_steer = &mlx4_priv(dev)->steer[port - 1]; |
b12d93d6 YP |
166 | new_entry = kzalloc(sizeof *new_entry, GFP_KERNEL); |
167 | if (!new_entry) | |
168 | return -ENOMEM; | |
169 | ||
170 | INIT_LIST_HEAD(&new_entry->duplicates); | |
171 | new_entry->index = index; | |
172 | list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]); | |
173 | ||
174 | /* If the given qpn is also a promisc qp, | |
175 | * it should be inserted to duplicates list | |
176 | */ | |
60d31c14 | 177 | pqp = get_promisc_qp(dev, port, steer, qpn); |
b12d93d6 YP |
178 | if (pqp) { |
179 | dqp = kmalloc(sizeof *dqp, GFP_KERNEL); | |
180 | if (!dqp) { | |
181 | err = -ENOMEM; | |
182 | goto out_alloc; | |
183 | } | |
184 | dqp->qpn = qpn; | |
185 | list_add_tail(&dqp->list, &new_entry->duplicates); | |
186 | } | |
187 | ||
188 | /* if no promisc qps for this vep, we are done */ | |
189 | if (list_empty(&s_steer->promisc_qps[steer])) | |
190 | return 0; | |
191 | ||
192 | /* now need to add all the promisc qps to the new | |
193 | * steering entry, as they should also receive the packets | |
194 | * destined to this address */ | |
195 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
196 | if (IS_ERR(mailbox)) { | |
197 | err = -ENOMEM; | |
198 | goto out_alloc; | |
199 | } | |
200 | mgm = mailbox->buf; | |
201 | ||
202 | err = mlx4_READ_ENTRY(dev, index, mailbox); | |
203 | if (err) | |
204 | goto out_mailbox; | |
205 | ||
206 | members_count = be32_to_cpu(mgm->members_count) & 0xffffff; | |
207 | prot = be32_to_cpu(mgm->members_count) >> 30; | |
208 | list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) { | |
209 | /* don't add already existing qpn */ | |
210 | if (pqp->qpn == qpn) | |
211 | continue; | |
0ec2c0f8 | 212 | if (members_count == dev->caps.num_qp_per_mgm) { |
b12d93d6 YP |
213 | /* out of space */ |
214 | err = -ENOMEM; | |
215 | goto out_mailbox; | |
216 | } | |
217 | ||
218 | /* add the qpn */ | |
219 | mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK); | |
220 | } | |
221 | /* update the qps count and update the entry with all the promisc qps*/ | |
222 | mgm->members_count = cpu_to_be32(members_count | (prot << 30)); | |
223 | err = mlx4_WRITE_ENTRY(dev, index, mailbox); | |
224 | ||
225 | out_mailbox: | |
226 | mlx4_free_cmd_mailbox(dev, mailbox); | |
227 | if (!err) | |
228 | return 0; | |
229 | out_alloc: | |
230 | if (dqp) { | |
231 | list_del(&dqp->list); | |
a14b289d | 232 | kfree(dqp); |
b12d93d6 YP |
233 | } |
234 | list_del(&new_entry->list); | |
235 | kfree(new_entry); | |
236 | return err; | |
237 | } | |
238 | ||
239 | /* update the data structures with existing steering entry */ | |
0ec2c0f8 | 240 | static int existing_steering_entry(struct mlx4_dev *dev, u8 port, |
b12d93d6 YP |
241 | enum mlx4_steer_type steer, |
242 | unsigned int index, u32 qpn) | |
243 | { | |
244 | struct mlx4_steer *s_steer; | |
245 | struct mlx4_steer_index *tmp_entry, *entry = NULL; | |
246 | struct mlx4_promisc_qp *pqp; | |
247 | struct mlx4_promisc_qp *dqp; | |
b12d93d6 | 248 | |
982290a7 MB |
249 | if (port < 1 || port > dev->caps.num_ports) |
250 | return -EINVAL; | |
251 | ||
4c41b367 | 252 | s_steer = &mlx4_priv(dev)->steer[port - 1]; |
b12d93d6 | 253 | |
60d31c14 | 254 | pqp = get_promisc_qp(dev, port, steer, qpn); |
b12d93d6 YP |
255 | if (!pqp) |
256 | return 0; /* nothing to do */ | |
257 | ||
258 | list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) { | |
259 | if (tmp_entry->index == index) { | |
260 | entry = tmp_entry; | |
261 | break; | |
262 | } | |
263 | } | |
264 | if (unlikely(!entry)) { | |
265 | mlx4_warn(dev, "Steering entry at index %x is not registered\n", index); | |
266 | return -EINVAL; | |
267 | } | |
268 | ||
269 | /* the given qpn is listed as a promisc qpn | |
270 | * we need to add it as a duplicate to this entry | |
25985edc | 271 | * for future references */ |
b12d93d6 | 272 | list_for_each_entry(dqp, &entry->duplicates, list) { |
1645a540 | 273 | if (qpn == dqp->qpn) |
b12d93d6 YP |
274 | return 0; /* qp is already duplicated */ |
275 | } | |
276 | ||
277 | /* add the qp as a duplicate on this index */ | |
278 | dqp = kmalloc(sizeof *dqp, GFP_KERNEL); | |
279 | if (!dqp) | |
280 | return -ENOMEM; | |
281 | dqp->qpn = qpn; | |
282 | list_add_tail(&dqp->list, &entry->duplicates); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | /* Check whether a qpn is a duplicate on steering entry | |
288 | * If so, it should not be removed from mgm */ | |
0ec2c0f8 | 289 | static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port, |
b12d93d6 YP |
290 | enum mlx4_steer_type steer, |
291 | unsigned int index, u32 qpn) | |
292 | { | |
293 | struct mlx4_steer *s_steer; | |
294 | struct mlx4_steer_index *tmp_entry, *entry = NULL; | |
295 | struct mlx4_promisc_qp *dqp, *tmp_dqp; | |
b12d93d6 | 296 | |
982290a7 MB |
297 | if (port < 1 || port > dev->caps.num_ports) |
298 | return NULL; | |
299 | ||
4c41b367 | 300 | s_steer = &mlx4_priv(dev)->steer[port - 1]; |
b12d93d6 YP |
301 | |
302 | /* if qp is not promisc, it cannot be duplicated */ | |
60d31c14 | 303 | if (!get_promisc_qp(dev, port, steer, qpn)) |
b12d93d6 YP |
304 | return false; |
305 | ||
306 | /* The qp is promisc qp so it is a duplicate on this index | |
307 | * Find the index entry, and remove the duplicate */ | |
308 | list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) { | |
309 | if (tmp_entry->index == index) { | |
310 | entry = tmp_entry; | |
311 | break; | |
312 | } | |
313 | } | |
314 | if (unlikely(!entry)) { | |
315 | mlx4_warn(dev, "Steering entry for index %x is not registered\n", index); | |
316 | return false; | |
317 | } | |
318 | list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) { | |
319 | if (dqp->qpn == qpn) { | |
320 | list_del(&dqp->list); | |
321 | kfree(dqp); | |
322 | } | |
323 | } | |
324 | return true; | |
325 | } | |
326 | ||
1645a540 SM |
327 | /* Returns true if all the QPs != tqpn contained in this entry |
328 | * are Promisc QPs. Returns false otherwise. | |
329 | */ | |
330 | static bool promisc_steering_entry(struct mlx4_dev *dev, u8 port, | |
331 | enum mlx4_steer_type steer, | |
332 | unsigned int index, u32 tqpn, | |
333 | u32 *members_count) | |
b12d93d6 | 334 | { |
b12d93d6 YP |
335 | struct mlx4_cmd_mailbox *mailbox; |
336 | struct mlx4_mgm *mgm; | |
1645a540 | 337 | u32 m_count; |
b12d93d6 YP |
338 | bool ret = false; |
339 | int i; | |
b12d93d6 | 340 | |
982290a7 | 341 | if (port < 1 || port > dev->caps.num_ports) |
1645a540 | 342 | return false; |
b12d93d6 YP |
343 | |
344 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
345 | if (IS_ERR(mailbox)) | |
346 | return false; | |
347 | mgm = mailbox->buf; | |
348 | ||
349 | if (mlx4_READ_ENTRY(dev, index, mailbox)) | |
350 | goto out; | |
1645a540 SM |
351 | m_count = be32_to_cpu(mgm->members_count) & 0xffffff; |
352 | if (members_count) | |
353 | *members_count = m_count; | |
354 | ||
355 | for (i = 0; i < m_count; i++) { | |
356 | u32 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK; | |
60d31c14 | 357 | if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) { |
b12d93d6 YP |
358 | /* the qp is not promisc, the entry can't be removed */ |
359 | goto out; | |
360 | } | |
361 | } | |
1645a540 SM |
362 | ret = true; |
363 | out: | |
364 | mlx4_free_cmd_mailbox(dev, mailbox); | |
365 | return ret; | |
366 | } | |
367 | ||
368 | /* IF a steering entry contains only promisc QPs, it can be removed. */ | |
369 | static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port, | |
370 | enum mlx4_steer_type steer, | |
371 | unsigned int index, u32 tqpn) | |
372 | { | |
373 | struct mlx4_steer *s_steer; | |
374 | struct mlx4_steer_index *entry = NULL, *tmp_entry; | |
375 | u32 members_count; | |
376 | bool ret = false; | |
377 | ||
378 | if (port < 1 || port > dev->caps.num_ports) | |
379 | return NULL; | |
380 | ||
381 | s_steer = &mlx4_priv(dev)->steer[port - 1]; | |
382 | ||
383 | if (!promisc_steering_entry(dev, port, steer, index, | |
384 | tqpn, &members_count)) | |
385 | goto out; | |
386 | ||
387 | /* All the qps currently registered for this entry are promiscuous, | |
b12d93d6 YP |
388 | * Checking for duplicates */ |
389 | ret = true; | |
390 | list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) { | |
391 | if (entry->index == index) { | |
0d7869ac YP |
392 | if (list_empty(&entry->duplicates) || |
393 | members_count == 1) { | |
394 | struct mlx4_promisc_qp *pqp, *tmp_pqp; | |
395 | /* If there is only 1 entry in duplicates then | |
396 | * this is the QP we want to delete, going over | |
397 | * the list and deleting the entry. | |
398 | */ | |
b12d93d6 | 399 | list_del(&entry->list); |
0d7869ac YP |
400 | list_for_each_entry_safe(pqp, tmp_pqp, |
401 | &entry->duplicates, | |
402 | list) { | |
403 | list_del(&pqp->list); | |
404 | kfree(pqp); | |
405 | } | |
b12d93d6 YP |
406 | kfree(entry); |
407 | } else { | |
408 | /* This entry contains duplicates so it shouldn't be removed */ | |
409 | ret = false; | |
410 | goto out; | |
411 | } | |
412 | } | |
413 | } | |
414 | ||
415 | out: | |
b12d93d6 YP |
416 | return ret; |
417 | } | |
418 | ||
0ec2c0f8 | 419 | static int add_promisc_qp(struct mlx4_dev *dev, u8 port, |
b12d93d6 YP |
420 | enum mlx4_steer_type steer, u32 qpn) |
421 | { | |
422 | struct mlx4_steer *s_steer; | |
423 | struct mlx4_cmd_mailbox *mailbox; | |
424 | struct mlx4_mgm *mgm; | |
425 | struct mlx4_steer_index *entry; | |
426 | struct mlx4_promisc_qp *pqp; | |
427 | struct mlx4_promisc_qp *dqp; | |
428 | u32 members_count; | |
429 | u32 prot; | |
430 | int i; | |
431 | bool found; | |
b12d93d6 | 432 | int err; |
b12d93d6 | 433 | struct mlx4_priv *priv = mlx4_priv(dev); |
0ec2c0f8 | 434 | |
982290a7 MB |
435 | if (port < 1 || port > dev->caps.num_ports) |
436 | return -EINVAL; | |
437 | ||
4c41b367 | 438 | s_steer = &mlx4_priv(dev)->steer[port - 1]; |
b12d93d6 YP |
439 | |
440 | mutex_lock(&priv->mcg_table.mutex); | |
441 | ||
60d31c14 | 442 | if (get_promisc_qp(dev, port, steer, qpn)) { |
b12d93d6 YP |
443 | err = 0; /* Noting to do, already exists */ |
444 | goto out_mutex; | |
445 | } | |
446 | ||
447 | pqp = kmalloc(sizeof *pqp, GFP_KERNEL); | |
448 | if (!pqp) { | |
449 | err = -ENOMEM; | |
450 | goto out_mutex; | |
451 | } | |
452 | pqp->qpn = qpn; | |
453 | ||
454 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
455 | if (IS_ERR(mailbox)) { | |
456 | err = -ENOMEM; | |
457 | goto out_alloc; | |
458 | } | |
459 | mgm = mailbox->buf; | |
460 | ||
816e5984 EE |
461 | if (!(mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)) { |
462 | /* The promisc QP needs to be added for each one of the steering | |
463 | * entries. If it already exists, needs to be added as | |
464 | * a duplicate for this entry. | |
465 | */ | |
466 | list_for_each_entry(entry, | |
467 | &s_steer->steer_entries[steer], | |
468 | list) { | |
469 | err = mlx4_READ_ENTRY(dev, entry->index, mailbox); | |
470 | if (err) | |
471 | goto out_mailbox; | |
b12d93d6 | 472 | |
816e5984 EE |
473 | members_count = be32_to_cpu(mgm->members_count) & |
474 | 0xffffff; | |
475 | prot = be32_to_cpu(mgm->members_count) >> 30; | |
476 | found = false; | |
477 | for (i = 0; i < members_count; i++) { | |
478 | if ((be32_to_cpu(mgm->qp[i]) & | |
479 | MGM_QPN_MASK) == qpn) { | |
480 | /* Entry already exists. | |
481 | * Add to duplicates. | |
482 | */ | |
483 | dqp = kmalloc(sizeof(*dqp), GFP_KERNEL); | |
484 | if (!dqp) { | |
485 | err = -ENOMEM; | |
486 | goto out_mailbox; | |
487 | } | |
488 | dqp->qpn = qpn; | |
489 | list_add_tail(&dqp->list, | |
490 | &entry->duplicates); | |
491 | found = true; | |
492 | } | |
493 | } | |
494 | if (!found) { | |
495 | /* Need to add the qpn to mgm */ | |
496 | if (members_count == | |
497 | dev->caps.num_qp_per_mgm) { | |
498 | /* entry is full */ | |
499b95f6 | 499 | err = -ENOMEM; |
b12d93d6 | 500 | goto out_mailbox; |
499b95f6 | 501 | } |
816e5984 EE |
502 | mgm->qp[members_count++] = |
503 | cpu_to_be32(qpn & MGM_QPN_MASK); | |
504 | mgm->members_count = | |
505 | cpu_to_be32(members_count | | |
506 | (prot << 30)); | |
507 | err = mlx4_WRITE_ENTRY(dev, entry->index, | |
508 | mailbox); | |
509 | if (err) | |
510 | goto out_mailbox; | |
b12d93d6 | 511 | } |
b12d93d6 | 512 | } |
b12d93d6 YP |
513 | } |
514 | ||
515 | /* add the new qpn to list of promisc qps */ | |
516 | list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]); | |
517 | /* now need to add all the promisc qps to default entry */ | |
518 | memset(mgm, 0, sizeof *mgm); | |
519 | members_count = 0; | |
75908376 AG |
520 | list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list) { |
521 | if (members_count == dev->caps.num_qp_per_mgm) { | |
522 | /* entry is full */ | |
523 | err = -ENOMEM; | |
524 | goto out_list; | |
525 | } | |
b12d93d6 | 526 | mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK); |
75908376 | 527 | } |
b12d93d6 YP |
528 | mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30); |
529 | ||
0ec2c0f8 | 530 | err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox); |
b12d93d6 YP |
531 | if (err) |
532 | goto out_list; | |
533 | ||
534 | mlx4_free_cmd_mailbox(dev, mailbox); | |
535 | mutex_unlock(&priv->mcg_table.mutex); | |
536 | return 0; | |
537 | ||
538 | out_list: | |
539 | list_del(&pqp->list); | |
540 | out_mailbox: | |
541 | mlx4_free_cmd_mailbox(dev, mailbox); | |
542 | out_alloc: | |
543 | kfree(pqp); | |
544 | out_mutex: | |
545 | mutex_unlock(&priv->mcg_table.mutex); | |
546 | return err; | |
547 | } | |
548 | ||
0ec2c0f8 | 549 | static int remove_promisc_qp(struct mlx4_dev *dev, u8 port, |
b12d93d6 YP |
550 | enum mlx4_steer_type steer, u32 qpn) |
551 | { | |
552 | struct mlx4_priv *priv = mlx4_priv(dev); | |
553 | struct mlx4_steer *s_steer; | |
554 | struct mlx4_cmd_mailbox *mailbox; | |
555 | struct mlx4_mgm *mgm; | |
1645a540 | 556 | struct mlx4_steer_index *entry, *tmp_entry; |
b12d93d6 YP |
557 | struct mlx4_promisc_qp *pqp; |
558 | struct mlx4_promisc_qp *dqp; | |
559 | u32 members_count; | |
560 | bool found; | |
561 | bool back_to_list = false; | |
aab2bb0e | 562 | int i; |
b12d93d6 | 563 | int err; |
b12d93d6 | 564 | |
982290a7 MB |
565 | if (port < 1 || port > dev->caps.num_ports) |
566 | return -EINVAL; | |
567 | ||
4c41b367 | 568 | s_steer = &mlx4_priv(dev)->steer[port - 1]; |
b12d93d6 YP |
569 | mutex_lock(&priv->mcg_table.mutex); |
570 | ||
60d31c14 | 571 | pqp = get_promisc_qp(dev, port, steer, qpn); |
b12d93d6 YP |
572 | if (unlikely(!pqp)) { |
573 | mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn); | |
574 | /* nothing to do */ | |
575 | err = 0; | |
576 | goto out_mutex; | |
577 | } | |
578 | ||
579 | /*remove from list of promisc qps */ | |
580 | list_del(&pqp->list); | |
b12d93d6 YP |
581 | |
582 | /* set the default entry not to include the removed one */ | |
583 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
584 | if (IS_ERR(mailbox)) { | |
585 | err = -ENOMEM; | |
586 | back_to_list = true; | |
587 | goto out_list; | |
588 | } | |
589 | mgm = mailbox->buf; | |
590 | members_count = 0; | |
591 | list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list) | |
592 | mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK); | |
593 | mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30); | |
594 | ||
0ec2c0f8 | 595 | err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox); |
b12d93d6 YP |
596 | if (err) |
597 | goto out_mailbox; | |
598 | ||
816e5984 | 599 | if (!(mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)) { |
1645a540 SM |
600 | /* Remove the QP from all the steering entries */ |
601 | list_for_each_entry_safe(entry, tmp_entry, | |
602 | &s_steer->steer_entries[steer], | |
603 | list) { | |
816e5984 EE |
604 | found = false; |
605 | list_for_each_entry(dqp, &entry->duplicates, list) { | |
606 | if (dqp->qpn == qpn) { | |
607 | found = true; | |
608 | break; | |
609 | } | |
b12d93d6 | 610 | } |
816e5984 EE |
611 | if (found) { |
612 | /* A duplicate, no need to change the MGM, | |
613 | * only update the duplicates list | |
614 | */ | |
615 | list_del(&dqp->list); | |
616 | kfree(dqp); | |
617 | } else { | |
618 | int loc = -1; | |
619 | ||
620 | err = mlx4_READ_ENTRY(dev, | |
621 | entry->index, | |
622 | mailbox); | |
623 | if (err) | |
624 | goto out_mailbox; | |
625 | members_count = | |
626 | be32_to_cpu(mgm->members_count) & | |
627 | 0xffffff; | |
1645a540 SM |
628 | if (!members_count) { |
629 | mlx4_warn(dev, "QP %06x wasn't found in entry %x mcount=0. deleting entry...\n", | |
630 | qpn, entry->index); | |
631 | list_del(&entry->list); | |
632 | kfree(entry); | |
633 | continue; | |
634 | } | |
635 | ||
816e5984 EE |
636 | for (i = 0; i < members_count; ++i) |
637 | if ((be32_to_cpu(mgm->qp[i]) & | |
638 | MGM_QPN_MASK) == qpn) { | |
639 | loc = i; | |
640 | break; | |
641 | } | |
642 | ||
643 | if (loc < 0) { | |
644 | mlx4_err(dev, "QP %06x wasn't found in entry %d\n", | |
645 | qpn, entry->index); | |
646 | err = -EINVAL; | |
b12d93d6 | 647 | goto out_mailbox; |
aab2bb0e DB |
648 | } |
649 | ||
1645a540 | 650 | /* Copy the last QP in this MGM |
816e5984 EE |
651 | * over removed QP |
652 | */ | |
653 | mgm->qp[loc] = mgm->qp[members_count - 1]; | |
654 | mgm->qp[members_count - 1] = 0; | |
655 | mgm->members_count = | |
656 | cpu_to_be32(--members_count | | |
657 | (MLX4_PROT_ETH << 30)); | |
658 | ||
659 | err = mlx4_WRITE_ENTRY(dev, | |
660 | entry->index, | |
661 | mailbox); | |
662 | if (err) | |
663 | goto out_mailbox; | |
aab2bb0e | 664 | } |
b12d93d6 | 665 | } |
b12d93d6 YP |
666 | } |
667 | ||
668 | out_mailbox: | |
669 | mlx4_free_cmd_mailbox(dev, mailbox); | |
670 | out_list: | |
671 | if (back_to_list) | |
672 | list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]); | |
53020092 YP |
673 | else |
674 | kfree(pqp); | |
b12d93d6 YP |
675 | out_mutex: |
676 | mutex_unlock(&priv->mcg_table.mutex); | |
677 | return err; | |
678 | } | |
679 | ||
225c7b1f RD |
680 | /* |
681 | * Caller must hold MCG table semaphore. gid and mgm parameters must | |
682 | * be properly aligned for command interface. | |
683 | * | |
684 | * Returns 0 unless a firmware command error occurs. | |
685 | * | |
686 | * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1 | |
687 | * and *mgm holds MGM entry. | |
688 | * | |
689 | * if GID is found in AMGM, *index = index in AMGM, *prev = index of | |
690 | * previous entry in hash chain and *mgm holds AMGM entry. | |
691 | * | |
692 | * If no AMGM exists for given gid, *index = -1, *prev = index of last | |
693 | * entry in hash chain and *mgm holds end of hash chain. | |
694 | */ | |
0345584e YP |
695 | static int find_entry(struct mlx4_dev *dev, u8 port, |
696 | u8 *gid, enum mlx4_protocol prot, | |
0345584e | 697 | struct mlx4_cmd_mailbox *mgm_mailbox, |
deb8b3e8 | 698 | int *prev, int *index) |
225c7b1f RD |
699 | { |
700 | struct mlx4_cmd_mailbox *mailbox; | |
701 | struct mlx4_mgm *mgm = mgm_mailbox->buf; | |
702 | u8 *mgid; | |
703 | int err; | |
deb8b3e8 | 704 | u16 hash; |
ccf86321 OG |
705 | u8 op_mod = (prot == MLX4_PROT_ETH) ? |
706 | !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0; | |
225c7b1f RD |
707 | |
708 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
709 | if (IS_ERR(mailbox)) | |
710 | return -ENOMEM; | |
711 | mgid = mailbox->buf; | |
712 | ||
713 | memcpy(mgid, gid, 16); | |
714 | ||
deb8b3e8 | 715 | err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod); |
225c7b1f RD |
716 | mlx4_free_cmd_mailbox(dev, mailbox); |
717 | if (err) | |
718 | return err; | |
719 | ||
720 | if (0) | |
deb8b3e8 | 721 | mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash); |
225c7b1f | 722 | |
deb8b3e8 | 723 | *index = hash; |
225c7b1f RD |
724 | *prev = -1; |
725 | ||
726 | do { | |
0345584e | 727 | err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox); |
225c7b1f RD |
728 | if (err) |
729 | return err; | |
730 | ||
0345584e | 731 | if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) { |
deb8b3e8 | 732 | if (*index != hash) { |
1a91de28 | 733 | mlx4_err(dev, "Found zero MGID in AMGM\n"); |
225c7b1f RD |
734 | err = -EINVAL; |
735 | } | |
736 | return err; | |
737 | } | |
738 | ||
da995a8a | 739 | if (!memcmp(mgm->gid, gid, 16) && |
0345584e | 740 | be32_to_cpu(mgm->members_count) >> 30 == prot) |
225c7b1f RD |
741 | return err; |
742 | ||
743 | *prev = *index; | |
744 | *index = be32_to_cpu(mgm->next_gid_index) >> 6; | |
745 | } while (*index); | |
746 | ||
747 | *index = -1; | |
748 | return err; | |
749 | } | |
750 | ||
c2c19dc3 HHZ |
751 | static const u8 __promisc_mode[] = { |
752 | [MLX4_FS_REGULAR] = 0x0, | |
753 | [MLX4_FS_ALL_DEFAULT] = 0x1, | |
754 | [MLX4_FS_MC_DEFAULT] = 0x3, | |
755 | [MLX4_FS_UC_SNIFFER] = 0x4, | |
756 | [MLX4_FS_MC_SNIFFER] = 0x5, | |
757 | }; | |
758 | ||
759 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, | |
760 | enum mlx4_net_trans_promisc_mode flow_type) | |
761 | { | |
fe66bb2d | 762 | if (flow_type >= MLX4_FS_MODE_NUM) { |
c2c19dc3 HHZ |
763 | mlx4_err(dev, "Invalid flow type. type = %d\n", flow_type); |
764 | return -EINVAL; | |
765 | } | |
766 | return __promisc_mode[flow_type]; | |
767 | } | |
768 | EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode); | |
769 | ||
0ff1fb65 HHZ |
770 | static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl, |
771 | struct mlx4_net_trans_rule_hw_ctrl *hw) | |
772 | { | |
bcf37297 | 773 | u8 flags = 0; |
0ff1fb65 | 774 | |
bcf37297 HHZ |
775 | flags = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0; |
776 | flags |= ctrl->exclusive ? (1 << 2) : 0; | |
777 | flags |= ctrl->allow_loopback ? (1 << 3) : 0; | |
0ff1fb65 | 778 | |
bcf37297 HHZ |
779 | hw->flags = flags; |
780 | hw->type = __promisc_mode[ctrl->promisc_mode]; | |
781 | hw->prio = cpu_to_be16(ctrl->priority); | |
015465f8 | 782 | hw->port = ctrl->port; |
0ff1fb65 HHZ |
783 | hw->qpn = cpu_to_be32(ctrl->qpn); |
784 | } | |
785 | ||
a8edc3bf HHZ |
786 | const u16 __sw_id_hw[] = { |
787 | [MLX4_NET_TRANS_RULE_ID_ETH] = 0xE001, | |
788 | [MLX4_NET_TRANS_RULE_ID_IB] = 0xE005, | |
789 | [MLX4_NET_TRANS_RULE_ID_IPV6] = 0xE003, | |
790 | [MLX4_NET_TRANS_RULE_ID_IPV4] = 0xE002, | |
791 | [MLX4_NET_TRANS_RULE_ID_TCP] = 0xE004, | |
7ffdf726 OG |
792 | [MLX4_NET_TRANS_RULE_ID_UDP] = 0xE006, |
793 | [MLX4_NET_TRANS_RULE_ID_VXLAN] = 0xE008 | |
0ff1fb65 HHZ |
794 | }; |
795 | ||
c2c19dc3 HHZ |
796 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, |
797 | enum mlx4_net_trans_rule_id id) | |
798 | { | |
fe66bb2d | 799 | if (id >= MLX4_NET_TRANS_RULE_NUM) { |
c2c19dc3 HHZ |
800 | mlx4_err(dev, "Invalid network rule id. id = %d\n", id); |
801 | return -EINVAL; | |
802 | } | |
803 | return __sw_id_hw[id]; | |
804 | } | |
805 | EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id); | |
806 | ||
807 | static const int __rule_hw_sz[] = { | |
808 | [MLX4_NET_TRANS_RULE_ID_ETH] = | |
809 | sizeof(struct mlx4_net_trans_rule_hw_eth), | |
810 | [MLX4_NET_TRANS_RULE_ID_IB] = | |
811 | sizeof(struct mlx4_net_trans_rule_hw_ib), | |
812 | [MLX4_NET_TRANS_RULE_ID_IPV6] = 0, | |
813 | [MLX4_NET_TRANS_RULE_ID_IPV4] = | |
814 | sizeof(struct mlx4_net_trans_rule_hw_ipv4), | |
815 | [MLX4_NET_TRANS_RULE_ID_TCP] = | |
816 | sizeof(struct mlx4_net_trans_rule_hw_tcp_udp), | |
817 | [MLX4_NET_TRANS_RULE_ID_UDP] = | |
7ffdf726 OG |
818 | sizeof(struct mlx4_net_trans_rule_hw_tcp_udp), |
819 | [MLX4_NET_TRANS_RULE_ID_VXLAN] = | |
820 | sizeof(struct mlx4_net_trans_rule_hw_vxlan) | |
c2c19dc3 HHZ |
821 | }; |
822 | ||
823 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, | |
824 | enum mlx4_net_trans_rule_id id) | |
825 | { | |
fe66bb2d | 826 | if (id >= MLX4_NET_TRANS_RULE_NUM) { |
c2c19dc3 HHZ |
827 | mlx4_err(dev, "Invalid network rule id. id = %d\n", id); |
828 | return -EINVAL; | |
829 | } | |
830 | ||
831 | return __rule_hw_sz[id]; | |
832 | } | |
833 | EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz); | |
834 | ||
0ff1fb65 HHZ |
835 | static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec, |
836 | struct _rule_hw *rule_hw) | |
837 | { | |
c2c19dc3 | 838 | if (mlx4_hw_rule_sz(dev, spec->id) < 0) |
0ff1fb65 | 839 | return -EINVAL; |
c2c19dc3 | 840 | memset(rule_hw, 0, mlx4_hw_rule_sz(dev, spec->id)); |
0ff1fb65 | 841 | rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]); |
c2c19dc3 | 842 | rule_hw->size = mlx4_hw_rule_sz(dev, spec->id) >> 2; |
0ff1fb65 HHZ |
843 | |
844 | switch (spec->id) { | |
845 | case MLX4_NET_TRANS_RULE_ID_ETH: | |
846 | memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN); | |
847 | memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk, | |
848 | ETH_ALEN); | |
849 | memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN); | |
850 | memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk, | |
851 | ETH_ALEN); | |
852 | if (spec->eth.ether_type_enable) { | |
853 | rule_hw->eth.ether_type_enable = 1; | |
854 | rule_hw->eth.ether_type = spec->eth.ether_type; | |
855 | } | |
ba60a356 HHZ |
856 | rule_hw->eth.vlan_tag = spec->eth.vlan_id; |
857 | rule_hw->eth.vlan_tag_msk = spec->eth.vlan_id_msk; | |
0ff1fb65 HHZ |
858 | break; |
859 | ||
860 | case MLX4_NET_TRANS_RULE_ID_IB: | |
ba60a356 | 861 | rule_hw->ib.l3_qpn = spec->ib.l3_qpn; |
0ff1fb65 HHZ |
862 | rule_hw->ib.qpn_mask = spec->ib.qpn_msk; |
863 | memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16); | |
864 | memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16); | |
865 | break; | |
866 | ||
867 | case MLX4_NET_TRANS_RULE_ID_IPV6: | |
868 | return -EOPNOTSUPP; | |
869 | ||
870 | case MLX4_NET_TRANS_RULE_ID_IPV4: | |
871 | rule_hw->ipv4.src_ip = spec->ipv4.src_ip; | |
872 | rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk; | |
873 | rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip; | |
874 | rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk; | |
875 | break; | |
876 | ||
877 | case MLX4_NET_TRANS_RULE_ID_TCP: | |
878 | case MLX4_NET_TRANS_RULE_ID_UDP: | |
879 | rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port; | |
880 | rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk; | |
881 | rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port; | |
882 | rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk; | |
883 | break; | |
884 | ||
7ffdf726 OG |
885 | case MLX4_NET_TRANS_RULE_ID_VXLAN: |
886 | rule_hw->vxlan.vni = | |
887 | cpu_to_be32(be32_to_cpu(spec->vxlan.vni) << 8); | |
888 | rule_hw->vxlan.vni_mask = | |
889 | cpu_to_be32(be32_to_cpu(spec->vxlan.vni_mask) << 8); | |
890 | break; | |
891 | ||
0ff1fb65 HHZ |
892 | default: |
893 | return -EINVAL; | |
894 | } | |
895 | ||
896 | return __rule_hw_sz[spec->id]; | |
897 | } | |
898 | ||
899 | static void mlx4_err_rule(struct mlx4_dev *dev, char *str, | |
900 | struct mlx4_net_trans_rule *rule) | |
901 | { | |
902 | #define BUF_SIZE 256 | |
903 | struct mlx4_spec_list *cur; | |
904 | char buf[BUF_SIZE]; | |
905 | int len = 0; | |
906 | ||
907 | mlx4_err(dev, "%s", str); | |
908 | len += snprintf(buf + len, BUF_SIZE - len, | |
909 | "port = %d prio = 0x%x qp = 0x%x ", | |
910 | rule->port, rule->priority, rule->qpn); | |
911 | ||
912 | list_for_each_entry(cur, &rule->list, list) { | |
913 | switch (cur->id) { | |
914 | case MLX4_NET_TRANS_RULE_ID_ETH: | |
915 | len += snprintf(buf + len, BUF_SIZE - len, | |
916 | "dmac = %pM ", &cur->eth.dst_mac); | |
917 | if (cur->eth.ether_type) | |
918 | len += snprintf(buf + len, BUF_SIZE - len, | |
919 | "ethertype = 0x%x ", | |
920 | be16_to_cpu(cur->eth.ether_type)); | |
921 | if (cur->eth.vlan_id) | |
922 | len += snprintf(buf + len, BUF_SIZE - len, | |
923 | "vlan-id = %d ", | |
924 | be16_to_cpu(cur->eth.vlan_id)); | |
925 | break; | |
926 | ||
927 | case MLX4_NET_TRANS_RULE_ID_IPV4: | |
928 | if (cur->ipv4.src_ip) | |
929 | len += snprintf(buf + len, BUF_SIZE - len, | |
930 | "src-ip = %pI4 ", | |
931 | &cur->ipv4.src_ip); | |
932 | if (cur->ipv4.dst_ip) | |
933 | len += snprintf(buf + len, BUF_SIZE - len, | |
934 | "dst-ip = %pI4 ", | |
935 | &cur->ipv4.dst_ip); | |
936 | break; | |
937 | ||
938 | case MLX4_NET_TRANS_RULE_ID_TCP: | |
939 | case MLX4_NET_TRANS_RULE_ID_UDP: | |
940 | if (cur->tcp_udp.src_port) | |
941 | len += snprintf(buf + len, BUF_SIZE - len, | |
942 | "src-port = %d ", | |
943 | be16_to_cpu(cur->tcp_udp.src_port)); | |
944 | if (cur->tcp_udp.dst_port) | |
945 | len += snprintf(buf + len, BUF_SIZE - len, | |
946 | "dst-port = %d ", | |
947 | be16_to_cpu(cur->tcp_udp.dst_port)); | |
948 | break; | |
949 | ||
950 | case MLX4_NET_TRANS_RULE_ID_IB: | |
951 | len += snprintf(buf + len, BUF_SIZE - len, | |
952 | "dst-gid = %pI6\n", cur->ib.dst_gid); | |
953 | len += snprintf(buf + len, BUF_SIZE - len, | |
954 | "dst-gid-mask = %pI6\n", | |
955 | cur->ib.dst_gid_msk); | |
956 | break; | |
957 | ||
958 | case MLX4_NET_TRANS_RULE_ID_IPV6: | |
959 | break; | |
960 | ||
961 | default: | |
962 | break; | |
963 | } | |
964 | } | |
965 | len += snprintf(buf + len, BUF_SIZE - len, "\n"); | |
966 | mlx4_err(dev, "%s", buf); | |
967 | ||
968 | if (len >= BUF_SIZE) | |
1a91de28 | 969 | mlx4_err(dev, "Network rule error message was truncated, print buffer is too small\n"); |
0ff1fb65 HHZ |
970 | } |
971 | ||
972 | int mlx4_flow_attach(struct mlx4_dev *dev, | |
973 | struct mlx4_net_trans_rule *rule, u64 *reg_id) | |
974 | { | |
975 | struct mlx4_cmd_mailbox *mailbox; | |
976 | struct mlx4_spec_list *cur; | |
977 | u32 size = 0; | |
978 | int ret; | |
979 | ||
980 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
981 | if (IS_ERR(mailbox)) | |
982 | return PTR_ERR(mailbox); | |
983 | ||
0ff1fb65 HHZ |
984 | trans_rule_ctrl_to_hw(rule, mailbox->buf); |
985 | ||
986 | size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); | |
987 | ||
988 | list_for_each_entry(cur, &rule->list, list) { | |
989 | ret = parse_trans_rule(dev, cur, mailbox->buf + size); | |
990 | if (ret < 0) { | |
991 | mlx4_free_cmd_mailbox(dev, mailbox); | |
75720384 | 992 | return ret; |
0ff1fb65 HHZ |
993 | } |
994 | size += ret; | |
995 | } | |
996 | ||
997 | ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id); | |
998 | if (ret == -ENOMEM) | |
999 | mlx4_err_rule(dev, | |
1a91de28 | 1000 | "mcg table is full. Fail to register network rule\n", |
0ff1fb65 HHZ |
1001 | rule); |
1002 | else if (ret) | |
1a91de28 | 1003 | mlx4_err_rule(dev, "Fail to register network rule\n", rule); |
0ff1fb65 HHZ |
1004 | |
1005 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1006 | ||
1007 | return ret; | |
1008 | } | |
1009 | EXPORT_SYMBOL_GPL(mlx4_flow_attach); | |
1010 | ||
1011 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id) | |
1012 | { | |
1013 | int err; | |
1014 | ||
1015 | err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id); | |
1016 | if (err) | |
1017 | mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n", | |
1018 | reg_id); | |
1019 | return err; | |
1020 | } | |
1021 | EXPORT_SYMBOL_GPL(mlx4_flow_detach); | |
1022 | ||
b95089d0 OG |
1023 | int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, |
1024 | int port, int qpn, u16 prio, u64 *reg_id) | |
1025 | { | |
1026 | int err; | |
1027 | struct mlx4_spec_list spec_eth_outer = { {NULL} }; | |
1028 | struct mlx4_spec_list spec_vxlan = { {NULL} }; | |
1029 | struct mlx4_spec_list spec_eth_inner = { {NULL} }; | |
1030 | ||
1031 | struct mlx4_net_trans_rule rule = { | |
1032 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
1033 | .exclusive = 0, | |
1034 | .allow_loopback = 1, | |
1035 | .promisc_mode = MLX4_FS_REGULAR, | |
1036 | }; | |
1037 | ||
1038 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); | |
1039 | ||
1040 | rule.port = port; | |
1041 | rule.qpn = qpn; | |
1042 | rule.priority = prio; | |
1043 | INIT_LIST_HEAD(&rule.list); | |
1044 | ||
1045 | spec_eth_outer.id = MLX4_NET_TRANS_RULE_ID_ETH; | |
1046 | memcpy(spec_eth_outer.eth.dst_mac, addr, ETH_ALEN); | |
1047 | memcpy(spec_eth_outer.eth.dst_mac_msk, &mac_mask, ETH_ALEN); | |
1048 | ||
1049 | spec_vxlan.id = MLX4_NET_TRANS_RULE_ID_VXLAN; /* any vxlan header */ | |
1050 | spec_eth_inner.id = MLX4_NET_TRANS_RULE_ID_ETH; /* any inner eth header */ | |
1051 | ||
1052 | list_add_tail(&spec_eth_outer.list, &rule.list); | |
1053 | list_add_tail(&spec_vxlan.list, &rule.list); | |
1054 | list_add_tail(&spec_eth_inner.list, &rule.list); | |
1055 | ||
1056 | err = mlx4_flow_attach(dev, &rule, reg_id); | |
1057 | return err; | |
1058 | } | |
1059 | EXPORT_SYMBOL(mlx4_tunnel_steer_add); | |
1060 | ||
4de65803 MB |
1061 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, |
1062 | u32 max_range_qpn) | |
1063 | { | |
1064 | int err; | |
1065 | u64 in_param; | |
1066 | ||
1067 | in_param = ((u64) min_range_qpn) << 32; | |
1068 | in_param |= ((u64) max_range_qpn) & 0xFFFFFFFF; | |
1069 | ||
1070 | err = mlx4_cmd(dev, in_param, 0, 0, | |
1071 | MLX4_FLOW_STEERING_IB_UC_QP_RANGE, | |
1072 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1073 | ||
1074 | return err; | |
1075 | } | |
1076 | EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE); | |
1077 | ||
0345584e YP |
1078 | int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
1079 | int block_mcast_loopback, enum mlx4_protocol prot, | |
1080 | enum mlx4_steer_type steer) | |
225c7b1f RD |
1081 | { |
1082 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1083 | struct mlx4_cmd_mailbox *mailbox; | |
1084 | struct mlx4_mgm *mgm; | |
1085 | u32 members_count; | |
225c7b1f RD |
1086 | int index, prev; |
1087 | int link = 0; | |
1088 | int i; | |
1089 | int err; | |
0345584e | 1090 | u8 port = gid[5]; |
b12d93d6 | 1091 | u8 new_entry = 0; |
225c7b1f RD |
1092 | |
1093 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1094 | if (IS_ERR(mailbox)) | |
1095 | return PTR_ERR(mailbox); | |
1096 | mgm = mailbox->buf; | |
1097 | ||
1098 | mutex_lock(&priv->mcg_table.mutex); | |
deb8b3e8 EE |
1099 | err = find_entry(dev, port, gid, prot, |
1100 | mailbox, &prev, &index); | |
225c7b1f RD |
1101 | if (err) |
1102 | goto out; | |
1103 | ||
1104 | if (index != -1) { | |
b12d93d6 YP |
1105 | if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) { |
1106 | new_entry = 1; | |
225c7b1f | 1107 | memcpy(mgm->gid, gid, 16); |
b12d93d6 | 1108 | } |
225c7b1f RD |
1109 | } else { |
1110 | link = 1; | |
1111 | ||
1112 | index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap); | |
1113 | if (index == -1) { | |
1114 | mlx4_err(dev, "No AMGM entries left\n"); | |
1115 | err = -ENOMEM; | |
1116 | goto out; | |
1117 | } | |
1118 | index += dev->caps.num_mgms; | |
1119 | ||
0ec2c0f8 | 1120 | new_entry = 1; |
225c7b1f RD |
1121 | memset(mgm, 0, sizeof *mgm); |
1122 | memcpy(mgm->gid, gid, 16); | |
1123 | } | |
1124 | ||
da995a8a | 1125 | members_count = be32_to_cpu(mgm->members_count) & 0xffffff; |
0ec2c0f8 | 1126 | if (members_count == dev->caps.num_qp_per_mgm) { |
1a91de28 | 1127 | mlx4_err(dev, "MGM at index %x is full\n", index); |
225c7b1f RD |
1128 | err = -ENOMEM; |
1129 | goto out; | |
1130 | } | |
1131 | ||
1132 | for (i = 0; i < members_count; ++i) | |
521e575b | 1133 | if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) { |
225c7b1f RD |
1134 | mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn); |
1135 | err = 0; | |
1136 | goto out; | |
1137 | } | |
1138 | ||
521e575b RL |
1139 | if (block_mcast_loopback) |
1140 | mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) | | |
e6a17622 | 1141 | (1U << MGM_BLCK_LB_BIT)); |
521e575b RL |
1142 | else |
1143 | mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK); | |
1144 | ||
0345584e | 1145 | mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30); |
225c7b1f | 1146 | |
0345584e | 1147 | err = mlx4_WRITE_ENTRY(dev, index, mailbox); |
225c7b1f RD |
1148 | if (err) |
1149 | goto out; | |
1150 | ||
1151 | if (!link) | |
1152 | goto out; | |
1153 | ||
0345584e | 1154 | err = mlx4_READ_ENTRY(dev, prev, mailbox); |
225c7b1f RD |
1155 | if (err) |
1156 | goto out; | |
1157 | ||
1158 | mgm->next_gid_index = cpu_to_be32(index << 6); | |
1159 | ||
0345584e | 1160 | err = mlx4_WRITE_ENTRY(dev, prev, mailbox); |
225c7b1f RD |
1161 | if (err) |
1162 | goto out; | |
1163 | ||
1164 | out: | |
b12d93d6 YP |
1165 | if (prot == MLX4_PROT_ETH) { |
1166 | /* manage the steering entry for promisc mode */ | |
1167 | if (new_entry) | |
0ec2c0f8 | 1168 | new_steering_entry(dev, port, steer, index, qp->qpn); |
b12d93d6 | 1169 | else |
0ec2c0f8 | 1170 | existing_steering_entry(dev, port, steer, |
b12d93d6 YP |
1171 | index, qp->qpn); |
1172 | } | |
225c7b1f RD |
1173 | if (err && link && index != -1) { |
1174 | if (index < dev->caps.num_mgms) | |
1a91de28 | 1175 | mlx4_warn(dev, "Got AMGM index %d < %d\n", |
225c7b1f RD |
1176 | index, dev->caps.num_mgms); |
1177 | else | |
1178 | mlx4_bitmap_free(&priv->mcg_table.bitmap, | |
7c6d74d2 | 1179 | index - dev->caps.num_mgms, MLX4_USE_RR); |
225c7b1f RD |
1180 | } |
1181 | mutex_unlock(&priv->mcg_table.mutex); | |
1182 | ||
1183 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1184 | return err; | |
1185 | } | |
225c7b1f | 1186 | |
0345584e YP |
1187 | int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
1188 | enum mlx4_protocol prot, enum mlx4_steer_type steer) | |
225c7b1f RD |
1189 | { |
1190 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1191 | struct mlx4_cmd_mailbox *mailbox; | |
1192 | struct mlx4_mgm *mgm; | |
1193 | u32 members_count; | |
225c7b1f | 1194 | int prev, index; |
aab2bb0e | 1195 | int i, loc = -1; |
225c7b1f | 1196 | int err; |
0345584e | 1197 | u8 port = gid[5]; |
b12d93d6 | 1198 | bool removed_entry = false; |
225c7b1f RD |
1199 | |
1200 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1201 | if (IS_ERR(mailbox)) | |
1202 | return PTR_ERR(mailbox); | |
1203 | mgm = mailbox->buf; | |
1204 | ||
1205 | mutex_lock(&priv->mcg_table.mutex); | |
1206 | ||
deb8b3e8 EE |
1207 | err = find_entry(dev, port, gid, prot, |
1208 | mailbox, &prev, &index); | |
225c7b1f RD |
1209 | if (err) |
1210 | goto out; | |
1211 | ||
1212 | if (index == -1) { | |
5b095d98 | 1213 | mlx4_err(dev, "MGID %pI6 not found\n", gid); |
225c7b1f RD |
1214 | err = -EINVAL; |
1215 | goto out; | |
1216 | } | |
1217 | ||
1645a540 SM |
1218 | /* If this QP is also a promisc QP, it shouldn't be removed only if |
1219 | * at least one none promisc QP is also attached to this MCG | |
1220 | */ | |
b12d93d6 | 1221 | if (prot == MLX4_PROT_ETH && |
1645a540 SM |
1222 | check_duplicate_entry(dev, port, steer, index, qp->qpn) && |
1223 | !promisc_steering_entry(dev, port, steer, index, qp->qpn, NULL)) | |
1224 | goto out; | |
b12d93d6 | 1225 | |
da995a8a | 1226 | members_count = be32_to_cpu(mgm->members_count) & 0xffffff; |
aab2bb0e DB |
1227 | for (i = 0; i < members_count; ++i) |
1228 | if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) { | |
225c7b1f | 1229 | loc = i; |
aab2bb0e DB |
1230 | break; |
1231 | } | |
225c7b1f RD |
1232 | |
1233 | if (loc == -1) { | |
1234 | mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn); | |
1235 | err = -EINVAL; | |
1236 | goto out; | |
1237 | } | |
1238 | ||
aab2bb0e DB |
1239 | /* copy the last QP in this MGM over removed QP */ |
1240 | mgm->qp[loc] = mgm->qp[members_count - 1]; | |
1241 | mgm->qp[members_count - 1] = 0; | |
0345584e | 1242 | mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30); |
225c7b1f | 1243 | |
b12d93d6 | 1244 | if (prot == MLX4_PROT_ETH) |
0ec2c0f8 EE |
1245 | removed_entry = can_remove_steering_entry(dev, port, steer, |
1246 | index, qp->qpn); | |
aab2bb0e | 1247 | if (members_count && (prot != MLX4_PROT_ETH || !removed_entry)) { |
0345584e | 1248 | err = mlx4_WRITE_ENTRY(dev, index, mailbox); |
225c7b1f | 1249 | goto out; |
4dc51b32 | 1250 | } |
225c7b1f | 1251 | |
b12d93d6 YP |
1252 | /* We are going to delete the entry, members count should be 0 */ |
1253 | mgm->members_count = cpu_to_be32((u32) prot << 30); | |
1254 | ||
225c7b1f RD |
1255 | if (prev == -1) { |
1256 | /* Remove entry from MGM */ | |
1257 | int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6; | |
1258 | if (amgm_index) { | |
0345584e | 1259 | err = mlx4_READ_ENTRY(dev, amgm_index, mailbox); |
225c7b1f RD |
1260 | if (err) |
1261 | goto out; | |
1262 | } else | |
1263 | memset(mgm->gid, 0, 16); | |
1264 | ||
0345584e | 1265 | err = mlx4_WRITE_ENTRY(dev, index, mailbox); |
225c7b1f RD |
1266 | if (err) |
1267 | goto out; | |
1268 | ||
1269 | if (amgm_index) { | |
1270 | if (amgm_index < dev->caps.num_mgms) | |
1a91de28 | 1271 | mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d\n", |
225c7b1f RD |
1272 | index, amgm_index, dev->caps.num_mgms); |
1273 | else | |
1274 | mlx4_bitmap_free(&priv->mcg_table.bitmap, | |
7c6d74d2 | 1275 | amgm_index - dev->caps.num_mgms, MLX4_USE_RR); |
225c7b1f RD |
1276 | } |
1277 | } else { | |
1278 | /* Remove entry from AMGM */ | |
1279 | int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6; | |
0345584e | 1280 | err = mlx4_READ_ENTRY(dev, prev, mailbox); |
225c7b1f RD |
1281 | if (err) |
1282 | goto out; | |
1283 | ||
1284 | mgm->next_gid_index = cpu_to_be32(cur_next_index << 6); | |
1285 | ||
0345584e | 1286 | err = mlx4_WRITE_ENTRY(dev, prev, mailbox); |
225c7b1f RD |
1287 | if (err) |
1288 | goto out; | |
1289 | ||
1290 | if (index < dev->caps.num_mgms) | |
1a91de28 | 1291 | mlx4_warn(dev, "entry %d had next AMGM index %d < %d\n", |
225c7b1f RD |
1292 | prev, index, dev->caps.num_mgms); |
1293 | else | |
1294 | mlx4_bitmap_free(&priv->mcg_table.bitmap, | |
7c6d74d2 | 1295 | index - dev->caps.num_mgms, MLX4_USE_RR); |
225c7b1f RD |
1296 | } |
1297 | ||
1298 | out: | |
1299 | mutex_unlock(&priv->mcg_table.mutex); | |
1300 | ||
1301 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1302 | return err; | |
1303 | } | |
0345584e | 1304 | |
0ec2c0f8 EE |
1305 | static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp, |
1306 | u8 gid[16], u8 attach, u8 block_loopback, | |
1307 | enum mlx4_protocol prot) | |
1308 | { | |
1309 | struct mlx4_cmd_mailbox *mailbox; | |
1310 | int err = 0; | |
1311 | int qpn; | |
1312 | ||
1313 | if (!mlx4_is_mfunc(dev)) | |
1314 | return -EBADF; | |
1315 | ||
1316 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1317 | if (IS_ERR(mailbox)) | |
1318 | return PTR_ERR(mailbox); | |
1319 | ||
1320 | memcpy(mailbox->buf, gid, 16); | |
1321 | qpn = qp->qpn; | |
1322 | qpn |= (prot << 28); | |
1323 | if (attach && block_loopback) | |
1324 | qpn |= (1 << 31); | |
1325 | ||
1326 | err = mlx4_cmd(dev, mailbox->dma, qpn, attach, | |
1327 | MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A, | |
1328 | MLX4_CMD_WRAPPED); | |
1329 | ||
1330 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1331 | return err; | |
1332 | } | |
0345584e | 1333 | |
fd91c49f HHZ |
1334 | int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, |
1335 | u8 gid[16], u8 port, | |
1336 | int block_mcast_loopback, | |
1337 | enum mlx4_protocol prot, u64 *reg_id) | |
0345584e | 1338 | { |
0ff1fb65 HHZ |
1339 | struct mlx4_spec_list spec = { {NULL} }; |
1340 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); | |
1341 | ||
1342 | struct mlx4_net_trans_rule rule = { | |
1343 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
1344 | .exclusive = 0, | |
f9162539 | 1345 | .promisc_mode = MLX4_FS_REGULAR, |
0ff1fb65 HHZ |
1346 | .priority = MLX4_DOMAIN_NIC, |
1347 | }; | |
1348 | ||
248c62aa | 1349 | rule.allow_loopback = !block_mcast_loopback; |
0ff1fb65 HHZ |
1350 | rule.port = port; |
1351 | rule.qpn = qp->qpn; | |
1352 | INIT_LIST_HEAD(&rule.list); | |
1353 | ||
1354 | switch (prot) { | |
1355 | case MLX4_PROT_ETH: | |
1356 | spec.id = MLX4_NET_TRANS_RULE_ID_ETH; | |
1357 | memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN); | |
1358 | memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN); | |
1359 | break; | |
1360 | ||
1361 | case MLX4_PROT_IB_IPV6: | |
1362 | spec.id = MLX4_NET_TRANS_RULE_ID_IB; | |
1363 | memcpy(spec.ib.dst_gid, gid, 16); | |
1364 | memset(&spec.ib.dst_gid_msk, 0xff, 16); | |
1365 | break; | |
1366 | default: | |
1367 | return -EINVAL; | |
1368 | } | |
1369 | list_add_tail(&spec.list, &rule.list); | |
1370 | ||
1371 | return mlx4_flow_attach(dev, &rule, reg_id); | |
fd91c49f HHZ |
1372 | } |
1373 | ||
1374 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
1375 | u8 port, int block_mcast_loopback, | |
1376 | enum mlx4_protocol prot, u64 *reg_id) | |
1377 | { | |
1378 | switch (dev->caps.steering_mode) { | |
1379 | case MLX4_STEERING_MODE_A0: | |
1380 | if (prot == MLX4_PROT_ETH) | |
1381 | return 0; | |
1382 | ||
1383 | case MLX4_STEERING_MODE_B0: | |
1384 | if (prot == MLX4_PROT_ETH) | |
1385 | gid[7] |= (MLX4_MC_STEER << 1); | |
1386 | ||
1387 | if (mlx4_is_mfunc(dev)) | |
1388 | return mlx4_QP_ATTACH(dev, qp, gid, 1, | |
1389 | block_mcast_loopback, prot); | |
1390 | return mlx4_qp_attach_common(dev, qp, gid, | |
1391 | block_mcast_loopback, prot, | |
1392 | MLX4_MC_STEER); | |
0ff1fb65 | 1393 | |
fd91c49f HHZ |
1394 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
1395 | return mlx4_trans_to_dmfs_attach(dev, qp, gid, port, | |
1396 | block_mcast_loopback, | |
1397 | prot, reg_id); | |
c96d97f4 HHZ |
1398 | default: |
1399 | return -EINVAL; | |
1400 | } | |
0345584e YP |
1401 | } |
1402 | EXPORT_SYMBOL_GPL(mlx4_multicast_attach); | |
1403 | ||
1404 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
0ff1fb65 | 1405 | enum mlx4_protocol prot, u64 reg_id) |
0345584e | 1406 | { |
c96d97f4 HHZ |
1407 | switch (dev->caps.steering_mode) { |
1408 | case MLX4_STEERING_MODE_A0: | |
1409 | if (prot == MLX4_PROT_ETH) | |
1410 | return 0; | |
0345584e | 1411 | |
c96d97f4 HHZ |
1412 | case MLX4_STEERING_MODE_B0: |
1413 | if (prot == MLX4_PROT_ETH) | |
1414 | gid[7] |= (MLX4_MC_STEER << 1); | |
0ec2c0f8 | 1415 | |
c96d97f4 HHZ |
1416 | if (mlx4_is_mfunc(dev)) |
1417 | return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot); | |
1418 | ||
1419 | return mlx4_qp_detach_common(dev, qp, gid, prot, | |
1420 | MLX4_MC_STEER); | |
0345584e | 1421 | |
0ff1fb65 HHZ |
1422 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
1423 | return mlx4_flow_detach(dev, reg_id); | |
1424 | ||
c96d97f4 HHZ |
1425 | default: |
1426 | return -EINVAL; | |
1427 | } | |
0345584e | 1428 | } |
225c7b1f RD |
1429 | EXPORT_SYMBOL_GPL(mlx4_multicast_detach); |
1430 | ||
592e49dd HHZ |
1431 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, |
1432 | u32 qpn, enum mlx4_net_trans_promisc_mode mode) | |
1433 | { | |
1434 | struct mlx4_net_trans_rule rule; | |
1435 | u64 *regid_p; | |
1436 | ||
1437 | switch (mode) { | |
f9162539 | 1438 | case MLX4_FS_ALL_DEFAULT: |
592e49dd HHZ |
1439 | regid_p = &dev->regid_promisc_array[port]; |
1440 | break; | |
f9162539 | 1441 | case MLX4_FS_MC_DEFAULT: |
592e49dd HHZ |
1442 | regid_p = &dev->regid_allmulti_array[port]; |
1443 | break; | |
1444 | default: | |
1445 | return -1; | |
1446 | } | |
1447 | ||
1448 | if (*regid_p != 0) | |
1449 | return -1; | |
1450 | ||
1451 | rule.promisc_mode = mode; | |
1452 | rule.port = port; | |
1453 | rule.qpn = qpn; | |
1454 | INIT_LIST_HEAD(&rule.list); | |
1455 | mlx4_err(dev, "going promisc on %x\n", port); | |
1456 | ||
1457 | return mlx4_flow_attach(dev, &rule, regid_p); | |
1458 | } | |
1459 | EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add); | |
1460 | ||
1461 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, | |
1462 | enum mlx4_net_trans_promisc_mode mode) | |
1463 | { | |
1464 | int ret; | |
1465 | u64 *regid_p; | |
1466 | ||
1467 | switch (mode) { | |
f9162539 | 1468 | case MLX4_FS_ALL_DEFAULT: |
592e49dd HHZ |
1469 | regid_p = &dev->regid_promisc_array[port]; |
1470 | break; | |
f9162539 | 1471 | case MLX4_FS_MC_DEFAULT: |
592e49dd HHZ |
1472 | regid_p = &dev->regid_allmulti_array[port]; |
1473 | break; | |
1474 | default: | |
1475 | return -1; | |
1476 | } | |
1477 | ||
1478 | if (*regid_p == 0) | |
1479 | return -1; | |
1480 | ||
1481 | ret = mlx4_flow_detach(dev, *regid_p); | |
1482 | if (ret == 0) | |
1483 | *regid_p = 0; | |
1484 | ||
1485 | return ret; | |
1486 | } | |
1487 | EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove); | |
1488 | ||
ffe455ad | 1489 | int mlx4_unicast_attach(struct mlx4_dev *dev, |
0ec2c0f8 EE |
1490 | struct mlx4_qp *qp, u8 gid[16], |
1491 | int block_mcast_loopback, enum mlx4_protocol prot) | |
1492 | { | |
0ec2c0f8 EE |
1493 | if (prot == MLX4_PROT_ETH) |
1494 | gid[7] |= (MLX4_UC_STEER << 1); | |
1495 | ||
1496 | if (mlx4_is_mfunc(dev)) | |
1497 | return mlx4_QP_ATTACH(dev, qp, gid, 1, | |
1498 | block_mcast_loopback, prot); | |
1499 | ||
1500 | return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback, | |
1501 | prot, MLX4_UC_STEER); | |
1502 | } | |
1503 | EXPORT_SYMBOL_GPL(mlx4_unicast_attach); | |
1504 | ||
ffe455ad | 1505 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, |
0ec2c0f8 EE |
1506 | u8 gid[16], enum mlx4_protocol prot) |
1507 | { | |
0ec2c0f8 EE |
1508 | if (prot == MLX4_PROT_ETH) |
1509 | gid[7] |= (MLX4_UC_STEER << 1); | |
1510 | ||
1511 | if (mlx4_is_mfunc(dev)) | |
1512 | return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot); | |
1513 | ||
1514 | return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER); | |
1515 | } | |
1516 | EXPORT_SYMBOL_GPL(mlx4_unicast_detach); | |
1517 | ||
1518 | int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, | |
1519 | struct mlx4_vhcr *vhcr, | |
1520 | struct mlx4_cmd_mailbox *inbox, | |
1521 | struct mlx4_cmd_mailbox *outbox, | |
1522 | struct mlx4_cmd_info *cmd) | |
1523 | { | |
1524 | u32 qpn = (u32) vhcr->in_param & 0xffffffff; | |
449fc488 | 1525 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_param >> 62); |
0ec2c0f8 EE |
1526 | enum mlx4_steer_type steer = vhcr->in_modifier; |
1527 | ||
449fc488 MB |
1528 | if (port < 0) |
1529 | return -EINVAL; | |
1530 | ||
0ec2c0f8 EE |
1531 | /* Promiscuous unicast is not allowed in mfunc */ |
1532 | if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER) | |
1533 | return 0; | |
1534 | ||
1535 | if (vhcr->op_modifier) | |
1536 | return add_promisc_qp(dev, port, steer, qpn); | |
1537 | else | |
1538 | return remove_promisc_qp(dev, port, steer, qpn); | |
1539 | } | |
1540 | ||
1541 | static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn, | |
1542 | enum mlx4_steer_type steer, u8 add, u8 port) | |
1543 | { | |
1544 | return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add, | |
1545 | MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A, | |
1546 | MLX4_CMD_WRAPPED); | |
1547 | } | |
b12d93d6 YP |
1548 | |
1549 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port) | |
1550 | { | |
0ec2c0f8 EE |
1551 | if (mlx4_is_mfunc(dev)) |
1552 | return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port); | |
b12d93d6 | 1553 | |
0ec2c0f8 | 1554 | return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn); |
b12d93d6 YP |
1555 | } |
1556 | EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add); | |
1557 | ||
1558 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port) | |
1559 | { | |
0ec2c0f8 EE |
1560 | if (mlx4_is_mfunc(dev)) |
1561 | return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port); | |
b12d93d6 | 1562 | |
0ec2c0f8 | 1563 | return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn); |
b12d93d6 YP |
1564 | } |
1565 | EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove); | |
1566 | ||
1567 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port) | |
1568 | { | |
0ec2c0f8 EE |
1569 | if (mlx4_is_mfunc(dev)) |
1570 | return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port); | |
b12d93d6 | 1571 | |
0ec2c0f8 | 1572 | return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn); |
b12d93d6 YP |
1573 | } |
1574 | EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add); | |
1575 | ||
1576 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port) | |
1577 | { | |
0ec2c0f8 EE |
1578 | if (mlx4_is_mfunc(dev)) |
1579 | return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port); | |
1580 | ||
1581 | return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn); | |
b12d93d6 YP |
1582 | } |
1583 | EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove); | |
1584 | ||
3d73c288 | 1585 | int mlx4_init_mcg_table(struct mlx4_dev *dev) |
225c7b1f RD |
1586 | { |
1587 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1588 | int err; | |
1589 | ||
0ff1fb65 HHZ |
1590 | /* No need for mcg_table when fw managed the mcg table*/ |
1591 | if (dev->caps.steering_mode == | |
1592 | MLX4_STEERING_MODE_DEVICE_MANAGED) | |
1593 | return 0; | |
93fc9e1b YP |
1594 | err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms, |
1595 | dev->caps.num_amgms - 1, 0, 0); | |
225c7b1f RD |
1596 | if (err) |
1597 | return err; | |
1598 | ||
1599 | mutex_init(&priv->mcg_table.mutex); | |
1600 | ||
1601 | return 0; | |
1602 | } | |
1603 | ||
1604 | void mlx4_cleanup_mcg_table(struct mlx4_dev *dev) | |
1605 | { | |
0ff1fb65 HHZ |
1606 | if (dev->caps.steering_mode != |
1607 | MLX4_STEERING_MODE_DEVICE_MANAGED) | |
1608 | mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap); | |
225c7b1f | 1609 | } |