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mlx4_core: Allow guests to have IB ports
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
ee49bd93 42#include <linux/timer.h>
3142788b 43#include <linux/semaphore.h>
27bf91d6 44#include <linux/workqueue.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
37608eea 47#include <linux/mlx4/driver.h>
225c7b1f 48#include <linux/mlx4/doorbell.h>
623ed84b 49#include <linux/mlx4/cmd.h>
225c7b1f
RD		 50
51#define DRV_NAME "mlx4_core"
ab9c17a0 52#define PFX DRV_NAME ": "
7d4b6bcc
YP		 53#define DRV_VERSION "1.1"
54#define DRV_RELDATE "Dec, 2011"
225c7b1f 55
e5395e92
AV		 56#define MLX4_NUM_UP 8
57#define MLX4_NUM_TC 8
58#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
59#define MLX4_RATELIMIT_DEFAULT 0xffff
60
61struct mlx4_set_port_prio2tc_context {
62 u8 prio2tc[4];
63};
64
65struct mlx4_port_scheduler_tc_cfg_be {
66 __be16 pg;
67 __be16 bw_precentage;
68 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
69 __be16 max_bw_value;
70};
71
72struct mlx4_set_port_scheduler_context {
73 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
74};
75
225c7b1f
RD		 76enum {
77 MLX4_HCR_BASE = 0x80680,
78 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 79 MLX4_CLR_INT_SIZE = 0x00008,
80 MLX4_SLAVE_COMM_BASE = 0x0,
81 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 82};
83
225c7b1f 84enum {
0ec2c0f8
EE		 85 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
86 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
87 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 88};
89
225c7b1f
RD		 90enum {
91 MLX4_NUM_PDS = 1 << 15
92};
93
94enum {
95 MLX4_CMPT_TYPE_QP = 0,
96 MLX4_CMPT_TYPE_SRQ = 1,
97 MLX4_CMPT_TYPE_CQ = 2,
98 MLX4_CMPT_TYPE_EQ = 3,
99 MLX4_CMPT_NUM_TYPE
100};
101
102enum {
103 MLX4_CMPT_SHIFT = 24,
104 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
105};
106
623ed84b
JM		 107enum mlx4_mr_state {
108 MLX4_MR_DISABLED = 0,
109 MLX4_MR_EN_HW,
110 MLX4_MR_EN_SW
111};
112
113#define MLX4_COMM_TIME 10000
114enum {
115 MLX4_COMM_CMD_RESET,
116 MLX4_COMM_CMD_VHCR0,
117 MLX4_COMM_CMD_VHCR1,
118 MLX4_COMM_CMD_VHCR2,
119 MLX4_COMM_CMD_VHCR_EN,
120 MLX4_COMM_CMD_VHCR_POST,
121 MLX4_COMM_CMD_FLR = 254
122};
123
124/*The flag indicates that the slave should delay the RESET cmd*/
125#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
126/*indicates how many retries will be done if we are in the middle of FLR*/
127#define NUM_OF_RESET_RETRIES 10
128#define SLEEP_TIME_IN_RESET (2 * 1000)
129enum mlx4_resource {
130 RES_QP,
131 RES_CQ,
132 RES_SRQ,
133 RES_XRCD,
134 RES_MPT,
135 RES_MTT,
136 RES_MAC,
137 RES_VLAN,
138 RES_EQ,
139 RES_COUNTER,
140 MLX4_NUM_OF_RESOURCE_TYPE
141};
142
143enum mlx4_alloc_mode {
144 RES_OP_RESERVE,
145 RES_OP_RESERVE_AND_MAP,
146 RES_OP_MAP_ICM,
147};
148
b8924951
JM		 149enum mlx4_res_tracker_free_type {
150 RES_TR_FREE_ALL,
151 RES_TR_FREE_SLAVES_ONLY,
152 RES_TR_FREE_STRUCTS_ONLY,
153};
623ed84b
JM		 154
155/*
156 *Virtual HCR structures.
157 * mlx4_vhcr is the sw representation, in machine endianess
158 *
159 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
160 * to FW to go through communication channel.
161 * It is big endian, and has the same structure as the physical HCR
162 * used by command interface
163 */
164struct mlx4_vhcr {
165 u64 in_param;
166 u64 out_param;
167 u32 in_modifier;
168 u32 errno;
169 u16 op;
170 u16 token;
171 u8 op_modifier;
172 u8 e_bit;
173};
174
175struct mlx4_vhcr_cmd {
176 __be64 in_param;
177 __be32 in_modifier;
178 __be64 out_param;
179 __be16 token;
180 u16 reserved;
181 u8 status;
182 u8 flags;
183 __be16 opcode;
184};
185
186struct mlx4_cmd_info {
187 u16 opcode;
188 bool has_inbox;
189 bool has_outbox;
190 bool out_is_imm;
191 bool encode_slave_id;
192 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
193 struct mlx4_cmd_mailbox *inbox);
194 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
195 struct mlx4_cmd_mailbox *inbox,
196 struct mlx4_cmd_mailbox *outbox,
197 struct mlx4_cmd_info *cmd);
198};
199
225c7b1f
RD		 200#ifdef CONFIG_MLX4_DEBUG
201extern int mlx4_debug_level;
7b0f5df4
RD		 202#else /* CONFIG_MLX4_DEBUG */
203#define mlx4_debug_level (0)
204#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 205
206#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 207do { \
208 if (mlx4_debug_level) \
209 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
210} while (0)
225c7b1f 211
225c7b1f 212#define mlx4_err(mdev, format, arg...) \
0a645e80 213 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 214#define mlx4_info(mdev, format, arg...) \
0a645e80 215 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 216#define mlx4_warn(mdev, format, arg...) \
0a645e80 217 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 218
0ec2c0f8 219extern int mlx4_log_num_mgm_entry_size;
2b8fb286 220extern int log_mtts_per_seg;
0ec2c0f8 221
623ed84b
JM		 222#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
223#define ALL_SLAVES 0xff
224
225c7b1f
RD		 225struct mlx4_bitmap {
226 u32 last;
227 u32 top;
228 u32 max;
93fc9e1b 229 u32 reserved_top;
225c7b1f 230 u32 mask;
42d1e017 231 u32 avail;
225c7b1f
RD		 232 spinlock_t lock;
233 unsigned long *table;
234};
235
236struct mlx4_buddy {
237 unsigned long **bits;
e4044cfc 238 unsigned int *num_free;
225c7b1f
RD		 239 int max_order;
240 spinlock_t lock;
241};
242
243struct mlx4_icm;
244
245struct mlx4_icm_table {
246 u64 virt;
247 int num_icm;
248 int num_obj;
249 int obj_size;
250 int lowmem;
5b0bf5e2 251 int coherent;
225c7b1f
RD		 252 struct mutex mutex;
253 struct mlx4_icm **icm;
254};
255
c82e9aa0
EC		 256/*
257 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
258 */
259struct mlx4_mpt_entry {
260 __be32 flags;
261 __be32 qpn;
262 __be32 key;
263 __be32 pd_flags;
264 __be64 start;
265 __be64 length;
266 __be32 lkey;
267 __be32 win_cnt;
268 u8 reserved1[3];
269 u8 mtt_rep;
2b8fb286 270 __be64 mtt_addr;
c82e9aa0
EC		 271 __be32 mtt_sz;
272 __be32 entity_size;
273 __be32 first_byte_offset;
274} __packed;
275
276/*
277 * Must be packed because start is 64 bits but only aligned to 32 bits.
278 */
279struct mlx4_eq_context {
280 __be32 flags;
281 u16 reserved1[3];
282 __be16 page_offset;
283 u8 log_eq_size;
284 u8 reserved2[4];
285 u8 eq_period;
286 u8 reserved3;
287 u8 eq_max_count;
288 u8 reserved4[3];
289 u8 intr;
290 u8 log_page_size;
291 u8 reserved5[2];
292 u8 mtt_base_addr_h;
293 __be32 mtt_base_addr_l;
294 u32 reserved6[2];
295 __be32 consumer_index;
296 __be32 producer_index;
297 u32 reserved7[4];
298};
299
300struct mlx4_cq_context {
301 __be32 flags;
302 u16 reserved1[3];
303 __be16 page_offset;
304 __be32 logsize_usrpage;
305 __be16 cq_period;
306 __be16 cq_max_count;
307 u8 reserved2[3];
308 u8 comp_eqn;
309 u8 log_page_size;
310 u8 reserved3[2];
311 u8 mtt_base_addr_h;
312 __be32 mtt_base_addr_l;
313 __be32 last_notified_index;
314 __be32 solicit_producer_index;
315 __be32 consumer_index;
316 __be32 producer_index;
317 u32 reserved4[2];
318 __be64 db_rec_addr;
319};
320
321struct mlx4_srq_context {
322 __be32 state_logsize_srqn;
323 u8 logstride;
324 u8 reserved1;
325 __be16 xrcd;
326 __be32 pg_offset_cqn;
327 u32 reserved2;
328 u8 log_page_size;
329 u8 reserved3[2];
330 u8 mtt_base_addr_h;
331 __be32 mtt_base_addr_l;
332 __be32 pd;
333 __be16 limit_watermark;
334 __be16 wqe_cnt;
335 u16 reserved4;
336 __be16 wqe_counter;
337 u32 reserved5;
338 __be64 db_rec_addr;
339};
340
225c7b1f
RD		 341struct mlx4_eq {
342 struct mlx4_dev *dev;
343 void __iomem *doorbell;
344 int eqn;
345 u32 cons_index;
346 u16 irq;
347 u16 have_irq;
348 int nent;
349 struct mlx4_buf_list *page_list;
350 struct mlx4_mtt mtt;
351};
352
623ed84b
JM		 353struct mlx4_slave_eqe {
354 u8 type;
355 u8 port;
356 u32 param;
357};
358
359struct mlx4_slave_event_eq_info {
803143fb 360 int eqn;
623ed84b 361 u16 token;
623ed84b
JM		 362};
363
225c7b1f
RD		 364struct mlx4_profile {
365 int num_qp;
366 int rdmarc_per_qp;
367 int num_srq;
368 int num_cq;
369 int num_mcg;
370 int num_mpt;
db5a7a65 371 unsigned num_mtt;
225c7b1f
RD		 372};
373
374struct mlx4_fw {
375 u64 clr_int_base;
376 u64 catas_offset;
623ed84b 377 u64 comm_base;
225c7b1f
RD		 378 struct mlx4_icm *fw_icm;
379 struct mlx4_icm *aux_icm;
380 u32 catas_size;
381 u16 fw_pages;
382 u8 clr_int_bar;
383 u8 catas_bar;
623ed84b
JM		 384 u8 comm_bar;
385};
386
387struct mlx4_comm {
388 u32 slave_write;
389 u32 slave_read;
225c7b1f
RD		 390};
391
ffe455ad
EE		 392enum {
393 MLX4_MCAST_CONFIG = 0,
394 MLX4_MCAST_DISABLE = 1,
395 MLX4_MCAST_ENABLE = 2,
396};
397
623ed84b
JM		 398#define VLAN_FLTR_SIZE 128
399
400struct mlx4_vlan_fltr {
401 __be32 entry[VLAN_FLTR_SIZE];
402};
403
ffe455ad
EE		 404struct mlx4_mcast_entry {
405 struct list_head list;
406 u64 addr;
407};
408
b12d93d6
YP		 409struct mlx4_promisc_qp {
410 struct list_head list;
411 u32 qpn;
412};
413
414struct mlx4_steer_index {
415 struct list_head list;
416 unsigned int index;
417 struct list_head duplicates;
418};
419
803143fb
MA		 420#define MLX4_EVENT_TYPES_NUM 64
421
623ed84b
JM		 422struct mlx4_slave_state {
423 u8 comm_toggle;
424 u8 last_cmd;
425 u8 init_port_mask;
426 bool active;
427 u8 function;
428 dma_addr_t vhcr_dma;
429 u16 mtu[MLX4_MAX_PORTS + 1];
430 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
431 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
432 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
433 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
803143fb
MA		 434 /* event type to eq number lookup */
435 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
623ed84b
JM		 436 u16 eq_pi;
437 u16 eq_ci;
438 spinlock_t lock;
439 /*initialized via the kzalloc*/
440 u8 is_slave_going_down;
441 u32 cookie;
442};
443
444struct slave_list {
445 struct mutex mutex;
446 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
447};
448
449struct mlx4_resource_tracker {
450 spinlock_t lock;
451 /* tree for each resources */
452 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
453 /* num_of_slave's lists, one per slave */
454 struct slave_list *slave_list;
455};
456
457#define SLAVE_EVENT_EQ_SIZE 128
458struct mlx4_slave_event_eq {
459 u32 eqn;
460 u32 cons;
461 u32 prod;
462 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
463};
464
465struct mlx4_master_qp0_state {
466 int proxy_qp0_active;
467 int qp0_active;
468 int port_active;
469};
470
471struct mlx4_mfunc_master_ctx {
472 struct mlx4_slave_state *slave_state;
473 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
474 int init_port_ref[MLX4_MAX_PORTS + 1];
475 u16 max_mtu[MLX4_MAX_PORTS + 1];
476 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
477 struct mlx4_resource_tracker res_tracker;
478 struct workqueue_struct *comm_wq;
479 struct work_struct comm_work;
480 struct work_struct slave_event_work;
481 struct work_struct slave_flr_event_work;
482 spinlock_t slave_state_lock;
f5311ac1 483 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 484 struct mlx4_eqe cmd_eqe;
485 struct mlx4_slave_event_eq slave_eq;
486 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
487};
488
489struct mlx4_mfunc {
490 struct mlx4_comm __iomem *comm;
491 struct mlx4_vhcr_cmd *vhcr;
492 dma_addr_t vhcr_dma;
493
494 struct mlx4_mfunc_master_ctx master;
495};
496
225c7b1f
RD		 497struct mlx4_cmd {
498 struct pci_pool *pool;
499 void __iomem *hcr;
500 struct mutex hcr_mutex;
501 struct semaphore poll_sem;
502 struct semaphore event_sem;
623ed84b 503 struct semaphore slave_sem;
225c7b1f
RD		 504 int max_cmds;
505 spinlock_t context_lock;
506 int free_head;
507 struct mlx4_cmd_context *context;
508 u16 token_mask;
509 u8 use_events;
510 u8 toggle;
623ed84b 511 u8 comm_toggle;
225c7b1f
RD		 512};
513
514struct mlx4_uar_table {
515 struct mlx4_bitmap bitmap;
516};
517
518struct mlx4_mr_table {
519 struct mlx4_bitmap mpt_bitmap;
520 struct mlx4_buddy mtt_buddy;
521 u64 mtt_base;
522 u64 mpt_base;
523 struct mlx4_icm_table mtt_table;
524 struct mlx4_icm_table dmpt_table;
525};
526
527struct mlx4_cq_table {
528 struct mlx4_bitmap bitmap;
529 spinlock_t lock;
530 struct radix_tree_root tree;
531 struct mlx4_icm_table table;
532 struct mlx4_icm_table cmpt_table;
533};
534
535struct mlx4_eq_table {
536 struct mlx4_bitmap bitmap;
b8dd786f 537 char *irq_names;
225c7b1f 538 void __iomem *clr_int;
b8dd786f 539 void __iomem **uar_map;
225c7b1f 540 u32 clr_mask;
b8dd786f 541 struct mlx4_eq *eq;
fa0681d2 542 struct mlx4_icm_table table;
225c7b1f
RD		 543 struct mlx4_icm_table cmpt_table;
544 int have_irq;
545 u8 inta_pin;
546};
547
548struct mlx4_srq_table {
549 struct mlx4_bitmap bitmap;
550 spinlock_t lock;
551 struct radix_tree_root tree;
552 struct mlx4_icm_table table;
553 struct mlx4_icm_table cmpt_table;
554};
555
556struct mlx4_qp_table {
557 struct mlx4_bitmap bitmap;
558 u32 rdmarc_base;
559 int rdmarc_shift;
560 spinlock_t lock;
561 struct mlx4_icm_table qp_table;
562 struct mlx4_icm_table auxc_table;
563 struct mlx4_icm_table altc_table;
564 struct mlx4_icm_table rdmarc_table;
565 struct mlx4_icm_table cmpt_table;
566};
567
568struct mlx4_mcg_table {
569 struct mutex mutex;
570 struct mlx4_bitmap bitmap;
571 struct mlx4_icm_table table;
572};
573
574struct mlx4_catas_err {
575 u32 __iomem *map;
ee49bd93
JM		 576 struct timer_list timer;
577 struct list_head list;
225c7b1f
RD		 578};
579
2a2336f8
YP		 580#define MLX4_MAX_MAC_NUM 128
581#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
582
583struct mlx4_mac_table {
584 __be64 entries[MLX4_MAX_MAC_NUM];
585 int refs[MLX4_MAX_MAC_NUM];
586 struct mutex mutex;
587 int total;
588 int max;
589};
590
591#define MLX4_MAX_VLAN_NUM 128
592#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
593
594struct mlx4_vlan_table {
595 __be32 entries[MLX4_MAX_VLAN_NUM];
596 int refs[MLX4_MAX_VLAN_NUM];
597 struct mutex mutex;
598 int total;
599 int max;
600};
601
ffe455ad
EE		 602#define SET_PORT_GEN_ALL_VALID 0x7
603#define SET_PORT_PROMISC_SHIFT 31
604#define SET_PORT_MC_PROMISC_SHIFT 30
605
606enum {
607 MCAST_DIRECT_ONLY = 0,
608 MCAST_DIRECT = 1,
609 MCAST_DEFAULT = 2
610};
611
612
613struct mlx4_set_port_general_context {
614 u8 reserved[3];
615 u8 flags;
616 u16 reserved2;
617 __be16 mtu;
618 u8 pptx;
619 u8 pfctx;
620 u16 reserved3;
621 u8 pprx;
622 u8 pfcrx;
623 u16 reserved4;
624};
625
626struct mlx4_set_port_rqp_calc_context {
627 __be32 base_qpn;
628 u8 rererved;
629 u8 n_mac;
630 u8 n_vlan;
631 u8 n_prio;
632 u8 reserved2[3];
633 u8 mac_miss;
634 u8 intra_no_vlan;
635 u8 no_vlan;
636 u8 intra_vlan_miss;
637 u8 vlan_miss;
638 u8 reserved3[3];
639 u8 no_vlan_prio;
640 __be32 promisc;
641 __be32 mcast;
642};
643
1679200f
YP		 644struct mlx4_mac_entry {
645 u64 mac;
646};
647
2a2336f8
YP		 648struct mlx4_port_info {
649 struct mlx4_dev *dev;
650 int port;
7ff93f8b
YP		 651 char dev_name[16];
652 struct device_attribute port_attr;
653 enum mlx4_port_type tmp_type;
096335b3
OG		 654 char dev_mtu_name[16];
655 struct device_attribute port_mtu_attr;
2a2336f8 656 struct mlx4_mac_table mac_table;
1679200f 657 struct radix_tree_root mac_tree;
2a2336f8 658 struct mlx4_vlan_table vlan_table;
1679200f 659 int base_qpn;
2a2336f8
YP		 660};
661
27bf91d6
YP		 662struct mlx4_sense {
663 struct mlx4_dev *dev;
664 u8 do_sense_port[MLX4_MAX_PORTS + 1];
665 u8 sense_allowed[MLX4_MAX_PORTS + 1];
666 struct delayed_work sense_poll;
667};
668
0b7ca5a9
YP		 669struct mlx4_msix_ctl {
670 u64 pool_bm;
730c41d5 671 struct mutex pool_lock;
0b7ca5a9
YP		 672};
673
b12d93d6
YP		 674struct mlx4_steer {
675 struct list_head promisc_qps[MLX4_NUM_STEERS];
676 struct list_head steer_entries[MLX4_NUM_STEERS];
b12d93d6
YP		 677};
678
225c7b1f
RD		 679struct mlx4_priv {
680 struct mlx4_dev dev;
681
682 struct list_head dev_list;
683 struct list_head ctx_list;
684 spinlock_t ctx_lock;
685
6296883c
YP		 686 struct list_head pgdir_list;
687 struct mutex pgdir_mutex;
688
225c7b1f
RD		 689 struct mlx4_fw fw;
690 struct mlx4_cmd cmd;
623ed84b 691 struct mlx4_mfunc mfunc;
225c7b1f
RD		 692
693 struct mlx4_bitmap pd_bitmap;
012a8ff5 694 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 695 struct mlx4_uar_table uar_table;
696 struct mlx4_mr_table mr_table;
697 struct mlx4_cq_table cq_table;
698 struct mlx4_eq_table eq_table;
699 struct mlx4_srq_table srq_table;
700 struct mlx4_qp_table qp_table;
701 struct mlx4_mcg_table mcg_table;
f2a3f6a3 702 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 703
704 struct mlx4_catas_err catas_err;
705
706 void __iomem *clr_base;
707
708 struct mlx4_uar driver_uar;
709 void __iomem *kar;
2a2336f8 710 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 711 struct mlx4_sense sense;
7ff93f8b 712 struct mutex port_mutex;
0b7ca5a9 713 struct mlx4_msix_ctl msix_ctl;
b12d93d6 714 struct mlx4_steer *steer;
c1b43dca
EC		 715 struct list_head bf_list;
716 struct mutex bf_mutex;
717 struct io_mapping *bf_mapping;
ea51b377 718 int reserved_mtts;
225c7b1f
RD		 719};
720
721static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
722{
723 return container_of(dev, struct mlx4_priv, dev);
724}
725
27bf91d6
YP		 726#define MLX4_SENSE_RANGE (HZ * 3)
727
728extern struct workqueue_struct *mlx4_wq;
729
225c7b1f
RD		 730u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
731void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 732u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
733void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 734u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 735int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
736 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 737void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
738
739int mlx4_reset(struct mlx4_dev *dev);
740
b8dd786f
YP		 741int mlx4_alloc_eq_table(struct mlx4_dev *dev);
742void mlx4_free_eq_table(struct mlx4_dev *dev);
743
225c7b1f 744int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 745int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 746int mlx4_init_uar_table(struct mlx4_dev *dev);
747int mlx4_init_mr_table(struct mlx4_dev *dev);
748int mlx4_init_eq_table(struct mlx4_dev *dev);
749int mlx4_init_cq_table(struct mlx4_dev *dev);
750int mlx4_init_qp_table(struct mlx4_dev *dev);
751int mlx4_init_srq_table(struct mlx4_dev *dev);
752int mlx4_init_mcg_table(struct mlx4_dev *dev);
753
754void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 755void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 756void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
757void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
758void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
759void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
760void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
761void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
762void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 763int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
764void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
765int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
766void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
767int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
768void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
769int __mlx4_mr_reserve(struct mlx4_dev *dev);
770void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
771int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
772void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
773u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
774void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 775
623ed84b
JM		 776int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
777 struct mlx4_vhcr *vhcr,
778 struct mlx4_cmd_mailbox *inbox,
779 struct mlx4_cmd_mailbox *outbox,
780 struct mlx4_cmd_info *cmd);
781int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
782 struct mlx4_vhcr *vhcr,
783 struct mlx4_cmd_mailbox *inbox,
784 struct mlx4_cmd_mailbox *outbox,
785 struct mlx4_cmd_info *cmd);
786int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
787 struct mlx4_vhcr *vhcr,
788 struct mlx4_cmd_mailbox *inbox,
789 struct mlx4_cmd_mailbox *outbox,
790 struct mlx4_cmd_info *cmd);
791int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
792 struct mlx4_vhcr *vhcr,
793 struct mlx4_cmd_mailbox *inbox,
794 struct mlx4_cmd_mailbox *outbox,
795 struct mlx4_cmd_info *cmd);
796int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
797 struct mlx4_vhcr *vhcr,
798 struct mlx4_cmd_mailbox *inbox,
799 struct mlx4_cmd_mailbox *outbox,
800 struct mlx4_cmd_info *cmd);
801int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
802 struct mlx4_vhcr *vhcr,
803 struct mlx4_cmd_mailbox *inbox,
804 struct mlx4_cmd_mailbox *outbox,
805 struct mlx4_cmd_info *cmd);
806int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
807 struct mlx4_vhcr *vhcr,
808 struct mlx4_cmd_mailbox *inbox,
809 struct mlx4_cmd_mailbox *outbox,
810 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 811int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
812 int *base);
813void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
814int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
815void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
816int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
817int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
818 int start_index, int npages, u64 *page_list);
ba062d52
JM		 819int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
820void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
821int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
822void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
623ed84b 823
ee49bd93
JM		 824void mlx4_start_catas_poll(struct mlx4_dev *dev);
825void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 826void mlx4_catas_init(void);
ee49bd93 827int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 828int mlx4_register_device(struct mlx4_dev *dev);
829void mlx4_unregister_device(struct mlx4_dev *dev);
00f5ce99
JM		 830void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
831 unsigned long param);
225c7b1f
RD		 832
833struct mlx4_dev_cap;
834struct mlx4_init_hca_param;
835
836u64 mlx4_make_profile(struct mlx4_dev *dev,
837 struct mlx4_profile *request,
838 struct mlx4_dev_cap *dev_cap,
839 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 840void mlx4_master_comm_channel(struct work_struct *work);
841void mlx4_gen_slave_eqe(struct work_struct *work);
842void mlx4_master_handle_slave_flr(struct work_struct *work);
843
844int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
845 struct mlx4_vhcr *vhcr,
846 struct mlx4_cmd_mailbox *inbox,
847 struct mlx4_cmd_mailbox *outbox,
848 struct mlx4_cmd_info *cmd);
849int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
850 struct mlx4_vhcr *vhcr,
851 struct mlx4_cmd_mailbox *inbox,
852 struct mlx4_cmd_mailbox *outbox,
853 struct mlx4_cmd_info *cmd);
854int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
855 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
856 struct mlx4_cmd_mailbox *outbox,
857 struct mlx4_cmd_info *cmd);
858int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
859 struct mlx4_vhcr *vhcr,
860 struct mlx4_cmd_mailbox *inbox,
861 struct mlx4_cmd_mailbox *outbox,
862 struct mlx4_cmd_info *cmd);
863int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
864 struct mlx4_vhcr *vhcr,
865 struct mlx4_cmd_mailbox *inbox,
866 struct mlx4_cmd_mailbox *outbox,
867 struct mlx4_cmd_info *cmd);
868int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
869 struct mlx4_vhcr *vhcr,
870 struct mlx4_cmd_mailbox *inbox,
871 struct mlx4_cmd_mailbox *outbox,
872 struct mlx4_cmd_info *cmd);
873int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
874 struct mlx4_vhcr *vhcr,
875 struct mlx4_cmd_mailbox *inbox,
876 struct mlx4_cmd_mailbox *outbox,
877 struct mlx4_cmd_info *cmd);
878int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
879 struct mlx4_vhcr *vhcr,
880 struct mlx4_cmd_mailbox *inbox,
881 struct mlx4_cmd_mailbox *outbox,
882 struct mlx4_cmd_info *cmd);
883int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
884 struct mlx4_vhcr *vhcr,
885 struct mlx4_cmd_mailbox *inbox,
886 struct mlx4_cmd_mailbox *outbox,
887 struct mlx4_cmd_info *cmd);
888int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
889 struct mlx4_vhcr *vhcr,
890 struct mlx4_cmd_mailbox *inbox,
891 struct mlx4_cmd_mailbox *outbox,
892 struct mlx4_cmd_info *cmd);
893int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
894 struct mlx4_vhcr *vhcr,
895 struct mlx4_cmd_mailbox *inbox,
896 struct mlx4_cmd_mailbox *outbox,
897 struct mlx4_cmd_info *cmd);
898int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
899 struct mlx4_vhcr *vhcr,
900 struct mlx4_cmd_mailbox *inbox,
901 struct mlx4_cmd_mailbox *outbox,
902 struct mlx4_cmd_info *cmd);
903int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
904 struct mlx4_vhcr *vhcr,
905 struct mlx4_cmd_mailbox *inbox,
906 struct mlx4_cmd_mailbox *outbox,
907 struct mlx4_cmd_info *cmd);
908int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
909 struct mlx4_vhcr *vhcr,
910 struct mlx4_cmd_mailbox *inbox,
911 struct mlx4_cmd_mailbox *outbox,
912 struct mlx4_cmd_info *cmd);
913int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
914 struct mlx4_vhcr *vhcr,
915 struct mlx4_cmd_mailbox *inbox,
916 struct mlx4_cmd_mailbox *outbox,
917 struct mlx4_cmd_info *cmd);
918int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
919 struct mlx4_vhcr *vhcr,
920 struct mlx4_cmd_mailbox *inbox,
921 struct mlx4_cmd_mailbox *outbox,
922 struct mlx4_cmd_info *cmd);
923int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
924 struct mlx4_vhcr *vhcr,
925 struct mlx4_cmd_mailbox *inbox,
926 struct mlx4_cmd_mailbox *outbox,
927 struct mlx4_cmd_info *cmd);
928int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
929 struct mlx4_vhcr *vhcr,
930 struct mlx4_cmd_mailbox *inbox,
931 struct mlx4_cmd_mailbox *outbox,
932 struct mlx4_cmd_info *cmd);
933
934int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 935
225c7b1f
RD		 936int mlx4_cmd_init(struct mlx4_dev *dev);
937void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 938int mlx4_multi_func_init(struct mlx4_dev *dev);
939void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 940void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
941int mlx4_cmd_use_events(struct mlx4_dev *dev);
942void mlx4_cmd_use_polling(struct mlx4_dev *dev);
943
ab9c17a0
JM		 944int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
945 unsigned long timeout);
946
225c7b1f
RD		 947void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
948void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
949
950void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
951
952void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
953
954void mlx4_handle_catas_err(struct mlx4_dev *dev);
955
ab6dc30d
YP		 956int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
957 enum mlx4_port_type *type);
27bf91d6
YP		 958void mlx4_do_sense_ports(struct mlx4_dev *dev,
959 enum mlx4_port_type *stype,
960 enum mlx4_port_type *defaults);
961void mlx4_start_sense(struct mlx4_dev *dev);
962void mlx4_stop_sense(struct mlx4_dev *dev);
963void mlx4_sense_init(struct mlx4_dev *dev);
964int mlx4_check_port_params(struct mlx4_dev *dev,
965 enum mlx4_port_type *port_type);
966int mlx4_change_port_types(struct mlx4_dev *dev,
967 enum mlx4_port_type *port_types);
968
2a2336f8
YP		 969void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
970void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
971
7ff93f8b 972int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
623ed84b
JM		 973/* resource tracker functions*/
974int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
975 enum mlx4_resource resource_type,
976 int resource_id, int *slave);
977void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
978int mlx4_init_resource_tracker(struct mlx4_dev *dev);
979
b8924951
JM		 980void mlx4_free_resource_tracker(struct mlx4_dev *dev,
981 enum mlx4_res_tracker_free_type type);
623ed84b 982
b91cb3eb
JM		 983int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
984 struct mlx4_vhcr *vhcr,
985 struct mlx4_cmd_mailbox *inbox,
986 struct mlx4_cmd_mailbox *outbox,
987 struct mlx4_cmd_info *cmd);
623ed84b
JM		 988int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
989 struct mlx4_vhcr *vhcr,
990 struct mlx4_cmd_mailbox *inbox,
991 struct mlx4_cmd_mailbox *outbox,
992 struct mlx4_cmd_info *cmd);
993int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
994 struct mlx4_vhcr *vhcr,
995 struct mlx4_cmd_mailbox *inbox,
996 struct mlx4_cmd_mailbox *outbox,
997 struct mlx4_cmd_info *cmd);
998int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
999 struct mlx4_vhcr *vhcr,
1000 struct mlx4_cmd_mailbox *inbox,
1001 struct mlx4_cmd_mailbox *outbox,
1002 struct mlx4_cmd_info *cmd);
b91cb3eb
JM		 1003int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1004 struct mlx4_vhcr *vhcr,
1005 struct mlx4_cmd_mailbox *inbox,
1006 struct mlx4_cmd_mailbox *outbox,
1007 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1008int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1009 struct mlx4_vhcr *vhcr,
1010 struct mlx4_cmd_mailbox *inbox,
1011 struct mlx4_cmd_mailbox *outbox,
1012 struct mlx4_cmd_info *cmd);
9a5aa622 1013int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
7ff93f8b 1014
623ed84b
JM		 1015
1016int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1017 struct mlx4_vhcr *vhcr,
1018 struct mlx4_cmd_mailbox *inbox,
1019 struct mlx4_cmd_mailbox *outbox,
1020 struct mlx4_cmd_info *cmd);
1021
1022int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1027int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1028 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1029int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1030 int block_mcast_loopback, enum mlx4_protocol prot,
1031 enum mlx4_steer_type steer);
623ed84b
JM		 1032int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd);
1037int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1038 struct mlx4_vhcr *vhcr,
1039 struct mlx4_cmd_mailbox *inbox,
1040 struct mlx4_cmd_mailbox *outbox,
1041 struct mlx4_cmd_info *cmd);
1042int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1043 int port, void *buf);
1044int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1045 struct mlx4_cmd_mailbox *outbox);
1046int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1047 struct mlx4_vhcr *vhcr,
1048 struct mlx4_cmd_mailbox *inbox,
1049 struct mlx4_cmd_mailbox *outbox,
1050 struct mlx4_cmd_info *cmd);
1051int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1052 struct mlx4_vhcr *vhcr,
1053 struct mlx4_cmd_mailbox *inbox,
1054 struct mlx4_cmd_mailbox *outbox,
1055 struct mlx4_cmd_info *cmd);
1056int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1057 struct mlx4_vhcr *vhcr,
1058 struct mlx4_cmd_mailbox *inbox,
1059 struct mlx4_cmd_mailbox *outbox,
1060 struct mlx4_cmd_info *cmd);
f5311ac1 1061
0ec2c0f8
EE		 1062int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1063int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1064
5cc914f1
MA		 1065static inline void set_param_l(u64 *arg, u32 val)
1066{
1067 *((u32 *)arg) = val;
1068}
1069
1070static inline void set_param_h(u64 *arg, u32 val)
1071{
1072 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1073}
1074
1075static inline u32 get_param_l(u64 *arg)
1076{
1077 return (u32) (*arg & 0xffffffff);
1078}
1079
1080static inline u32 get_param_h(u64 *arg)
1081{
1082 return (u32)(*arg >> 32);
1083}
1084
c82e9aa0
EC		 1085static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1086{
1087 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1088}
1089
f5311ac1
JM		 1090#define NOT_MASKED_PD_BITS 17
1091
225c7b1f 1092#endif /* MLX4_H */
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