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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. | |
51a379d0 | 5 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
6 | * Copyright (c) 2004 Voltaire, Inc. All rights reserved. |
7 | * | |
8 | * This software is available to you under a choice of one of two | |
9 | * licenses. You may choose to be licensed under the terms of the GNU | |
10 | * General Public License (GPL) Version 2, available from the file | |
11 | * COPYING in the main directory of this source tree, or the | |
12 | * OpenIB.org BSD license below: | |
13 | * | |
14 | * Redistribution and use in source and binary forms, with or | |
15 | * without modification, are permitted provided that the following | |
16 | * conditions are met: | |
17 | * | |
18 | * - Redistributions of source code must retain the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer. | |
21 | * | |
22 | * - Redistributions in binary form must reproduce the above | |
23 | * copyright notice, this list of conditions and the following | |
24 | * disclaimer in the documentation and/or other materials | |
25 | * provided with the distribution. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
28 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
29 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
30 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
31 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
32 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
33 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
34 | * SOFTWARE. | |
35 | */ | |
36 | ||
37 | #ifndef MLX4_H | |
38 | #define MLX4_H | |
39 | ||
525f5f44 | 40 | #include <linux/mutex.h> |
225c7b1f | 41 | #include <linux/radix-tree.h> |
4af1c048 | 42 | #include <linux/rbtree.h> |
ee49bd93 | 43 | #include <linux/timer.h> |
3142788b | 44 | #include <linux/semaphore.h> |
27bf91d6 | 45 | #include <linux/workqueue.h> |
225c7b1f RD |
46 | |
47 | #include <linux/mlx4/device.h> | |
37608eea | 48 | #include <linux/mlx4/driver.h> |
225c7b1f | 49 | #include <linux/mlx4/doorbell.h> |
623ed84b | 50 | #include <linux/mlx4/cmd.h> |
225c7b1f RD |
51 | |
52 | #define DRV_NAME "mlx4_core" | |
ab9c17a0 | 53 | #define PFX DRV_NAME ": " |
169a1d85 AV |
54 | #define DRV_VERSION "2.2-1" |
55 | #define DRV_RELDATE "Feb, 2014" | |
225c7b1f | 56 | |
0ff1fb65 HHZ |
57 | #define MLX4_FS_UDP_UC_EN (1 << 1) |
58 | #define MLX4_FS_TCP_UC_EN (1 << 2) | |
59 | #define MLX4_FS_NUM_OF_L2_ADDR 8 | |
60 | #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 | |
61 | #define MLX4_FS_NUM_MCG (1 << 17) | |
62 | ||
e448834e SM |
63 | #define INIT_HCA_TPT_MW_ENABLE (1 << 7) |
64 | ||
e5395e92 AV |
65 | struct mlx4_set_port_prio2tc_context { |
66 | u8 prio2tc[4]; | |
67 | }; | |
68 | ||
69 | struct mlx4_port_scheduler_tc_cfg_be { | |
70 | __be16 pg; | |
71 | __be16 bw_precentage; | |
72 | __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */ | |
73 | __be16 max_bw_value; | |
74 | }; | |
75 | ||
76 | struct mlx4_set_port_scheduler_context { | |
77 | struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC]; | |
78 | }; | |
79 | ||
225c7b1f RD |
80 | enum { |
81 | MLX4_HCR_BASE = 0x80680, | |
82 | MLX4_HCR_SIZE = 0x0001c, | |
623ed84b JM |
83 | MLX4_CLR_INT_SIZE = 0x00008, |
84 | MLX4_SLAVE_COMM_BASE = 0x0, | |
ddd8a6c1 EE |
85 | MLX4_COMM_PAGESIZE = 0x1000, |
86 | MLX4_CLOCK_SIZE = 0x00008 | |
225c7b1f RD |
87 | }; |
88 | ||
225c7b1f | 89 | enum { |
3c439b55 JM |
90 | MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, |
91 | MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, | |
92 | MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, | |
93 | MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), | |
0ec2c0f8 | 94 | MLX4_MTT_ENTRY_PER_SEG = 8, |
225c7b1f RD |
95 | }; |
96 | ||
225c7b1f RD |
97 | enum { |
98 | MLX4_NUM_PDS = 1 << 15 | |
99 | }; | |
100 | ||
101 | enum { | |
102 | MLX4_CMPT_TYPE_QP = 0, | |
103 | MLX4_CMPT_TYPE_SRQ = 1, | |
104 | MLX4_CMPT_TYPE_CQ = 2, | |
105 | MLX4_CMPT_TYPE_EQ = 3, | |
106 | MLX4_CMPT_NUM_TYPE | |
107 | }; | |
108 | ||
109 | enum { | |
110 | MLX4_CMPT_SHIFT = 24, | |
111 | MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT | |
112 | }; | |
113 | ||
b20e519a SM |
114 | enum mlx4_mpt_state { |
115 | MLX4_MPT_DISABLED = 0, | |
116 | MLX4_MPT_EN_HW, | |
117 | MLX4_MPT_EN_SW | |
623ed84b JM |
118 | }; |
119 | ||
120 | #define MLX4_COMM_TIME 10000 | |
121 | enum { | |
122 | MLX4_COMM_CMD_RESET, | |
123 | MLX4_COMM_CMD_VHCR0, | |
124 | MLX4_COMM_CMD_VHCR1, | |
125 | MLX4_COMM_CMD_VHCR2, | |
126 | MLX4_COMM_CMD_VHCR_EN, | |
127 | MLX4_COMM_CMD_VHCR_POST, | |
128 | MLX4_COMM_CMD_FLR = 254 | |
129 | }; | |
130 | ||
99ec41d0 JM |
131 | enum { |
132 | MLX4_VF_SMI_DISABLED, | |
133 | MLX4_VF_SMI_ENABLED | |
134 | }; | |
135 | ||
623ed84b JM |
136 | /*The flag indicates that the slave should delay the RESET cmd*/ |
137 | #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb | |
138 | /*indicates how many retries will be done if we are in the middle of FLR*/ | |
139 | #define NUM_OF_RESET_RETRIES 10 | |
140 | #define SLEEP_TIME_IN_RESET (2 * 1000) | |
141 | enum mlx4_resource { | |
142 | RES_QP, | |
143 | RES_CQ, | |
144 | RES_SRQ, | |
145 | RES_XRCD, | |
146 | RES_MPT, | |
147 | RES_MTT, | |
148 | RES_MAC, | |
149 | RES_VLAN, | |
150 | RES_EQ, | |
151 | RES_COUNTER, | |
1b9c6b06 | 152 | RES_FS_RULE, |
623ed84b JM |
153 | MLX4_NUM_OF_RESOURCE_TYPE |
154 | }; | |
155 | ||
156 | enum mlx4_alloc_mode { | |
157 | RES_OP_RESERVE, | |
158 | RES_OP_RESERVE_AND_MAP, | |
159 | RES_OP_MAP_ICM, | |
160 | }; | |
161 | ||
b8924951 JM |
162 | enum mlx4_res_tracker_free_type { |
163 | RES_TR_FREE_ALL, | |
164 | RES_TR_FREE_SLAVES_ONLY, | |
165 | RES_TR_FREE_STRUCTS_ONLY, | |
166 | }; | |
623ed84b JM |
167 | |
168 | /* | |
169 | *Virtual HCR structures. | |
170 | * mlx4_vhcr is the sw representation, in machine endianess | |
171 | * | |
172 | * mlx4_vhcr_cmd is the formalized structure, the one that is passed | |
173 | * to FW to go through communication channel. | |
174 | * It is big endian, and has the same structure as the physical HCR | |
175 | * used by command interface | |
176 | */ | |
177 | struct mlx4_vhcr { | |
178 | u64 in_param; | |
179 | u64 out_param; | |
180 | u32 in_modifier; | |
181 | u32 errno; | |
182 | u16 op; | |
183 | u16 token; | |
184 | u8 op_modifier; | |
185 | u8 e_bit; | |
186 | }; | |
187 | ||
188 | struct mlx4_vhcr_cmd { | |
189 | __be64 in_param; | |
190 | __be32 in_modifier; | |
191 | __be64 out_param; | |
192 | __be16 token; | |
193 | u16 reserved; | |
194 | u8 status; | |
195 | u8 flags; | |
196 | __be16 opcode; | |
197 | }; | |
198 | ||
199 | struct mlx4_cmd_info { | |
200 | u16 opcode; | |
201 | bool has_inbox; | |
202 | bool has_outbox; | |
203 | bool out_is_imm; | |
204 | bool encode_slave_id; | |
205 | int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, | |
206 | struct mlx4_cmd_mailbox *inbox); | |
207 | int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, | |
208 | struct mlx4_cmd_mailbox *inbox, | |
209 | struct mlx4_cmd_mailbox *outbox, | |
210 | struct mlx4_cmd_info *cmd); | |
211 | }; | |
212 | ||
225c7b1f RD |
213 | #ifdef CONFIG_MLX4_DEBUG |
214 | extern int mlx4_debug_level; | |
7b0f5df4 RD |
215 | #else /* CONFIG_MLX4_DEBUG */ |
216 | #define mlx4_debug_level (0) | |
217 | #endif /* CONFIG_MLX4_DEBUG */ | |
225c7b1f | 218 | |
1a91de28 | 219 | #define mlx4_dbg(mdev, format, ...) \ |
0a645e80 JP |
220 | do { \ |
221 | if (mlx4_debug_level) \ | |
1a91de28 JP |
222 | dev_printk(KERN_DEBUG, &(mdev)->pdev->dev, format, \ |
223 | ##__VA_ARGS__); \ | |
0a645e80 | 224 | } while (0) |
225c7b1f | 225 | |
1a91de28 JP |
226 | #define mlx4_err(mdev, format, ...) \ |
227 | dev_err(&(mdev)->pdev->dev, format, ##__VA_ARGS__) | |
228 | #define mlx4_info(mdev, format, ...) \ | |
229 | dev_info(&(mdev)->pdev->dev, format, ##__VA_ARGS__) | |
230 | #define mlx4_warn(mdev, format, ...) \ | |
231 | dev_warn(&(mdev)->pdev->dev, format, ##__VA_ARGS__) | |
225c7b1f | 232 | |
0ec2c0f8 | 233 | extern int mlx4_log_num_mgm_entry_size; |
2b8fb286 | 234 | extern int log_mtts_per_seg; |
0ec2c0f8 | 235 | |
623ed84b JM |
236 | #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) |
237 | #define ALL_SLAVES 0xff | |
238 | ||
225c7b1f RD |
239 | struct mlx4_bitmap { |
240 | u32 last; | |
241 | u32 top; | |
242 | u32 max; | |
93fc9e1b | 243 | u32 reserved_top; |
225c7b1f | 244 | u32 mask; |
42d1e017 | 245 | u32 avail; |
225c7b1f RD |
246 | spinlock_t lock; |
247 | unsigned long *table; | |
248 | }; | |
249 | ||
250 | struct mlx4_buddy { | |
251 | unsigned long **bits; | |
e4044cfc | 252 | unsigned int *num_free; |
3de819e6 | 253 | u32 max_order; |
225c7b1f RD |
254 | spinlock_t lock; |
255 | }; | |
256 | ||
257 | struct mlx4_icm; | |
258 | ||
259 | struct mlx4_icm_table { | |
260 | u64 virt; | |
261 | int num_icm; | |
3de819e6 | 262 | u32 num_obj; |
225c7b1f RD |
263 | int obj_size; |
264 | int lowmem; | |
5b0bf5e2 | 265 | int coherent; |
225c7b1f RD |
266 | struct mutex mutex; |
267 | struct mlx4_icm **icm; | |
268 | }; | |
269 | ||
cc1ade94 SM |
270 | #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) |
271 | #define MLX4_MPT_FLAG_FREE (0x3UL << 28) | |
272 | #define MLX4_MPT_FLAG_MIO (1 << 17) | |
273 | #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) | |
274 | #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) | |
275 | #define MLX4_MPT_FLAG_REGION (1 << 8) | |
276 | ||
e630664c MB |
277 | #define MLX4_MPT_PD_MASK (0x1FFFFUL) |
278 | #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) | |
cc1ade94 SM |
279 | #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) |
280 | #define MLX4_MPT_PD_FLAG_RAE (1 << 28) | |
281 | #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) | |
282 | ||
283 | #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) | |
284 | ||
285 | #define MLX4_MPT_STATUS_SW 0xF0 | |
286 | #define MLX4_MPT_STATUS_HW 0x00 | |
287 | ||
c82e9aa0 EC |
288 | /* |
289 | * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. | |
290 | */ | |
291 | struct mlx4_mpt_entry { | |
292 | __be32 flags; | |
293 | __be32 qpn; | |
294 | __be32 key; | |
295 | __be32 pd_flags; | |
296 | __be64 start; | |
297 | __be64 length; | |
298 | __be32 lkey; | |
299 | __be32 win_cnt; | |
300 | u8 reserved1[3]; | |
301 | u8 mtt_rep; | |
2b8fb286 | 302 | __be64 mtt_addr; |
c82e9aa0 EC |
303 | __be32 mtt_sz; |
304 | __be32 entity_size; | |
305 | __be32 first_byte_offset; | |
306 | } __packed; | |
307 | ||
308 | /* | |
309 | * Must be packed because start is 64 bits but only aligned to 32 bits. | |
310 | */ | |
311 | struct mlx4_eq_context { | |
312 | __be32 flags; | |
313 | u16 reserved1[3]; | |
314 | __be16 page_offset; | |
315 | u8 log_eq_size; | |
316 | u8 reserved2[4]; | |
317 | u8 eq_period; | |
318 | u8 reserved3; | |
319 | u8 eq_max_count; | |
320 | u8 reserved4[3]; | |
321 | u8 intr; | |
322 | u8 log_page_size; | |
323 | u8 reserved5[2]; | |
324 | u8 mtt_base_addr_h; | |
325 | __be32 mtt_base_addr_l; | |
326 | u32 reserved6[2]; | |
327 | __be32 consumer_index; | |
328 | __be32 producer_index; | |
329 | u32 reserved7[4]; | |
330 | }; | |
331 | ||
332 | struct mlx4_cq_context { | |
333 | __be32 flags; | |
334 | u16 reserved1[3]; | |
335 | __be16 page_offset; | |
336 | __be32 logsize_usrpage; | |
337 | __be16 cq_period; | |
338 | __be16 cq_max_count; | |
339 | u8 reserved2[3]; | |
340 | u8 comp_eqn; | |
341 | u8 log_page_size; | |
342 | u8 reserved3[2]; | |
343 | u8 mtt_base_addr_h; | |
344 | __be32 mtt_base_addr_l; | |
345 | __be32 last_notified_index; | |
346 | __be32 solicit_producer_index; | |
347 | __be32 consumer_index; | |
348 | __be32 producer_index; | |
349 | u32 reserved4[2]; | |
350 | __be64 db_rec_addr; | |
351 | }; | |
352 | ||
353 | struct mlx4_srq_context { | |
354 | __be32 state_logsize_srqn; | |
355 | u8 logstride; | |
356 | u8 reserved1; | |
357 | __be16 xrcd; | |
358 | __be32 pg_offset_cqn; | |
359 | u32 reserved2; | |
360 | u8 log_page_size; | |
361 | u8 reserved3[2]; | |
362 | u8 mtt_base_addr_h; | |
363 | __be32 mtt_base_addr_l; | |
364 | __be32 pd; | |
365 | __be16 limit_watermark; | |
366 | __be16 wqe_cnt; | |
367 | u16 reserved4; | |
368 | __be16 wqe_counter; | |
369 | u32 reserved5; | |
370 | __be64 db_rec_addr; | |
371 | }; | |
372 | ||
225c7b1f RD |
373 | struct mlx4_eq { |
374 | struct mlx4_dev *dev; | |
375 | void __iomem *doorbell; | |
376 | int eqn; | |
377 | u32 cons_index; | |
378 | u16 irq; | |
379 | u16 have_irq; | |
380 | int nent; | |
381 | struct mlx4_buf_list *page_list; | |
382 | struct mlx4_mtt mtt; | |
383 | }; | |
384 | ||
623ed84b JM |
385 | struct mlx4_slave_eqe { |
386 | u8 type; | |
387 | u8 port; | |
388 | u32 param; | |
389 | }; | |
390 | ||
391 | struct mlx4_slave_event_eq_info { | |
803143fb | 392 | int eqn; |
623ed84b | 393 | u16 token; |
623ed84b JM |
394 | }; |
395 | ||
225c7b1f RD |
396 | struct mlx4_profile { |
397 | int num_qp; | |
398 | int rdmarc_per_qp; | |
399 | int num_srq; | |
400 | int num_cq; | |
401 | int num_mcg; | |
402 | int num_mpt; | |
db5a7a65 | 403 | unsigned num_mtt; |
225c7b1f RD |
404 | }; |
405 | ||
406 | struct mlx4_fw { | |
407 | u64 clr_int_base; | |
408 | u64 catas_offset; | |
623ed84b | 409 | u64 comm_base; |
ddd8a6c1 | 410 | u64 clock_offset; |
225c7b1f RD |
411 | struct mlx4_icm *fw_icm; |
412 | struct mlx4_icm *aux_icm; | |
413 | u32 catas_size; | |
414 | u16 fw_pages; | |
415 | u8 clr_int_bar; | |
416 | u8 catas_bar; | |
623ed84b | 417 | u8 comm_bar; |
ddd8a6c1 | 418 | u8 clock_bar; |
623ed84b JM |
419 | }; |
420 | ||
421 | struct mlx4_comm { | |
422 | u32 slave_write; | |
423 | u32 slave_read; | |
225c7b1f RD |
424 | }; |
425 | ||
ffe455ad EE |
426 | enum { |
427 | MLX4_MCAST_CONFIG = 0, | |
428 | MLX4_MCAST_DISABLE = 1, | |
429 | MLX4_MCAST_ENABLE = 2, | |
430 | }; | |
431 | ||
623ed84b JM |
432 | #define VLAN_FLTR_SIZE 128 |
433 | ||
434 | struct mlx4_vlan_fltr { | |
435 | __be32 entry[VLAN_FLTR_SIZE]; | |
436 | }; | |
437 | ||
ffe455ad EE |
438 | struct mlx4_mcast_entry { |
439 | struct list_head list; | |
440 | u64 addr; | |
441 | }; | |
442 | ||
b12d93d6 YP |
443 | struct mlx4_promisc_qp { |
444 | struct list_head list; | |
445 | u32 qpn; | |
446 | }; | |
447 | ||
448 | struct mlx4_steer_index { | |
449 | struct list_head list; | |
450 | unsigned int index; | |
451 | struct list_head duplicates; | |
452 | }; | |
453 | ||
803143fb MA |
454 | #define MLX4_EVENT_TYPES_NUM 64 |
455 | ||
623ed84b JM |
456 | struct mlx4_slave_state { |
457 | u8 comm_toggle; | |
458 | u8 last_cmd; | |
459 | u8 init_port_mask; | |
460 | bool active; | |
2c957ff2 | 461 | bool old_vlan_api; |
623ed84b JM |
462 | u8 function; |
463 | dma_addr_t vhcr_dma; | |
464 | u16 mtu[MLX4_MAX_PORTS + 1]; | |
465 | __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; | |
466 | struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; | |
467 | struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; | |
468 | struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; | |
803143fb MA |
469 | /* event type to eq number lookup */ |
470 | struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; | |
623ed84b JM |
471 | u16 eq_pi; |
472 | u16 eq_ci; | |
473 | spinlock_t lock; | |
474 | /*initialized via the kzalloc*/ | |
475 | u8 is_slave_going_down; | |
476 | u32 cookie; | |
993c401e | 477 | enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; |
623ed84b JM |
478 | }; |
479 | ||
0eb62b93 RE |
480 | #define MLX4_VGT 4095 |
481 | #define NO_INDX (-1) | |
482 | ||
483 | struct mlx4_vport_state { | |
484 | u64 mac; | |
485 | u16 default_vlan; | |
486 | u8 default_qos; | |
487 | u32 tx_rate; | |
488 | bool spoofchk; | |
948e306d | 489 | u32 link_state; |
0eb62b93 RE |
490 | }; |
491 | ||
492 | struct mlx4_vf_admin_state { | |
493 | struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; | |
99ec41d0 | 494 | u8 enable_smi[MLX4_MAX_PORTS + 1]; |
0eb62b93 RE |
495 | }; |
496 | ||
497 | struct mlx4_vport_oper_state { | |
498 | struct mlx4_vport_state state; | |
499 | int mac_idx; | |
500 | int vlan_idx; | |
501 | }; | |
99ec41d0 | 502 | |
0eb62b93 RE |
503 | struct mlx4_vf_oper_state { |
504 | struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; | |
99ec41d0 | 505 | u8 smi_enabled[MLX4_MAX_PORTS + 1]; |
0eb62b93 RE |
506 | }; |
507 | ||
623ed84b JM |
508 | struct slave_list { |
509 | struct mutex mutex; | |
510 | struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; | |
511 | }; | |
512 | ||
5a0d0a61 | 513 | struct resource_allocator { |
146f3ef4 | 514 | spinlock_t alloc_lock; /* protect quotas */ |
5a0d0a61 JM |
515 | union { |
516 | int res_reserved; | |
517 | int res_port_rsvd[MLX4_MAX_PORTS]; | |
518 | }; | |
519 | union { | |
520 | int res_free; | |
521 | int res_port_free[MLX4_MAX_PORTS]; | |
522 | }; | |
523 | int *quota; | |
524 | int *allocated; | |
525 | int *guaranteed; | |
526 | }; | |
527 | ||
623ed84b JM |
528 | struct mlx4_resource_tracker { |
529 | spinlock_t lock; | |
530 | /* tree for each resources */ | |
4af1c048 | 531 | struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; |
623ed84b JM |
532 | /* num_of_slave's lists, one per slave */ |
533 | struct slave_list *slave_list; | |
5a0d0a61 | 534 | struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; |
623ed84b JM |
535 | }; |
536 | ||
537 | #define SLAVE_EVENT_EQ_SIZE 128 | |
538 | struct mlx4_slave_event_eq { | |
539 | u32 eqn; | |
540 | u32 cons; | |
541 | u32 prod; | |
992e8e6e | 542 | spinlock_t event_lock; |
623ed84b JM |
543 | struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; |
544 | }; | |
545 | ||
546 | struct mlx4_master_qp0_state { | |
547 | int proxy_qp0_active; | |
548 | int qp0_active; | |
549 | int port_active; | |
550 | }; | |
551 | ||
552 | struct mlx4_mfunc_master_ctx { | |
553 | struct mlx4_slave_state *slave_state; | |
0eb62b93 RE |
554 | struct mlx4_vf_admin_state *vf_admin; |
555 | struct mlx4_vf_oper_state *vf_oper; | |
623ed84b JM |
556 | struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; |
557 | int init_port_ref[MLX4_MAX_PORTS + 1]; | |
558 | u16 max_mtu[MLX4_MAX_PORTS + 1]; | |
559 | int disable_mcast_ref[MLX4_MAX_PORTS + 1]; | |
560 | struct mlx4_resource_tracker res_tracker; | |
561 | struct workqueue_struct *comm_wq; | |
562 | struct work_struct comm_work; | |
563 | struct work_struct slave_event_work; | |
564 | struct work_struct slave_flr_event_work; | |
565 | spinlock_t slave_state_lock; | |
f5311ac1 | 566 | __be32 comm_arm_bit_vector[4]; |
623ed84b JM |
567 | struct mlx4_eqe cmd_eqe; |
568 | struct mlx4_slave_event_eq slave_eq; | |
569 | struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; | |
570 | }; | |
571 | ||
572 | struct mlx4_mfunc { | |
573 | struct mlx4_comm __iomem *comm; | |
574 | struct mlx4_vhcr_cmd *vhcr; | |
575 | dma_addr_t vhcr_dma; | |
576 | ||
577 | struct mlx4_mfunc_master_ctx master; | |
578 | }; | |
579 | ||
fe6f700d YP |
580 | #define MGM_QPN_MASK 0x00FFFFFF |
581 | #define MGM_BLCK_LB_BIT 30 | |
582 | ||
583 | struct mlx4_mgm { | |
584 | __be32 next_gid_index; | |
585 | __be32 members_count; | |
586 | u32 reserved[2]; | |
587 | u8 gid[16]; | |
588 | __be32 qp[MLX4_MAX_QP_PER_MGM]; | |
589 | }; | |
590 | ||
225c7b1f RD |
591 | struct mlx4_cmd { |
592 | struct pci_pool *pool; | |
593 | void __iomem *hcr; | |
594 | struct mutex hcr_mutex; | |
f3d4c89e | 595 | struct mutex slave_cmd_mutex; |
225c7b1f RD |
596 | struct semaphore poll_sem; |
597 | struct semaphore event_sem; | |
598 | int max_cmds; | |
599 | spinlock_t context_lock; | |
600 | int free_head; | |
601 | struct mlx4_cmd_context *context; | |
602 | u16 token_mask; | |
603 | u8 use_events; | |
604 | u8 toggle; | |
623ed84b | 605 | u8 comm_toggle; |
225c7b1f RD |
606 | }; |
607 | ||
b01978ca JM |
608 | enum { |
609 | MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, | |
610 | MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, | |
0a6eac24 | 611 | MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, |
b01978ca JM |
612 | }; |
613 | struct mlx4_vf_immed_vlan_work { | |
614 | struct work_struct work; | |
615 | struct mlx4_priv *priv; | |
616 | int flags; | |
617 | int slave; | |
618 | int vlan_ix; | |
619 | int orig_vlan_ix; | |
620 | u8 port; | |
621 | u8 qos; | |
622 | u16 vlan_id; | |
623 | u16 orig_vlan_id; | |
624 | }; | |
625 | ||
626 | ||
225c7b1f RD |
627 | struct mlx4_uar_table { |
628 | struct mlx4_bitmap bitmap; | |
629 | }; | |
630 | ||
631 | struct mlx4_mr_table { | |
632 | struct mlx4_bitmap mpt_bitmap; | |
633 | struct mlx4_buddy mtt_buddy; | |
634 | u64 mtt_base; | |
635 | u64 mpt_base; | |
636 | struct mlx4_icm_table mtt_table; | |
637 | struct mlx4_icm_table dmpt_table; | |
638 | }; | |
639 | ||
640 | struct mlx4_cq_table { | |
641 | struct mlx4_bitmap bitmap; | |
642 | spinlock_t lock; | |
643 | struct radix_tree_root tree; | |
644 | struct mlx4_icm_table table; | |
645 | struct mlx4_icm_table cmpt_table; | |
646 | }; | |
647 | ||
648 | struct mlx4_eq_table { | |
649 | struct mlx4_bitmap bitmap; | |
b8dd786f | 650 | char *irq_names; |
225c7b1f | 651 | void __iomem *clr_int; |
b8dd786f | 652 | void __iomem **uar_map; |
225c7b1f | 653 | u32 clr_mask; |
b8dd786f | 654 | struct mlx4_eq *eq; |
fa0681d2 | 655 | struct mlx4_icm_table table; |
225c7b1f RD |
656 | struct mlx4_icm_table cmpt_table; |
657 | int have_irq; | |
658 | u8 inta_pin; | |
659 | }; | |
660 | ||
661 | struct mlx4_srq_table { | |
662 | struct mlx4_bitmap bitmap; | |
663 | spinlock_t lock; | |
664 | struct radix_tree_root tree; | |
665 | struct mlx4_icm_table table; | |
666 | struct mlx4_icm_table cmpt_table; | |
667 | }; | |
668 | ||
669 | struct mlx4_qp_table { | |
670 | struct mlx4_bitmap bitmap; | |
671 | u32 rdmarc_base; | |
672 | int rdmarc_shift; | |
673 | spinlock_t lock; | |
674 | struct mlx4_icm_table qp_table; | |
675 | struct mlx4_icm_table auxc_table; | |
676 | struct mlx4_icm_table altc_table; | |
677 | struct mlx4_icm_table rdmarc_table; | |
678 | struct mlx4_icm_table cmpt_table; | |
679 | }; | |
680 | ||
681 | struct mlx4_mcg_table { | |
682 | struct mutex mutex; | |
683 | struct mlx4_bitmap bitmap; | |
684 | struct mlx4_icm_table table; | |
685 | }; | |
686 | ||
687 | struct mlx4_catas_err { | |
688 | u32 __iomem *map; | |
ee49bd93 JM |
689 | struct timer_list timer; |
690 | struct list_head list; | |
225c7b1f RD |
691 | }; |
692 | ||
2a2336f8 YP |
693 | #define MLX4_MAX_MAC_NUM 128 |
694 | #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) | |
695 | ||
696 | struct mlx4_mac_table { | |
697 | __be64 entries[MLX4_MAX_MAC_NUM]; | |
698 | int refs[MLX4_MAX_MAC_NUM]; | |
699 | struct mutex mutex; | |
700 | int total; | |
701 | int max; | |
702 | }; | |
703 | ||
111c6094 JM |
704 | #define MLX4_ROCE_GID_ENTRY_SIZE 16 |
705 | ||
706 | struct mlx4_roce_gid_entry { | |
707 | u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; | |
708 | }; | |
709 | ||
710 | struct mlx4_roce_gid_table { | |
711 | struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; | |
712 | struct mutex mutex; | |
713 | }; | |
714 | ||
2a2336f8 YP |
715 | #define MLX4_MAX_VLAN_NUM 128 |
716 | #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) | |
717 | ||
718 | struct mlx4_vlan_table { | |
719 | __be32 entries[MLX4_MAX_VLAN_NUM]; | |
720 | int refs[MLX4_MAX_VLAN_NUM]; | |
721 | struct mutex mutex; | |
722 | int total; | |
723 | int max; | |
724 | }; | |
725 | ||
ffe455ad EE |
726 | #define SET_PORT_GEN_ALL_VALID 0x7 |
727 | #define SET_PORT_PROMISC_SHIFT 31 | |
728 | #define SET_PORT_MC_PROMISC_SHIFT 30 | |
729 | ||
730 | enum { | |
731 | MCAST_DIRECT_ONLY = 0, | |
732 | MCAST_DIRECT = 1, | |
733 | MCAST_DEFAULT = 2 | |
734 | }; | |
735 | ||
736 | ||
737 | struct mlx4_set_port_general_context { | |
738 | u8 reserved[3]; | |
739 | u8 flags; | |
740 | u16 reserved2; | |
741 | __be16 mtu; | |
742 | u8 pptx; | |
743 | u8 pfctx; | |
744 | u16 reserved3; | |
745 | u8 pprx; | |
746 | u8 pfcrx; | |
747 | u16 reserved4; | |
748 | }; | |
749 | ||
750 | struct mlx4_set_port_rqp_calc_context { | |
751 | __be32 base_qpn; | |
752 | u8 rererved; | |
753 | u8 n_mac; | |
754 | u8 n_vlan; | |
755 | u8 n_prio; | |
756 | u8 reserved2[3]; | |
757 | u8 mac_miss; | |
758 | u8 intra_no_vlan; | |
759 | u8 no_vlan; | |
760 | u8 intra_vlan_miss; | |
761 | u8 vlan_miss; | |
762 | u8 reserved3[3]; | |
763 | u8 no_vlan_prio; | |
764 | __be32 promisc; | |
765 | __be32 mcast; | |
766 | }; | |
767 | ||
2a2336f8 YP |
768 | struct mlx4_port_info { |
769 | struct mlx4_dev *dev; | |
770 | int port; | |
7ff93f8b YP |
771 | char dev_name[16]; |
772 | struct device_attribute port_attr; | |
773 | enum mlx4_port_type tmp_type; | |
096335b3 OG |
774 | char dev_mtu_name[16]; |
775 | struct device_attribute port_mtu_attr; | |
2a2336f8 YP |
776 | struct mlx4_mac_table mac_table; |
777 | struct mlx4_vlan_table vlan_table; | |
111c6094 | 778 | struct mlx4_roce_gid_table gid_table; |
1679200f | 779 | int base_qpn; |
2a2336f8 YP |
780 | }; |
781 | ||
27bf91d6 YP |
782 | struct mlx4_sense { |
783 | struct mlx4_dev *dev; | |
784 | u8 do_sense_port[MLX4_MAX_PORTS + 1]; | |
785 | u8 sense_allowed[MLX4_MAX_PORTS + 1]; | |
786 | struct delayed_work sense_poll; | |
787 | }; | |
788 | ||
0b7ca5a9 YP |
789 | struct mlx4_msix_ctl { |
790 | u64 pool_bm; | |
730c41d5 | 791 | struct mutex pool_lock; |
0b7ca5a9 YP |
792 | }; |
793 | ||
b12d93d6 YP |
794 | struct mlx4_steer { |
795 | struct list_head promisc_qps[MLX4_NUM_STEERS]; | |
796 | struct list_head steer_entries[MLX4_NUM_STEERS]; | |
b12d93d6 YP |
797 | }; |
798 | ||
839f1243 RD |
799 | enum { |
800 | MLX4_PCI_DEV_IS_VF = 1 << 0, | |
ca3e57a5 | 801 | MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, |
839f1243 RD |
802 | }; |
803 | ||
7c6d74d2 JM |
804 | enum { |
805 | MLX4_NO_RR = 0, | |
806 | MLX4_USE_RR = 1, | |
807 | }; | |
808 | ||
225c7b1f RD |
809 | struct mlx4_priv { |
810 | struct mlx4_dev dev; | |
811 | ||
812 | struct list_head dev_list; | |
813 | struct list_head ctx_list; | |
814 | spinlock_t ctx_lock; | |
815 | ||
839f1243 | 816 | int pci_dev_data; |
befdf897 | 817 | int removed; |
839f1243 | 818 | |
6296883c YP |
819 | struct list_head pgdir_list; |
820 | struct mutex pgdir_mutex; | |
821 | ||
225c7b1f RD |
822 | struct mlx4_fw fw; |
823 | struct mlx4_cmd cmd; | |
623ed84b | 824 | struct mlx4_mfunc mfunc; |
225c7b1f RD |
825 | |
826 | struct mlx4_bitmap pd_bitmap; | |
012a8ff5 | 827 | struct mlx4_bitmap xrcd_bitmap; |
225c7b1f RD |
828 | struct mlx4_uar_table uar_table; |
829 | struct mlx4_mr_table mr_table; | |
830 | struct mlx4_cq_table cq_table; | |
831 | struct mlx4_eq_table eq_table; | |
832 | struct mlx4_srq_table srq_table; | |
833 | struct mlx4_qp_table qp_table; | |
834 | struct mlx4_mcg_table mcg_table; | |
f2a3f6a3 | 835 | struct mlx4_bitmap counters_bitmap; |
225c7b1f RD |
836 | |
837 | struct mlx4_catas_err catas_err; | |
838 | ||
839 | void __iomem *clr_base; | |
840 | ||
841 | struct mlx4_uar driver_uar; | |
842 | void __iomem *kar; | |
2a2336f8 | 843 | struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 844 | struct mlx4_sense sense; |
7ff93f8b | 845 | struct mutex port_mutex; |
0b7ca5a9 | 846 | struct mlx4_msix_ctl msix_ctl; |
b12d93d6 | 847 | struct mlx4_steer *steer; |
c1b43dca EC |
848 | struct list_head bf_list; |
849 | struct mutex bf_mutex; | |
850 | struct io_mapping *bf_mapping; | |
ddd8a6c1 | 851 | void __iomem *clock_mapping; |
ea51b377 | 852 | int reserved_mtts; |
0ff1fb65 | 853 | int fs_hash_mode; |
54679e14 | 854 | u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; |
afa8fd1d | 855 | __be64 slave_node_guids[MLX4_MFUNC_MAX]; |
54679e14 | 856 | |
fe6f700d YP |
857 | atomic_t opreq_count; |
858 | struct work_struct opreq_task; | |
225c7b1f RD |
859 | }; |
860 | ||
861 | static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) | |
862 | { | |
863 | return container_of(dev, struct mlx4_priv, dev); | |
864 | } | |
865 | ||
27bf91d6 YP |
866 | #define MLX4_SENSE_RANGE (HZ * 3) |
867 | ||
868 | extern struct workqueue_struct *mlx4_wq; | |
869 | ||
225c7b1f | 870 | u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); |
7c6d74d2 | 871 | void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); |
a3cdcbfa | 872 | u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); |
7c6d74d2 JM |
873 | void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, |
874 | int use_rr); | |
42d1e017 | 875 | u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); |
93fc9e1b YP |
876 | int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, |
877 | u32 reserved_bot, u32 resetrved_top); | |
225c7b1f RD |
878 | void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); |
879 | ||
880 | int mlx4_reset(struct mlx4_dev *dev); | |
881 | ||
b8dd786f YP |
882 | int mlx4_alloc_eq_table(struct mlx4_dev *dev); |
883 | void mlx4_free_eq_table(struct mlx4_dev *dev); | |
884 | ||
225c7b1f | 885 | int mlx4_init_pd_table(struct mlx4_dev *dev); |
012a8ff5 | 886 | int mlx4_init_xrcd_table(struct mlx4_dev *dev); |
225c7b1f RD |
887 | int mlx4_init_uar_table(struct mlx4_dev *dev); |
888 | int mlx4_init_mr_table(struct mlx4_dev *dev); | |
889 | int mlx4_init_eq_table(struct mlx4_dev *dev); | |
890 | int mlx4_init_cq_table(struct mlx4_dev *dev); | |
891 | int mlx4_init_qp_table(struct mlx4_dev *dev); | |
892 | int mlx4_init_srq_table(struct mlx4_dev *dev); | |
893 | int mlx4_init_mcg_table(struct mlx4_dev *dev); | |
894 | ||
895 | void mlx4_cleanup_pd_table(struct mlx4_dev *dev); | |
012a8ff5 | 896 | void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); |
225c7b1f RD |
897 | void mlx4_cleanup_uar_table(struct mlx4_dev *dev); |
898 | void mlx4_cleanup_mr_table(struct mlx4_dev *dev); | |
899 | void mlx4_cleanup_eq_table(struct mlx4_dev *dev); | |
900 | void mlx4_cleanup_cq_table(struct mlx4_dev *dev); | |
901 | void mlx4_cleanup_qp_table(struct mlx4_dev *dev); | |
902 | void mlx4_cleanup_srq_table(struct mlx4_dev *dev); | |
903 | void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); | |
40f2287b | 904 | int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); |
c82e9aa0 EC |
905 | void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); |
906 | int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); | |
907 | void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); | |
908 | int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); | |
909 | void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); | |
b20e519a SM |
910 | int __mlx4_mpt_reserve(struct mlx4_dev *dev); |
911 | void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); | |
40f2287b | 912 | int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); |
b20e519a | 913 | void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); |
c82e9aa0 EC |
914 | u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); |
915 | void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); | |
225c7b1f | 916 | |
623ed84b JM |
917 | int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, |
918 | struct mlx4_vhcr *vhcr, | |
919 | struct mlx4_cmd_mailbox *inbox, | |
920 | struct mlx4_cmd_mailbox *outbox, | |
921 | struct mlx4_cmd_info *cmd); | |
922 | int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, | |
923 | struct mlx4_vhcr *vhcr, | |
924 | struct mlx4_cmd_mailbox *inbox, | |
925 | struct mlx4_cmd_mailbox *outbox, | |
926 | struct mlx4_cmd_info *cmd); | |
927 | int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
928 | struct mlx4_vhcr *vhcr, | |
929 | struct mlx4_cmd_mailbox *inbox, | |
930 | struct mlx4_cmd_mailbox *outbox, | |
931 | struct mlx4_cmd_info *cmd); | |
932 | int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
933 | struct mlx4_vhcr *vhcr, | |
934 | struct mlx4_cmd_mailbox *inbox, | |
935 | struct mlx4_cmd_mailbox *outbox, | |
936 | struct mlx4_cmd_info *cmd); | |
937 | int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
938 | struct mlx4_vhcr *vhcr, | |
939 | struct mlx4_cmd_mailbox *inbox, | |
940 | struct mlx4_cmd_mailbox *outbox, | |
941 | struct mlx4_cmd_info *cmd); | |
942 | int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
943 | struct mlx4_vhcr *vhcr, | |
944 | struct mlx4_cmd_mailbox *inbox, | |
945 | struct mlx4_cmd_mailbox *outbox, | |
946 | struct mlx4_cmd_info *cmd); | |
947 | int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, | |
948 | struct mlx4_vhcr *vhcr, | |
949 | struct mlx4_cmd_mailbox *inbox, | |
950 | struct mlx4_cmd_mailbox *outbox, | |
951 | struct mlx4_cmd_info *cmd); | |
c82e9aa0 EC |
952 | int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, |
953 | int *base); | |
954 | void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
955 | int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
956 | void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
c82e9aa0 EC |
957 | int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
958 | int start_index, int npages, u64 *page_list); | |
ba062d52 JM |
959 | int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
960 | void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
961 | int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); | |
962 | void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
623ed84b | 963 | |
ee49bd93 JM |
964 | void mlx4_start_catas_poll(struct mlx4_dev *dev); |
965 | void mlx4_stop_catas_poll(struct mlx4_dev *dev); | |
27bf91d6 | 966 | void mlx4_catas_init(void); |
ee49bd93 | 967 | int mlx4_restart_one(struct pci_dev *pdev); |
225c7b1f RD |
968 | int mlx4_register_device(struct mlx4_dev *dev); |
969 | void mlx4_unregister_device(struct mlx4_dev *dev); | |
00f5ce99 JM |
970 | void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, |
971 | unsigned long param); | |
225c7b1f RD |
972 | |
973 | struct mlx4_dev_cap; | |
974 | struct mlx4_init_hca_param; | |
975 | ||
976 | u64 mlx4_make_profile(struct mlx4_dev *dev, | |
977 | struct mlx4_profile *request, | |
978 | struct mlx4_dev_cap *dev_cap, | |
979 | struct mlx4_init_hca_param *init_hca); | |
623ed84b JM |
980 | void mlx4_master_comm_channel(struct work_struct *work); |
981 | void mlx4_gen_slave_eqe(struct work_struct *work); | |
982 | void mlx4_master_handle_slave_flr(struct work_struct *work); | |
983 | ||
984 | int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, | |
985 | struct mlx4_vhcr *vhcr, | |
986 | struct mlx4_cmd_mailbox *inbox, | |
987 | struct mlx4_cmd_mailbox *outbox, | |
988 | struct mlx4_cmd_info *cmd); | |
989 | int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, | |
990 | struct mlx4_vhcr *vhcr, | |
991 | struct mlx4_cmd_mailbox *inbox, | |
992 | struct mlx4_cmd_mailbox *outbox, | |
993 | struct mlx4_cmd_info *cmd); | |
994 | int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
995 | struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, | |
996 | struct mlx4_cmd_mailbox *outbox, | |
997 | struct mlx4_cmd_info *cmd); | |
998 | int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, | |
999 | struct mlx4_vhcr *vhcr, | |
1000 | struct mlx4_cmd_mailbox *inbox, | |
1001 | struct mlx4_cmd_mailbox *outbox, | |
1002 | struct mlx4_cmd_info *cmd); | |
1003 | int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1004 | struct mlx4_vhcr *vhcr, | |
1005 | struct mlx4_cmd_mailbox *inbox, | |
1006 | struct mlx4_cmd_mailbox *outbox, | |
1007 | struct mlx4_cmd_info *cmd); | |
1008 | int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1009 | struct mlx4_vhcr *vhcr, | |
1010 | struct mlx4_cmd_mailbox *inbox, | |
1011 | struct mlx4_cmd_mailbox *outbox, | |
1012 | struct mlx4_cmd_info *cmd); | |
1013 | int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1014 | struct mlx4_vhcr *vhcr, | |
1015 | struct mlx4_cmd_mailbox *inbox, | |
1016 | struct mlx4_cmd_mailbox *outbox, | |
1017 | struct mlx4_cmd_info *cmd); | |
1018 | int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1019 | struct mlx4_vhcr *vhcr, | |
1020 | struct mlx4_cmd_mailbox *inbox, | |
1021 | struct mlx4_cmd_mailbox *outbox, | |
1022 | struct mlx4_cmd_info *cmd); | |
1023 | int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1024 | struct mlx4_vhcr *vhcr, | |
1025 | struct mlx4_cmd_mailbox *inbox, | |
1026 | struct mlx4_cmd_mailbox *outbox, | |
1027 | struct mlx4_cmd_info *cmd); | |
1028 | int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1029 | struct mlx4_vhcr *vhcr, | |
1030 | struct mlx4_cmd_mailbox *inbox, | |
1031 | struct mlx4_cmd_mailbox *outbox, | |
1032 | struct mlx4_cmd_info *cmd); | |
1033 | int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1034 | struct mlx4_vhcr *vhcr, | |
1035 | struct mlx4_cmd_mailbox *inbox, | |
1036 | struct mlx4_cmd_mailbox *outbox, | |
1037 | struct mlx4_cmd_info *cmd); | |
1038 | int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1039 | struct mlx4_vhcr *vhcr, | |
1040 | struct mlx4_cmd_mailbox *inbox, | |
1041 | struct mlx4_cmd_mailbox *outbox, | |
1042 | struct mlx4_cmd_info *cmd); | |
1043 | int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1044 | struct mlx4_vhcr *vhcr, | |
1045 | struct mlx4_cmd_mailbox *inbox, | |
1046 | struct mlx4_cmd_mailbox *outbox, | |
1047 | struct mlx4_cmd_info *cmd); | |
1048 | int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1049 | struct mlx4_vhcr *vhcr, | |
1050 | struct mlx4_cmd_mailbox *inbox, | |
1051 | struct mlx4_cmd_mailbox *outbox, | |
1052 | struct mlx4_cmd_info *cmd); | |
1053 | int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1054 | struct mlx4_vhcr *vhcr, | |
1055 | struct mlx4_cmd_mailbox *inbox, | |
1056 | struct mlx4_cmd_mailbox *outbox, | |
1057 | struct mlx4_cmd_info *cmd); | |
1058 | int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1059 | struct mlx4_vhcr *vhcr, | |
1060 | struct mlx4_cmd_mailbox *inbox, | |
1061 | struct mlx4_cmd_mailbox *outbox, | |
1062 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1063 | int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, |
1064 | struct mlx4_vhcr *vhcr, | |
1065 | struct mlx4_cmd_mailbox *inbox, | |
1066 | struct mlx4_cmd_mailbox *outbox, | |
1067 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1068 | int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, |
1069 | struct mlx4_vhcr *vhcr, | |
1070 | struct mlx4_cmd_mailbox *inbox, | |
1071 | struct mlx4_cmd_mailbox *outbox, | |
1072 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1073 | int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, |
1074 | struct mlx4_vhcr *vhcr, | |
1075 | struct mlx4_cmd_mailbox *inbox, | |
1076 | struct mlx4_cmd_mailbox *outbox, | |
1077 | struct mlx4_cmd_info *cmd); | |
1078 | int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1079 | struct mlx4_vhcr *vhcr, | |
1080 | struct mlx4_cmd_mailbox *inbox, | |
1081 | struct mlx4_cmd_mailbox *outbox, | |
1082 | struct mlx4_cmd_info *cmd); | |
1083 | int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1084 | struct mlx4_vhcr *vhcr, | |
1085 | struct mlx4_cmd_mailbox *inbox, | |
1086 | struct mlx4_cmd_mailbox *outbox, | |
1087 | struct mlx4_cmd_info *cmd); | |
1088 | int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1089 | struct mlx4_vhcr *vhcr, | |
1090 | struct mlx4_cmd_mailbox *inbox, | |
1091 | struct mlx4_cmd_mailbox *outbox, | |
1092 | struct mlx4_cmd_info *cmd); | |
1093 | int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1094 | struct mlx4_vhcr *vhcr, | |
1095 | struct mlx4_cmd_mailbox *inbox, | |
1096 | struct mlx4_cmd_mailbox *outbox, | |
1097 | struct mlx4_cmd_info *cmd); | |
1098 | int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1099 | struct mlx4_vhcr *vhcr, | |
1100 | struct mlx4_cmd_mailbox *inbox, | |
1101 | struct mlx4_cmd_mailbox *outbox, | |
1102 | struct mlx4_cmd_info *cmd); | |
1103 | int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1104 | struct mlx4_vhcr *vhcr, | |
1105 | struct mlx4_cmd_mailbox *inbox, | |
1106 | struct mlx4_cmd_mailbox *outbox, | |
1107 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1108 | int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, |
1109 | struct mlx4_vhcr *vhcr, | |
1110 | struct mlx4_cmd_mailbox *inbox, | |
1111 | struct mlx4_cmd_mailbox *outbox, | |
1112 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1113 | int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, |
1114 | struct mlx4_vhcr *vhcr, | |
1115 | struct mlx4_cmd_mailbox *inbox, | |
1116 | struct mlx4_cmd_mailbox *outbox, | |
1117 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1118 | |
1119 | int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); | |
225c7b1f | 1120 | |
225c7b1f RD |
1121 | int mlx4_cmd_init(struct mlx4_dev *dev); |
1122 | void mlx4_cmd_cleanup(struct mlx4_dev *dev); | |
ab9c17a0 JM |
1123 | int mlx4_multi_func_init(struct mlx4_dev *dev); |
1124 | void mlx4_multi_func_cleanup(struct mlx4_dev *dev); | |
225c7b1f RD |
1125 | void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); |
1126 | int mlx4_cmd_use_events(struct mlx4_dev *dev); | |
1127 | void mlx4_cmd_use_polling(struct mlx4_dev *dev); | |
1128 | ||
ab9c17a0 JM |
1129 | int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, |
1130 | unsigned long timeout); | |
1131 | ||
225c7b1f RD |
1132 | void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); |
1133 | void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); | |
1134 | ||
1135 | void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); | |
1136 | ||
1137 | void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); | |
1138 | ||
1139 | void mlx4_handle_catas_err(struct mlx4_dev *dev); | |
1140 | ||
ab6dc30d YP |
1141 | int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, |
1142 | enum mlx4_port_type *type); | |
27bf91d6 YP |
1143 | void mlx4_do_sense_ports(struct mlx4_dev *dev, |
1144 | enum mlx4_port_type *stype, | |
1145 | enum mlx4_port_type *defaults); | |
1146 | void mlx4_start_sense(struct mlx4_dev *dev); | |
1147 | void mlx4_stop_sense(struct mlx4_dev *dev); | |
1148 | void mlx4_sense_init(struct mlx4_dev *dev); | |
1149 | int mlx4_check_port_params(struct mlx4_dev *dev, | |
1150 | enum mlx4_port_type *port_type); | |
1151 | int mlx4_change_port_types(struct mlx4_dev *dev, | |
1152 | enum mlx4_port_type *port_types); | |
1153 | ||
2a2336f8 YP |
1154 | void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); |
1155 | void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); | |
111c6094 JM |
1156 | void mlx4_init_roce_gid_table(struct mlx4_dev *dev, |
1157 | struct mlx4_roce_gid_table *table); | |
2009d005 | 1158 | void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
3f7fb021 | 1159 | int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2a2336f8 | 1160 | |
6634961c | 1161 | int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); |
623ed84b JM |
1162 | /* resource tracker functions*/ |
1163 | int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, | |
1164 | enum mlx4_resource resource_type, | |
aa1ec3dd | 1165 | u64 resource_id, int *slave); |
623ed84b | 1166 | void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); |
111c6094 | 1167 | void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); |
623ed84b JM |
1168 | int mlx4_init_resource_tracker(struct mlx4_dev *dev); |
1169 | ||
b8924951 JM |
1170 | void mlx4_free_resource_tracker(struct mlx4_dev *dev, |
1171 | enum mlx4_res_tracker_free_type type); | |
623ed84b | 1172 | |
b91cb3eb JM |
1173 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
1174 | struct mlx4_vhcr *vhcr, | |
1175 | struct mlx4_cmd_mailbox *inbox, | |
1176 | struct mlx4_cmd_mailbox *outbox, | |
1177 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1178 | int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1179 | struct mlx4_vhcr *vhcr, | |
1180 | struct mlx4_cmd_mailbox *inbox, | |
1181 | struct mlx4_cmd_mailbox *outbox, | |
1182 | struct mlx4_cmd_info *cmd); | |
1183 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, | |
1184 | struct mlx4_vhcr *vhcr, | |
1185 | struct mlx4_cmd_mailbox *inbox, | |
1186 | struct mlx4_cmd_mailbox *outbox, | |
1187 | struct mlx4_cmd_info *cmd); | |
1188 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, | |
1189 | struct mlx4_vhcr *vhcr, | |
1190 | struct mlx4_cmd_mailbox *inbox, | |
1191 | struct mlx4_cmd_mailbox *outbox, | |
1192 | struct mlx4_cmd_info *cmd); | |
b91cb3eb JM |
1193 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
1194 | struct mlx4_vhcr *vhcr, | |
1195 | struct mlx4_cmd_mailbox *inbox, | |
1196 | struct mlx4_cmd_mailbox *outbox, | |
1197 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1198 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1199 | struct mlx4_vhcr *vhcr, | |
1200 | struct mlx4_cmd_mailbox *inbox, | |
1201 | struct mlx4_cmd_mailbox *outbox, | |
1202 | struct mlx4_cmd_info *cmd); | |
9a5aa622 | 1203 | int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); |
7ff93f8b | 1204 | |
6634961c JM |
1205 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
1206 | int *gid_tbl_len, int *pkey_tbl_len); | |
623ed84b JM |
1207 | |
1208 | int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, | |
1209 | struct mlx4_vhcr *vhcr, | |
1210 | struct mlx4_cmd_mailbox *inbox, | |
1211 | struct mlx4_cmd_mailbox *outbox, | |
1212 | struct mlx4_cmd_info *cmd); | |
1213 | ||
ce8d9e0d MB |
1214 | int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, |
1215 | struct mlx4_vhcr *vhcr, | |
1216 | struct mlx4_cmd_mailbox *inbox, | |
1217 | struct mlx4_cmd_mailbox *outbox, | |
1218 | struct mlx4_cmd_info *cmd); | |
1219 | ||
623ed84b JM |
1220 | int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, |
1221 | struct mlx4_vhcr *vhcr, | |
1222 | struct mlx4_cmd_mailbox *inbox, | |
1223 | struct mlx4_cmd_mailbox *outbox, | |
1224 | struct mlx4_cmd_info *cmd); | |
b12d93d6 YP |
1225 | int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
1226 | enum mlx4_protocol prot, enum mlx4_steer_type steer); | |
1227 | int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
1228 | int block_mcast_loopback, enum mlx4_protocol prot, | |
1229 | enum mlx4_steer_type steer); | |
fd91c49f HHZ |
1230 | int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, |
1231 | u8 gid[16], u8 port, | |
1232 | int block_mcast_loopback, | |
1233 | enum mlx4_protocol prot, u64 *reg_id); | |
623ed84b JM |
1234 | int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, |
1235 | struct mlx4_vhcr *vhcr, | |
1236 | struct mlx4_cmd_mailbox *inbox, | |
1237 | struct mlx4_cmd_mailbox *outbox, | |
1238 | struct mlx4_cmd_info *cmd); | |
1239 | int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, | |
1240 | struct mlx4_vhcr *vhcr, | |
1241 | struct mlx4_cmd_mailbox *inbox, | |
1242 | struct mlx4_cmd_mailbox *outbox, | |
1243 | struct mlx4_cmd_info *cmd); | |
1244 | int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, | |
1245 | int port, void *buf); | |
1246 | int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, | |
1247 | struct mlx4_cmd_mailbox *outbox); | |
1248 | int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, | |
1249 | struct mlx4_vhcr *vhcr, | |
1250 | struct mlx4_cmd_mailbox *inbox, | |
1251 | struct mlx4_cmd_mailbox *outbox, | |
1252 | struct mlx4_cmd_info *cmd); | |
1253 | int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, | |
1254 | struct mlx4_vhcr *vhcr, | |
1255 | struct mlx4_cmd_mailbox *inbox, | |
1256 | struct mlx4_cmd_mailbox *outbox, | |
1257 | struct mlx4_cmd_info *cmd); | |
1258 | int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, | |
1259 | struct mlx4_vhcr *vhcr, | |
1260 | struct mlx4_cmd_mailbox *inbox, | |
1261 | struct mlx4_cmd_mailbox *outbox, | |
1262 | struct mlx4_cmd_info *cmd); | |
8fcfb4db HHZ |
1263 | int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, |
1264 | struct mlx4_vhcr *vhcr, | |
1265 | struct mlx4_cmd_mailbox *inbox, | |
1266 | struct mlx4_cmd_mailbox *outbox, | |
1267 | struct mlx4_cmd_info *cmd); | |
1268 | int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, | |
1269 | struct mlx4_vhcr *vhcr, | |
1270 | struct mlx4_cmd_mailbox *inbox, | |
1271 | struct mlx4_cmd_mailbox *outbox, | |
1272 | struct mlx4_cmd_info *cmd); | |
f5311ac1 | 1273 | |
0ec2c0f8 EE |
1274 | int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); |
1275 | int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); | |
1276 | ||
5cc914f1 MA |
1277 | static inline void set_param_l(u64 *arg, u32 val) |
1278 | { | |
e7dbeba8 | 1279 | *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; |
5cc914f1 MA |
1280 | } |
1281 | ||
1282 | static inline void set_param_h(u64 *arg, u32 val) | |
1283 | { | |
1284 | *arg = (*arg & 0xffffffff) | ((u64) val << 32); | |
1285 | } | |
1286 | ||
1287 | static inline u32 get_param_l(u64 *arg) | |
1288 | { | |
1289 | return (u32) (*arg & 0xffffffff); | |
1290 | } | |
1291 | ||
1292 | static inline u32 get_param_h(u64 *arg) | |
1293 | { | |
1294 | return (u32)(*arg >> 32); | |
1295 | } | |
1296 | ||
c82e9aa0 EC |
1297 | static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) |
1298 | { | |
1299 | return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; | |
1300 | } | |
1301 | ||
f5311ac1 JM |
1302 | #define NOT_MASKED_PD_BITS 17 |
1303 | ||
b01978ca JM |
1304 | void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); |
1305 | ||
5a0d0a61 JM |
1306 | void mlx4_init_quotas(struct mlx4_dev *dev); |
1307 | ||
449fc488 | 1308 | int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); |
f74462ac MB |
1309 | /* Returns the VF index of slave */ |
1310 | int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); | |
114840c3 | 1311 | int mlx4_config_mad_demux(struct mlx4_dev *dev); |
b6ffaeff | 1312 | |
225c7b1f | 1313 | #endif /* MLX4_H */ |