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net/mlx4_core: Add firmware commands to support device managed flow steering
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
4af1c048 42#include <linux/rbtree.h>
ee49bd93 43#include <linux/timer.h>
3142788b 44#include <linux/semaphore.h>
27bf91d6 45#include <linux/workqueue.h>
225c7b1f
RD		 46
47#include <linux/mlx4/device.h>
37608eea 48#include <linux/mlx4/driver.h>
225c7b1f 49#include <linux/mlx4/doorbell.h>
623ed84b 50#include <linux/mlx4/cmd.h>
225c7b1f
RD		 51
52#define DRV_NAME "mlx4_core"
ab9c17a0 53#define PFX DRV_NAME ": "
7d4b6bcc
YP		 54#define DRV_VERSION "1.1"
55#define DRV_RELDATE "Dec, 2011"
225c7b1f 56
e5395e92
AV		 57#define MLX4_NUM_UP 8
58#define MLX4_NUM_TC 8
59#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
60#define MLX4_RATELIMIT_DEFAULT 0xffff
61
62struct mlx4_set_port_prio2tc_context {
63 u8 prio2tc[4];
64};
65
66struct mlx4_port_scheduler_tc_cfg_be {
67 __be16 pg;
68 __be16 bw_precentage;
69 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
70 __be16 max_bw_value;
71};
72
73struct mlx4_set_port_scheduler_context {
74 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
75};
76
225c7b1f
RD		 77enum {
78 MLX4_HCR_BASE = 0x80680,
79 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 80 MLX4_CLR_INT_SIZE = 0x00008,
81 MLX4_SLAVE_COMM_BASE = 0x0,
82 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 83};
84
225c7b1f 85enum {
0ec2c0f8
EE		 86 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
87 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
88 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 89};
90
225c7b1f
RD		 91enum {
92 MLX4_NUM_PDS = 1 << 15
93};
94
95enum {
96 MLX4_CMPT_TYPE_QP = 0,
97 MLX4_CMPT_TYPE_SRQ = 1,
98 MLX4_CMPT_TYPE_CQ = 2,
99 MLX4_CMPT_TYPE_EQ = 3,
100 MLX4_CMPT_NUM_TYPE
101};
102
103enum {
104 MLX4_CMPT_SHIFT = 24,
105 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
106};
107
623ed84b
JM		 108enum mlx4_mr_state {
109 MLX4_MR_DISABLED = 0,
110 MLX4_MR_EN_HW,
111 MLX4_MR_EN_SW
112};
113
114#define MLX4_COMM_TIME 10000
115enum {
116 MLX4_COMM_CMD_RESET,
117 MLX4_COMM_CMD_VHCR0,
118 MLX4_COMM_CMD_VHCR1,
119 MLX4_COMM_CMD_VHCR2,
120 MLX4_COMM_CMD_VHCR_EN,
121 MLX4_COMM_CMD_VHCR_POST,
122 MLX4_COMM_CMD_FLR = 254
123};
124
125/*The flag indicates that the slave should delay the RESET cmd*/
126#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
127/*indicates how many retries will be done if we are in the middle of FLR*/
128#define NUM_OF_RESET_RETRIES 10
129#define SLEEP_TIME_IN_RESET (2 * 1000)
130enum mlx4_resource {
131 RES_QP,
132 RES_CQ,
133 RES_SRQ,
134 RES_XRCD,
135 RES_MPT,
136 RES_MTT,
137 RES_MAC,
138 RES_VLAN,
139 RES_EQ,
140 RES_COUNTER,
141 MLX4_NUM_OF_RESOURCE_TYPE
142};
143
144enum mlx4_alloc_mode {
145 RES_OP_RESERVE,
146 RES_OP_RESERVE_AND_MAP,
147 RES_OP_MAP_ICM,
148};
149
b8924951
JM		 150enum mlx4_res_tracker_free_type {
151 RES_TR_FREE_ALL,
152 RES_TR_FREE_SLAVES_ONLY,
153 RES_TR_FREE_STRUCTS_ONLY,
154};
623ed84b
JM		 155
156/*
157 *Virtual HCR structures.
158 * mlx4_vhcr is the sw representation, in machine endianess
159 *
160 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
161 * to FW to go through communication channel.
162 * It is big endian, and has the same structure as the physical HCR
163 * used by command interface
164 */
165struct mlx4_vhcr {
166 u64 in_param;
167 u64 out_param;
168 u32 in_modifier;
169 u32 errno;
170 u16 op;
171 u16 token;
172 u8 op_modifier;
173 u8 e_bit;
174};
175
176struct mlx4_vhcr_cmd {
177 __be64 in_param;
178 __be32 in_modifier;
179 __be64 out_param;
180 __be16 token;
181 u16 reserved;
182 u8 status;
183 u8 flags;
184 __be16 opcode;
185};
186
187struct mlx4_cmd_info {
188 u16 opcode;
189 bool has_inbox;
190 bool has_outbox;
191 bool out_is_imm;
192 bool encode_slave_id;
193 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
194 struct mlx4_cmd_mailbox *inbox);
195 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
196 struct mlx4_cmd_mailbox *inbox,
197 struct mlx4_cmd_mailbox *outbox,
198 struct mlx4_cmd_info *cmd);
199};
200
225c7b1f
RD		 201#ifdef CONFIG_MLX4_DEBUG
202extern int mlx4_debug_level;
7b0f5df4
RD		 203#else /* CONFIG_MLX4_DEBUG */
204#define mlx4_debug_level (0)
205#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 206
207#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 208do { \
209 if (mlx4_debug_level) \
210 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
211} while (0)
225c7b1f 212
225c7b1f 213#define mlx4_err(mdev, format, arg...) \
0a645e80 214 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 215#define mlx4_info(mdev, format, arg...) \
0a645e80 216 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 217#define mlx4_warn(mdev, format, arg...) \
0a645e80 218 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 219
0ec2c0f8 220extern int mlx4_log_num_mgm_entry_size;
2b8fb286 221extern int log_mtts_per_seg;
0ec2c0f8 222
623ed84b
JM		 223#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
224#define ALL_SLAVES 0xff
225
225c7b1f
RD		 226struct mlx4_bitmap {
227 u32 last;
228 u32 top;
229 u32 max;
93fc9e1b 230 u32 reserved_top;
225c7b1f 231 u32 mask;
42d1e017 232 u32 avail;
225c7b1f
RD		 233 spinlock_t lock;
234 unsigned long *table;
235};
236
237struct mlx4_buddy {
238 unsigned long **bits;
e4044cfc 239 unsigned int *num_free;
225c7b1f
RD		 240 int max_order;
241 spinlock_t lock;
242};
243
244struct mlx4_icm;
245
246struct mlx4_icm_table {
247 u64 virt;
248 int num_icm;
249 int num_obj;
250 int obj_size;
251 int lowmem;
5b0bf5e2 252 int coherent;
225c7b1f
RD		 253 struct mutex mutex;
254 struct mlx4_icm **icm;
255};
256
c82e9aa0
EC		 257/*
258 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
259 */
260struct mlx4_mpt_entry {
261 __be32 flags;
262 __be32 qpn;
263 __be32 key;
264 __be32 pd_flags;
265 __be64 start;
266 __be64 length;
267 __be32 lkey;
268 __be32 win_cnt;
269 u8 reserved1[3];
270 u8 mtt_rep;
2b8fb286 271 __be64 mtt_addr;
c82e9aa0
EC		 272 __be32 mtt_sz;
273 __be32 entity_size;
274 __be32 first_byte_offset;
275} __packed;
276
277/*
278 * Must be packed because start is 64 bits but only aligned to 32 bits.
279 */
280struct mlx4_eq_context {
281 __be32 flags;
282 u16 reserved1[3];
283 __be16 page_offset;
284 u8 log_eq_size;
285 u8 reserved2[4];
286 u8 eq_period;
287 u8 reserved3;
288 u8 eq_max_count;
289 u8 reserved4[3];
290 u8 intr;
291 u8 log_page_size;
292 u8 reserved5[2];
293 u8 mtt_base_addr_h;
294 __be32 mtt_base_addr_l;
295 u32 reserved6[2];
296 __be32 consumer_index;
297 __be32 producer_index;
298 u32 reserved7[4];
299};
300
301struct mlx4_cq_context {
302 __be32 flags;
303 u16 reserved1[3];
304 __be16 page_offset;
305 __be32 logsize_usrpage;
306 __be16 cq_period;
307 __be16 cq_max_count;
308 u8 reserved2[3];
309 u8 comp_eqn;
310 u8 log_page_size;
311 u8 reserved3[2];
312 u8 mtt_base_addr_h;
313 __be32 mtt_base_addr_l;
314 __be32 last_notified_index;
315 __be32 solicit_producer_index;
316 __be32 consumer_index;
317 __be32 producer_index;
318 u32 reserved4[2];
319 __be64 db_rec_addr;
320};
321
322struct mlx4_srq_context {
323 __be32 state_logsize_srqn;
324 u8 logstride;
325 u8 reserved1;
326 __be16 xrcd;
327 __be32 pg_offset_cqn;
328 u32 reserved2;
329 u8 log_page_size;
330 u8 reserved3[2];
331 u8 mtt_base_addr_h;
332 __be32 mtt_base_addr_l;
333 __be32 pd;
334 __be16 limit_watermark;
335 __be16 wqe_cnt;
336 u16 reserved4;
337 __be16 wqe_counter;
338 u32 reserved5;
339 __be64 db_rec_addr;
340};
341
623ed84b
JM		 342struct mlx4_eqe {
343 u8 reserved1;
344 u8 type;
345 u8 reserved2;
346 u8 subtype;
347 union {
348 u32 raw[6];
349 struct {
350 __be32 cqn;
351 } __packed comp;
352 struct {
353 u16 reserved1;
354 __be16 token;
355 u32 reserved2;
356 u8 reserved3[3];
357 u8 status;
358 __be64 out_param;
359 } __packed cmd;
360 struct {
361 __be32 qpn;
362 } __packed qp;
363 struct {
364 __be32 srqn;
365 } __packed srq;
366 struct {
367 __be32 cqn;
368 u32 reserved1;
369 u8 reserved2[3];
370 u8 syndrome;
371 } __packed cq_err;
372 struct {
373 u32 reserved1[2];
374 __be32 port;
375 } __packed port_change;
376 struct {
377 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
378 u32 reserved;
379 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
380 } __packed comm_channel_arm;
381 struct {
382 u8 port;
383 u8 reserved[3];
384 __be64 mac;
385 } __packed mac_update;
386 struct {
387 u8 port;
388 } __packed sw_event;
389 struct {
390 __be32 slave_id;
391 } __packed flr_event;
5984be90
JM		 392 struct {
393 __be16 current_temperature;
394 __be16 warning_threshold;
395 } __packed warming;
623ed84b
JM		 396 } event;
397 u8 slave_id;
398 u8 reserved3[2];
399 u8 owner;
400} __packed;
401
225c7b1f
RD		 402struct mlx4_eq {
403 struct mlx4_dev *dev;
404 void __iomem *doorbell;
405 int eqn;
406 u32 cons_index;
407 u16 irq;
408 u16 have_irq;
409 int nent;
410 struct mlx4_buf_list *page_list;
411 struct mlx4_mtt mtt;
412};
413
623ed84b
JM		 414struct mlx4_slave_eqe {
415 u8 type;
416 u8 port;
417 u32 param;
418};
419
420struct mlx4_slave_event_eq_info {
803143fb 421 int eqn;
623ed84b 422 u16 token;
623ed84b
JM		 423};
424
225c7b1f
RD		 425struct mlx4_profile {
426 int num_qp;
427 int rdmarc_per_qp;
428 int num_srq;
429 int num_cq;
430 int num_mcg;
431 int num_mpt;
db5a7a65 432 unsigned num_mtt;
225c7b1f
RD		 433};
434
435struct mlx4_fw {
436 u64 clr_int_base;
437 u64 catas_offset;
623ed84b 438 u64 comm_base;
225c7b1f
RD		 439 struct mlx4_icm *fw_icm;
440 struct mlx4_icm *aux_icm;
441 u32 catas_size;
442 u16 fw_pages;
443 u8 clr_int_bar;
444 u8 catas_bar;
623ed84b
JM		 445 u8 comm_bar;
446};
447
448struct mlx4_comm {
449 u32 slave_write;
450 u32 slave_read;
225c7b1f
RD		 451};
452
ffe455ad
EE		 453enum {
454 MLX4_MCAST_CONFIG = 0,
455 MLX4_MCAST_DISABLE = 1,
456 MLX4_MCAST_ENABLE = 2,
457};
458
623ed84b
JM		 459#define VLAN_FLTR_SIZE 128
460
461struct mlx4_vlan_fltr {
462 __be32 entry[VLAN_FLTR_SIZE];
463};
464
ffe455ad
EE		 465struct mlx4_mcast_entry {
466 struct list_head list;
467 u64 addr;
468};
469
b12d93d6
YP		 470struct mlx4_promisc_qp {
471 struct list_head list;
472 u32 qpn;
473};
474
475struct mlx4_steer_index {
476 struct list_head list;
477 unsigned int index;
478 struct list_head duplicates;
479};
480
803143fb
MA		 481#define MLX4_EVENT_TYPES_NUM 64
482
623ed84b
JM		 483struct mlx4_slave_state {
484 u8 comm_toggle;
485 u8 last_cmd;
486 u8 init_port_mask;
487 bool active;
488 u8 function;
489 dma_addr_t vhcr_dma;
490 u16 mtu[MLX4_MAX_PORTS + 1];
491 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
492 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
493 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
494 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
803143fb
MA		 495 /* event type to eq number lookup */
496 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
623ed84b
JM		 497 u16 eq_pi;
498 u16 eq_ci;
499 spinlock_t lock;
500 /*initialized via the kzalloc*/
501 u8 is_slave_going_down;
502 u32 cookie;
503};
504
505struct slave_list {
506 struct mutex mutex;
507 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
508};
509
510struct mlx4_resource_tracker {
511 spinlock_t lock;
512 /* tree for each resources */
4af1c048 513 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
623ed84b
JM		 514 /* num_of_slave's lists, one per slave */
515 struct slave_list *slave_list;
516};
517
518#define SLAVE_EVENT_EQ_SIZE 128
519struct mlx4_slave_event_eq {
520 u32 eqn;
521 u32 cons;
522 u32 prod;
523 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
524};
525
526struct mlx4_master_qp0_state {
527 int proxy_qp0_active;
528 int qp0_active;
529 int port_active;
530};
531
532struct mlx4_mfunc_master_ctx {
533 struct mlx4_slave_state *slave_state;
534 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
535 int init_port_ref[MLX4_MAX_PORTS + 1];
536 u16 max_mtu[MLX4_MAX_PORTS + 1];
537 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
538 struct mlx4_resource_tracker res_tracker;
539 struct workqueue_struct *comm_wq;
540 struct work_struct comm_work;
541 struct work_struct slave_event_work;
542 struct work_struct slave_flr_event_work;
543 spinlock_t slave_state_lock;
f5311ac1 544 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 545 struct mlx4_eqe cmd_eqe;
546 struct mlx4_slave_event_eq slave_eq;
547 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
548};
549
550struct mlx4_mfunc {
551 struct mlx4_comm __iomem *comm;
552 struct mlx4_vhcr_cmd *vhcr;
553 dma_addr_t vhcr_dma;
554
555 struct mlx4_mfunc_master_ctx master;
556};
557
225c7b1f
RD		 558struct mlx4_cmd {
559 struct pci_pool *pool;
560 void __iomem *hcr;
561 struct mutex hcr_mutex;
562 struct semaphore poll_sem;
563 struct semaphore event_sem;
623ed84b 564 struct semaphore slave_sem;
225c7b1f
RD		 565 int max_cmds;
566 spinlock_t context_lock;
567 int free_head;
568 struct mlx4_cmd_context *context;
569 u16 token_mask;
570 u8 use_events;
571 u8 toggle;
623ed84b 572 u8 comm_toggle;
225c7b1f
RD		 573};
574
575struct mlx4_uar_table {
576 struct mlx4_bitmap bitmap;
577};
578
579struct mlx4_mr_table {
580 struct mlx4_bitmap mpt_bitmap;
581 struct mlx4_buddy mtt_buddy;
582 u64 mtt_base;
583 u64 mpt_base;
584 struct mlx4_icm_table mtt_table;
585 struct mlx4_icm_table dmpt_table;
586};
587
588struct mlx4_cq_table {
589 struct mlx4_bitmap bitmap;
590 spinlock_t lock;
591 struct radix_tree_root tree;
592 struct mlx4_icm_table table;
593 struct mlx4_icm_table cmpt_table;
594};
595
596struct mlx4_eq_table {
597 struct mlx4_bitmap bitmap;
b8dd786f 598 char *irq_names;
225c7b1f 599 void __iomem *clr_int;
b8dd786f 600 void __iomem **uar_map;
225c7b1f 601 u32 clr_mask;
b8dd786f 602 struct mlx4_eq *eq;
fa0681d2 603 struct mlx4_icm_table table;
225c7b1f
RD		 604 struct mlx4_icm_table cmpt_table;
605 int have_irq;
606 u8 inta_pin;
607};
608
609struct mlx4_srq_table {
610 struct mlx4_bitmap bitmap;
611 spinlock_t lock;
612 struct radix_tree_root tree;
613 struct mlx4_icm_table table;
614 struct mlx4_icm_table cmpt_table;
615};
616
617struct mlx4_qp_table {
618 struct mlx4_bitmap bitmap;
619 u32 rdmarc_base;
620 int rdmarc_shift;
621 spinlock_t lock;
622 struct mlx4_icm_table qp_table;
623 struct mlx4_icm_table auxc_table;
624 struct mlx4_icm_table altc_table;
625 struct mlx4_icm_table rdmarc_table;
626 struct mlx4_icm_table cmpt_table;
627};
628
629struct mlx4_mcg_table {
630 struct mutex mutex;
631 struct mlx4_bitmap bitmap;
632 struct mlx4_icm_table table;
633};
634
635struct mlx4_catas_err {
636 u32 __iomem *map;
ee49bd93
JM		 637 struct timer_list timer;
638 struct list_head list;
225c7b1f
RD		 639};
640
2a2336f8
YP		 641#define MLX4_MAX_MAC_NUM 128
642#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
643
644struct mlx4_mac_table {
645 __be64 entries[MLX4_MAX_MAC_NUM];
646 int refs[MLX4_MAX_MAC_NUM];
647 struct mutex mutex;
648 int total;
649 int max;
650};
651
652#define MLX4_MAX_VLAN_NUM 128
653#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
654
655struct mlx4_vlan_table {
656 __be32 entries[MLX4_MAX_VLAN_NUM];
657 int refs[MLX4_MAX_VLAN_NUM];
658 struct mutex mutex;
659 int total;
660 int max;
661};
662
ffe455ad
EE		 663#define SET_PORT_GEN_ALL_VALID 0x7
664#define SET_PORT_PROMISC_SHIFT 31
665#define SET_PORT_MC_PROMISC_SHIFT 30
666
667enum {
668 MCAST_DIRECT_ONLY = 0,
669 MCAST_DIRECT = 1,
670 MCAST_DEFAULT = 2
671};
672
673
674struct mlx4_set_port_general_context {
675 u8 reserved[3];
676 u8 flags;
677 u16 reserved2;
678 __be16 mtu;
679 u8 pptx;
680 u8 pfctx;
681 u16 reserved3;
682 u8 pprx;
683 u8 pfcrx;
684 u16 reserved4;
685};
686
687struct mlx4_set_port_rqp_calc_context {
688 __be32 base_qpn;
689 u8 rererved;
690 u8 n_mac;
691 u8 n_vlan;
692 u8 n_prio;
693 u8 reserved2[3];
694 u8 mac_miss;
695 u8 intra_no_vlan;
696 u8 no_vlan;
697 u8 intra_vlan_miss;
698 u8 vlan_miss;
699 u8 reserved3[3];
700 u8 no_vlan_prio;
701 __be32 promisc;
702 __be32 mcast;
703};
704
1679200f
YP		 705struct mlx4_mac_entry {
706 u64 mac;
707};
708
2a2336f8
YP		 709struct mlx4_port_info {
710 struct mlx4_dev *dev;
711 int port;
7ff93f8b
YP		 712 char dev_name[16];
713 struct device_attribute port_attr;
714 enum mlx4_port_type tmp_type;
096335b3
OG		 715 char dev_mtu_name[16];
716 struct device_attribute port_mtu_attr;
2a2336f8 717 struct mlx4_mac_table mac_table;
1679200f 718 struct radix_tree_root mac_tree;
2a2336f8 719 struct mlx4_vlan_table vlan_table;
1679200f 720 int base_qpn;
2a2336f8
YP		 721};
722
27bf91d6
YP		 723struct mlx4_sense {
724 struct mlx4_dev *dev;
725 u8 do_sense_port[MLX4_MAX_PORTS + 1];
726 u8 sense_allowed[MLX4_MAX_PORTS + 1];
727 struct delayed_work sense_poll;
728};
729
0b7ca5a9
YP		 730struct mlx4_msix_ctl {
731 u64 pool_bm;
730c41d5 732 struct mutex pool_lock;
0b7ca5a9
YP		 733};
734
b12d93d6
YP		 735struct mlx4_steer {
736 struct list_head promisc_qps[MLX4_NUM_STEERS];
737 struct list_head steer_entries[MLX4_NUM_STEERS];
b12d93d6
YP		 738};
739
225c7b1f
RD		 740struct mlx4_priv {
741 struct mlx4_dev dev;
742
743 struct list_head dev_list;
744 struct list_head ctx_list;
745 spinlock_t ctx_lock;
746
6296883c
YP		 747 struct list_head pgdir_list;
748 struct mutex pgdir_mutex;
749
225c7b1f
RD		 750 struct mlx4_fw fw;
751 struct mlx4_cmd cmd;
623ed84b 752 struct mlx4_mfunc mfunc;
225c7b1f
RD		 753
754 struct mlx4_bitmap pd_bitmap;
012a8ff5 755 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 756 struct mlx4_uar_table uar_table;
757 struct mlx4_mr_table mr_table;
758 struct mlx4_cq_table cq_table;
759 struct mlx4_eq_table eq_table;
760 struct mlx4_srq_table srq_table;
761 struct mlx4_qp_table qp_table;
762 struct mlx4_mcg_table mcg_table;
f2a3f6a3 763 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 764
765 struct mlx4_catas_err catas_err;
766
767 void __iomem *clr_base;
768
769 struct mlx4_uar driver_uar;
770 void __iomem *kar;
2a2336f8 771 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 772 struct mlx4_sense sense;
7ff93f8b 773 struct mutex port_mutex;
0b7ca5a9 774 struct mlx4_msix_ctl msix_ctl;
b12d93d6 775 struct mlx4_steer *steer;
c1b43dca
EC		 776 struct list_head bf_list;
777 struct mutex bf_mutex;
778 struct io_mapping *bf_mapping;
ea51b377 779 int reserved_mtts;
225c7b1f
RD		 780};
781
782static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
783{
784 return container_of(dev, struct mlx4_priv, dev);
785}
786
27bf91d6
YP		 787#define MLX4_SENSE_RANGE (HZ * 3)
788
789extern struct workqueue_struct *mlx4_wq;
790
225c7b1f
RD		 791u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
792void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 793u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
794void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 795u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 796int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
797 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 798void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
799
800int mlx4_reset(struct mlx4_dev *dev);
801
b8dd786f
YP		 802int mlx4_alloc_eq_table(struct mlx4_dev *dev);
803void mlx4_free_eq_table(struct mlx4_dev *dev);
804
225c7b1f 805int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 806int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 807int mlx4_init_uar_table(struct mlx4_dev *dev);
808int mlx4_init_mr_table(struct mlx4_dev *dev);
809int mlx4_init_eq_table(struct mlx4_dev *dev);
810int mlx4_init_cq_table(struct mlx4_dev *dev);
811int mlx4_init_qp_table(struct mlx4_dev *dev);
812int mlx4_init_srq_table(struct mlx4_dev *dev);
813int mlx4_init_mcg_table(struct mlx4_dev *dev);
814
815void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 816void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 817void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
818void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
819void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
820void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
821void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
822void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
823void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 824int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
825void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
826int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
827void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
828int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
829void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
830int __mlx4_mr_reserve(struct mlx4_dev *dev);
831void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
832int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
833void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
834u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
835void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 836
623ed84b
JM		 837int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
838 struct mlx4_vhcr *vhcr,
839 struct mlx4_cmd_mailbox *inbox,
840 struct mlx4_cmd_mailbox *outbox,
841 struct mlx4_cmd_info *cmd);
842int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
843 struct mlx4_vhcr *vhcr,
844 struct mlx4_cmd_mailbox *inbox,
845 struct mlx4_cmd_mailbox *outbox,
846 struct mlx4_cmd_info *cmd);
847int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
848 struct mlx4_vhcr *vhcr,
849 struct mlx4_cmd_mailbox *inbox,
850 struct mlx4_cmd_mailbox *outbox,
851 struct mlx4_cmd_info *cmd);
852int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
853 struct mlx4_vhcr *vhcr,
854 struct mlx4_cmd_mailbox *inbox,
855 struct mlx4_cmd_mailbox *outbox,
856 struct mlx4_cmd_info *cmd);
857int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
858 struct mlx4_vhcr *vhcr,
859 struct mlx4_cmd_mailbox *inbox,
860 struct mlx4_cmd_mailbox *outbox,
861 struct mlx4_cmd_info *cmd);
862int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
863 struct mlx4_vhcr *vhcr,
864 struct mlx4_cmd_mailbox *inbox,
865 struct mlx4_cmd_mailbox *outbox,
866 struct mlx4_cmd_info *cmd);
867int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
868 struct mlx4_vhcr *vhcr,
869 struct mlx4_cmd_mailbox *inbox,
870 struct mlx4_cmd_mailbox *outbox,
871 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 872int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
873 int *base);
874void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
875int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
876void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
877int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
878int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
879 int start_index, int npages, u64 *page_list);
ba062d52
JM		 880int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
881void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
882int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
883void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
623ed84b 884
ee49bd93
JM		 885void mlx4_start_catas_poll(struct mlx4_dev *dev);
886void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 887void mlx4_catas_init(void);
ee49bd93 888int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 889int mlx4_register_device(struct mlx4_dev *dev);
890void mlx4_unregister_device(struct mlx4_dev *dev);
37608eea 891void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
225c7b1f
RD		 892
893struct mlx4_dev_cap;
894struct mlx4_init_hca_param;
895
896u64 mlx4_make_profile(struct mlx4_dev *dev,
897 struct mlx4_profile *request,
898 struct mlx4_dev_cap *dev_cap,
899 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 900void mlx4_master_comm_channel(struct work_struct *work);
901void mlx4_gen_slave_eqe(struct work_struct *work);
902void mlx4_master_handle_slave_flr(struct work_struct *work);
903
904int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
905 struct mlx4_vhcr *vhcr,
906 struct mlx4_cmd_mailbox *inbox,
907 struct mlx4_cmd_mailbox *outbox,
908 struct mlx4_cmd_info *cmd);
909int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
910 struct mlx4_vhcr *vhcr,
911 struct mlx4_cmd_mailbox *inbox,
912 struct mlx4_cmd_mailbox *outbox,
913 struct mlx4_cmd_info *cmd);
914int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
915 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
916 struct mlx4_cmd_mailbox *outbox,
917 struct mlx4_cmd_info *cmd);
918int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
919 struct mlx4_vhcr *vhcr,
920 struct mlx4_cmd_mailbox *inbox,
921 struct mlx4_cmd_mailbox *outbox,
922 struct mlx4_cmd_info *cmd);
923int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
924 struct mlx4_vhcr *vhcr,
925 struct mlx4_cmd_mailbox *inbox,
926 struct mlx4_cmd_mailbox *outbox,
927 struct mlx4_cmd_info *cmd);
928int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
929 struct mlx4_vhcr *vhcr,
930 struct mlx4_cmd_mailbox *inbox,
931 struct mlx4_cmd_mailbox *outbox,
932 struct mlx4_cmd_info *cmd);
933int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
934 struct mlx4_vhcr *vhcr,
935 struct mlx4_cmd_mailbox *inbox,
936 struct mlx4_cmd_mailbox *outbox,
937 struct mlx4_cmd_info *cmd);
938int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
939 struct mlx4_vhcr *vhcr,
940 struct mlx4_cmd_mailbox *inbox,
941 struct mlx4_cmd_mailbox *outbox,
942 struct mlx4_cmd_info *cmd);
943int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
944 struct mlx4_vhcr *vhcr,
945 struct mlx4_cmd_mailbox *inbox,
946 struct mlx4_cmd_mailbox *outbox,
947 struct mlx4_cmd_info *cmd);
948int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
949 struct mlx4_vhcr *vhcr,
950 struct mlx4_cmd_mailbox *inbox,
951 struct mlx4_cmd_mailbox *outbox,
952 struct mlx4_cmd_info *cmd);
953int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
954 struct mlx4_vhcr *vhcr,
955 struct mlx4_cmd_mailbox *inbox,
956 struct mlx4_cmd_mailbox *outbox,
957 struct mlx4_cmd_info *cmd);
958int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
959 struct mlx4_vhcr *vhcr,
960 struct mlx4_cmd_mailbox *inbox,
961 struct mlx4_cmd_mailbox *outbox,
962 struct mlx4_cmd_info *cmd);
963int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd);
968int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
969 struct mlx4_vhcr *vhcr,
970 struct mlx4_cmd_mailbox *inbox,
971 struct mlx4_cmd_mailbox *outbox,
972 struct mlx4_cmd_info *cmd);
973int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
974 struct mlx4_vhcr *vhcr,
975 struct mlx4_cmd_mailbox *inbox,
976 struct mlx4_cmd_mailbox *outbox,
977 struct mlx4_cmd_info *cmd);
978int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
979 struct mlx4_vhcr *vhcr,
980 struct mlx4_cmd_mailbox *inbox,
981 struct mlx4_cmd_mailbox *outbox,
982 struct mlx4_cmd_info *cmd);
983int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
984 struct mlx4_vhcr *vhcr,
985 struct mlx4_cmd_mailbox *inbox,
986 struct mlx4_cmd_mailbox *outbox,
987 struct mlx4_cmd_info *cmd);
988int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
989 struct mlx4_vhcr *vhcr,
990 struct mlx4_cmd_mailbox *inbox,
991 struct mlx4_cmd_mailbox *outbox,
992 struct mlx4_cmd_info *cmd);
993
994int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 995
225c7b1f
RD		 996int mlx4_cmd_init(struct mlx4_dev *dev);
997void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 998int mlx4_multi_func_init(struct mlx4_dev *dev);
999void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 1000void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1001int mlx4_cmd_use_events(struct mlx4_dev *dev);
1002void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1003
ab9c17a0
JM		 1004int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1005 unsigned long timeout);
1006
225c7b1f
RD		 1007void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1008void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1009
1010void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1011
1012void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1013
1014void mlx4_handle_catas_err(struct mlx4_dev *dev);
1015
ab6dc30d
YP		 1016int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1017 enum mlx4_port_type *type);
27bf91d6
YP		 1018void mlx4_do_sense_ports(struct mlx4_dev *dev,
1019 enum mlx4_port_type *stype,
1020 enum mlx4_port_type *defaults);
1021void mlx4_start_sense(struct mlx4_dev *dev);
1022void mlx4_stop_sense(struct mlx4_dev *dev);
1023void mlx4_sense_init(struct mlx4_dev *dev);
1024int mlx4_check_port_params(struct mlx4_dev *dev,
1025 enum mlx4_port_type *port_type);
1026int mlx4_change_port_types(struct mlx4_dev *dev,
1027 enum mlx4_port_type *port_types);
1028
2a2336f8
YP		 1029void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1030void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1031
7ff93f8b 1032int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
623ed84b
JM		 1033/* resource tracker functions*/
1034int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1035 enum mlx4_resource resource_type,
aa1ec3dd 1036 u64 resource_id, int *slave);
623ed84b
JM		 1037void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1038int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1039
b8924951
JM		 1040void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1041 enum mlx4_res_tracker_free_type type);
623ed84b 1042
b91cb3eb
JM		 1043int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1044 struct mlx4_vhcr *vhcr,
1045 struct mlx4_cmd_mailbox *inbox,
1046 struct mlx4_cmd_mailbox *outbox,
1047 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1048int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1049 struct mlx4_vhcr *vhcr,
1050 struct mlx4_cmd_mailbox *inbox,
1051 struct mlx4_cmd_mailbox *outbox,
1052 struct mlx4_cmd_info *cmd);
1053int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1054 struct mlx4_vhcr *vhcr,
1055 struct mlx4_cmd_mailbox *inbox,
1056 struct mlx4_cmd_mailbox *outbox,
1057 struct mlx4_cmd_info *cmd);
1058int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1059 struct mlx4_vhcr *vhcr,
1060 struct mlx4_cmd_mailbox *inbox,
1061 struct mlx4_cmd_mailbox *outbox,
1062 struct mlx4_cmd_info *cmd);
b91cb3eb
JM		 1063int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1064 struct mlx4_vhcr *vhcr,
1065 struct mlx4_cmd_mailbox *inbox,
1066 struct mlx4_cmd_mailbox *outbox,
1067 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1068int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1069 struct mlx4_vhcr *vhcr,
1070 struct mlx4_cmd_mailbox *inbox,
1071 struct mlx4_cmd_mailbox *outbox,
1072 struct mlx4_cmd_info *cmd);
9a5aa622 1073int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
7ff93f8b 1074
623ed84b
JM		 1075
1076int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1077 struct mlx4_vhcr *vhcr,
1078 struct mlx4_cmd_mailbox *inbox,
1079 struct mlx4_cmd_mailbox *outbox,
1080 struct mlx4_cmd_info *cmd);
1081
1082int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1083 struct mlx4_vhcr *vhcr,
1084 struct mlx4_cmd_mailbox *inbox,
1085 struct mlx4_cmd_mailbox *outbox,
1086 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1087int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1088 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1089int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1090 int block_mcast_loopback, enum mlx4_protocol prot,
1091 enum mlx4_steer_type steer);
623ed84b
JM		 1092int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1093 struct mlx4_vhcr *vhcr,
1094 struct mlx4_cmd_mailbox *inbox,
1095 struct mlx4_cmd_mailbox *outbox,
1096 struct mlx4_cmd_info *cmd);
1097int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1098 struct mlx4_vhcr *vhcr,
1099 struct mlx4_cmd_mailbox *inbox,
1100 struct mlx4_cmd_mailbox *outbox,
1101 struct mlx4_cmd_info *cmd);
1102int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1103 int port, void *buf);
1104int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1105 struct mlx4_cmd_mailbox *outbox);
1106int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1107 struct mlx4_vhcr *vhcr,
1108 struct mlx4_cmd_mailbox *inbox,
1109 struct mlx4_cmd_mailbox *outbox,
1110 struct mlx4_cmd_info *cmd);
1111int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1112 struct mlx4_vhcr *vhcr,
1113 struct mlx4_cmd_mailbox *inbox,
1114 struct mlx4_cmd_mailbox *outbox,
1115 struct mlx4_cmd_info *cmd);
1116int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1117 struct mlx4_vhcr *vhcr,
1118 struct mlx4_cmd_mailbox *inbox,
1119 struct mlx4_cmd_mailbox *outbox,
1120 struct mlx4_cmd_info *cmd);
8fcfb4db
HHZ		 1121int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1122 struct mlx4_vhcr *vhcr,
1123 struct mlx4_cmd_mailbox *inbox,
1124 struct mlx4_cmd_mailbox *outbox,
1125 struct mlx4_cmd_info *cmd);
1126int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1127 struct mlx4_vhcr *vhcr,
1128 struct mlx4_cmd_mailbox *inbox,
1129 struct mlx4_cmd_mailbox *outbox,
1130 struct mlx4_cmd_info *cmd);
f5311ac1 1131
0ec2c0f8
EE		 1132int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1133int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1134
5cc914f1
MA		 1135static inline void set_param_l(u64 *arg, u32 val)
1136{
1137 *((u32 *)arg) = val;
1138}
1139
1140static inline void set_param_h(u64 *arg, u32 val)
1141{
1142 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1143}
1144
1145static inline u32 get_param_l(u64 *arg)
1146{
1147 return (u32) (*arg & 0xffffffff);
1148}
1149
1150static inline u32 get_param_h(u64 *arg)
1151{
1152 return (u32)(*arg >> 32);
1153}
1154
c82e9aa0
EC		 1155static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1156{
1157 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1158}
1159
f5311ac1
JM		 1160#define NOT_MASKED_PD_BITS 17
1161
225c7b1f 1162#endif /* MLX4_H */
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