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mlx4_core: Disable memory windows for virtual functions
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
4af1c048 42#include <linux/rbtree.h>
ee49bd93 43#include <linux/timer.h>
3142788b 44#include <linux/semaphore.h>
27bf91d6 45#include <linux/workqueue.h>
225c7b1f
RD		 46
47#include <linux/mlx4/device.h>
37608eea 48#include <linux/mlx4/driver.h>
225c7b1f 49#include <linux/mlx4/doorbell.h>
623ed84b 50#include <linux/mlx4/cmd.h>
225c7b1f
RD		 51
52#define DRV_NAME "mlx4_core"
ab9c17a0 53#define PFX DRV_NAME ": "
7d4b6bcc
YP		 54#define DRV_VERSION "1.1"
55#define DRV_RELDATE "Dec, 2011"
225c7b1f 56
0ff1fb65
HHZ		 57#define MLX4_FS_UDP_UC_EN (1 << 1)
58#define MLX4_FS_TCP_UC_EN (1 << 2)
59#define MLX4_FS_NUM_OF_L2_ADDR 8
60#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61#define MLX4_FS_NUM_MCG (1 << 17)
62
63enum {
64 MLX4_FS_L2_HASH = 0,
65 MLX4_FS_L2_L3_L4_HASH,
66};
67
e5395e92
AV		 68#define MLX4_NUM_UP 8
69#define MLX4_NUM_TC 8
70#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
71#define MLX4_RATELIMIT_DEFAULT 0xffff
72
73struct mlx4_set_port_prio2tc_context {
74 u8 prio2tc[4];
75};
76
77struct mlx4_port_scheduler_tc_cfg_be {
78 __be16 pg;
79 __be16 bw_precentage;
80 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
81 __be16 max_bw_value;
82};
83
84struct mlx4_set_port_scheduler_context {
85 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
86};
87
225c7b1f
RD		 88enum {
89 MLX4_HCR_BASE = 0x80680,
90 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 91 MLX4_CLR_INT_SIZE = 0x00008,
92 MLX4_SLAVE_COMM_BASE = 0x0,
93 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 94};
95
225c7b1f 96enum {
3c439b55
JM		 97 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
98 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
99 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
100 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
0ec2c0f8 101 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 102};
103
225c7b1f
RD		 104enum {
105 MLX4_NUM_PDS = 1 << 15
106};
107
108enum {
109 MLX4_CMPT_TYPE_QP = 0,
110 MLX4_CMPT_TYPE_SRQ = 1,
111 MLX4_CMPT_TYPE_CQ = 2,
112 MLX4_CMPT_TYPE_EQ = 3,
113 MLX4_CMPT_NUM_TYPE
114};
115
116enum {
117 MLX4_CMPT_SHIFT = 24,
118 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
119};
120
b20e519a
SM		 121enum mlx4_mpt_state {
122 MLX4_MPT_DISABLED = 0,
123 MLX4_MPT_EN_HW,
124 MLX4_MPT_EN_SW
623ed84b
JM		 125};
126
127#define MLX4_COMM_TIME 10000
128enum {
129 MLX4_COMM_CMD_RESET,
130 MLX4_COMM_CMD_VHCR0,
131 MLX4_COMM_CMD_VHCR1,
132 MLX4_COMM_CMD_VHCR2,
133 MLX4_COMM_CMD_VHCR_EN,
134 MLX4_COMM_CMD_VHCR_POST,
135 MLX4_COMM_CMD_FLR = 254
136};
137
138/*The flag indicates that the slave should delay the RESET cmd*/
139#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
140/*indicates how many retries will be done if we are in the middle of FLR*/
141#define NUM_OF_RESET_RETRIES 10
142#define SLEEP_TIME_IN_RESET (2 * 1000)
143enum mlx4_resource {
144 RES_QP,
145 RES_CQ,
146 RES_SRQ,
147 RES_XRCD,
148 RES_MPT,
149 RES_MTT,
150 RES_MAC,
151 RES_VLAN,
152 RES_EQ,
153 RES_COUNTER,
1b9c6b06 154 RES_FS_RULE,
623ed84b
JM		 155 MLX4_NUM_OF_RESOURCE_TYPE
156};
157
158enum mlx4_alloc_mode {
159 RES_OP_RESERVE,
160 RES_OP_RESERVE_AND_MAP,
161 RES_OP_MAP_ICM,
162};
163
b8924951
JM		 164enum mlx4_res_tracker_free_type {
165 RES_TR_FREE_ALL,
166 RES_TR_FREE_SLAVES_ONLY,
167 RES_TR_FREE_STRUCTS_ONLY,
168};
623ed84b
JM		 169
170/*
171 *Virtual HCR structures.
172 * mlx4_vhcr is the sw representation, in machine endianess
173 *
174 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
175 * to FW to go through communication channel.
176 * It is big endian, and has the same structure as the physical HCR
177 * used by command interface
178 */
179struct mlx4_vhcr {
180 u64 in_param;
181 u64 out_param;
182 u32 in_modifier;
183 u32 errno;
184 u16 op;
185 u16 token;
186 u8 op_modifier;
187 u8 e_bit;
188};
189
190struct mlx4_vhcr_cmd {
191 __be64 in_param;
192 __be32 in_modifier;
193 __be64 out_param;
194 __be16 token;
195 u16 reserved;
196 u8 status;
197 u8 flags;
198 __be16 opcode;
199};
200
201struct mlx4_cmd_info {
202 u16 opcode;
203 bool has_inbox;
204 bool has_outbox;
205 bool out_is_imm;
206 bool encode_slave_id;
207 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox);
209 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
210 struct mlx4_cmd_mailbox *inbox,
211 struct mlx4_cmd_mailbox *outbox,
212 struct mlx4_cmd_info *cmd);
213};
214
225c7b1f
RD		 215#ifdef CONFIG_MLX4_DEBUG
216extern int mlx4_debug_level;
7b0f5df4
RD		 217#else /* CONFIG_MLX4_DEBUG */
218#define mlx4_debug_level (0)
219#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 220
221#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 222do { \
223 if (mlx4_debug_level) \
224 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
225} while (0)
225c7b1f 226
225c7b1f 227#define mlx4_err(mdev, format, arg...) \
0a645e80 228 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 229#define mlx4_info(mdev, format, arg...) \
0a645e80 230 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 231#define mlx4_warn(mdev, format, arg...) \
0a645e80 232 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 233
0ec2c0f8 234extern int mlx4_log_num_mgm_entry_size;
2b8fb286 235extern int log_mtts_per_seg;
0ec2c0f8 236
623ed84b
JM		 237#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
238#define ALL_SLAVES 0xff
239
225c7b1f
RD		 240struct mlx4_bitmap {
241 u32 last;
242 u32 top;
243 u32 max;
93fc9e1b 244 u32 reserved_top;
225c7b1f 245 u32 mask;
42d1e017 246 u32 avail;
225c7b1f
RD		 247 spinlock_t lock;
248 unsigned long *table;
249};
250
251struct mlx4_buddy {
252 unsigned long **bits;
e4044cfc 253 unsigned int *num_free;
3de819e6 254 u32 max_order;
225c7b1f
RD		 255 spinlock_t lock;
256};
257
258struct mlx4_icm;
259
260struct mlx4_icm_table {
261 u64 virt;
262 int num_icm;
3de819e6 263 u32 num_obj;
225c7b1f
RD		 264 int obj_size;
265 int lowmem;
5b0bf5e2 266 int coherent;
225c7b1f
RD		 267 struct mutex mutex;
268 struct mlx4_icm **icm;
269};
270
cc1ade94
SM		 271#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
272#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
273#define MLX4_MPT_FLAG_MIO (1 << 17)
274#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
275#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
276#define MLX4_MPT_FLAG_REGION (1 << 8)
277
278#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
279#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
280#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
281
282#define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
283
284#define MLX4_MPT_STATUS_SW 0xF0
285#define MLX4_MPT_STATUS_HW 0x00
286
c82e9aa0
EC		 287/*
288 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
289 */
290struct mlx4_mpt_entry {
291 __be32 flags;
292 __be32 qpn;
293 __be32 key;
294 __be32 pd_flags;
295 __be64 start;
296 __be64 length;
297 __be32 lkey;
298 __be32 win_cnt;
299 u8 reserved1[3];
300 u8 mtt_rep;
2b8fb286 301 __be64 mtt_addr;
c82e9aa0
EC		 302 __be32 mtt_sz;
303 __be32 entity_size;
304 __be32 first_byte_offset;
305} __packed;
306
307/*
308 * Must be packed because start is 64 bits but only aligned to 32 bits.
309 */
310struct mlx4_eq_context {
311 __be32 flags;
312 u16 reserved1[3];
313 __be16 page_offset;
314 u8 log_eq_size;
315 u8 reserved2[4];
316 u8 eq_period;
317 u8 reserved3;
318 u8 eq_max_count;
319 u8 reserved4[3];
320 u8 intr;
321 u8 log_page_size;
322 u8 reserved5[2];
323 u8 mtt_base_addr_h;
324 __be32 mtt_base_addr_l;
325 u32 reserved6[2];
326 __be32 consumer_index;
327 __be32 producer_index;
328 u32 reserved7[4];
329};
330
331struct mlx4_cq_context {
332 __be32 flags;
333 u16 reserved1[3];
334 __be16 page_offset;
335 __be32 logsize_usrpage;
336 __be16 cq_period;
337 __be16 cq_max_count;
338 u8 reserved2[3];
339 u8 comp_eqn;
340 u8 log_page_size;
341 u8 reserved3[2];
342 u8 mtt_base_addr_h;
343 __be32 mtt_base_addr_l;
344 __be32 last_notified_index;
345 __be32 solicit_producer_index;
346 __be32 consumer_index;
347 __be32 producer_index;
348 u32 reserved4[2];
349 __be64 db_rec_addr;
350};
351
352struct mlx4_srq_context {
353 __be32 state_logsize_srqn;
354 u8 logstride;
355 u8 reserved1;
356 __be16 xrcd;
357 __be32 pg_offset_cqn;
358 u32 reserved2;
359 u8 log_page_size;
360 u8 reserved3[2];
361 u8 mtt_base_addr_h;
362 __be32 mtt_base_addr_l;
363 __be32 pd;
364 __be16 limit_watermark;
365 __be16 wqe_cnt;
366 u16 reserved4;
367 __be16 wqe_counter;
368 u32 reserved5;
369 __be64 db_rec_addr;
370};
371
225c7b1f
RD		 372struct mlx4_eq {
373 struct mlx4_dev *dev;
374 void __iomem *doorbell;
375 int eqn;
376 u32 cons_index;
377 u16 irq;
378 u16 have_irq;
379 int nent;
380 struct mlx4_buf_list *page_list;
381 struct mlx4_mtt mtt;
382};
383
623ed84b
JM		 384struct mlx4_slave_eqe {
385 u8 type;
386 u8 port;
387 u32 param;
388};
389
390struct mlx4_slave_event_eq_info {
803143fb 391 int eqn;
623ed84b 392 u16 token;
623ed84b
JM		 393};
394
225c7b1f
RD		 395struct mlx4_profile {
396 int num_qp;
397 int rdmarc_per_qp;
398 int num_srq;
399 int num_cq;
400 int num_mcg;
401 int num_mpt;
db5a7a65 402 unsigned num_mtt;
225c7b1f
RD		 403};
404
405struct mlx4_fw {
406 u64 clr_int_base;
407 u64 catas_offset;
623ed84b 408 u64 comm_base;
225c7b1f
RD		 409 struct mlx4_icm *fw_icm;
410 struct mlx4_icm *aux_icm;
411 u32 catas_size;
412 u16 fw_pages;
413 u8 clr_int_bar;
414 u8 catas_bar;
623ed84b
JM		 415 u8 comm_bar;
416};
417
418struct mlx4_comm {
419 u32 slave_write;
420 u32 slave_read;
225c7b1f
RD		 421};
422
ffe455ad
EE		 423enum {
424 MLX4_MCAST_CONFIG = 0,
425 MLX4_MCAST_DISABLE = 1,
426 MLX4_MCAST_ENABLE = 2,
427};
428
623ed84b
JM		 429#define VLAN_FLTR_SIZE 128
430
431struct mlx4_vlan_fltr {
432 __be32 entry[VLAN_FLTR_SIZE];
433};
434
ffe455ad
EE		 435struct mlx4_mcast_entry {
436 struct list_head list;
437 u64 addr;
438};
439
b12d93d6
YP		 440struct mlx4_promisc_qp {
441 struct list_head list;
442 u32 qpn;
443};
444
445struct mlx4_steer_index {
446 struct list_head list;
447 unsigned int index;
448 struct list_head duplicates;
449};
450
803143fb
MA		 451#define MLX4_EVENT_TYPES_NUM 64
452
623ed84b
JM		 453struct mlx4_slave_state {
454 u8 comm_toggle;
455 u8 last_cmd;
456 u8 init_port_mask;
457 bool active;
458 u8 function;
459 dma_addr_t vhcr_dma;
460 u16 mtu[MLX4_MAX_PORTS + 1];
461 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
462 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
463 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
464 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
803143fb
MA		 465 /* event type to eq number lookup */
466 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
623ed84b
JM		 467 u16 eq_pi;
468 u16 eq_ci;
469 spinlock_t lock;
470 /*initialized via the kzalloc*/
471 u8 is_slave_going_down;
472 u32 cookie;
993c401e 473 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
623ed84b
JM		 474};
475
476struct slave_list {
477 struct mutex mutex;
478 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
479};
480
481struct mlx4_resource_tracker {
482 spinlock_t lock;
483 /* tree for each resources */
4af1c048 484 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
623ed84b
JM		 485 /* num_of_slave's lists, one per slave */
486 struct slave_list *slave_list;
487};
488
489#define SLAVE_EVENT_EQ_SIZE 128
490struct mlx4_slave_event_eq {
491 u32 eqn;
492 u32 cons;
493 u32 prod;
992e8e6e 494 spinlock_t event_lock;
623ed84b
JM		 495 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
496};
497
498struct mlx4_master_qp0_state {
499 int proxy_qp0_active;
500 int qp0_active;
501 int port_active;
502};
503
504struct mlx4_mfunc_master_ctx {
505 struct mlx4_slave_state *slave_state;
506 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
507 int init_port_ref[MLX4_MAX_PORTS + 1];
508 u16 max_mtu[MLX4_MAX_PORTS + 1];
509 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
510 struct mlx4_resource_tracker res_tracker;
511 struct workqueue_struct *comm_wq;
512 struct work_struct comm_work;
513 struct work_struct slave_event_work;
514 struct work_struct slave_flr_event_work;
515 spinlock_t slave_state_lock;
f5311ac1 516 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 517 struct mlx4_eqe cmd_eqe;
518 struct mlx4_slave_event_eq slave_eq;
519 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
520};
521
522struct mlx4_mfunc {
523 struct mlx4_comm __iomem *comm;
524 struct mlx4_vhcr_cmd *vhcr;
525 dma_addr_t vhcr_dma;
526
527 struct mlx4_mfunc_master_ctx master;
528};
529
225c7b1f
RD		 530struct mlx4_cmd {
531 struct pci_pool *pool;
532 void __iomem *hcr;
533 struct mutex hcr_mutex;
f3d4c89e 534 struct mutex slave_cmd_mutex;
225c7b1f
RD		 535 struct semaphore poll_sem;
536 struct semaphore event_sem;
537 int max_cmds;
538 spinlock_t context_lock;
539 int free_head;
540 struct mlx4_cmd_context *context;
541 u16 token_mask;
542 u8 use_events;
543 u8 toggle;
623ed84b 544 u8 comm_toggle;
225c7b1f
RD		 545};
546
547struct mlx4_uar_table {
548 struct mlx4_bitmap bitmap;
549};
550
551struct mlx4_mr_table {
552 struct mlx4_bitmap mpt_bitmap;
553 struct mlx4_buddy mtt_buddy;
554 u64 mtt_base;
555 u64 mpt_base;
556 struct mlx4_icm_table mtt_table;
557 struct mlx4_icm_table dmpt_table;
558};
559
560struct mlx4_cq_table {
561 struct mlx4_bitmap bitmap;
562 spinlock_t lock;
563 struct radix_tree_root tree;
564 struct mlx4_icm_table table;
565 struct mlx4_icm_table cmpt_table;
566};
567
568struct mlx4_eq_table {
569 struct mlx4_bitmap bitmap;
b8dd786f 570 char *irq_names;
225c7b1f 571 void __iomem *clr_int;
b8dd786f 572 void __iomem **uar_map;
225c7b1f 573 u32 clr_mask;
b8dd786f 574 struct mlx4_eq *eq;
fa0681d2 575 struct mlx4_icm_table table;
225c7b1f
RD		 576 struct mlx4_icm_table cmpt_table;
577 int have_irq;
578 u8 inta_pin;
579};
580
581struct mlx4_srq_table {
582 struct mlx4_bitmap bitmap;
583 spinlock_t lock;
584 struct radix_tree_root tree;
585 struct mlx4_icm_table table;
586 struct mlx4_icm_table cmpt_table;
587};
588
589struct mlx4_qp_table {
590 struct mlx4_bitmap bitmap;
591 u32 rdmarc_base;
592 int rdmarc_shift;
593 spinlock_t lock;
594 struct mlx4_icm_table qp_table;
595 struct mlx4_icm_table auxc_table;
596 struct mlx4_icm_table altc_table;
597 struct mlx4_icm_table rdmarc_table;
598 struct mlx4_icm_table cmpt_table;
599};
600
601struct mlx4_mcg_table {
602 struct mutex mutex;
603 struct mlx4_bitmap bitmap;
604 struct mlx4_icm_table table;
605};
606
607struct mlx4_catas_err {
608 u32 __iomem *map;
ee49bd93
JM		 609 struct timer_list timer;
610 struct list_head list;
225c7b1f
RD		 611};
612
2a2336f8
YP		 613#define MLX4_MAX_MAC_NUM 128
614#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
615
616struct mlx4_mac_table {
617 __be64 entries[MLX4_MAX_MAC_NUM];
618 int refs[MLX4_MAX_MAC_NUM];
619 struct mutex mutex;
620 int total;
621 int max;
622};
623
624#define MLX4_MAX_VLAN_NUM 128
625#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
626
627struct mlx4_vlan_table {
628 __be32 entries[MLX4_MAX_VLAN_NUM];
629 int refs[MLX4_MAX_VLAN_NUM];
630 struct mutex mutex;
631 int total;
632 int max;
633};
634
ffe455ad
EE		 635#define SET_PORT_GEN_ALL_VALID 0x7
636#define SET_PORT_PROMISC_SHIFT 31
637#define SET_PORT_MC_PROMISC_SHIFT 30
638
639enum {
640 MCAST_DIRECT_ONLY = 0,
641 MCAST_DIRECT = 1,
642 MCAST_DEFAULT = 2
643};
644
645
646struct mlx4_set_port_general_context {
647 u8 reserved[3];
648 u8 flags;
649 u16 reserved2;
650 __be16 mtu;
651 u8 pptx;
652 u8 pfctx;
653 u16 reserved3;
654 u8 pprx;
655 u8 pfcrx;
656 u16 reserved4;
657};
658
659struct mlx4_set_port_rqp_calc_context {
660 __be32 base_qpn;
661 u8 rererved;
662 u8 n_mac;
663 u8 n_vlan;
664 u8 n_prio;
665 u8 reserved2[3];
666 u8 mac_miss;
667 u8 intra_no_vlan;
668 u8 no_vlan;
669 u8 intra_vlan_miss;
670 u8 vlan_miss;
671 u8 reserved3[3];
672 u8 no_vlan_prio;
673 __be32 promisc;
674 __be32 mcast;
675};
676
1679200f
YP		 677struct mlx4_mac_entry {
678 u64 mac;
0ff1fb65 679 u64 reg_id;
1679200f
YP		 680};
681
2a2336f8
YP		 682struct mlx4_port_info {
683 struct mlx4_dev *dev;
684 int port;
7ff93f8b
YP		 685 char dev_name[16];
686 struct device_attribute port_attr;
687 enum mlx4_port_type tmp_type;
096335b3
OG		 688 char dev_mtu_name[16];
689 struct device_attribute port_mtu_attr;
2a2336f8 690 struct mlx4_mac_table mac_table;
1679200f 691 struct radix_tree_root mac_tree;
2a2336f8 692 struct mlx4_vlan_table vlan_table;
1679200f 693 int base_qpn;
2a2336f8
YP		 694};
695
27bf91d6
YP		 696struct mlx4_sense {
697 struct mlx4_dev *dev;
698 u8 do_sense_port[MLX4_MAX_PORTS + 1];
699 u8 sense_allowed[MLX4_MAX_PORTS + 1];
700 struct delayed_work sense_poll;
701};
702
0b7ca5a9
YP		 703struct mlx4_msix_ctl {
704 u64 pool_bm;
730c41d5 705 struct mutex pool_lock;
0b7ca5a9
YP		 706};
707
b12d93d6
YP		 708struct mlx4_steer {
709 struct list_head promisc_qps[MLX4_NUM_STEERS];
710 struct list_head steer_entries[MLX4_NUM_STEERS];
b12d93d6
YP		 711};
712
a8edc3bf
HHZ		 713struct mlx4_net_trans_rule_hw_ctrl {
714 __be32 ctrl;
715 __be32 vf_vep_port;
716 __be32 qpn;
717 __be32 reserved;
718};
719
720struct mlx4_net_trans_rule_hw_ib {
721 u8 size;
722 u8 rsvd1;
723 __be16 id;
724 u32 rsvd2;
725 __be32 qpn;
726 __be32 qpn_mask;
727 u8 dst_gid[16];
728 u8 dst_gid_msk[16];
729} __packed;
730
731struct mlx4_net_trans_rule_hw_eth {
732 u8 size;
733 u8 rsvd;
734 __be16 id;
735 u8 rsvd1[6];
736 u8 dst_mac[6];
737 u16 rsvd2;
738 u8 dst_mac_msk[6];
739 u16 rsvd3;
740 u8 src_mac[6];
741 u16 rsvd4;
742 u8 src_mac_msk[6];
743 u8 rsvd5;
744 u8 ether_type_enable;
745 __be16 ether_type;
746 __be16 vlan_id_msk;
747 __be16 vlan_id;
748} __packed;
749
750struct mlx4_net_trans_rule_hw_tcp_udp {
751 u8 size;
752 u8 rsvd;
753 __be16 id;
754 __be16 rsvd1[3];
755 __be16 dst_port;
756 __be16 rsvd2;
757 __be16 dst_port_msk;
758 __be16 rsvd3;
759 __be16 src_port;
760 __be16 rsvd4;
761 __be16 src_port_msk;
762} __packed;
763
764struct mlx4_net_trans_rule_hw_ipv4 {
765 u8 size;
766 u8 rsvd;
767 __be16 id;
768 __be32 rsvd1;
769 __be32 dst_ip;
770 __be32 dst_ip_msk;
771 __be32 src_ip;
772 __be32 src_ip_msk;
773} __packed;
774
775struct _rule_hw {
776 union {
777 struct {
778 u8 size;
779 u8 rsvd;
780 __be16 id;
781 };
782 struct mlx4_net_trans_rule_hw_eth eth;
783 struct mlx4_net_trans_rule_hw_ib ib;
784 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
785 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
786 };
787};
788
839f1243
RD		 789enum {
790 MLX4_PCI_DEV_IS_VF = 1 << 0,
ca3e57a5 791 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
839f1243
RD		 792};
793
225c7b1f
RD		 794struct mlx4_priv {
795 struct mlx4_dev dev;
796
797 struct list_head dev_list;
798 struct list_head ctx_list;
799 spinlock_t ctx_lock;
800
839f1243
RD		 801 int pci_dev_data;
802
6296883c
YP		 803 struct list_head pgdir_list;
804 struct mutex pgdir_mutex;
805
225c7b1f
RD		 806 struct mlx4_fw fw;
807 struct mlx4_cmd cmd;
623ed84b 808 struct mlx4_mfunc mfunc;
225c7b1f
RD		 809
810 struct mlx4_bitmap pd_bitmap;
012a8ff5 811 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 812 struct mlx4_uar_table uar_table;
813 struct mlx4_mr_table mr_table;
814 struct mlx4_cq_table cq_table;
815 struct mlx4_eq_table eq_table;
816 struct mlx4_srq_table srq_table;
817 struct mlx4_qp_table qp_table;
818 struct mlx4_mcg_table mcg_table;
f2a3f6a3 819 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 820
821 struct mlx4_catas_err catas_err;
822
823 void __iomem *clr_base;
824
825 struct mlx4_uar driver_uar;
826 void __iomem *kar;
2a2336f8 827 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 828 struct mlx4_sense sense;
7ff93f8b 829 struct mutex port_mutex;
0b7ca5a9 830 struct mlx4_msix_ctl msix_ctl;
b12d93d6 831 struct mlx4_steer *steer;
c1b43dca
EC		 832 struct list_head bf_list;
833 struct mutex bf_mutex;
834 struct io_mapping *bf_mapping;
ea51b377 835 int reserved_mtts;
0ff1fb65 836 int fs_hash_mode;
54679e14 837 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
afa8fd1d 838 __be64 slave_node_guids[MLX4_MFUNC_MAX];
54679e14 839
225c7b1f
RD		 840};
841
842static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
843{
844 return container_of(dev, struct mlx4_priv, dev);
845}
846
27bf91d6
YP		 847#define MLX4_SENSE_RANGE (HZ * 3)
848
849extern struct workqueue_struct *mlx4_wq;
850
225c7b1f
RD		 851u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
852void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 853u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
854void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 855u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 856int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
857 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 858void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
859
860int mlx4_reset(struct mlx4_dev *dev);
861
b8dd786f
YP		 862int mlx4_alloc_eq_table(struct mlx4_dev *dev);
863void mlx4_free_eq_table(struct mlx4_dev *dev);
864
225c7b1f 865int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 866int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 867int mlx4_init_uar_table(struct mlx4_dev *dev);
868int mlx4_init_mr_table(struct mlx4_dev *dev);
869int mlx4_init_eq_table(struct mlx4_dev *dev);
870int mlx4_init_cq_table(struct mlx4_dev *dev);
871int mlx4_init_qp_table(struct mlx4_dev *dev);
872int mlx4_init_srq_table(struct mlx4_dev *dev);
873int mlx4_init_mcg_table(struct mlx4_dev *dev);
874
875void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 876void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 877void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
878void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
879void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
880void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
881void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
882void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
883void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 884int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
885void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
886int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
887void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
888int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
889void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
b20e519a
SM		 890int __mlx4_mpt_reserve(struct mlx4_dev *dev);
891void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
892int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
893void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
c82e9aa0
EC		 894u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
895void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 896
623ed84b
JM		 897int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
898 struct mlx4_vhcr *vhcr,
899 struct mlx4_cmd_mailbox *inbox,
900 struct mlx4_cmd_mailbox *outbox,
901 struct mlx4_cmd_info *cmd);
902int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
903 struct mlx4_vhcr *vhcr,
904 struct mlx4_cmd_mailbox *inbox,
905 struct mlx4_cmd_mailbox *outbox,
906 struct mlx4_cmd_info *cmd);
907int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
908 struct mlx4_vhcr *vhcr,
909 struct mlx4_cmd_mailbox *inbox,
910 struct mlx4_cmd_mailbox *outbox,
911 struct mlx4_cmd_info *cmd);
912int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
913 struct mlx4_vhcr *vhcr,
914 struct mlx4_cmd_mailbox *inbox,
915 struct mlx4_cmd_mailbox *outbox,
916 struct mlx4_cmd_info *cmd);
917int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
918 struct mlx4_vhcr *vhcr,
919 struct mlx4_cmd_mailbox *inbox,
920 struct mlx4_cmd_mailbox *outbox,
921 struct mlx4_cmd_info *cmd);
922int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
923 struct mlx4_vhcr *vhcr,
924 struct mlx4_cmd_mailbox *inbox,
925 struct mlx4_cmd_mailbox *outbox,
926 struct mlx4_cmd_info *cmd);
927int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
928 struct mlx4_vhcr *vhcr,
929 struct mlx4_cmd_mailbox *inbox,
930 struct mlx4_cmd_mailbox *outbox,
931 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 932int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
933 int *base);
934void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
935int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
936void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
937int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
938int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
939 int start_index, int npages, u64 *page_list);
ba062d52
JM		 940int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
941void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
942int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
943void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
623ed84b 944
ee49bd93
JM		 945void mlx4_start_catas_poll(struct mlx4_dev *dev);
946void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 947void mlx4_catas_init(void);
ee49bd93 948int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 949int mlx4_register_device(struct mlx4_dev *dev);
950void mlx4_unregister_device(struct mlx4_dev *dev);
00f5ce99
JM		 951void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
952 unsigned long param);
225c7b1f
RD		 953
954struct mlx4_dev_cap;
955struct mlx4_init_hca_param;
956
957u64 mlx4_make_profile(struct mlx4_dev *dev,
958 struct mlx4_profile *request,
959 struct mlx4_dev_cap *dev_cap,
960 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 961void mlx4_master_comm_channel(struct work_struct *work);
962void mlx4_gen_slave_eqe(struct work_struct *work);
963void mlx4_master_handle_slave_flr(struct work_struct *work);
964
965int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
966 struct mlx4_vhcr *vhcr,
967 struct mlx4_cmd_mailbox *inbox,
968 struct mlx4_cmd_mailbox *outbox,
969 struct mlx4_cmd_info *cmd);
970int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
971 struct mlx4_vhcr *vhcr,
972 struct mlx4_cmd_mailbox *inbox,
973 struct mlx4_cmd_mailbox *outbox,
974 struct mlx4_cmd_info *cmd);
975int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
976 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
977 struct mlx4_cmd_mailbox *outbox,
978 struct mlx4_cmd_info *cmd);
979int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
980 struct mlx4_vhcr *vhcr,
981 struct mlx4_cmd_mailbox *inbox,
982 struct mlx4_cmd_mailbox *outbox,
983 struct mlx4_cmd_info *cmd);
984int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
985 struct mlx4_vhcr *vhcr,
986 struct mlx4_cmd_mailbox *inbox,
987 struct mlx4_cmd_mailbox *outbox,
988 struct mlx4_cmd_info *cmd);
989int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
990 struct mlx4_vhcr *vhcr,
991 struct mlx4_cmd_mailbox *inbox,
992 struct mlx4_cmd_mailbox *outbox,
993 struct mlx4_cmd_info *cmd);
994int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
995 struct mlx4_vhcr *vhcr,
996 struct mlx4_cmd_mailbox *inbox,
997 struct mlx4_cmd_mailbox *outbox,
998 struct mlx4_cmd_info *cmd);
999int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1000 struct mlx4_vhcr *vhcr,
1001 struct mlx4_cmd_mailbox *inbox,
1002 struct mlx4_cmd_mailbox *outbox,
1003 struct mlx4_cmd_info *cmd);
1004int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1005 struct mlx4_vhcr *vhcr,
1006 struct mlx4_cmd_mailbox *inbox,
1007 struct mlx4_cmd_mailbox *outbox,
1008 struct mlx4_cmd_info *cmd);
1009int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1010 struct mlx4_vhcr *vhcr,
1011 struct mlx4_cmd_mailbox *inbox,
1012 struct mlx4_cmd_mailbox *outbox,
1013 struct mlx4_cmd_info *cmd);
1014int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1015 struct mlx4_vhcr *vhcr,
1016 struct mlx4_cmd_mailbox *inbox,
1017 struct mlx4_cmd_mailbox *outbox,
1018 struct mlx4_cmd_info *cmd);
1019int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1020 struct mlx4_vhcr *vhcr,
1021 struct mlx4_cmd_mailbox *inbox,
1022 struct mlx4_cmd_mailbox *outbox,
1023 struct mlx4_cmd_info *cmd);
1024int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1025 struct mlx4_vhcr *vhcr,
1026 struct mlx4_cmd_mailbox *inbox,
1027 struct mlx4_cmd_mailbox *outbox,
1028 struct mlx4_cmd_info *cmd);
1029int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1030 struct mlx4_vhcr *vhcr,
1031 struct mlx4_cmd_mailbox *inbox,
1032 struct mlx4_cmd_mailbox *outbox,
1033 struct mlx4_cmd_info *cmd);
1034int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1035 struct mlx4_vhcr *vhcr,
1036 struct mlx4_cmd_mailbox *inbox,
1037 struct mlx4_cmd_mailbox *outbox,
1038 struct mlx4_cmd_info *cmd);
1039int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1040 struct mlx4_vhcr *vhcr,
1041 struct mlx4_cmd_mailbox *inbox,
1042 struct mlx4_cmd_mailbox *outbox,
1043 struct mlx4_cmd_info *cmd);
54679e14
JM		 1044int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1045 struct mlx4_vhcr *vhcr,
1046 struct mlx4_cmd_mailbox *inbox,
1047 struct mlx4_cmd_mailbox *outbox,
1048 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1049int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1050 struct mlx4_vhcr *vhcr,
1051 struct mlx4_cmd_mailbox *inbox,
1052 struct mlx4_cmd_mailbox *outbox,
1053 struct mlx4_cmd_info *cmd);
54679e14
JM		 1054int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1055 struct mlx4_vhcr *vhcr,
1056 struct mlx4_cmd_mailbox *inbox,
1057 struct mlx4_cmd_mailbox *outbox,
1058 struct mlx4_cmd_info *cmd);
1059int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1060 struct mlx4_vhcr *vhcr,
1061 struct mlx4_cmd_mailbox *inbox,
1062 struct mlx4_cmd_mailbox *outbox,
1063 struct mlx4_cmd_info *cmd);
1064int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1065 struct mlx4_vhcr *vhcr,
1066 struct mlx4_cmd_mailbox *inbox,
1067 struct mlx4_cmd_mailbox *outbox,
1068 struct mlx4_cmd_info *cmd);
1069int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1070 struct mlx4_vhcr *vhcr,
1071 struct mlx4_cmd_mailbox *inbox,
1072 struct mlx4_cmd_mailbox *outbox,
1073 struct mlx4_cmd_info *cmd);
1074int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1075 struct mlx4_vhcr *vhcr,
1076 struct mlx4_cmd_mailbox *inbox,
1077 struct mlx4_cmd_mailbox *outbox,
1078 struct mlx4_cmd_info *cmd);
1079int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1080 struct mlx4_vhcr *vhcr,
1081 struct mlx4_cmd_mailbox *inbox,
1082 struct mlx4_cmd_mailbox *outbox,
1083 struct mlx4_cmd_info *cmd);
1084int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1085 struct mlx4_vhcr *vhcr,
1086 struct mlx4_cmd_mailbox *inbox,
1087 struct mlx4_cmd_mailbox *outbox,
1088 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1089int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1090 struct mlx4_vhcr *vhcr,
1091 struct mlx4_cmd_mailbox *inbox,
1092 struct mlx4_cmd_mailbox *outbox,
1093 struct mlx4_cmd_info *cmd);
54679e14
JM		 1094int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1095 struct mlx4_vhcr *vhcr,
1096 struct mlx4_cmd_mailbox *inbox,
1097 struct mlx4_cmd_mailbox *outbox,
1098 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1099
1100int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 1101
225c7b1f
RD		 1102int mlx4_cmd_init(struct mlx4_dev *dev);
1103void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 1104int mlx4_multi_func_init(struct mlx4_dev *dev);
1105void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 1106void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1107int mlx4_cmd_use_events(struct mlx4_dev *dev);
1108void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1109
ab9c17a0
JM		 1110int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1111 unsigned long timeout);
1112
225c7b1f
RD		 1113void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1114void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1115
1116void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1117
1118void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1119
1120void mlx4_handle_catas_err(struct mlx4_dev *dev);
1121
ab6dc30d
YP		 1122int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1123 enum mlx4_port_type *type);
27bf91d6
YP		 1124void mlx4_do_sense_ports(struct mlx4_dev *dev,
1125 enum mlx4_port_type *stype,
1126 enum mlx4_port_type *defaults);
1127void mlx4_start_sense(struct mlx4_dev *dev);
1128void mlx4_stop_sense(struct mlx4_dev *dev);
1129void mlx4_sense_init(struct mlx4_dev *dev);
1130int mlx4_check_port_params(struct mlx4_dev *dev,
1131 enum mlx4_port_type *port_type);
1132int mlx4_change_port_types(struct mlx4_dev *dev,
1133 enum mlx4_port_type *port_types);
1134
2a2336f8
YP		 1135void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1136void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1137
6634961c 1138int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
623ed84b
JM		 1139/* resource tracker functions*/
1140int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1141 enum mlx4_resource resource_type,
aa1ec3dd 1142 u64 resource_id, int *slave);
623ed84b
JM		 1143void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1144int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1145
b8924951
JM		 1146void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1147 enum mlx4_res_tracker_free_type type);
623ed84b 1148
b91cb3eb
JM		 1149int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1150 struct mlx4_vhcr *vhcr,
1151 struct mlx4_cmd_mailbox *inbox,
1152 struct mlx4_cmd_mailbox *outbox,
1153 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1154int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1155 struct mlx4_vhcr *vhcr,
1156 struct mlx4_cmd_mailbox *inbox,
1157 struct mlx4_cmd_mailbox *outbox,
1158 struct mlx4_cmd_info *cmd);
1159int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1160 struct mlx4_vhcr *vhcr,
1161 struct mlx4_cmd_mailbox *inbox,
1162 struct mlx4_cmd_mailbox *outbox,
1163 struct mlx4_cmd_info *cmd);
1164int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1165 struct mlx4_vhcr *vhcr,
1166 struct mlx4_cmd_mailbox *inbox,
1167 struct mlx4_cmd_mailbox *outbox,
1168 struct mlx4_cmd_info *cmd);
b91cb3eb
JM		 1169int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1170 struct mlx4_vhcr *vhcr,
1171 struct mlx4_cmd_mailbox *inbox,
1172 struct mlx4_cmd_mailbox *outbox,
1173 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1174int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1175 struct mlx4_vhcr *vhcr,
1176 struct mlx4_cmd_mailbox *inbox,
1177 struct mlx4_cmd_mailbox *outbox,
1178 struct mlx4_cmd_info *cmd);
9a5aa622 1179int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
7ff93f8b 1180
6634961c
JM		 1181int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1182 int *gid_tbl_len, int *pkey_tbl_len);
623ed84b
JM		 1183
1184int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1185 struct mlx4_vhcr *vhcr,
1186 struct mlx4_cmd_mailbox *inbox,
1187 struct mlx4_cmd_mailbox *outbox,
1188 struct mlx4_cmd_info *cmd);
1189
1190int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1191 struct mlx4_vhcr *vhcr,
1192 struct mlx4_cmd_mailbox *inbox,
1193 struct mlx4_cmd_mailbox *outbox,
1194 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1195int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1196 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1197int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1198 int block_mcast_loopback, enum mlx4_protocol prot,
1199 enum mlx4_steer_type steer);
623ed84b
JM		 1200int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1201 struct mlx4_vhcr *vhcr,
1202 struct mlx4_cmd_mailbox *inbox,
1203 struct mlx4_cmd_mailbox *outbox,
1204 struct mlx4_cmd_info *cmd);
1205int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1206 struct mlx4_vhcr *vhcr,
1207 struct mlx4_cmd_mailbox *inbox,
1208 struct mlx4_cmd_mailbox *outbox,
1209 struct mlx4_cmd_info *cmd);
1210int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1211 int port, void *buf);
1212int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1213 struct mlx4_cmd_mailbox *outbox);
1214int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1215 struct mlx4_vhcr *vhcr,
1216 struct mlx4_cmd_mailbox *inbox,
1217 struct mlx4_cmd_mailbox *outbox,
1218 struct mlx4_cmd_info *cmd);
1219int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1220 struct mlx4_vhcr *vhcr,
1221 struct mlx4_cmd_mailbox *inbox,
1222 struct mlx4_cmd_mailbox *outbox,
1223 struct mlx4_cmd_info *cmd);
1224int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1225 struct mlx4_vhcr *vhcr,
1226 struct mlx4_cmd_mailbox *inbox,
1227 struct mlx4_cmd_mailbox *outbox,
1228 struct mlx4_cmd_info *cmd);
8fcfb4db
HHZ		 1229int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1230 struct mlx4_vhcr *vhcr,
1231 struct mlx4_cmd_mailbox *inbox,
1232 struct mlx4_cmd_mailbox *outbox,
1233 struct mlx4_cmd_info *cmd);
1234int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1235 struct mlx4_vhcr *vhcr,
1236 struct mlx4_cmd_mailbox *inbox,
1237 struct mlx4_cmd_mailbox *outbox,
1238 struct mlx4_cmd_info *cmd);
f5311ac1 1239
0ec2c0f8
EE		 1240int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1241int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1242
5cc914f1
MA		 1243static inline void set_param_l(u64 *arg, u32 val)
1244{
1245 *((u32 *)arg) = val;
1246}
1247
1248static inline void set_param_h(u64 *arg, u32 val)
1249{
1250 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1251}
1252
1253static inline u32 get_param_l(u64 *arg)
1254{
1255 return (u32) (*arg & 0xffffffff);
1256}
1257
1258static inline u32 get_param_h(u64 *arg)
1259{
1260 return (u32)(*arg >> 32);
1261}
1262
c82e9aa0
EC		 1263static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1264{
1265 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1266}
1267
f5311ac1
JM		 1268#define NOT_MASKED_PD_BITS 17
1269
225c7b1f 1270#endif /* MLX4_H */
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