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net/mlx4_core: Fix endianness bug in set_param_l
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
4af1c048 42#include <linux/rbtree.h>
ee49bd93 43#include <linux/timer.h>
3142788b 44#include <linux/semaphore.h>
27bf91d6 45#include <linux/workqueue.h>
225c7b1f
RD		 46
47#include <linux/mlx4/device.h>
37608eea 48#include <linux/mlx4/driver.h>
225c7b1f 49#include <linux/mlx4/doorbell.h>
623ed84b 50#include <linux/mlx4/cmd.h>
225c7b1f
RD		 51
52#define DRV_NAME "mlx4_core"
ab9c17a0 53#define PFX DRV_NAME ": "
7d4b6bcc
YP		 54#define DRV_VERSION "1.1"
55#define DRV_RELDATE "Dec, 2011"
225c7b1f 56
0ff1fb65
HHZ		 57#define MLX4_FS_UDP_UC_EN (1 << 1)
58#define MLX4_FS_TCP_UC_EN (1 << 2)
59#define MLX4_FS_NUM_OF_L2_ADDR 8
60#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61#define MLX4_FS_NUM_MCG (1 << 17)
62
e448834e
SM		 63#define INIT_HCA_TPT_MW_ENABLE (1 << 7)
64
e5395e92
AV		 65#define MLX4_NUM_UP 8
66#define MLX4_NUM_TC 8
67#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
68#define MLX4_RATELIMIT_DEFAULT 0xffff
69
70struct mlx4_set_port_prio2tc_context {
71 u8 prio2tc[4];
72};
73
74struct mlx4_port_scheduler_tc_cfg_be {
75 __be16 pg;
76 __be16 bw_precentage;
77 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
78 __be16 max_bw_value;
79};
80
81struct mlx4_set_port_scheduler_context {
82 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
83};
84
225c7b1f
RD		 85enum {
86 MLX4_HCR_BASE = 0x80680,
87 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 88 MLX4_CLR_INT_SIZE = 0x00008,
89 MLX4_SLAVE_COMM_BASE = 0x0,
90 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 91};
92
225c7b1f 93enum {
3c439b55
JM		 94 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
95 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
96 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
97 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
0ec2c0f8 98 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 99};
100
225c7b1f
RD		 101enum {
102 MLX4_NUM_PDS = 1 << 15
103};
104
105enum {
106 MLX4_CMPT_TYPE_QP = 0,
107 MLX4_CMPT_TYPE_SRQ = 1,
108 MLX4_CMPT_TYPE_CQ = 2,
109 MLX4_CMPT_TYPE_EQ = 3,
110 MLX4_CMPT_NUM_TYPE
111};
112
113enum {
114 MLX4_CMPT_SHIFT = 24,
115 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
116};
117
b20e519a
SM		 118enum mlx4_mpt_state {
119 MLX4_MPT_DISABLED = 0,
120 MLX4_MPT_EN_HW,
121 MLX4_MPT_EN_SW
623ed84b
JM		 122};
123
124#define MLX4_COMM_TIME 10000
125enum {
126 MLX4_COMM_CMD_RESET,
127 MLX4_COMM_CMD_VHCR0,
128 MLX4_COMM_CMD_VHCR1,
129 MLX4_COMM_CMD_VHCR2,
130 MLX4_COMM_CMD_VHCR_EN,
131 MLX4_COMM_CMD_VHCR_POST,
132 MLX4_COMM_CMD_FLR = 254
133};
134
135/*The flag indicates that the slave should delay the RESET cmd*/
136#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
137/*indicates how many retries will be done if we are in the middle of FLR*/
138#define NUM_OF_RESET_RETRIES 10
139#define SLEEP_TIME_IN_RESET (2 * 1000)
140enum mlx4_resource {
141 RES_QP,
142 RES_CQ,
143 RES_SRQ,
144 RES_XRCD,
145 RES_MPT,
146 RES_MTT,
147 RES_MAC,
148 RES_VLAN,
149 RES_EQ,
150 RES_COUNTER,
1b9c6b06 151 RES_FS_RULE,
623ed84b
JM		 152 MLX4_NUM_OF_RESOURCE_TYPE
153};
154
155enum mlx4_alloc_mode {
156 RES_OP_RESERVE,
157 RES_OP_RESERVE_AND_MAP,
158 RES_OP_MAP_ICM,
159};
160
b8924951
JM		 161enum mlx4_res_tracker_free_type {
162 RES_TR_FREE_ALL,
163 RES_TR_FREE_SLAVES_ONLY,
164 RES_TR_FREE_STRUCTS_ONLY,
165};
623ed84b
JM		 166
167/*
168 *Virtual HCR structures.
169 * mlx4_vhcr is the sw representation, in machine endianess
170 *
171 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
172 * to FW to go through communication channel.
173 * It is big endian, and has the same structure as the physical HCR
174 * used by command interface
175 */
176struct mlx4_vhcr {
177 u64 in_param;
178 u64 out_param;
179 u32 in_modifier;
180 u32 errno;
181 u16 op;
182 u16 token;
183 u8 op_modifier;
184 u8 e_bit;
185};
186
187struct mlx4_vhcr_cmd {
188 __be64 in_param;
189 __be32 in_modifier;
190 __be64 out_param;
191 __be16 token;
192 u16 reserved;
193 u8 status;
194 u8 flags;
195 __be16 opcode;
196};
197
198struct mlx4_cmd_info {
199 u16 opcode;
200 bool has_inbox;
201 bool has_outbox;
202 bool out_is_imm;
203 bool encode_slave_id;
204 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
205 struct mlx4_cmd_mailbox *inbox);
206 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
207 struct mlx4_cmd_mailbox *inbox,
208 struct mlx4_cmd_mailbox *outbox,
209 struct mlx4_cmd_info *cmd);
210};
211
225c7b1f
RD		 212#ifdef CONFIG_MLX4_DEBUG
213extern int mlx4_debug_level;
7b0f5df4
RD		 214#else /* CONFIG_MLX4_DEBUG */
215#define mlx4_debug_level (0)
216#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 217
218#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 219do { \
220 if (mlx4_debug_level) \
221 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
222} while (0)
225c7b1f 223
225c7b1f 224#define mlx4_err(mdev, format, arg...) \
0a645e80 225 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 226#define mlx4_info(mdev, format, arg...) \
0a645e80 227 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 228#define mlx4_warn(mdev, format, arg...) \
0a645e80 229 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 230
0ec2c0f8 231extern int mlx4_log_num_mgm_entry_size;
2b8fb286 232extern int log_mtts_per_seg;
0ec2c0f8 233
623ed84b
JM		 234#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
235#define ALL_SLAVES 0xff
236
225c7b1f
RD		 237struct mlx4_bitmap {
238 u32 last;
239 u32 top;
240 u32 max;
93fc9e1b 241 u32 reserved_top;
225c7b1f 242 u32 mask;
42d1e017 243 u32 avail;
225c7b1f
RD		 244 spinlock_t lock;
245 unsigned long *table;
246};
247
248struct mlx4_buddy {
249 unsigned long **bits;
e4044cfc 250 unsigned int *num_free;
3de819e6 251 u32 max_order;
225c7b1f
RD		 252 spinlock_t lock;
253};
254
255struct mlx4_icm;
256
257struct mlx4_icm_table {
258 u64 virt;
259 int num_icm;
3de819e6 260 u32 num_obj;
225c7b1f
RD		 261 int obj_size;
262 int lowmem;
5b0bf5e2 263 int coherent;
225c7b1f
RD		 264 struct mutex mutex;
265 struct mlx4_icm **icm;
266};
267
cc1ade94
SM		 268#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
269#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
270#define MLX4_MPT_FLAG_MIO (1 << 17)
271#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
272#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
273#define MLX4_MPT_FLAG_REGION (1 << 8)
274
275#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
276#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
277#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
278
279#define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
280
281#define MLX4_MPT_STATUS_SW 0xF0
282#define MLX4_MPT_STATUS_HW 0x00
283
c82e9aa0
EC		 284/*
285 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
286 */
287struct mlx4_mpt_entry {
288 __be32 flags;
289 __be32 qpn;
290 __be32 key;
291 __be32 pd_flags;
292 __be64 start;
293 __be64 length;
294 __be32 lkey;
295 __be32 win_cnt;
296 u8 reserved1[3];
297 u8 mtt_rep;
2b8fb286 298 __be64 mtt_addr;
c82e9aa0
EC		 299 __be32 mtt_sz;
300 __be32 entity_size;
301 __be32 first_byte_offset;
302} __packed;
303
304/*
305 * Must be packed because start is 64 bits but only aligned to 32 bits.
306 */
307struct mlx4_eq_context {
308 __be32 flags;
309 u16 reserved1[3];
310 __be16 page_offset;
311 u8 log_eq_size;
312 u8 reserved2[4];
313 u8 eq_period;
314 u8 reserved3;
315 u8 eq_max_count;
316 u8 reserved4[3];
317 u8 intr;
318 u8 log_page_size;
319 u8 reserved5[2];
320 u8 mtt_base_addr_h;
321 __be32 mtt_base_addr_l;
322 u32 reserved6[2];
323 __be32 consumer_index;
324 __be32 producer_index;
325 u32 reserved7[4];
326};
327
328struct mlx4_cq_context {
329 __be32 flags;
330 u16 reserved1[3];
331 __be16 page_offset;
332 __be32 logsize_usrpage;
333 __be16 cq_period;
334 __be16 cq_max_count;
335 u8 reserved2[3];
336 u8 comp_eqn;
337 u8 log_page_size;
338 u8 reserved3[2];
339 u8 mtt_base_addr_h;
340 __be32 mtt_base_addr_l;
341 __be32 last_notified_index;
342 __be32 solicit_producer_index;
343 __be32 consumer_index;
344 __be32 producer_index;
345 u32 reserved4[2];
346 __be64 db_rec_addr;
347};
348
349struct mlx4_srq_context {
350 __be32 state_logsize_srqn;
351 u8 logstride;
352 u8 reserved1;
353 __be16 xrcd;
354 __be32 pg_offset_cqn;
355 u32 reserved2;
356 u8 log_page_size;
357 u8 reserved3[2];
358 u8 mtt_base_addr_h;
359 __be32 mtt_base_addr_l;
360 __be32 pd;
361 __be16 limit_watermark;
362 __be16 wqe_cnt;
363 u16 reserved4;
364 __be16 wqe_counter;
365 u32 reserved5;
366 __be64 db_rec_addr;
367};
368
225c7b1f
RD		 369struct mlx4_eq {
370 struct mlx4_dev *dev;
371 void __iomem *doorbell;
372 int eqn;
373 u32 cons_index;
374 u16 irq;
375 u16 have_irq;
376 int nent;
377 struct mlx4_buf_list *page_list;
378 struct mlx4_mtt mtt;
379};
380
623ed84b
JM		 381struct mlx4_slave_eqe {
382 u8 type;
383 u8 port;
384 u32 param;
385};
386
387struct mlx4_slave_event_eq_info {
803143fb 388 int eqn;
623ed84b 389 u16 token;
623ed84b
JM		 390};
391
225c7b1f
RD		 392struct mlx4_profile {
393 int num_qp;
394 int rdmarc_per_qp;
395 int num_srq;
396 int num_cq;
397 int num_mcg;
398 int num_mpt;
db5a7a65 399 unsigned num_mtt;
225c7b1f
RD		 400};
401
402struct mlx4_fw {
403 u64 clr_int_base;
404 u64 catas_offset;
623ed84b 405 u64 comm_base;
225c7b1f
RD		 406 struct mlx4_icm *fw_icm;
407 struct mlx4_icm *aux_icm;
408 u32 catas_size;
409 u16 fw_pages;
410 u8 clr_int_bar;
411 u8 catas_bar;
623ed84b
JM		 412 u8 comm_bar;
413};
414
415struct mlx4_comm {
416 u32 slave_write;
417 u32 slave_read;
225c7b1f
RD		 418};
419
ffe455ad
EE		 420enum {
421 MLX4_MCAST_CONFIG = 0,
422 MLX4_MCAST_DISABLE = 1,
423 MLX4_MCAST_ENABLE = 2,
424};
425
623ed84b
JM		 426#define VLAN_FLTR_SIZE 128
427
428struct mlx4_vlan_fltr {
429 __be32 entry[VLAN_FLTR_SIZE];
430};
431
ffe455ad
EE		 432struct mlx4_mcast_entry {
433 struct list_head list;
434 u64 addr;
435};
436
b12d93d6
YP		 437struct mlx4_promisc_qp {
438 struct list_head list;
439 u32 qpn;
440};
441
442struct mlx4_steer_index {
443 struct list_head list;
444 unsigned int index;
445 struct list_head duplicates;
446};
447
803143fb
MA		 448#define MLX4_EVENT_TYPES_NUM 64
449
623ed84b
JM		 450struct mlx4_slave_state {
451 u8 comm_toggle;
452 u8 last_cmd;
453 u8 init_port_mask;
454 bool active;
455 u8 function;
456 dma_addr_t vhcr_dma;
457 u16 mtu[MLX4_MAX_PORTS + 1];
458 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
459 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
460 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
461 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
803143fb
MA		 462 /* event type to eq number lookup */
463 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
623ed84b
JM		 464 u16 eq_pi;
465 u16 eq_ci;
466 spinlock_t lock;
467 /*initialized via the kzalloc*/
468 u8 is_slave_going_down;
469 u32 cookie;
993c401e 470 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
623ed84b
JM		 471};
472
473struct slave_list {
474 struct mutex mutex;
475 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
476};
477
478struct mlx4_resource_tracker {
479 spinlock_t lock;
480 /* tree for each resources */
4af1c048 481 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
623ed84b
JM		 482 /* num_of_slave's lists, one per slave */
483 struct slave_list *slave_list;
484};
485
486#define SLAVE_EVENT_EQ_SIZE 128
487struct mlx4_slave_event_eq {
488 u32 eqn;
489 u32 cons;
490 u32 prod;
992e8e6e 491 spinlock_t event_lock;
623ed84b
JM		 492 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
493};
494
495struct mlx4_master_qp0_state {
496 int proxy_qp0_active;
497 int qp0_active;
498 int port_active;
499};
500
501struct mlx4_mfunc_master_ctx {
502 struct mlx4_slave_state *slave_state;
503 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
504 int init_port_ref[MLX4_MAX_PORTS + 1];
505 u16 max_mtu[MLX4_MAX_PORTS + 1];
506 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
507 struct mlx4_resource_tracker res_tracker;
508 struct workqueue_struct *comm_wq;
509 struct work_struct comm_work;
510 struct work_struct slave_event_work;
511 struct work_struct slave_flr_event_work;
512 spinlock_t slave_state_lock;
f5311ac1 513 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 514 struct mlx4_eqe cmd_eqe;
515 struct mlx4_slave_event_eq slave_eq;
516 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
517};
518
519struct mlx4_mfunc {
520 struct mlx4_comm __iomem *comm;
521 struct mlx4_vhcr_cmd *vhcr;
522 dma_addr_t vhcr_dma;
523
524 struct mlx4_mfunc_master_ctx master;
525};
526
225c7b1f
RD		 527struct mlx4_cmd {
528 struct pci_pool *pool;
529 void __iomem *hcr;
530 struct mutex hcr_mutex;
f3d4c89e 531 struct mutex slave_cmd_mutex;
225c7b1f
RD		 532 struct semaphore poll_sem;
533 struct semaphore event_sem;
534 int max_cmds;
535 spinlock_t context_lock;
536 int free_head;
537 struct mlx4_cmd_context *context;
538 u16 token_mask;
539 u8 use_events;
540 u8 toggle;
623ed84b 541 u8 comm_toggle;
225c7b1f
RD		 542};
543
544struct mlx4_uar_table {
545 struct mlx4_bitmap bitmap;
546};
547
548struct mlx4_mr_table {
549 struct mlx4_bitmap mpt_bitmap;
550 struct mlx4_buddy mtt_buddy;
551 u64 mtt_base;
552 u64 mpt_base;
553 struct mlx4_icm_table mtt_table;
554 struct mlx4_icm_table dmpt_table;
555};
556
557struct mlx4_cq_table {
558 struct mlx4_bitmap bitmap;
559 spinlock_t lock;
560 struct radix_tree_root tree;
561 struct mlx4_icm_table table;
562 struct mlx4_icm_table cmpt_table;
563};
564
565struct mlx4_eq_table {
566 struct mlx4_bitmap bitmap;
b8dd786f 567 char *irq_names;
225c7b1f 568 void __iomem *clr_int;
b8dd786f 569 void __iomem **uar_map;
225c7b1f 570 u32 clr_mask;
b8dd786f 571 struct mlx4_eq *eq;
fa0681d2 572 struct mlx4_icm_table table;
225c7b1f
RD		 573 struct mlx4_icm_table cmpt_table;
574 int have_irq;
575 u8 inta_pin;
576};
577
578struct mlx4_srq_table {
579 struct mlx4_bitmap bitmap;
580 spinlock_t lock;
581 struct radix_tree_root tree;
582 struct mlx4_icm_table table;
583 struct mlx4_icm_table cmpt_table;
584};
585
586struct mlx4_qp_table {
587 struct mlx4_bitmap bitmap;
588 u32 rdmarc_base;
589 int rdmarc_shift;
590 spinlock_t lock;
591 struct mlx4_icm_table qp_table;
592 struct mlx4_icm_table auxc_table;
593 struct mlx4_icm_table altc_table;
594 struct mlx4_icm_table rdmarc_table;
595 struct mlx4_icm_table cmpt_table;
596};
597
598struct mlx4_mcg_table {
599 struct mutex mutex;
600 struct mlx4_bitmap bitmap;
601 struct mlx4_icm_table table;
602};
603
604struct mlx4_catas_err {
605 u32 __iomem *map;
ee49bd93
JM		 606 struct timer_list timer;
607 struct list_head list;
225c7b1f
RD		 608};
609
2a2336f8
YP		 610#define MLX4_MAX_MAC_NUM 128
611#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
612
613struct mlx4_mac_table {
614 __be64 entries[MLX4_MAX_MAC_NUM];
615 int refs[MLX4_MAX_MAC_NUM];
616 struct mutex mutex;
617 int total;
618 int max;
619};
620
621#define MLX4_MAX_VLAN_NUM 128
622#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
623
624struct mlx4_vlan_table {
625 __be32 entries[MLX4_MAX_VLAN_NUM];
626 int refs[MLX4_MAX_VLAN_NUM];
627 struct mutex mutex;
628 int total;
629 int max;
630};
631
ffe455ad
EE		 632#define SET_PORT_GEN_ALL_VALID 0x7
633#define SET_PORT_PROMISC_SHIFT 31
634#define SET_PORT_MC_PROMISC_SHIFT 30
635
636enum {
637 MCAST_DIRECT_ONLY = 0,
638 MCAST_DIRECT = 1,
639 MCAST_DEFAULT = 2
640};
641
642
643struct mlx4_set_port_general_context {
644 u8 reserved[3];
645 u8 flags;
646 u16 reserved2;
647 __be16 mtu;
648 u8 pptx;
649 u8 pfctx;
650 u16 reserved3;
651 u8 pprx;
652 u8 pfcrx;
653 u16 reserved4;
654};
655
656struct mlx4_set_port_rqp_calc_context {
657 __be32 base_qpn;
658 u8 rererved;
659 u8 n_mac;
660 u8 n_vlan;
661 u8 n_prio;
662 u8 reserved2[3];
663 u8 mac_miss;
664 u8 intra_no_vlan;
665 u8 no_vlan;
666 u8 intra_vlan_miss;
667 u8 vlan_miss;
668 u8 reserved3[3];
669 u8 no_vlan_prio;
670 __be32 promisc;
671 __be32 mcast;
672};
673
2a2336f8
YP		 674struct mlx4_port_info {
675 struct mlx4_dev *dev;
676 int port;
7ff93f8b
YP		 677 char dev_name[16];
678 struct device_attribute port_attr;
679 enum mlx4_port_type tmp_type;
096335b3
OG		 680 char dev_mtu_name[16];
681 struct device_attribute port_mtu_attr;
2a2336f8
YP		 682 struct mlx4_mac_table mac_table;
683 struct mlx4_vlan_table vlan_table;
1679200f 684 int base_qpn;
2a2336f8
YP		 685};
686
27bf91d6
YP		 687struct mlx4_sense {
688 struct mlx4_dev *dev;
689 u8 do_sense_port[MLX4_MAX_PORTS + 1];
690 u8 sense_allowed[MLX4_MAX_PORTS + 1];
691 struct delayed_work sense_poll;
692};
693
0b7ca5a9
YP		 694struct mlx4_msix_ctl {
695 u64 pool_bm;
730c41d5 696 struct mutex pool_lock;
0b7ca5a9
YP		 697};
698
b12d93d6
YP		 699struct mlx4_steer {
700 struct list_head promisc_qps[MLX4_NUM_STEERS];
701 struct list_head steer_entries[MLX4_NUM_STEERS];
b12d93d6
YP		 702};
703
a8edc3bf
HHZ		 704struct mlx4_net_trans_rule_hw_ctrl {
705 __be32 ctrl;
015465f8
HHZ		 706 u8 rsvd1;
707 u8 funcid;
708 u8 vep;
709 u8 port;
a8edc3bf 710 __be32 qpn;
015465f8 711 __be32 rsvd2;
a8edc3bf
HHZ		 712};
713
714struct mlx4_net_trans_rule_hw_ib {
715 u8 size;
716 u8 rsvd1;
717 __be16 id;
718 u32 rsvd2;
719 __be32 qpn;
720 __be32 qpn_mask;
721 u8 dst_gid[16];
722 u8 dst_gid_msk[16];
723} __packed;
724
725struct mlx4_net_trans_rule_hw_eth {
726 u8 size;
727 u8 rsvd;
728 __be16 id;
729 u8 rsvd1[6];
730 u8 dst_mac[6];
731 u16 rsvd2;
732 u8 dst_mac_msk[6];
733 u16 rsvd3;
734 u8 src_mac[6];
735 u16 rsvd4;
736 u8 src_mac_msk[6];
737 u8 rsvd5;
738 u8 ether_type_enable;
739 __be16 ether_type;
740 __be16 vlan_id_msk;
741 __be16 vlan_id;
742} __packed;
743
744struct mlx4_net_trans_rule_hw_tcp_udp {
745 u8 size;
746 u8 rsvd;
747 __be16 id;
748 __be16 rsvd1[3];
749 __be16 dst_port;
750 __be16 rsvd2;
751 __be16 dst_port_msk;
752 __be16 rsvd3;
753 __be16 src_port;
754 __be16 rsvd4;
755 __be16 src_port_msk;
756} __packed;
757
758struct mlx4_net_trans_rule_hw_ipv4 {
759 u8 size;
760 u8 rsvd;
761 __be16 id;
762 __be32 rsvd1;
763 __be32 dst_ip;
764 __be32 dst_ip_msk;
765 __be32 src_ip;
766 __be32 src_ip_msk;
767} __packed;
768
769struct _rule_hw {
770 union {
771 struct {
772 u8 size;
773 u8 rsvd;
774 __be16 id;
775 };
776 struct mlx4_net_trans_rule_hw_eth eth;
777 struct mlx4_net_trans_rule_hw_ib ib;
778 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
779 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
780 };
781};
782
839f1243
RD		 783enum {
784 MLX4_PCI_DEV_IS_VF = 1 << 0,
ca3e57a5 785 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
839f1243
RD		 786};
787
225c7b1f
RD		 788struct mlx4_priv {
789 struct mlx4_dev dev;
790
791 struct list_head dev_list;
792 struct list_head ctx_list;
793 spinlock_t ctx_lock;
794
839f1243
RD		 795 int pci_dev_data;
796
6296883c
YP		 797 struct list_head pgdir_list;
798 struct mutex pgdir_mutex;
799
225c7b1f
RD		 800 struct mlx4_fw fw;
801 struct mlx4_cmd cmd;
623ed84b 802 struct mlx4_mfunc mfunc;
225c7b1f
RD		 803
804 struct mlx4_bitmap pd_bitmap;
012a8ff5 805 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 806 struct mlx4_uar_table uar_table;
807 struct mlx4_mr_table mr_table;
808 struct mlx4_cq_table cq_table;
809 struct mlx4_eq_table eq_table;
810 struct mlx4_srq_table srq_table;
811 struct mlx4_qp_table qp_table;
812 struct mlx4_mcg_table mcg_table;
f2a3f6a3 813 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 814
815 struct mlx4_catas_err catas_err;
816
817 void __iomem *clr_base;
818
819 struct mlx4_uar driver_uar;
820 void __iomem *kar;
2a2336f8 821 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 822 struct mlx4_sense sense;
7ff93f8b 823 struct mutex port_mutex;
0b7ca5a9 824 struct mlx4_msix_ctl msix_ctl;
b12d93d6 825 struct mlx4_steer *steer;
c1b43dca
EC		 826 struct list_head bf_list;
827 struct mutex bf_mutex;
828 struct io_mapping *bf_mapping;
ea51b377 829 int reserved_mtts;
0ff1fb65 830 int fs_hash_mode;
54679e14 831 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
afa8fd1d 832 __be64 slave_node_guids[MLX4_MFUNC_MAX];
54679e14 833
225c7b1f
RD		 834};
835
836static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
837{
838 return container_of(dev, struct mlx4_priv, dev);
839}
840
27bf91d6
YP		 841#define MLX4_SENSE_RANGE (HZ * 3)
842
843extern struct workqueue_struct *mlx4_wq;
844
225c7b1f
RD		 845u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
846void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 847u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
848void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 849u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 850int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
851 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 852void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
853
854int mlx4_reset(struct mlx4_dev *dev);
855
b8dd786f
YP		 856int mlx4_alloc_eq_table(struct mlx4_dev *dev);
857void mlx4_free_eq_table(struct mlx4_dev *dev);
858
225c7b1f 859int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 860int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 861int mlx4_init_uar_table(struct mlx4_dev *dev);
862int mlx4_init_mr_table(struct mlx4_dev *dev);
863int mlx4_init_eq_table(struct mlx4_dev *dev);
864int mlx4_init_cq_table(struct mlx4_dev *dev);
865int mlx4_init_qp_table(struct mlx4_dev *dev);
866int mlx4_init_srq_table(struct mlx4_dev *dev);
867int mlx4_init_mcg_table(struct mlx4_dev *dev);
868
869void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 870void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 871void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
872void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
873void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
874void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
875void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
876void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
877void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 878int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
879void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
880int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
881void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
882int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
883void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
b20e519a
SM		 884int __mlx4_mpt_reserve(struct mlx4_dev *dev);
885void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
886int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
887void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
c82e9aa0
EC		 888u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
889void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 890
623ed84b
JM		 891int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
892 struct mlx4_vhcr *vhcr,
893 struct mlx4_cmd_mailbox *inbox,
894 struct mlx4_cmd_mailbox *outbox,
895 struct mlx4_cmd_info *cmd);
896int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
897 struct mlx4_vhcr *vhcr,
898 struct mlx4_cmd_mailbox *inbox,
899 struct mlx4_cmd_mailbox *outbox,
900 struct mlx4_cmd_info *cmd);
901int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
902 struct mlx4_vhcr *vhcr,
903 struct mlx4_cmd_mailbox *inbox,
904 struct mlx4_cmd_mailbox *outbox,
905 struct mlx4_cmd_info *cmd);
906int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
907 struct mlx4_vhcr *vhcr,
908 struct mlx4_cmd_mailbox *inbox,
909 struct mlx4_cmd_mailbox *outbox,
910 struct mlx4_cmd_info *cmd);
911int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
912 struct mlx4_vhcr *vhcr,
913 struct mlx4_cmd_mailbox *inbox,
914 struct mlx4_cmd_mailbox *outbox,
915 struct mlx4_cmd_info *cmd);
916int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
917 struct mlx4_vhcr *vhcr,
918 struct mlx4_cmd_mailbox *inbox,
919 struct mlx4_cmd_mailbox *outbox,
920 struct mlx4_cmd_info *cmd);
921int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
922 struct mlx4_vhcr *vhcr,
923 struct mlx4_cmd_mailbox *inbox,
924 struct mlx4_cmd_mailbox *outbox,
925 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 926int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
927 int *base);
928void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
929int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
930void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
c82e9aa0
EC		 931int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
932 int start_index, int npages, u64 *page_list);
ba062d52
JM		 933int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
934void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
935int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
936void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
623ed84b 937
ee49bd93
JM		 938void mlx4_start_catas_poll(struct mlx4_dev *dev);
939void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 940void mlx4_catas_init(void);
ee49bd93 941int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 942int mlx4_register_device(struct mlx4_dev *dev);
943void mlx4_unregister_device(struct mlx4_dev *dev);
00f5ce99
JM		 944void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
945 unsigned long param);
225c7b1f
RD		 946
947struct mlx4_dev_cap;
948struct mlx4_init_hca_param;
949
950u64 mlx4_make_profile(struct mlx4_dev *dev,
951 struct mlx4_profile *request,
952 struct mlx4_dev_cap *dev_cap,
953 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 954void mlx4_master_comm_channel(struct work_struct *work);
955void mlx4_gen_slave_eqe(struct work_struct *work);
956void mlx4_master_handle_slave_flr(struct work_struct *work);
957
958int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
959 struct mlx4_vhcr *vhcr,
960 struct mlx4_cmd_mailbox *inbox,
961 struct mlx4_cmd_mailbox *outbox,
962 struct mlx4_cmd_info *cmd);
963int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd);
968int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
969 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr,
974 struct mlx4_cmd_mailbox *inbox,
975 struct mlx4_cmd_mailbox *outbox,
976 struct mlx4_cmd_info *cmd);
977int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
978 struct mlx4_vhcr *vhcr,
979 struct mlx4_cmd_mailbox *inbox,
980 struct mlx4_cmd_mailbox *outbox,
981 struct mlx4_cmd_info *cmd);
982int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
983 struct mlx4_vhcr *vhcr,
984 struct mlx4_cmd_mailbox *inbox,
985 struct mlx4_cmd_mailbox *outbox,
986 struct mlx4_cmd_info *cmd);
987int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
988 struct mlx4_vhcr *vhcr,
989 struct mlx4_cmd_mailbox *inbox,
990 struct mlx4_cmd_mailbox *outbox,
991 struct mlx4_cmd_info *cmd);
992int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
993 struct mlx4_vhcr *vhcr,
994 struct mlx4_cmd_mailbox *inbox,
995 struct mlx4_cmd_mailbox *outbox,
996 struct mlx4_cmd_info *cmd);
997int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
998 struct mlx4_vhcr *vhcr,
999 struct mlx4_cmd_mailbox *inbox,
1000 struct mlx4_cmd_mailbox *outbox,
1001 struct mlx4_cmd_info *cmd);
1002int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1003 struct mlx4_vhcr *vhcr,
1004 struct mlx4_cmd_mailbox *inbox,
1005 struct mlx4_cmd_mailbox *outbox,
1006 struct mlx4_cmd_info *cmd);
1007int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1008 struct mlx4_vhcr *vhcr,
1009 struct mlx4_cmd_mailbox *inbox,
1010 struct mlx4_cmd_mailbox *outbox,
1011 struct mlx4_cmd_info *cmd);
1012int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1013 struct mlx4_vhcr *vhcr,
1014 struct mlx4_cmd_mailbox *inbox,
1015 struct mlx4_cmd_mailbox *outbox,
1016 struct mlx4_cmd_info *cmd);
1017int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1018 struct mlx4_vhcr *vhcr,
1019 struct mlx4_cmd_mailbox *inbox,
1020 struct mlx4_cmd_mailbox *outbox,
1021 struct mlx4_cmd_info *cmd);
1022int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
1027int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1028 struct mlx4_vhcr *vhcr,
1029 struct mlx4_cmd_mailbox *inbox,
1030 struct mlx4_cmd_mailbox *outbox,
1031 struct mlx4_cmd_info *cmd);
1032int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd);
54679e14
JM		 1037int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1038 struct mlx4_vhcr *vhcr,
1039 struct mlx4_cmd_mailbox *inbox,
1040 struct mlx4_cmd_mailbox *outbox,
1041 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1042int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1043 struct mlx4_vhcr *vhcr,
1044 struct mlx4_cmd_mailbox *inbox,
1045 struct mlx4_cmd_mailbox *outbox,
1046 struct mlx4_cmd_info *cmd);
54679e14
JM		 1047int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1048 struct mlx4_vhcr *vhcr,
1049 struct mlx4_cmd_mailbox *inbox,
1050 struct mlx4_cmd_mailbox *outbox,
1051 struct mlx4_cmd_info *cmd);
1052int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr,
1054 struct mlx4_cmd_mailbox *inbox,
1055 struct mlx4_cmd_mailbox *outbox,
1056 struct mlx4_cmd_info *cmd);
1057int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
1062int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1063 struct mlx4_vhcr *vhcr,
1064 struct mlx4_cmd_mailbox *inbox,
1065 struct mlx4_cmd_mailbox *outbox,
1066 struct mlx4_cmd_info *cmd);
1067int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1068 struct mlx4_vhcr *vhcr,
1069 struct mlx4_cmd_mailbox *inbox,
1070 struct mlx4_cmd_mailbox *outbox,
1071 struct mlx4_cmd_info *cmd);
1072int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1073 struct mlx4_vhcr *vhcr,
1074 struct mlx4_cmd_mailbox *inbox,
1075 struct mlx4_cmd_mailbox *outbox,
1076 struct mlx4_cmd_info *cmd);
1077int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1078 struct mlx4_vhcr *vhcr,
1079 struct mlx4_cmd_mailbox *inbox,
1080 struct mlx4_cmd_mailbox *outbox,
1081 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1082int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1083 struct mlx4_vhcr *vhcr,
1084 struct mlx4_cmd_mailbox *inbox,
1085 struct mlx4_cmd_mailbox *outbox,
1086 struct mlx4_cmd_info *cmd);
54679e14
JM		 1087int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1088 struct mlx4_vhcr *vhcr,
1089 struct mlx4_cmd_mailbox *inbox,
1090 struct mlx4_cmd_mailbox *outbox,
1091 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1092
1093int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 1094
225c7b1f
RD		 1095int mlx4_cmd_init(struct mlx4_dev *dev);
1096void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 1097int mlx4_multi_func_init(struct mlx4_dev *dev);
1098void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 1099void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1100int mlx4_cmd_use_events(struct mlx4_dev *dev);
1101void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1102
ab9c17a0
JM		 1103int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1104 unsigned long timeout);
1105
225c7b1f
RD		 1106void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1107void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1108
1109void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1110
1111void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1112
1113void mlx4_handle_catas_err(struct mlx4_dev *dev);
1114
ab6dc30d
YP		 1115int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1116 enum mlx4_port_type *type);
27bf91d6
YP		 1117void mlx4_do_sense_ports(struct mlx4_dev *dev,
1118 enum mlx4_port_type *stype,
1119 enum mlx4_port_type *defaults);
1120void mlx4_start_sense(struct mlx4_dev *dev);
1121void mlx4_stop_sense(struct mlx4_dev *dev);
1122void mlx4_sense_init(struct mlx4_dev *dev);
1123int mlx4_check_port_params(struct mlx4_dev *dev,
1124 enum mlx4_port_type *port_type);
1125int mlx4_change_port_types(struct mlx4_dev *dev,
1126 enum mlx4_port_type *port_types);
1127
2a2336f8
YP		 1128void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1129void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1130
6634961c 1131int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
623ed84b
JM		 1132/* resource tracker functions*/
1133int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1134 enum mlx4_resource resource_type,
aa1ec3dd 1135 u64 resource_id, int *slave);
623ed84b
JM		 1136void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1137int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1138
b8924951
JM		 1139void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1140 enum mlx4_res_tracker_free_type type);
623ed84b 1141
b91cb3eb
JM		 1142int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1143 struct mlx4_vhcr *vhcr,
1144 struct mlx4_cmd_mailbox *inbox,
1145 struct mlx4_cmd_mailbox *outbox,
1146 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1147int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1148 struct mlx4_vhcr *vhcr,
1149 struct mlx4_cmd_mailbox *inbox,
1150 struct mlx4_cmd_mailbox *outbox,
1151 struct mlx4_cmd_info *cmd);
1152int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1153 struct mlx4_vhcr *vhcr,
1154 struct mlx4_cmd_mailbox *inbox,
1155 struct mlx4_cmd_mailbox *outbox,
1156 struct mlx4_cmd_info *cmd);
1157int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1158 struct mlx4_vhcr *vhcr,
1159 struct mlx4_cmd_mailbox *inbox,
1160 struct mlx4_cmd_mailbox *outbox,
1161 struct mlx4_cmd_info *cmd);
b91cb3eb
JM		 1162int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1163 struct mlx4_vhcr *vhcr,
1164 struct mlx4_cmd_mailbox *inbox,
1165 struct mlx4_cmd_mailbox *outbox,
1166 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1167int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1168 struct mlx4_vhcr *vhcr,
1169 struct mlx4_cmd_mailbox *inbox,
1170 struct mlx4_cmd_mailbox *outbox,
1171 struct mlx4_cmd_info *cmd);
9a5aa622 1172int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
7ff93f8b 1173
6634961c
JM		 1174int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1175 int *gid_tbl_len, int *pkey_tbl_len);
623ed84b
JM		 1176
1177int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1178 struct mlx4_vhcr *vhcr,
1179 struct mlx4_cmd_mailbox *inbox,
1180 struct mlx4_cmd_mailbox *outbox,
1181 struct mlx4_cmd_info *cmd);
1182
1183int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1184 struct mlx4_vhcr *vhcr,
1185 struct mlx4_cmd_mailbox *inbox,
1186 struct mlx4_cmd_mailbox *outbox,
1187 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1188int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1189 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1190int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1191 int block_mcast_loopback, enum mlx4_protocol prot,
1192 enum mlx4_steer_type steer);
623ed84b
JM		 1193int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1194 struct mlx4_vhcr *vhcr,
1195 struct mlx4_cmd_mailbox *inbox,
1196 struct mlx4_cmd_mailbox *outbox,
1197 struct mlx4_cmd_info *cmd);
1198int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1199 struct mlx4_vhcr *vhcr,
1200 struct mlx4_cmd_mailbox *inbox,
1201 struct mlx4_cmd_mailbox *outbox,
1202 struct mlx4_cmd_info *cmd);
1203int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1204 int port, void *buf);
1205int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1206 struct mlx4_cmd_mailbox *outbox);
1207int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1208 struct mlx4_vhcr *vhcr,
1209 struct mlx4_cmd_mailbox *inbox,
1210 struct mlx4_cmd_mailbox *outbox,
1211 struct mlx4_cmd_info *cmd);
1212int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1213 struct mlx4_vhcr *vhcr,
1214 struct mlx4_cmd_mailbox *inbox,
1215 struct mlx4_cmd_mailbox *outbox,
1216 struct mlx4_cmd_info *cmd);
1217int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1218 struct mlx4_vhcr *vhcr,
1219 struct mlx4_cmd_mailbox *inbox,
1220 struct mlx4_cmd_mailbox *outbox,
1221 struct mlx4_cmd_info *cmd);
8fcfb4db
HHZ		 1222int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1223 struct mlx4_vhcr *vhcr,
1224 struct mlx4_cmd_mailbox *inbox,
1225 struct mlx4_cmd_mailbox *outbox,
1226 struct mlx4_cmd_info *cmd);
1227int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1228 struct mlx4_vhcr *vhcr,
1229 struct mlx4_cmd_mailbox *inbox,
1230 struct mlx4_cmd_mailbox *outbox,
1231 struct mlx4_cmd_info *cmd);
f5311ac1 1232
0ec2c0f8
EE		 1233int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1234int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1235
5cc914f1
MA		 1236static inline void set_param_l(u64 *arg, u32 val)
1237{
e7dbeba8 1238 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
5cc914f1
MA		 1239}
1240
1241static inline void set_param_h(u64 *arg, u32 val)
1242{
1243 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1244}
1245
1246static inline u32 get_param_l(u64 *arg)
1247{
1248 return (u32) (*arg & 0xffffffff);
1249}
1250
1251static inline u32 get_param_h(u64 *arg)
1252{
1253 return (u32)(*arg >> 32);
1254}
1255
c82e9aa0
EC		 1256static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1257{
1258 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1259}
1260
f5311ac1
JM		 1261#define NOT_MASKED_PD_BITS 17
1262
225c7b1f 1263#endif /* MLX4_H */
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