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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. | |
51a379d0 | 5 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
6 | * Copyright (c) 2004 Voltaire, Inc. All rights reserved. |
7 | * | |
8 | * This software is available to you under a choice of one of two | |
9 | * licenses. You may choose to be licensed under the terms of the GNU | |
10 | * General Public License (GPL) Version 2, available from the file | |
11 | * COPYING in the main directory of this source tree, or the | |
12 | * OpenIB.org BSD license below: | |
13 | * | |
14 | * Redistribution and use in source and binary forms, with or | |
15 | * without modification, are permitted provided that the following | |
16 | * conditions are met: | |
17 | * | |
18 | * - Redistributions of source code must retain the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer. | |
21 | * | |
22 | * - Redistributions in binary form must reproduce the above | |
23 | * copyright notice, this list of conditions and the following | |
24 | * disclaimer in the documentation and/or other materials | |
25 | * provided with the distribution. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
28 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
29 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
30 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
31 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
32 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
33 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
34 | * SOFTWARE. | |
35 | */ | |
36 | ||
37 | #ifndef MLX4_H | |
38 | #define MLX4_H | |
39 | ||
525f5f44 | 40 | #include <linux/mutex.h> |
225c7b1f | 41 | #include <linux/radix-tree.h> |
4af1c048 | 42 | #include <linux/rbtree.h> |
ee49bd93 | 43 | #include <linux/timer.h> |
3142788b | 44 | #include <linux/semaphore.h> |
27bf91d6 | 45 | #include <linux/workqueue.h> |
3dca0f42 MB |
46 | #include <linux/interrupt.h> |
47 | #include <linux/spinlock.h> | |
09d4d087 | 48 | #include <net/devlink.h> |
a7e1f049 | 49 | #include <linux/rwsem.h> |
225c7b1f RD |
50 | |
51 | #include <linux/mlx4/device.h> | |
37608eea | 52 | #include <linux/mlx4/driver.h> |
225c7b1f | 53 | #include <linux/mlx4/doorbell.h> |
623ed84b | 54 | #include <linux/mlx4/cmd.h> |
666672d4 | 55 | #include "fw_qos.h" |
225c7b1f RD |
56 | |
57 | #define DRV_NAME "mlx4_core" | |
ab9c17a0 | 58 | #define PFX DRV_NAME ": " |
cea2a6d8 | 59 | #define DRV_VERSION "4.0-0" |
225c7b1f | 60 | |
0ff1fb65 HHZ |
61 | #define MLX4_FS_UDP_UC_EN (1 << 1) |
62 | #define MLX4_FS_TCP_UC_EN (1 << 2) | |
63 | #define MLX4_FS_NUM_OF_L2_ADDR 8 | |
64 | #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 | |
65 | #define MLX4_FS_NUM_MCG (1 << 17) | |
66 | ||
e448834e SM |
67 | #define INIT_HCA_TPT_MW_ENABLE (1 << 7) |
68 | ||
b72ca7e9 EBE |
69 | #define MLX4_QUERY_IF_STAT_RESET BIT(31) |
70 | ||
225c7b1f RD |
71 | enum { |
72 | MLX4_HCR_BASE = 0x80680, | |
73 | MLX4_HCR_SIZE = 0x0001c, | |
623ed84b JM |
74 | MLX4_CLR_INT_SIZE = 0x00008, |
75 | MLX4_SLAVE_COMM_BASE = 0x0, | |
ddd8a6c1 | 76 | MLX4_COMM_PAGESIZE = 0x1000, |
55ad3592 YH |
77 | MLX4_CLOCK_SIZE = 0x00008, |
78 | MLX4_COMM_CHAN_CAPS = 0x8, | |
79 | MLX4_COMM_CHAN_FLAGS = 0xc | |
225c7b1f RD |
80 | }; |
81 | ||
225c7b1f | 82 | enum { |
3c439b55 JM |
83 | MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, |
84 | MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, | |
85 | MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, | |
86 | MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), | |
0ec2c0f8 | 87 | MLX4_MTT_ENTRY_PER_SEG = 8, |
225c7b1f RD |
88 | }; |
89 | ||
225c7b1f RD |
90 | enum { |
91 | MLX4_NUM_PDS = 1 << 15 | |
92 | }; | |
93 | ||
94 | enum { | |
95 | MLX4_CMPT_TYPE_QP = 0, | |
96 | MLX4_CMPT_TYPE_SRQ = 1, | |
97 | MLX4_CMPT_TYPE_CQ = 2, | |
98 | MLX4_CMPT_TYPE_EQ = 3, | |
99 | MLX4_CMPT_NUM_TYPE | |
100 | }; | |
101 | ||
102 | enum { | |
103 | MLX4_CMPT_SHIFT = 24, | |
104 | MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT | |
105 | }; | |
106 | ||
b20e519a SM |
107 | enum mlx4_mpt_state { |
108 | MLX4_MPT_DISABLED = 0, | |
109 | MLX4_MPT_EN_HW, | |
110 | MLX4_MPT_EN_SW | |
623ed84b JM |
111 | }; |
112 | ||
113 | #define MLX4_COMM_TIME 10000 | |
55ad3592 | 114 | #define MLX4_COMM_OFFLINE_TIME_OUT 30000 |
0cd93027 YH |
115 | #define MLX4_COMM_CMD_NA_OP 0x0 |
116 | ||
55ad3592 | 117 | |
623ed84b JM |
118 | enum { |
119 | MLX4_COMM_CMD_RESET, | |
120 | MLX4_COMM_CMD_VHCR0, | |
121 | MLX4_COMM_CMD_VHCR1, | |
122 | MLX4_COMM_CMD_VHCR2, | |
123 | MLX4_COMM_CMD_VHCR_EN, | |
124 | MLX4_COMM_CMD_VHCR_POST, | |
125 | MLX4_COMM_CMD_FLR = 254 | |
126 | }; | |
127 | ||
99ec41d0 JM |
128 | enum { |
129 | MLX4_VF_SMI_DISABLED, | |
130 | MLX4_VF_SMI_ENABLED | |
131 | }; | |
132 | ||
623ed84b JM |
133 | /*The flag indicates that the slave should delay the RESET cmd*/ |
134 | #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb | |
135 | /*indicates how many retries will be done if we are in the middle of FLR*/ | |
136 | #define NUM_OF_RESET_RETRIES 10 | |
137 | #define SLEEP_TIME_IN_RESET (2 * 1000) | |
138 | enum mlx4_resource { | |
139 | RES_QP, | |
140 | RES_CQ, | |
141 | RES_SRQ, | |
142 | RES_XRCD, | |
143 | RES_MPT, | |
144 | RES_MTT, | |
145 | RES_MAC, | |
146 | RES_VLAN, | |
aa0c08fe | 147 | RES_NPORT_ID, |
623ed84b | 148 | RES_COUNTER, |
1b9c6b06 | 149 | RES_FS_RULE, |
aa0c08fe | 150 | RES_EQ, |
623ed84b JM |
151 | MLX4_NUM_OF_RESOURCE_TYPE |
152 | }; | |
153 | ||
154 | enum mlx4_alloc_mode { | |
155 | RES_OP_RESERVE, | |
156 | RES_OP_RESERVE_AND_MAP, | |
157 | RES_OP_MAP_ICM, | |
158 | }; | |
159 | ||
b8924951 JM |
160 | enum mlx4_res_tracker_free_type { |
161 | RES_TR_FREE_ALL, | |
162 | RES_TR_FREE_SLAVES_ONLY, | |
163 | RES_TR_FREE_STRUCTS_ONLY, | |
164 | }; | |
623ed84b JM |
165 | |
166 | /* | |
167 | *Virtual HCR structures. | |
dbedd44e | 168 | * mlx4_vhcr is the sw representation, in machine endianness |
623ed84b JM |
169 | * |
170 | * mlx4_vhcr_cmd is the formalized structure, the one that is passed | |
171 | * to FW to go through communication channel. | |
172 | * It is big endian, and has the same structure as the physical HCR | |
173 | * used by command interface | |
174 | */ | |
175 | struct mlx4_vhcr { | |
176 | u64 in_param; | |
177 | u64 out_param; | |
178 | u32 in_modifier; | |
179 | u32 errno; | |
180 | u16 op; | |
181 | u16 token; | |
182 | u8 op_modifier; | |
183 | u8 e_bit; | |
184 | }; | |
185 | ||
186 | struct mlx4_vhcr_cmd { | |
187 | __be64 in_param; | |
188 | __be32 in_modifier; | |
dc7d5004 | 189 | u32 reserved1; |
623ed84b JM |
190 | __be64 out_param; |
191 | __be16 token; | |
192 | u16 reserved; | |
193 | u8 status; | |
194 | u8 flags; | |
195 | __be16 opcode; | |
196 | }; | |
197 | ||
198 | struct mlx4_cmd_info { | |
199 | u16 opcode; | |
200 | bool has_inbox; | |
201 | bool has_outbox; | |
202 | bool out_is_imm; | |
203 | bool encode_slave_id; | |
204 | int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, | |
205 | struct mlx4_cmd_mailbox *inbox); | |
206 | int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, | |
207 | struct mlx4_cmd_mailbox *inbox, | |
208 | struct mlx4_cmd_mailbox *outbox, | |
209 | struct mlx4_cmd_info *cmd); | |
210 | }; | |
211 | ||
225c7b1f RD |
212 | #ifdef CONFIG_MLX4_DEBUG |
213 | extern int mlx4_debug_level; | |
7b0f5df4 RD |
214 | #else /* CONFIG_MLX4_DEBUG */ |
215 | #define mlx4_debug_level (0) | |
216 | #endif /* CONFIG_MLX4_DEBUG */ | |
225c7b1f | 217 | |
1a91de28 | 218 | #define mlx4_dbg(mdev, format, ...) \ |
0a645e80 JP |
219 | do { \ |
220 | if (mlx4_debug_level) \ | |
872bf2fb YH |
221 | dev_printk(KERN_DEBUG, \ |
222 | &(mdev)->persist->pdev->dev, format, \ | |
1a91de28 | 223 | ##__VA_ARGS__); \ |
0a645e80 | 224 | } while (0) |
225c7b1f | 225 | |
1a91de28 | 226 | #define mlx4_err(mdev, format, ...) \ |
872bf2fb | 227 | dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) |
1a91de28 | 228 | #define mlx4_info(mdev, format, ...) \ |
872bf2fb | 229 | dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) |
1a91de28 | 230 | #define mlx4_warn(mdev, format, ...) \ |
872bf2fb | 231 | dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) |
225c7b1f | 232 | |
2b8fb286 | 233 | extern int log_mtts_per_seg; |
f5aef5aa | 234 | extern int mlx4_internal_err_reset; |
0ec2c0f8 | 235 | |
5a2e87b1 JM |
236 | #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \ |
237 | MLX4_MFUNC_MAX)) | |
623ed84b JM |
238 | #define ALL_SLAVES 0xff |
239 | ||
225c7b1f RD |
240 | struct mlx4_bitmap { |
241 | u32 last; | |
242 | u32 top; | |
243 | u32 max; | |
93fc9e1b | 244 | u32 reserved_top; |
225c7b1f | 245 | u32 mask; |
42d1e017 | 246 | u32 avail; |
7a89399f | 247 | u32 effective_len; |
225c7b1f RD |
248 | spinlock_t lock; |
249 | unsigned long *table; | |
250 | }; | |
251 | ||
252 | struct mlx4_buddy { | |
253 | unsigned long **bits; | |
e4044cfc | 254 | unsigned int *num_free; |
3de819e6 | 255 | u32 max_order; |
225c7b1f RD |
256 | spinlock_t lock; |
257 | }; | |
258 | ||
259 | struct mlx4_icm; | |
260 | ||
261 | struct mlx4_icm_table { | |
262 | u64 virt; | |
263 | int num_icm; | |
3de819e6 | 264 | u32 num_obj; |
225c7b1f RD |
265 | int obj_size; |
266 | int lowmem; | |
5b0bf5e2 | 267 | int coherent; |
225c7b1f RD |
268 | struct mutex mutex; |
269 | struct mlx4_icm **icm; | |
270 | }; | |
271 | ||
cc1ade94 SM |
272 | #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) |
273 | #define MLX4_MPT_FLAG_FREE (0x3UL << 28) | |
274 | #define MLX4_MPT_FLAG_MIO (1 << 17) | |
275 | #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) | |
276 | #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) | |
277 | #define MLX4_MPT_FLAG_REGION (1 << 8) | |
278 | ||
e630664c MB |
279 | #define MLX4_MPT_PD_MASK (0x1FFFFUL) |
280 | #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) | |
cc1ade94 SM |
281 | #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) |
282 | #define MLX4_MPT_PD_FLAG_RAE (1 << 28) | |
283 | #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) | |
284 | ||
285 | #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) | |
286 | ||
287 | #define MLX4_MPT_STATUS_SW 0xF0 | |
288 | #define MLX4_MPT_STATUS_HW 0x00 | |
289 | ||
77507aa2 IS |
290 | #define MLX4_CQE_SIZE_MASK_STRIDE 0x3 |
291 | #define MLX4_EQE_SIZE_MASK_STRIDE 0x30 | |
292 | ||
c66fa19c MB |
293 | #define MLX4_EQ_ASYNC 0 |
294 | #define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \ | |
295 | !!((int)(vector) >= MLX4_EQ_ASYNC)) | |
296 | #define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \ | |
297 | !!((int)(vector) >= MLX4_EQ_ASYNC)) | |
298 | ||
c82e9aa0 EC |
299 | /* |
300 | * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. | |
301 | */ | |
302 | struct mlx4_mpt_entry { | |
303 | __be32 flags; | |
304 | __be32 qpn; | |
305 | __be32 key; | |
306 | __be32 pd_flags; | |
307 | __be64 start; | |
308 | __be64 length; | |
309 | __be32 lkey; | |
310 | __be32 win_cnt; | |
311 | u8 reserved1[3]; | |
312 | u8 mtt_rep; | |
2b8fb286 | 313 | __be64 mtt_addr; |
c82e9aa0 EC |
314 | __be32 mtt_sz; |
315 | __be32 entity_size; | |
316 | __be32 first_byte_offset; | |
317 | } __packed; | |
318 | ||
319 | /* | |
320 | * Must be packed because start is 64 bits but only aligned to 32 bits. | |
321 | */ | |
322 | struct mlx4_eq_context { | |
323 | __be32 flags; | |
324 | u16 reserved1[3]; | |
325 | __be16 page_offset; | |
326 | u8 log_eq_size; | |
327 | u8 reserved2[4]; | |
328 | u8 eq_period; | |
329 | u8 reserved3; | |
330 | u8 eq_max_count; | |
331 | u8 reserved4[3]; | |
332 | u8 intr; | |
333 | u8 log_page_size; | |
334 | u8 reserved5[2]; | |
335 | u8 mtt_base_addr_h; | |
336 | __be32 mtt_base_addr_l; | |
337 | u32 reserved6[2]; | |
338 | __be32 consumer_index; | |
339 | __be32 producer_index; | |
340 | u32 reserved7[4]; | |
341 | }; | |
342 | ||
343 | struct mlx4_cq_context { | |
344 | __be32 flags; | |
345 | u16 reserved1[3]; | |
346 | __be16 page_offset; | |
347 | __be32 logsize_usrpage; | |
348 | __be16 cq_period; | |
349 | __be16 cq_max_count; | |
350 | u8 reserved2[3]; | |
351 | u8 comp_eqn; | |
352 | u8 log_page_size; | |
353 | u8 reserved3[2]; | |
354 | u8 mtt_base_addr_h; | |
355 | __be32 mtt_base_addr_l; | |
356 | __be32 last_notified_index; | |
357 | __be32 solicit_producer_index; | |
358 | __be32 consumer_index; | |
359 | __be32 producer_index; | |
360 | u32 reserved4[2]; | |
361 | __be64 db_rec_addr; | |
362 | }; | |
363 | ||
364 | struct mlx4_srq_context { | |
365 | __be32 state_logsize_srqn; | |
366 | u8 logstride; | |
367 | u8 reserved1; | |
368 | __be16 xrcd; | |
369 | __be32 pg_offset_cqn; | |
370 | u32 reserved2; | |
371 | u8 log_page_size; | |
372 | u8 reserved3[2]; | |
373 | u8 mtt_base_addr_h; | |
374 | __be32 mtt_base_addr_l; | |
375 | __be32 pd; | |
376 | __be16 limit_watermark; | |
377 | __be16 wqe_cnt; | |
378 | u16 reserved4; | |
379 | __be16 wqe_counter; | |
380 | u32 reserved5; | |
381 | __be64 db_rec_addr; | |
382 | }; | |
383 | ||
3dca0f42 MB |
384 | struct mlx4_eq_tasklet { |
385 | struct list_head list; | |
386 | struct list_head process_list; | |
387 | struct tasklet_struct task; | |
388 | /* lock on completion tasklet list */ | |
389 | spinlock_t lock; | |
390 | }; | |
391 | ||
225c7b1f RD |
392 | struct mlx4_eq { |
393 | struct mlx4_dev *dev; | |
394 | void __iomem *doorbell; | |
395 | int eqn; | |
396 | u32 cons_index; | |
397 | u16 irq; | |
398 | u16 have_irq; | |
399 | int nent; | |
400 | struct mlx4_buf_list *page_list; | |
401 | struct mlx4_mtt mtt; | |
3dca0f42 | 402 | struct mlx4_eq_tasklet tasklet_ctx; |
c66fa19c MB |
403 | struct mlx4_active_ports actv_ports; |
404 | u32 ref_count; | |
de161803 | 405 | cpumask_var_t affinity_mask; |
225c7b1f RD |
406 | }; |
407 | ||
623ed84b JM |
408 | struct mlx4_slave_eqe { |
409 | u8 type; | |
410 | u8 port; | |
411 | u32 param; | |
412 | }; | |
413 | ||
414 | struct mlx4_slave_event_eq_info { | |
803143fb | 415 | int eqn; |
623ed84b | 416 | u16 token; |
623ed84b JM |
417 | }; |
418 | ||
225c7b1f RD |
419 | struct mlx4_profile { |
420 | int num_qp; | |
421 | int rdmarc_per_qp; | |
422 | int num_srq; | |
423 | int num_cq; | |
424 | int num_mcg; | |
425 | int num_mpt; | |
db5a7a65 | 426 | unsigned num_mtt; |
225c7b1f RD |
427 | }; |
428 | ||
429 | struct mlx4_fw { | |
430 | u64 clr_int_base; | |
431 | u64 catas_offset; | |
623ed84b | 432 | u64 comm_base; |
ddd8a6c1 | 433 | u64 clock_offset; |
225c7b1f RD |
434 | struct mlx4_icm *fw_icm; |
435 | struct mlx4_icm *aux_icm; | |
436 | u32 catas_size; | |
437 | u16 fw_pages; | |
438 | u8 clr_int_bar; | |
439 | u8 catas_bar; | |
623ed84b | 440 | u8 comm_bar; |
ddd8a6c1 | 441 | u8 clock_bar; |
623ed84b JM |
442 | }; |
443 | ||
444 | struct mlx4_comm { | |
445 | u32 slave_write; | |
446 | u32 slave_read; | |
225c7b1f RD |
447 | }; |
448 | ||
ffe455ad EE |
449 | enum { |
450 | MLX4_MCAST_CONFIG = 0, | |
451 | MLX4_MCAST_DISABLE = 1, | |
452 | MLX4_MCAST_ENABLE = 2, | |
453 | }; | |
454 | ||
623ed84b JM |
455 | #define VLAN_FLTR_SIZE 128 |
456 | ||
457 | struct mlx4_vlan_fltr { | |
458 | __be32 entry[VLAN_FLTR_SIZE]; | |
459 | }; | |
460 | ||
ffe455ad EE |
461 | struct mlx4_mcast_entry { |
462 | struct list_head list; | |
463 | u64 addr; | |
464 | }; | |
465 | ||
b12d93d6 YP |
466 | struct mlx4_promisc_qp { |
467 | struct list_head list; | |
468 | u32 qpn; | |
469 | }; | |
470 | ||
471 | struct mlx4_steer_index { | |
472 | struct list_head list; | |
473 | unsigned int index; | |
474 | struct list_head duplicates; | |
475 | }; | |
476 | ||
803143fb MA |
477 | #define MLX4_EVENT_TYPES_NUM 64 |
478 | ||
623ed84b JM |
479 | struct mlx4_slave_state { |
480 | u8 comm_toggle; | |
481 | u8 last_cmd; | |
482 | u8 init_port_mask; | |
483 | bool active; | |
2c957ff2 | 484 | bool old_vlan_api; |
b42959dc | 485 | bool vst_qinq_supported; |
623ed84b JM |
486 | u8 function; |
487 | dma_addr_t vhcr_dma; | |
40fb4fc1 | 488 | u16 user_mtu[MLX4_MAX_PORTS + 1]; |
623ed84b JM |
489 | u16 mtu[MLX4_MAX_PORTS + 1]; |
490 | __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; | |
491 | struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; | |
492 | struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; | |
493 | struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; | |
803143fb MA |
494 | /* event type to eq number lookup */ |
495 | struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; | |
623ed84b JM |
496 | u16 eq_pi; |
497 | u16 eq_ci; | |
498 | spinlock_t lock; | |
499 | /*initialized via the kzalloc*/ | |
500 | u8 is_slave_going_down; | |
501 | u32 cookie; | |
993c401e | 502 | enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; |
623ed84b JM |
503 | }; |
504 | ||
0eb62b93 RE |
505 | #define MLX4_VGT 4095 |
506 | #define NO_INDX (-1) | |
507 | ||
508 | struct mlx4_vport_state { | |
509 | u64 mac; | |
510 | u16 default_vlan; | |
511 | u8 default_qos; | |
7c3d21c8 | 512 | __be16 vlan_proto; |
0eb62b93 RE |
513 | u32 tx_rate; |
514 | bool spoofchk; | |
948e306d | 515 | u32 link_state; |
08068cd5 | 516 | u8 qos_vport; |
773af94e | 517 | __be64 guid; |
0eb62b93 RE |
518 | }; |
519 | ||
520 | struct mlx4_vf_admin_state { | |
521 | struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; | |
99ec41d0 | 522 | u8 enable_smi[MLX4_MAX_PORTS + 1]; |
0eb62b93 RE |
523 | }; |
524 | ||
525 | struct mlx4_vport_oper_state { | |
526 | struct mlx4_vport_state state; | |
527 | int mac_idx; | |
528 | int vlan_idx; | |
529 | }; | |
99ec41d0 | 530 | |
0eb62b93 RE |
531 | struct mlx4_vf_oper_state { |
532 | struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; | |
99ec41d0 | 533 | u8 smi_enabled[MLX4_MAX_PORTS + 1]; |
0eb62b93 RE |
534 | }; |
535 | ||
623ed84b JM |
536 | struct slave_list { |
537 | struct mutex mutex; | |
538 | struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; | |
539 | }; | |
540 | ||
5a0d0a61 | 541 | struct resource_allocator { |
146f3ef4 | 542 | spinlock_t alloc_lock; /* protect quotas */ |
5a0d0a61 JM |
543 | union { |
544 | int res_reserved; | |
545 | int res_port_rsvd[MLX4_MAX_PORTS]; | |
546 | }; | |
547 | union { | |
548 | int res_free; | |
549 | int res_port_free[MLX4_MAX_PORTS]; | |
550 | }; | |
551 | int *quota; | |
552 | int *allocated; | |
553 | int *guaranteed; | |
554 | }; | |
555 | ||
623ed84b JM |
556 | struct mlx4_resource_tracker { |
557 | spinlock_t lock; | |
558 | /* tree for each resources */ | |
4af1c048 | 559 | struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; |
623ed84b JM |
560 | /* num_of_slave's lists, one per slave */ |
561 | struct slave_list *slave_list; | |
5a0d0a61 | 562 | struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; |
623ed84b JM |
563 | }; |
564 | ||
565 | #define SLAVE_EVENT_EQ_SIZE 128 | |
566 | struct mlx4_slave_event_eq { | |
567 | u32 eqn; | |
568 | u32 cons; | |
569 | u32 prod; | |
992e8e6e | 570 | spinlock_t event_lock; |
623ed84b JM |
571 | struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; |
572 | }; | |
573 | ||
666672d4 IS |
574 | struct mlx4_qos_manager { |
575 | int num_of_qos_vfs; | |
576 | DECLARE_BITMAP(priority_bm, MLX4_NUM_UP); | |
577 | }; | |
578 | ||
623ed84b JM |
579 | struct mlx4_master_qp0_state { |
580 | int proxy_qp0_active; | |
581 | int qp0_active; | |
582 | int port_active; | |
583 | }; | |
584 | ||
585 | struct mlx4_mfunc_master_ctx { | |
586 | struct mlx4_slave_state *slave_state; | |
0eb62b93 RE |
587 | struct mlx4_vf_admin_state *vf_admin; |
588 | struct mlx4_vf_oper_state *vf_oper; | |
623ed84b JM |
589 | struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; |
590 | int init_port_ref[MLX4_MAX_PORTS + 1]; | |
591 | u16 max_mtu[MLX4_MAX_PORTS + 1]; | |
40fb4fc1 | 592 | u16 max_user_mtu[MLX4_MAX_PORTS + 1]; |
2a500090 EE |
593 | u8 pptx; |
594 | u8 pprx; | |
623ed84b JM |
595 | int disable_mcast_ref[MLX4_MAX_PORTS + 1]; |
596 | struct mlx4_resource_tracker res_tracker; | |
597 | struct workqueue_struct *comm_wq; | |
598 | struct work_struct comm_work; | |
599 | struct work_struct slave_event_work; | |
600 | struct work_struct slave_flr_event_work; | |
601 | spinlock_t slave_state_lock; | |
f5311ac1 | 602 | __be32 comm_arm_bit_vector[4]; |
623ed84b JM |
603 | struct mlx4_eqe cmd_eqe; |
604 | struct mlx4_slave_event_eq slave_eq; | |
605 | struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; | |
666672d4 | 606 | struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1]; |
623ed84b JM |
607 | }; |
608 | ||
609 | struct mlx4_mfunc { | |
610 | struct mlx4_comm __iomem *comm; | |
611 | struct mlx4_vhcr_cmd *vhcr; | |
612 | dma_addr_t vhcr_dma; | |
613 | ||
614 | struct mlx4_mfunc_master_ctx master; | |
615 | }; | |
616 | ||
fe6f700d YP |
617 | #define MGM_QPN_MASK 0x00FFFFFF |
618 | #define MGM_BLCK_LB_BIT 30 | |
619 | ||
620 | struct mlx4_mgm { | |
621 | __be32 next_gid_index; | |
622 | __be32 members_count; | |
623 | u32 reserved[2]; | |
624 | u8 gid[16]; | |
625 | __be32 qp[MLX4_MAX_QP_PER_MGM]; | |
626 | }; | |
627 | ||
225c7b1f RD |
628 | struct mlx4_cmd { |
629 | struct pci_pool *pool; | |
630 | void __iomem *hcr; | |
f3d4c89e | 631 | struct mutex slave_cmd_mutex; |
225c7b1f RD |
632 | struct semaphore poll_sem; |
633 | struct semaphore event_sem; | |
a7e1f049 | 634 | struct rw_semaphore switch_sem; |
225c7b1f RD |
635 | int max_cmds; |
636 | spinlock_t context_lock; | |
637 | int free_head; | |
638 | struct mlx4_cmd_context *context; | |
639 | u16 token_mask; | |
640 | u8 use_events; | |
641 | u8 toggle; | |
623ed84b | 642 | u8 comm_toggle; |
ffc39f6d | 643 | u8 initialized; |
225c7b1f RD |
644 | }; |
645 | ||
b01978ca JM |
646 | enum { |
647 | MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, | |
648 | MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, | |
0a6eac24 | 649 | MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, |
b01978ca JM |
650 | }; |
651 | struct mlx4_vf_immed_vlan_work { | |
652 | struct work_struct work; | |
653 | struct mlx4_priv *priv; | |
654 | int flags; | |
655 | int slave; | |
656 | int vlan_ix; | |
657 | int orig_vlan_ix; | |
658 | u8 port; | |
659 | u8 qos; | |
08068cd5 | 660 | u8 qos_vport; |
b01978ca JM |
661 | u16 vlan_id; |
662 | u16 orig_vlan_id; | |
7c3d21c8 | 663 | __be16 vlan_proto; |
b01978ca JM |
664 | }; |
665 | ||
666 | ||
225c7b1f RD |
667 | struct mlx4_uar_table { |
668 | struct mlx4_bitmap bitmap; | |
669 | }; | |
670 | ||
671 | struct mlx4_mr_table { | |
672 | struct mlx4_bitmap mpt_bitmap; | |
673 | struct mlx4_buddy mtt_buddy; | |
674 | u64 mtt_base; | |
675 | u64 mpt_base; | |
676 | struct mlx4_icm_table mtt_table; | |
677 | struct mlx4_icm_table dmpt_table; | |
678 | }; | |
679 | ||
680 | struct mlx4_cq_table { | |
681 | struct mlx4_bitmap bitmap; | |
682 | spinlock_t lock; | |
683 | struct radix_tree_root tree; | |
684 | struct mlx4_icm_table table; | |
685 | struct mlx4_icm_table cmpt_table; | |
686 | }; | |
687 | ||
688 | struct mlx4_eq_table { | |
689 | struct mlx4_bitmap bitmap; | |
b8dd786f | 690 | char *irq_names; |
225c7b1f | 691 | void __iomem *clr_int; |
b8dd786f | 692 | void __iomem **uar_map; |
225c7b1f | 693 | u32 clr_mask; |
b8dd786f | 694 | struct mlx4_eq *eq; |
fa0681d2 | 695 | struct mlx4_icm_table table; |
225c7b1f RD |
696 | struct mlx4_icm_table cmpt_table; |
697 | int have_irq; | |
698 | u8 inta_pin; | |
699 | }; | |
700 | ||
701 | struct mlx4_srq_table { | |
702 | struct mlx4_bitmap bitmap; | |
703 | spinlock_t lock; | |
704 | struct radix_tree_root tree; | |
705 | struct mlx4_icm_table table; | |
706 | struct mlx4_icm_table cmpt_table; | |
707 | }; | |
708 | ||
d57febe1 MB |
709 | enum mlx4_qp_table_zones { |
710 | MLX4_QP_TABLE_ZONE_GENERAL, | |
711 | MLX4_QP_TABLE_ZONE_RSS, | |
712 | MLX4_QP_TABLE_ZONE_RAW_ETH, | |
713 | MLX4_QP_TABLE_ZONE_NUM | |
714 | }; | |
715 | ||
225c7b1f | 716 | struct mlx4_qp_table { |
d57febe1 MB |
717 | struct mlx4_bitmap *bitmap_gen; |
718 | struct mlx4_zone_allocator *zones; | |
719 | u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM]; | |
225c7b1f RD |
720 | u32 rdmarc_base; |
721 | int rdmarc_shift; | |
722 | spinlock_t lock; | |
723 | struct mlx4_icm_table qp_table; | |
724 | struct mlx4_icm_table auxc_table; | |
725 | struct mlx4_icm_table altc_table; | |
726 | struct mlx4_icm_table rdmarc_table; | |
727 | struct mlx4_icm_table cmpt_table; | |
728 | }; | |
729 | ||
730 | struct mlx4_mcg_table { | |
731 | struct mutex mutex; | |
732 | struct mlx4_bitmap bitmap; | |
733 | struct mlx4_icm_table table; | |
734 | }; | |
735 | ||
736 | struct mlx4_catas_err { | |
737 | u32 __iomem *map; | |
ee49bd93 JM |
738 | struct timer_list timer; |
739 | struct list_head list; | |
225c7b1f RD |
740 | }; |
741 | ||
2a2336f8 YP |
742 | #define MLX4_MAX_MAC_NUM 128 |
743 | #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) | |
744 | ||
745 | struct mlx4_mac_table { | |
746 | __be64 entries[MLX4_MAX_MAC_NUM]; | |
747 | int refs[MLX4_MAX_MAC_NUM]; | |
5f61385d | 748 | bool is_dup[MLX4_MAX_MAC_NUM]; |
2a2336f8 YP |
749 | struct mutex mutex; |
750 | int total; | |
751 | int max; | |
752 | }; | |
753 | ||
111c6094 JM |
754 | #define MLX4_ROCE_GID_ENTRY_SIZE 16 |
755 | ||
756 | struct mlx4_roce_gid_entry { | |
757 | u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; | |
758 | }; | |
759 | ||
760 | struct mlx4_roce_gid_table { | |
761 | struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; | |
762 | struct mutex mutex; | |
763 | }; | |
764 | ||
2a2336f8 YP |
765 | #define MLX4_MAX_VLAN_NUM 128 |
766 | #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) | |
767 | ||
768 | struct mlx4_vlan_table { | |
769 | __be32 entries[MLX4_MAX_VLAN_NUM]; | |
770 | int refs[MLX4_MAX_VLAN_NUM]; | |
5f61385d | 771 | int is_dup[MLX4_MAX_VLAN_NUM]; |
2a2336f8 YP |
772 | struct mutex mutex; |
773 | int total; | |
774 | int max; | |
775 | }; | |
776 | ||
1f8176f7 SD |
777 | #define SET_PORT_GEN_ALL_VALID (MLX4_FLAG_V_MTU_MASK | \ |
778 | MLX4_FLAG_V_PPRX_MASK | \ | |
779 | MLX4_FLAG_V_PPTX_MASK) | |
ffe455ad EE |
780 | #define SET_PORT_PROMISC_SHIFT 31 |
781 | #define SET_PORT_MC_PROMISC_SHIFT 30 | |
782 | ||
783 | enum { | |
784 | MCAST_DIRECT_ONLY = 0, | |
785 | MCAST_DIRECT = 1, | |
786 | MCAST_DEFAULT = 2 | |
787 | }; | |
788 | ||
789 | ||
790 | struct mlx4_set_port_general_context { | |
78500b8c | 791 | u16 reserved1; |
40fb4fc1 | 792 | u8 flags2; |
ffe455ad | 793 | u8 flags; |
1da494cb MS |
794 | union { |
795 | u8 ignore_fcs; | |
796 | u8 roce_mode; | |
797 | }; | |
78500b8c | 798 | u8 reserved2; |
ffe455ad EE |
799 | __be16 mtu; |
800 | u8 pptx; | |
801 | u8 pfctx; | |
802 | u16 reserved3; | |
803 | u8 pprx; | |
804 | u8 pfcrx; | |
805 | u16 reserved4; | |
77fc29c4 HHZ |
806 | u32 reserved5; |
807 | u8 phv_en; | |
40fb4fc1 SD |
808 | u8 reserved6[5]; |
809 | __be16 user_mtu; | |
ffe455ad EE |
810 | }; |
811 | ||
812 | struct mlx4_set_port_rqp_calc_context { | |
813 | __be32 base_qpn; | |
814 | u8 rererved; | |
815 | u8 n_mac; | |
816 | u8 n_vlan; | |
817 | u8 n_prio; | |
818 | u8 reserved2[3]; | |
819 | u8 mac_miss; | |
820 | u8 intra_no_vlan; | |
821 | u8 no_vlan; | |
822 | u8 intra_vlan_miss; | |
823 | u8 vlan_miss; | |
824 | u8 reserved3[3]; | |
825 | u8 no_vlan_prio; | |
826 | __be32 promisc; | |
827 | __be32 mcast; | |
828 | }; | |
829 | ||
2a2336f8 YP |
830 | struct mlx4_port_info { |
831 | struct mlx4_dev *dev; | |
832 | int port; | |
7ff93f8b YP |
833 | char dev_name[16]; |
834 | struct device_attribute port_attr; | |
835 | enum mlx4_port_type tmp_type; | |
096335b3 OG |
836 | char dev_mtu_name[16]; |
837 | struct device_attribute port_mtu_attr; | |
2a2336f8 YP |
838 | struct mlx4_mac_table mac_table; |
839 | struct mlx4_vlan_table vlan_table; | |
111c6094 | 840 | struct mlx4_roce_gid_table gid_table; |
1679200f | 841 | int base_qpn; |
c66fa19c | 842 | struct cpu_rmap *rmap; |
09d4d087 | 843 | struct devlink_port devlink_port; |
2a2336f8 YP |
844 | }; |
845 | ||
27bf91d6 YP |
846 | struct mlx4_sense { |
847 | struct mlx4_dev *dev; | |
848 | u8 do_sense_port[MLX4_MAX_PORTS + 1]; | |
849 | u8 sense_allowed[MLX4_MAX_PORTS + 1]; | |
850 | struct delayed_work sense_poll; | |
851 | }; | |
852 | ||
0b7ca5a9 | 853 | struct mlx4_msix_ctl { |
c66fa19c | 854 | DECLARE_BITMAP(pool_bm, MAX_MSIX); |
730c41d5 | 855 | struct mutex pool_lock; |
0b7ca5a9 YP |
856 | }; |
857 | ||
b12d93d6 YP |
858 | struct mlx4_steer { |
859 | struct list_head promisc_qps[MLX4_NUM_STEERS]; | |
860 | struct list_head steer_entries[MLX4_NUM_STEERS]; | |
b12d93d6 YP |
861 | }; |
862 | ||
839f1243 RD |
863 | enum { |
864 | MLX4_PCI_DEV_IS_VF = 1 << 0, | |
ca3e57a5 | 865 | MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, |
839f1243 RD |
866 | }; |
867 | ||
7c6d74d2 JM |
868 | enum { |
869 | MLX4_NO_RR = 0, | |
870 | MLX4_USE_RR = 1, | |
871 | }; | |
872 | ||
225c7b1f RD |
873 | struct mlx4_priv { |
874 | struct mlx4_dev dev; | |
875 | ||
876 | struct list_head dev_list; | |
877 | struct list_head ctx_list; | |
878 | spinlock_t ctx_lock; | |
879 | ||
839f1243 | 880 | int pci_dev_data; |
befdf897 | 881 | int removed; |
839f1243 | 882 | |
6296883c YP |
883 | struct list_head pgdir_list; |
884 | struct mutex pgdir_mutex; | |
885 | ||
225c7b1f RD |
886 | struct mlx4_fw fw; |
887 | struct mlx4_cmd cmd; | |
623ed84b | 888 | struct mlx4_mfunc mfunc; |
225c7b1f RD |
889 | |
890 | struct mlx4_bitmap pd_bitmap; | |
012a8ff5 | 891 | struct mlx4_bitmap xrcd_bitmap; |
225c7b1f RD |
892 | struct mlx4_uar_table uar_table; |
893 | struct mlx4_mr_table mr_table; | |
894 | struct mlx4_cq_table cq_table; | |
895 | struct mlx4_eq_table eq_table; | |
896 | struct mlx4_srq_table srq_table; | |
897 | struct mlx4_qp_table qp_table; | |
898 | struct mlx4_mcg_table mcg_table; | |
f2a3f6a3 | 899 | struct mlx4_bitmap counters_bitmap; |
6de5f7f6 | 900 | int def_counter[MLX4_MAX_PORTS]; |
225c7b1f RD |
901 | |
902 | struct mlx4_catas_err catas_err; | |
903 | ||
904 | void __iomem *clr_base; | |
905 | ||
906 | struct mlx4_uar driver_uar; | |
907 | void __iomem *kar; | |
2a2336f8 | 908 | struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 909 | struct mlx4_sense sense; |
7ff93f8b | 910 | struct mutex port_mutex; |
0b7ca5a9 | 911 | struct mlx4_msix_ctl msix_ctl; |
b12d93d6 | 912 | struct mlx4_steer *steer; |
c1b43dca EC |
913 | struct list_head bf_list; |
914 | struct mutex bf_mutex; | |
915 | struct io_mapping *bf_mapping; | |
ddd8a6c1 | 916 | void __iomem *clock_mapping; |
ea51b377 | 917 | int reserved_mtts; |
0ff1fb65 | 918 | int fs_hash_mode; |
54679e14 | 919 | u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; |
53f33ae2 MS |
920 | struct mlx4_port_map v2p; /* cached port mapping configuration */ |
921 | struct mutex bond_mutex; /* for bond mode */ | |
afa8fd1d | 922 | __be64 slave_node_guids[MLX4_MFUNC_MAX]; |
54679e14 | 923 | |
fe6f700d YP |
924 | atomic_t opreq_count; |
925 | struct work_struct opreq_task; | |
225c7b1f RD |
926 | }; |
927 | ||
928 | static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) | |
929 | { | |
930 | return container_of(dev, struct mlx4_priv, dev); | |
931 | } | |
932 | ||
27bf91d6 YP |
933 | #define MLX4_SENSE_RANGE (HZ * 3) |
934 | ||
935 | extern struct workqueue_struct *mlx4_wq; | |
936 | ||
225c7b1f | 937 | u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); |
7c6d74d2 | 938 | void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); |
ddae0349 EE |
939 | u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, |
940 | int align, u32 skip_mask); | |
7c6d74d2 JM |
941 | void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, |
942 | int use_rr); | |
42d1e017 | 943 | u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); |
93fc9e1b YP |
944 | int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, |
945 | u32 reserved_bot, u32 resetrved_top); | |
225c7b1f RD |
946 | void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); |
947 | ||
948 | int mlx4_reset(struct mlx4_dev *dev); | |
949 | ||
b8dd786f YP |
950 | int mlx4_alloc_eq_table(struct mlx4_dev *dev); |
951 | void mlx4_free_eq_table(struct mlx4_dev *dev); | |
952 | ||
225c7b1f | 953 | int mlx4_init_pd_table(struct mlx4_dev *dev); |
012a8ff5 | 954 | int mlx4_init_xrcd_table(struct mlx4_dev *dev); |
225c7b1f RD |
955 | int mlx4_init_uar_table(struct mlx4_dev *dev); |
956 | int mlx4_init_mr_table(struct mlx4_dev *dev); | |
957 | int mlx4_init_eq_table(struct mlx4_dev *dev); | |
958 | int mlx4_init_cq_table(struct mlx4_dev *dev); | |
959 | int mlx4_init_qp_table(struct mlx4_dev *dev); | |
960 | int mlx4_init_srq_table(struct mlx4_dev *dev); | |
961 | int mlx4_init_mcg_table(struct mlx4_dev *dev); | |
962 | ||
963 | void mlx4_cleanup_pd_table(struct mlx4_dev *dev); | |
012a8ff5 | 964 | void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); |
225c7b1f RD |
965 | void mlx4_cleanup_uar_table(struct mlx4_dev *dev); |
966 | void mlx4_cleanup_mr_table(struct mlx4_dev *dev); | |
967 | void mlx4_cleanup_eq_table(struct mlx4_dev *dev); | |
968 | void mlx4_cleanup_cq_table(struct mlx4_dev *dev); | |
969 | void mlx4_cleanup_qp_table(struct mlx4_dev *dev); | |
970 | void mlx4_cleanup_srq_table(struct mlx4_dev *dev); | |
971 | void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); | |
8900b894 | 972 | int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); |
c82e9aa0 EC |
973 | void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); |
974 | int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); | |
975 | void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); | |
976 | int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); | |
977 | void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); | |
b20e519a SM |
978 | int __mlx4_mpt_reserve(struct mlx4_dev *dev); |
979 | void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); | |
8900b894 | 980 | int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index); |
b20e519a | 981 | void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); |
c82e9aa0 EC |
982 | u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); |
983 | void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); | |
225c7b1f | 984 | |
623ed84b JM |
985 | int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, |
986 | struct mlx4_vhcr *vhcr, | |
987 | struct mlx4_cmd_mailbox *inbox, | |
988 | struct mlx4_cmd_mailbox *outbox, | |
989 | struct mlx4_cmd_info *cmd); | |
990 | int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, | |
991 | struct mlx4_vhcr *vhcr, | |
992 | struct mlx4_cmd_mailbox *inbox, | |
993 | struct mlx4_cmd_mailbox *outbox, | |
994 | struct mlx4_cmd_info *cmd); | |
995 | int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
996 | struct mlx4_vhcr *vhcr, | |
997 | struct mlx4_cmd_mailbox *inbox, | |
998 | struct mlx4_cmd_mailbox *outbox, | |
999 | struct mlx4_cmd_info *cmd); | |
1000 | int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
1001 | struct mlx4_vhcr *vhcr, | |
1002 | struct mlx4_cmd_mailbox *inbox, | |
1003 | struct mlx4_cmd_mailbox *outbox, | |
1004 | struct mlx4_cmd_info *cmd); | |
1005 | int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
1006 | struct mlx4_vhcr *vhcr, | |
1007 | struct mlx4_cmd_mailbox *inbox, | |
1008 | struct mlx4_cmd_mailbox *outbox, | |
1009 | struct mlx4_cmd_info *cmd); | |
1010 | int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1011 | struct mlx4_vhcr *vhcr, | |
1012 | struct mlx4_cmd_mailbox *inbox, | |
1013 | struct mlx4_cmd_mailbox *outbox, | |
1014 | struct mlx4_cmd_info *cmd); | |
d475c95b MB |
1015 | int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, |
1016 | struct mlx4_vhcr *vhcr, | |
1017 | struct mlx4_cmd_mailbox *inbox, | |
1018 | struct mlx4_cmd_mailbox *outbox, | |
1019 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1020 | int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, |
1021 | struct mlx4_vhcr *vhcr, | |
1022 | struct mlx4_cmd_mailbox *inbox, | |
1023 | struct mlx4_cmd_mailbox *outbox, | |
1024 | struct mlx4_cmd_info *cmd); | |
c82e9aa0 | 1025 | int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, |
ddae0349 | 1026 | int *base, u8 flags); |
c82e9aa0 EC |
1027 | void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); |
1028 | int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
1029 | void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
c82e9aa0 EC |
1030 | int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
1031 | int start_index, int npages, u64 *page_list); | |
ba062d52 JM |
1032 | int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
1033 | void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
62a89055 EBE |
1034 | int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port, |
1035 | struct mlx4_counter *data); | |
ba062d52 JM |
1036 | int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
1037 | void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
623ed84b | 1038 | |
ee49bd93 JM |
1039 | void mlx4_start_catas_poll(struct mlx4_dev *dev); |
1040 | void mlx4_stop_catas_poll(struct mlx4_dev *dev); | |
ad9a0bf0 YH |
1041 | int mlx4_catas_init(struct mlx4_dev *dev); |
1042 | void mlx4_catas_end(struct mlx4_dev *dev); | |
ee49bd93 | 1043 | int mlx4_restart_one(struct pci_dev *pdev); |
225c7b1f RD |
1044 | int mlx4_register_device(struct mlx4_dev *dev); |
1045 | void mlx4_unregister_device(struct mlx4_dev *dev); | |
00f5ce99 JM |
1046 | void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, |
1047 | unsigned long param); | |
225c7b1f RD |
1048 | |
1049 | struct mlx4_dev_cap; | |
1050 | struct mlx4_init_hca_param; | |
1051 | ||
1052 | u64 mlx4_make_profile(struct mlx4_dev *dev, | |
1053 | struct mlx4_profile *request, | |
1054 | struct mlx4_dev_cap *dev_cap, | |
1055 | struct mlx4_init_hca_param *init_hca); | |
623ed84b JM |
1056 | void mlx4_master_comm_channel(struct work_struct *work); |
1057 | void mlx4_gen_slave_eqe(struct work_struct *work); | |
1058 | void mlx4_master_handle_slave_flr(struct work_struct *work); | |
1059 | ||
1060 | int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, | |
1061 | struct mlx4_vhcr *vhcr, | |
1062 | struct mlx4_cmd_mailbox *inbox, | |
1063 | struct mlx4_cmd_mailbox *outbox, | |
1064 | struct mlx4_cmd_info *cmd); | |
1065 | int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, | |
1066 | struct mlx4_vhcr *vhcr, | |
1067 | struct mlx4_cmd_mailbox *inbox, | |
1068 | struct mlx4_cmd_mailbox *outbox, | |
1069 | struct mlx4_cmd_info *cmd); | |
1070 | int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1071 | struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, | |
1072 | struct mlx4_cmd_mailbox *outbox, | |
1073 | struct mlx4_cmd_info *cmd); | |
1074 | int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, | |
1075 | struct mlx4_vhcr *vhcr, | |
1076 | struct mlx4_cmd_mailbox *inbox, | |
1077 | struct mlx4_cmd_mailbox *outbox, | |
1078 | struct mlx4_cmd_info *cmd); | |
1079 | int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1080 | struct mlx4_vhcr *vhcr, | |
1081 | struct mlx4_cmd_mailbox *inbox, | |
1082 | struct mlx4_cmd_mailbox *outbox, | |
1083 | struct mlx4_cmd_info *cmd); | |
1084 | int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1085 | struct mlx4_vhcr *vhcr, | |
1086 | struct mlx4_cmd_mailbox *inbox, | |
1087 | struct mlx4_cmd_mailbox *outbox, | |
1088 | struct mlx4_cmd_info *cmd); | |
1089 | int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1090 | struct mlx4_vhcr *vhcr, | |
1091 | struct mlx4_cmd_mailbox *inbox, | |
1092 | struct mlx4_cmd_mailbox *outbox, | |
1093 | struct mlx4_cmd_info *cmd); | |
1094 | int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1095 | struct mlx4_vhcr *vhcr, | |
1096 | struct mlx4_cmd_mailbox *inbox, | |
1097 | struct mlx4_cmd_mailbox *outbox, | |
1098 | struct mlx4_cmd_info *cmd); | |
1099 | int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1100 | struct mlx4_vhcr *vhcr, | |
1101 | struct mlx4_cmd_mailbox *inbox, | |
1102 | struct mlx4_cmd_mailbox *outbox, | |
1103 | struct mlx4_cmd_info *cmd); | |
1104 | int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1105 | struct mlx4_vhcr *vhcr, | |
1106 | struct mlx4_cmd_mailbox *inbox, | |
1107 | struct mlx4_cmd_mailbox *outbox, | |
1108 | struct mlx4_cmd_info *cmd); | |
1109 | int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1110 | struct mlx4_vhcr *vhcr, | |
1111 | struct mlx4_cmd_mailbox *inbox, | |
1112 | struct mlx4_cmd_mailbox *outbox, | |
1113 | struct mlx4_cmd_info *cmd); | |
1114 | int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1115 | struct mlx4_vhcr *vhcr, | |
1116 | struct mlx4_cmd_mailbox *inbox, | |
1117 | struct mlx4_cmd_mailbox *outbox, | |
1118 | struct mlx4_cmd_info *cmd); | |
1119 | int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1120 | struct mlx4_vhcr *vhcr, | |
1121 | struct mlx4_cmd_mailbox *inbox, | |
1122 | struct mlx4_cmd_mailbox *outbox, | |
1123 | struct mlx4_cmd_info *cmd); | |
1124 | int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1125 | struct mlx4_vhcr *vhcr, | |
1126 | struct mlx4_cmd_mailbox *inbox, | |
1127 | struct mlx4_cmd_mailbox *outbox, | |
1128 | struct mlx4_cmd_info *cmd); | |
1129 | int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1130 | struct mlx4_vhcr *vhcr, | |
1131 | struct mlx4_cmd_mailbox *inbox, | |
1132 | struct mlx4_cmd_mailbox *outbox, | |
1133 | struct mlx4_cmd_info *cmd); | |
1134 | int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1135 | struct mlx4_vhcr *vhcr, | |
1136 | struct mlx4_cmd_mailbox *inbox, | |
1137 | struct mlx4_cmd_mailbox *outbox, | |
1138 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1139 | int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, |
1140 | struct mlx4_vhcr *vhcr, | |
1141 | struct mlx4_cmd_mailbox *inbox, | |
1142 | struct mlx4_cmd_mailbox *outbox, | |
1143 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1144 | int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, |
1145 | struct mlx4_vhcr *vhcr, | |
1146 | struct mlx4_cmd_mailbox *inbox, | |
1147 | struct mlx4_cmd_mailbox *outbox, | |
1148 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1149 | int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, |
1150 | struct mlx4_vhcr *vhcr, | |
1151 | struct mlx4_cmd_mailbox *inbox, | |
1152 | struct mlx4_cmd_mailbox *outbox, | |
1153 | struct mlx4_cmd_info *cmd); | |
1154 | int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1155 | struct mlx4_vhcr *vhcr, | |
1156 | struct mlx4_cmd_mailbox *inbox, | |
1157 | struct mlx4_cmd_mailbox *outbox, | |
1158 | struct mlx4_cmd_info *cmd); | |
1159 | int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1160 | struct mlx4_vhcr *vhcr, | |
1161 | struct mlx4_cmd_mailbox *inbox, | |
1162 | struct mlx4_cmd_mailbox *outbox, | |
1163 | struct mlx4_cmd_info *cmd); | |
1164 | int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1165 | struct mlx4_vhcr *vhcr, | |
1166 | struct mlx4_cmd_mailbox *inbox, | |
1167 | struct mlx4_cmd_mailbox *outbox, | |
1168 | struct mlx4_cmd_info *cmd); | |
1169 | int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1170 | struct mlx4_vhcr *vhcr, | |
1171 | struct mlx4_cmd_mailbox *inbox, | |
1172 | struct mlx4_cmd_mailbox *outbox, | |
1173 | struct mlx4_cmd_info *cmd); | |
1174 | int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1175 | struct mlx4_vhcr *vhcr, | |
1176 | struct mlx4_cmd_mailbox *inbox, | |
1177 | struct mlx4_cmd_mailbox *outbox, | |
1178 | struct mlx4_cmd_info *cmd); | |
1179 | int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1180 | struct mlx4_vhcr *vhcr, | |
1181 | struct mlx4_cmd_mailbox *inbox, | |
1182 | struct mlx4_cmd_mailbox *outbox, | |
1183 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1184 | int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, |
1185 | struct mlx4_vhcr *vhcr, | |
1186 | struct mlx4_cmd_mailbox *inbox, | |
1187 | struct mlx4_cmd_mailbox *outbox, | |
1188 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1189 | int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, |
1190 | struct mlx4_vhcr *vhcr, | |
1191 | struct mlx4_cmd_mailbox *inbox, | |
1192 | struct mlx4_cmd_mailbox *outbox, | |
1193 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1194 | |
1195 | int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); | |
225c7b1f | 1196 | |
ffc39f6d MB |
1197 | enum { |
1198 | MLX4_CMD_CLEANUP_STRUCT = 1UL << 0, | |
1199 | MLX4_CMD_CLEANUP_POOL = 1UL << 1, | |
1200 | MLX4_CMD_CLEANUP_HCR = 1UL << 2, | |
1201 | MLX4_CMD_CLEANUP_VHCR = 1UL << 3, | |
1202 | MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1 | |
1203 | }; | |
1204 | ||
225c7b1f | 1205 | int mlx4_cmd_init(struct mlx4_dev *dev); |
ffc39f6d | 1206 | void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask); |
ab9c17a0 | 1207 | int mlx4_multi_func_init(struct mlx4_dev *dev); |
55ad3592 | 1208 | int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev); |
ab9c17a0 | 1209 | void mlx4_multi_func_cleanup(struct mlx4_dev *dev); |
225c7b1f RD |
1210 | void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); |
1211 | int mlx4_cmd_use_events(struct mlx4_dev *dev); | |
1212 | void mlx4_cmd_use_polling(struct mlx4_dev *dev); | |
1213 | ||
ab9c17a0 | 1214 | int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, |
0cd93027 | 1215 | u16 op, unsigned long timeout); |
ab9c17a0 | 1216 | |
3dca0f42 | 1217 | void mlx4_cq_tasklet_cb(unsigned long data); |
225c7b1f RD |
1218 | void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); |
1219 | void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); | |
1220 | ||
1221 | void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); | |
1222 | ||
1223 | void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); | |
1224 | ||
f6bc11e4 | 1225 | void mlx4_enter_error_state(struct mlx4_dev_persistent *persist); |
d585df1c | 1226 | int mlx4_comm_internal_err(u32 slave_read); |
225c7b1f | 1227 | |
ab6dc30d YP |
1228 | int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, |
1229 | enum mlx4_port_type *type); | |
27bf91d6 YP |
1230 | void mlx4_do_sense_ports(struct mlx4_dev *dev, |
1231 | enum mlx4_port_type *stype, | |
1232 | enum mlx4_port_type *defaults); | |
1233 | void mlx4_start_sense(struct mlx4_dev *dev); | |
1234 | void mlx4_stop_sense(struct mlx4_dev *dev); | |
1235 | void mlx4_sense_init(struct mlx4_dev *dev); | |
1236 | int mlx4_check_port_params(struct mlx4_dev *dev, | |
1237 | enum mlx4_port_type *port_type); | |
1238 | int mlx4_change_port_types(struct mlx4_dev *dev, | |
1239 | enum mlx4_port_type *port_types); | |
1240 | ||
2a2336f8 YP |
1241 | void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); |
1242 | void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); | |
111c6094 JM |
1243 | void mlx4_init_roce_gid_table(struct mlx4_dev *dev, |
1244 | struct mlx4_roce_gid_table *table); | |
2009d005 | 1245 | void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
3f7fb021 | 1246 | int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
5f61385d MS |
1247 | int mlx4_bond_vlan_table(struct mlx4_dev *dev); |
1248 | int mlx4_unbond_vlan_table(struct mlx4_dev *dev); | |
1249 | int mlx4_bond_mac_table(struct mlx4_dev *dev); | |
1250 | int mlx4_unbond_mac_table(struct mlx4_dev *dev); | |
2a2336f8 | 1251 | |
6634961c | 1252 | int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); |
623ed84b JM |
1253 | /* resource tracker functions*/ |
1254 | int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, | |
1255 | enum mlx4_resource resource_type, | |
aa1ec3dd | 1256 | u64 resource_id, int *slave); |
623ed84b | 1257 | void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); |
111c6094 | 1258 | void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); |
623ed84b JM |
1259 | int mlx4_init_resource_tracker(struct mlx4_dev *dev); |
1260 | ||
b8924951 JM |
1261 | void mlx4_free_resource_tracker(struct mlx4_dev *dev, |
1262 | enum mlx4_res_tracker_free_type type); | |
623ed84b | 1263 | |
b91cb3eb JM |
1264 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
1265 | struct mlx4_vhcr *vhcr, | |
1266 | struct mlx4_cmd_mailbox *inbox, | |
1267 | struct mlx4_cmd_mailbox *outbox, | |
1268 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1269 | int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1270 | struct mlx4_vhcr *vhcr, | |
1271 | struct mlx4_cmd_mailbox *inbox, | |
1272 | struct mlx4_cmd_mailbox *outbox, | |
1273 | struct mlx4_cmd_info *cmd); | |
1274 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, | |
1275 | struct mlx4_vhcr *vhcr, | |
1276 | struct mlx4_cmd_mailbox *inbox, | |
1277 | struct mlx4_cmd_mailbox *outbox, | |
1278 | struct mlx4_cmd_info *cmd); | |
1279 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, | |
1280 | struct mlx4_vhcr *vhcr, | |
1281 | struct mlx4_cmd_mailbox *inbox, | |
1282 | struct mlx4_cmd_mailbox *outbox, | |
1283 | struct mlx4_cmd_info *cmd); | |
b91cb3eb JM |
1284 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
1285 | struct mlx4_vhcr *vhcr, | |
1286 | struct mlx4_cmd_mailbox *inbox, | |
1287 | struct mlx4_cmd_mailbox *outbox, | |
1288 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1289 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1290 | struct mlx4_vhcr *vhcr, | |
1291 | struct mlx4_cmd_mailbox *inbox, | |
1292 | struct mlx4_cmd_mailbox *outbox, | |
1293 | struct mlx4_cmd_info *cmd); | |
9a5aa622 | 1294 | int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); |
7ff93f8b | 1295 | |
6634961c JM |
1296 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
1297 | int *gid_tbl_len, int *pkey_tbl_len); | |
623ed84b JM |
1298 | |
1299 | int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, | |
1300 | struct mlx4_vhcr *vhcr, | |
1301 | struct mlx4_cmd_mailbox *inbox, | |
1302 | struct mlx4_cmd_mailbox *outbox, | |
1303 | struct mlx4_cmd_info *cmd); | |
1304 | ||
ce8d9e0d MB |
1305 | int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, |
1306 | struct mlx4_vhcr *vhcr, | |
1307 | struct mlx4_cmd_mailbox *inbox, | |
1308 | struct mlx4_cmd_mailbox *outbox, | |
1309 | struct mlx4_cmd_info *cmd); | |
1310 | ||
623ed84b JM |
1311 | int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, |
1312 | struct mlx4_vhcr *vhcr, | |
1313 | struct mlx4_cmd_mailbox *inbox, | |
1314 | struct mlx4_cmd_mailbox *outbox, | |
1315 | struct mlx4_cmd_info *cmd); | |
b12d93d6 YP |
1316 | int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
1317 | enum mlx4_protocol prot, enum mlx4_steer_type steer); | |
1318 | int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
1319 | int block_mcast_loopback, enum mlx4_protocol prot, | |
1320 | enum mlx4_steer_type steer); | |
fd91c49f HHZ |
1321 | int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, |
1322 | u8 gid[16], u8 port, | |
1323 | int block_mcast_loopback, | |
1324 | enum mlx4_protocol prot, u64 *reg_id); | |
623ed84b JM |
1325 | int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, |
1326 | struct mlx4_vhcr *vhcr, | |
1327 | struct mlx4_cmd_mailbox *inbox, | |
1328 | struct mlx4_cmd_mailbox *outbox, | |
1329 | struct mlx4_cmd_info *cmd); | |
1330 | int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, | |
1331 | struct mlx4_vhcr *vhcr, | |
1332 | struct mlx4_cmd_mailbox *inbox, | |
1333 | struct mlx4_cmd_mailbox *outbox, | |
1334 | struct mlx4_cmd_info *cmd); | |
1335 | int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, | |
1336 | int port, void *buf); | |
623ed84b JM |
1337 | int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, |
1338 | struct mlx4_vhcr *vhcr, | |
1339 | struct mlx4_cmd_mailbox *inbox, | |
1340 | struct mlx4_cmd_mailbox *outbox, | |
1341 | struct mlx4_cmd_info *cmd); | |
1342 | int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, | |
1343 | struct mlx4_vhcr *vhcr, | |
1344 | struct mlx4_cmd_mailbox *inbox, | |
1345 | struct mlx4_cmd_mailbox *outbox, | |
1346 | struct mlx4_cmd_info *cmd); | |
1347 | int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, | |
1348 | struct mlx4_vhcr *vhcr, | |
1349 | struct mlx4_cmd_mailbox *inbox, | |
1350 | struct mlx4_cmd_mailbox *outbox, | |
1351 | struct mlx4_cmd_info *cmd); | |
8fcfb4db HHZ |
1352 | int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, |
1353 | struct mlx4_vhcr *vhcr, | |
1354 | struct mlx4_cmd_mailbox *inbox, | |
1355 | struct mlx4_cmd_mailbox *outbox, | |
1356 | struct mlx4_cmd_info *cmd); | |
1357 | int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, | |
1358 | struct mlx4_vhcr *vhcr, | |
1359 | struct mlx4_cmd_mailbox *inbox, | |
1360 | struct mlx4_cmd_mailbox *outbox, | |
1361 | struct mlx4_cmd_info *cmd); | |
6e806699 SM |
1362 | int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, |
1363 | struct mlx4_vhcr *vhcr, | |
1364 | struct mlx4_cmd_mailbox *inbox, | |
1365 | struct mlx4_cmd_mailbox *outbox, | |
1366 | struct mlx4_cmd_info *cmd); | |
f5311ac1 | 1367 | |
0ec2c0f8 EE |
1368 | int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); |
1369 | int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); | |
1370 | ||
5cc914f1 MA |
1371 | static inline void set_param_l(u64 *arg, u32 val) |
1372 | { | |
e7dbeba8 | 1373 | *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; |
5cc914f1 MA |
1374 | } |
1375 | ||
1376 | static inline void set_param_h(u64 *arg, u32 val) | |
1377 | { | |
1378 | *arg = (*arg & 0xffffffff) | ((u64) val << 32); | |
1379 | } | |
1380 | ||
1381 | static inline u32 get_param_l(u64 *arg) | |
1382 | { | |
1383 | return (u32) (*arg & 0xffffffff); | |
1384 | } | |
1385 | ||
1386 | static inline u32 get_param_h(u64 *arg) | |
1387 | { | |
1388 | return (u32)(*arg >> 32); | |
1389 | } | |
1390 | ||
c82e9aa0 EC |
1391 | static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) |
1392 | { | |
1393 | return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; | |
1394 | } | |
1395 | ||
f5311ac1 JM |
1396 | #define NOT_MASKED_PD_BITS 17 |
1397 | ||
b01978ca JM |
1398 | void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); |
1399 | ||
5a0d0a61 JM |
1400 | void mlx4_init_quotas(struct mlx4_dev *dev); |
1401 | ||
2b3ddf27 JM |
1402 | /* for VFs, replace zero MACs with randomly-generated MACs at driver start */ |
1403 | void mlx4_replace_zero_macs(struct mlx4_dev *dev); | |
449fc488 | 1404 | int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); |
f74462ac MB |
1405 | /* Returns the VF index of slave */ |
1406 | int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); | |
114840c3 | 1407 | int mlx4_config_mad_demux(struct mlx4_dev *dev); |
53f33ae2 | 1408 | int mlx4_do_bond(struct mlx4_dev *dev, bool enable); |
78efed27 MS |
1409 | int mlx4_bond_fs_rules(struct mlx4_dev *dev); |
1410 | int mlx4_unbond_fs_rules(struct mlx4_dev *dev); | |
b6ffaeff | 1411 | |
7a89399f MB |
1412 | enum mlx4_zone_flags { |
1413 | MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0, | |
1414 | MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1, | |
1415 | MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2, | |
1416 | MLX4_ZONE_USE_RR = 1UL << 3, | |
1417 | }; | |
1418 | ||
1419 | enum mlx4_zone_alloc_flags { | |
1420 | /* No two objects could overlap between zones. UID | |
1421 | * could be left unused. If this flag is given and | |
1422 | * two overlapped zones are used, an object will be free'd | |
1423 | * from the smallest possible matching zone. | |
1424 | */ | |
1425 | MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0, | |
1426 | }; | |
1427 | ||
1428 | struct mlx4_zone_allocator; | |
1429 | ||
1430 | /* Create a new zone allocator */ | |
1431 | struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags); | |
1432 | ||
1433 | /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator | |
1434 | * <zone_alloc>. Allocating an object from this zone adds an offset <offset>. | |
1435 | * Similarly, when searching for an object to free, this offset it taken into | |
1436 | * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap> | |
1437 | * is given through the MLX4_ZONE_USE_RR flag in <flags>. | |
1438 | * When an allocation fails, <zone_alloc> tries to allocate from other zones | |
1439 | * according to the policy set by <flags>. <puid> is the unique identifier | |
1440 | * received to this zone. | |
1441 | */ | |
1442 | int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc, | |
1443 | struct mlx4_bitmap *bitmap, | |
1444 | u32 flags, | |
1445 | int priority, | |
1446 | int offset, | |
1447 | u32 *puid); | |
1448 | ||
1449 | /* Remove bitmap indicated by <uid> from <zone_alloc> */ | |
1450 | int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid); | |
1451 | ||
1452 | /* Delete the zone allocator <zone_alloc. This function doesn't destroy | |
1453 | * the attached bitmaps. | |
1454 | */ | |
1455 | void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc); | |
1456 | ||
1457 | /* Allocate <count> objects with align <align> and skip_mask <skip_mask> | |
1458 | * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually | |
1459 | * allocated from is returned in <puid>. If the allocation fails, a negative | |
1460 | * number is returned. Otherwise, the offset of the first object is returned. | |
1461 | */ | |
1462 | u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count, | |
1463 | int align, u32 skip_mask, u32 *puid); | |
1464 | ||
1465 | /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator | |
1466 | * <zones>. | |
1467 | */ | |
1468 | u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones, | |
1469 | u32 uid, u32 obj, u32 count); | |
1470 | ||
1471 | /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of | |
1472 | * specifying the uid when freeing an object, zone allocator could figure it by | |
1473 | * itself. Other parameters are similar to mlx4_zone_free. | |
1474 | */ | |
1475 | u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count); | |
1476 | ||
1477 | /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */ | |
1478 | struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid); | |
1479 | ||
225c7b1f | 1480 | #endif /* MLX4_H */ |