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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #ifndef _MLX4_EN_H_ | |
35 | #define _MLX4_EN_H_ | |
36 | ||
f1b553fb | 37 | #include <linux/bitops.h> |
c27a02cd YP |
38 | #include <linux/compiler.h> |
39 | #include <linux/list.h> | |
40 | #include <linux/mutex.h> | |
41 | #include <linux/netdevice.h> | |
f1b553fb | 42 | #include <linux/if_vlan.h> |
ec693d47 | 43 | #include <linux/net_tstamp.h> |
564c274c AV |
44 | #ifdef CONFIG_MLX4_EN_DCB |
45 | #include <linux/dcbnl.h> | |
46 | #endif | |
1eb8c695 | 47 | #include <linux/cpu_rmap.h> |
ad7d4eae | 48 | #include <linux/ptp_clock_kernel.h> |
c27a02cd YP |
49 | |
50 | #include <linux/mlx4/device.h> | |
51 | #include <linux/mlx4/qp.h> | |
52 | #include <linux/mlx4/cq.h> | |
53 | #include <linux/mlx4/srq.h> | |
54 | #include <linux/mlx4/doorbell.h> | |
e7c1c2c4 | 55 | #include <linux/mlx4/cmd.h> |
c27a02cd YP |
56 | |
57 | #include "en_port.h" | |
58 | ||
59 | #define DRV_NAME "mlx4_en" | |
169a1d85 AV |
60 | #define DRV_VERSION "2.2-1" |
61 | #define DRV_RELDATE "Feb 2014" | |
c27a02cd | 62 | |
c27a02cd YP |
63 | #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) |
64 | ||
c27a02cd YP |
65 | /* |
66 | * Device constants | |
67 | */ | |
68 | ||
69 | ||
70 | #define MLX4_EN_PAGE_SHIFT 12 | |
71 | #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) | |
d317966b AV |
72 | #define DEF_RX_RINGS 16 |
73 | #define MAX_RX_RINGS 128 | |
1fb9876e | 74 | #define MIN_RX_RINGS 4 |
c27a02cd YP |
75 | #define TXBB_SIZE 64 |
76 | #define HEADROOM (2048 / TXBB_SIZE + 1) | |
c27a02cd YP |
77 | #define STAMP_STRIDE 64 |
78 | #define STAMP_DWORDS (STAMP_STRIDE / 4) | |
79 | #define STAMP_SHIFT 31 | |
80 | #define STAMP_VAL 0x7fffffff | |
81 | #define STATS_DELAY (HZ / 4) | |
b6c39bfc | 82 | #define SERVICE_TASK_DELAY (HZ / 4) |
82067281 | 83 | #define MAX_NUM_OF_FS_RULES 256 |
c27a02cd | 84 | |
1eb8c695 AV |
85 | #define MLX4_EN_FILTER_HASH_SHIFT 4 |
86 | #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 | |
87 | ||
c27a02cd YP |
88 | /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ |
89 | #define MAX_DESC_SIZE 512 | |
90 | #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) | |
91 | ||
92 | /* | |
93 | * OS related constants and tunables | |
94 | */ | |
95 | ||
0fef9d03 AV |
96 | #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 |
97 | ||
c27a02cd YP |
98 | #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) |
99 | ||
117980c4 TLSC |
100 | /* Use the maximum between 16384 and a single page */ |
101 | #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) | |
51151a16 ED |
102 | |
103 | #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER | |
c27a02cd | 104 | |
e6309cff | 105 | /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU |
c27a02cd YP |
106 | * and 4K allocations) */ |
107 | enum { | |
e6309cff ED |
108 | FRAG_SZ0 = 1536 - NET_IP_ALIGN, |
109 | FRAG_SZ1 = 4096, | |
c27a02cd YP |
110 | FRAG_SZ2 = 4096, |
111 | FRAG_SZ3 = MLX4_EN_ALLOC_SIZE | |
112 | }; | |
113 | #define MLX4_EN_MAX_RX_FRAGS 4 | |
114 | ||
bd531e36 YP |
115 | /* Maximum ring sizes */ |
116 | #define MLX4_EN_MAX_TX_SIZE 8192 | |
117 | #define MLX4_EN_MAX_RX_SIZE 8192 | |
118 | ||
4cce66cd | 119 | /* Minimum ring size for our page-allocation scheme to work */ |
c27a02cd YP |
120 | #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) |
121 | #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) | |
122 | ||
f813cad8 | 123 | #define MLX4_EN_SMALL_PKT_SIZE 64 |
ea1c1af1 | 124 | #define MLX4_EN_MIN_TX_RING_P_UP 1 |
bc6a4744 | 125 | #define MLX4_EN_MAX_TX_RING_P_UP 32 |
564c274c | 126 | #define MLX4_EN_NUM_UP 8 |
f813cad8 | 127 | #define MLX4_EN_DEF_TX_RING_SIZE 512 |
c27a02cd | 128 | #define MLX4_EN_DEF_RX_RING_SIZE 1024 |
d317966b AV |
129 | #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ |
130 | MLX4_EN_NUM_UP) | |
c27a02cd | 131 | |
fbc6daf1 AV |
132 | #define MLX4_EN_DEFAULT_TX_WORK 256 |
133 | ||
3db36fb2 YP |
134 | /* Target number of packets to coalesce with interrupt moderation */ |
135 | #define MLX4_EN_RX_COAL_TARGET 44 | |
c27a02cd YP |
136 | #define MLX4_EN_RX_COAL_TIME 0x10 |
137 | ||
e22979d9 | 138 | #define MLX4_EN_TX_COAL_PKTS 16 |
ecfd2ce1 | 139 | #define MLX4_EN_TX_COAL_TIME 0x10 |
c27a02cd YP |
140 | |
141 | #define MLX4_EN_RX_RATE_LOW 400000 | |
142 | #define MLX4_EN_RX_COAL_TIME_LOW 0 | |
143 | #define MLX4_EN_RX_RATE_HIGH 450000 | |
144 | #define MLX4_EN_RX_COAL_TIME_HIGH 128 | |
145 | #define MLX4_EN_RX_SIZE_THRESH 1024 | |
146 | #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) | |
147 | #define MLX4_EN_SAMPLE_INTERVAL 0 | |
46afd0fb | 148 | #define MLX4_EN_AVG_PKT_SMALL 256 |
c27a02cd YP |
149 | |
150 | #define MLX4_EN_AUTO_CONF 0xffff | |
151 | ||
152 | #define MLX4_EN_DEF_RX_PAUSE 1 | |
153 | #define MLX4_EN_DEF_TX_PAUSE 1 | |
154 | ||
af901ca1 | 155 | /* Interval between successive polls in the Tx routine when polling is used |
c27a02cd YP |
156 | instead of interrupts (in per-core Tx rings) - should be power of 2 */ |
157 | #define MLX4_EN_TX_POLL_MODER 16 | |
158 | #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) | |
159 | ||
c27a02cd YP |
160 | #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) |
161 | #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) | |
e7c1c2c4 | 162 | #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) |
c27a02cd YP |
163 | |
164 | #define MLX4_EN_MIN_MTU 46 | |
165 | #define ETH_BCAST 0xffffffffffffULL | |
166 | ||
e7c1c2c4 YP |
167 | #define MLX4_EN_LOOPBACK_RETRIES 5 |
168 | #define MLX4_EN_LOOPBACK_TIMEOUT 100 | |
169 | ||
c27a02cd YP |
170 | #ifdef MLX4_EN_PERF_STAT |
171 | /* Number of samples to 'average' */ | |
172 | #define AVG_SIZE 128 | |
173 | #define AVG_FACTOR 1024 | |
174 | #define NUM_PERF_STATS NUM_PERF_COUNTERS | |
175 | ||
176 | #define INC_PERF_COUNTER(cnt) (++(cnt)) | |
177 | #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) | |
178 | #define AVG_PERF_COUNTER(cnt, sample) \ | |
179 | ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) | |
180 | #define GET_PERF_COUNTER(cnt) (cnt) | |
181 | #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) | |
182 | ||
183 | #else | |
184 | ||
185 | #define NUM_PERF_STATS 0 | |
186 | #define INC_PERF_COUNTER(cnt) do {} while (0) | |
187 | #define ADD_PERF_COUNTER(cnt, add) do {} while (0) | |
188 | #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) | |
189 | #define GET_PERF_COUNTER(cnt) (0) | |
190 | #define GET_AVG_PERF_COUNTER(cnt) (0) | |
191 | #endif /* MLX4_EN_PERF_STAT */ | |
192 | ||
b97b33a3 EE |
193 | /* Constants for TX flow */ |
194 | enum { | |
195 | MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ | |
196 | MAX_BF = 256, | |
197 | MIN_PKT_LEN = 17, | |
198 | }; | |
199 | ||
c27a02cd YP |
200 | /* |
201 | * Configurables | |
202 | */ | |
203 | ||
204 | enum cq_type { | |
205 | RX = 0, | |
206 | TX = 1, | |
207 | }; | |
208 | ||
209 | ||
210 | /* | |
211 | * Useful macros | |
212 | */ | |
213 | #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) | |
214 | #define XNOR(x, y) (!(x) == !(y)) | |
c27a02cd YP |
215 | |
216 | ||
217 | struct mlx4_en_tx_info { | |
218 | struct sk_buff *skb; | |
98b16349 ED |
219 | u32 nr_txbb; |
220 | u32 nr_bytes; | |
221 | u8 linear; | |
222 | u8 data_offset; | |
223 | u8 inl; | |
224 | u8 ts_requested; | |
225 | } ____cacheline_aligned_in_smp; | |
c27a02cd YP |
226 | |
227 | ||
228 | #define MLX4_EN_BIT_DESC_OWN 0x80000000 | |
229 | #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) | |
230 | #define MLX4_EN_MEMTYPE_PAD 0x100 | |
231 | #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) | |
232 | ||
233 | ||
234 | struct mlx4_en_tx_desc { | |
235 | struct mlx4_wqe_ctrl_seg ctrl; | |
236 | union { | |
237 | struct mlx4_wqe_data_seg data; /* at least one data segment */ | |
238 | struct mlx4_wqe_lso_seg lso; | |
239 | struct mlx4_wqe_inline_seg inl; | |
240 | }; | |
241 | }; | |
242 | ||
243 | #define MLX4_EN_USE_SRQ 0x01000000 | |
244 | ||
725c8999 YP |
245 | #define MLX4_EN_CX3_LOW_ID 0x1000 |
246 | #define MLX4_EN_CX3_HIGH_ID 0x1005 | |
247 | ||
c27a02cd | 248 | struct mlx4_en_rx_alloc { |
51151a16 ED |
249 | struct page *page; |
250 | dma_addr_t dma; | |
70fbe079 AV |
251 | u32 page_offset; |
252 | u32 page_size; | |
c27a02cd YP |
253 | }; |
254 | ||
255 | struct mlx4_en_tx_ring { | |
98b16349 ED |
256 | /* cache line used and dirtied in tx completion |
257 | * (mlx4_en_free_tx_buf()) | |
258 | */ | |
259 | u32 last_nr_txbb; | |
260 | u32 cons; | |
261 | unsigned long wake_queue; | |
262 | ||
263 | /* cache line used and dirtied in mlx4_en_xmit() */ | |
264 | u32 prod ____cacheline_aligned_in_smp; | |
265 | unsigned long bytes; | |
266 | unsigned long packets; | |
267 | unsigned long tx_csum; | |
268 | unsigned long tso_packets; | |
269 | unsigned long xmit_more; | |
270 | struct mlx4_bf bf; | |
271 | unsigned long queue_stopped; | |
272 | ||
273 | /* Following part should be mostly read */ | |
274 | cpumask_t affinity_mask; | |
275 | struct mlx4_qp qp; | |
c27a02cd | 276 | struct mlx4_hwq_resources wqres; |
98b16349 ED |
277 | u32 size; /* number of TXBBs */ |
278 | u32 size_mask; | |
279 | u16 stride; | |
280 | u16 cqn; /* index of port CQ associated with this ring */ | |
281 | u32 buf_size; | |
282 | u32 doorbell_qpn; | |
283 | void *buf; | |
284 | struct mlx4_en_tx_info *tx_info; | |
285 | u8 *bounce_buf; | |
286 | struct mlx4_qp_context context; | |
287 | int qpn; | |
288 | enum mlx4_qp_state qp_state; | |
289 | u8 queue_index; | |
290 | bool bf_enabled; | |
291 | bool bf_alloced; | |
292 | struct netdev_queue *tx_queue; | |
293 | int hwtstamp_tx_type; | |
294 | int inline_thold; | |
295 | } ____cacheline_aligned_in_smp; | |
c27a02cd YP |
296 | |
297 | struct mlx4_en_rx_desc { | |
c27a02cd YP |
298 | /* actual number of entries depends on rx ring stride */ |
299 | struct mlx4_wqe_data_seg data[0]; | |
300 | }; | |
301 | ||
302 | struct mlx4_en_rx_ring { | |
c27a02cd YP |
303 | struct mlx4_hwq_resources wqres; |
304 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; | |
c27a02cd YP |
305 | u32 size ; /* number of Rx descs*/ |
306 | u32 actual_size; | |
307 | u32 size_mask; | |
308 | u16 stride; | |
309 | u16 log_stride; | |
310 | u16 cqn; /* index of port CQ associated with this ring */ | |
311 | u32 prod; | |
312 | u32 cons; | |
313 | u32 buf_size; | |
4a5f4dd8 | 314 | u8 fcs_del; |
c27a02cd YP |
315 | void *buf; |
316 | void *rx_info; | |
317 | unsigned long bytes; | |
318 | unsigned long packets; | |
e0d1095a | 319 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8501841a AV |
320 | unsigned long yields; |
321 | unsigned long misses; | |
322 | unsigned long cleaned; | |
323 | #endif | |
ad04378c YP |
324 | unsigned long csum_ok; |
325 | unsigned long csum_none; | |
ec693d47 | 326 | int hwtstamp_rx_filter; |
9e311e77 | 327 | cpumask_var_t affinity_mask; |
c27a02cd YP |
328 | }; |
329 | ||
c27a02cd YP |
330 | struct mlx4_en_cq { |
331 | struct mlx4_cq mcq; | |
332 | struct mlx4_hwq_resources wqres; | |
333 | int ring; | |
c27a02cd YP |
334 | struct net_device *dev; |
335 | struct napi_struct napi; | |
c27a02cd YP |
336 | int size; |
337 | int buf_size; | |
338 | unsigned vector; | |
339 | enum cq_type is_tx; | |
340 | u16 moder_time; | |
341 | u16 moder_cnt; | |
c27a02cd YP |
342 | struct mlx4_cqe *buf; |
343 | #define MLX4_EN_OPCODE_ERROR 0x1e | |
9e77a2b8 | 344 | |
e0d1095a | 345 | #ifdef CONFIG_NET_RX_BUSY_POLL |
9e77a2b8 AV |
346 | unsigned int state; |
347 | #define MLX4_EN_CQ_STATE_IDLE 0 | |
348 | #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */ | |
349 | #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */ | |
350 | #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL) | |
351 | #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */ | |
352 | #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */ | |
353 | #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD) | |
354 | #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD) | |
355 | spinlock_t poll_lock; /* protects from LLS/napi conflicts */ | |
e0d1095a | 356 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
35f6f453 | 357 | struct irq_desc *irq_desc; |
c27a02cd YP |
358 | }; |
359 | ||
360 | struct mlx4_en_port_profile { | |
361 | u32 flags; | |
362 | u32 tx_ring_num; | |
363 | u32 rx_ring_num; | |
364 | u32 tx_ring_size; | |
365 | u32 rx_ring_size; | |
d53b93f2 YP |
366 | u8 rx_pause; |
367 | u8 rx_ppp; | |
368 | u8 tx_pause; | |
369 | u8 tx_ppp; | |
93d3e367 | 370 | int rss_rings; |
b97b33a3 | 371 | int inline_thold; |
c27a02cd YP |
372 | }; |
373 | ||
374 | struct mlx4_en_profile { | |
375 | int rss_xor; | |
0533943c | 376 | int udp_rss; |
c27a02cd YP |
377 | u8 rss_mask; |
378 | u32 active_ports; | |
379 | u32 small_pkt_int; | |
c27a02cd | 380 | u8 no_reset; |
bc6a4744 | 381 | u8 num_tx_rings_p_up; |
c27a02cd YP |
382 | struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; |
383 | }; | |
384 | ||
385 | struct mlx4_en_dev { | |
386 | struct mlx4_dev *dev; | |
387 | struct pci_dev *pdev; | |
388 | struct mutex state_lock; | |
389 | struct net_device *pndev[MLX4_MAX_PORTS + 1]; | |
390 | u32 port_cnt; | |
391 | bool device_up; | |
392 | struct mlx4_en_profile profile; | |
393 | u32 LSO_support; | |
394 | struct workqueue_struct *workqueue; | |
395 | struct device *dma_device; | |
396 | void __iomem *uar_map; | |
397 | struct mlx4_uar priv_uar; | |
398 | struct mlx4_mr mr; | |
399 | u32 priv_pdn; | |
400 | spinlock_t uar_lock; | |
d7e1a487 | 401 | u8 mac_removed[MLX4_MAX_PORTS + 1]; |
ad7d4eae SB |
402 | rwlock_t clock_lock; |
403 | u32 nominal_c_mult; | |
ec693d47 AV |
404 | struct cyclecounter cycles; |
405 | struct timecounter clock; | |
406 | unsigned long last_overflow_check; | |
b6c39bfc | 407 | unsigned long overflow_period; |
ad7d4eae SB |
408 | struct ptp_clock *ptp_clock; |
409 | struct ptp_clock_info ptp_clock_info; | |
c27a02cd YP |
410 | }; |
411 | ||
412 | ||
413 | struct mlx4_en_rss_map { | |
c27a02cd | 414 | int base_qpn; |
b6b912e0 YP |
415 | struct mlx4_qp qps[MAX_RX_RINGS]; |
416 | enum mlx4_qp_state state[MAX_RX_RINGS]; | |
c27a02cd YP |
417 | struct mlx4_qp indir_qp; |
418 | enum mlx4_qp_state indir_state; | |
419 | }; | |
420 | ||
e7c1c2c4 YP |
421 | struct mlx4_en_port_state { |
422 | int link_state; | |
423 | int link_speed; | |
424 | int transciver; | |
425 | }; | |
426 | ||
c27a02cd YP |
427 | struct mlx4_en_pkt_stats { |
428 | unsigned long broadcast; | |
429 | unsigned long rx_prio[8]; | |
430 | unsigned long tx_prio[8]; | |
431 | #define NUM_PKT_STATS 17 | |
432 | }; | |
433 | ||
434 | struct mlx4_en_port_stats { | |
c27a02cd | 435 | unsigned long tso_packets; |
9fab426d | 436 | unsigned long xmit_more; |
c27a02cd YP |
437 | unsigned long queue_stopped; |
438 | unsigned long wake_queue; | |
439 | unsigned long tx_timeout; | |
440 | unsigned long rx_alloc_failed; | |
441 | unsigned long rx_chksum_good; | |
442 | unsigned long rx_chksum_none; | |
443 | unsigned long tx_chksum_offload; | |
9fab426d | 444 | #define NUM_PORT_STATS 9 |
c27a02cd YP |
445 | }; |
446 | ||
447 | struct mlx4_en_perf_stats { | |
448 | u32 tx_poll; | |
449 | u64 tx_pktsz_avg; | |
450 | u32 inflight_avg; | |
451 | u16 tx_coal_avg; | |
452 | u16 rx_coal_avg; | |
453 | u32 napi_quota; | |
454 | #define NUM_PERF_COUNTERS 6 | |
455 | }; | |
456 | ||
6d199937 YP |
457 | enum mlx4_en_mclist_act { |
458 | MCLIST_NONE, | |
459 | MCLIST_REM, | |
460 | MCLIST_ADD, | |
461 | }; | |
462 | ||
463 | struct mlx4_en_mc_list { | |
464 | struct list_head list; | |
465 | enum mlx4_en_mclist_act action; | |
466 | u8 addr[ETH_ALEN]; | |
0ff1fb65 | 467 | u64 reg_id; |
837052d0 | 468 | u64 tunnel_reg_id; |
6d199937 YP |
469 | }; |
470 | ||
c27a02cd YP |
471 | struct mlx4_en_frag_info { |
472 | u16 frag_size; | |
473 | u16 frag_prefix_size; | |
474 | u16 frag_stride; | |
475 | u16 frag_align; | |
c27a02cd YP |
476 | }; |
477 | ||
564c274c AV |
478 | #ifdef CONFIG_MLX4_EN_DCB |
479 | /* Minimal TC BW - setting to 0 will block traffic */ | |
480 | #define MLX4_EN_BW_MIN 1 | |
481 | #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ | |
482 | ||
483 | #define MLX4_EN_TC_ETS 7 | |
484 | ||
485 | #endif | |
486 | ||
82067281 | 487 | struct ethtool_flow_id { |
0d256c0e | 488 | struct list_head list; |
82067281 HHZ |
489 | struct ethtool_rx_flow_spec flow_spec; |
490 | u64 id; | |
491 | }; | |
492 | ||
79aeaccd YB |
493 | enum { |
494 | MLX4_EN_FLAG_PROMISC = (1 << 0), | |
495 | MLX4_EN_FLAG_MC_PROMISC = (1 << 1), | |
496 | /* whether we need to enable hardware loopback by putting dmac | |
497 | * in Tx WQE | |
498 | */ | |
499 | MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), | |
500 | /* whether we need to drop packets that hardware loopback-ed */ | |
cc5387f7 YB |
501 | MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), |
502 | MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4) | |
79aeaccd YB |
503 | }; |
504 | ||
c07cb4b0 YB |
505 | #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) |
506 | #define MLX4_EN_MAC_HASH_IDX 5 | |
507 | ||
c27a02cd YP |
508 | struct mlx4_en_priv { |
509 | struct mlx4_en_dev *mdev; | |
510 | struct mlx4_en_port_profile *prof; | |
511 | struct net_device *dev; | |
f1b553fb | 512 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
c27a02cd YP |
513 | struct net_device_stats stats; |
514 | struct net_device_stats ret_stats; | |
e7c1c2c4 | 515 | struct mlx4_en_port_state port_state; |
c27a02cd | 516 | spinlock_t stats_lock; |
82067281 | 517 | struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; |
0d256c0e HHZ |
518 | /* To allow rules removal while port is going down */ |
519 | struct list_head ethtool_list; | |
c27a02cd | 520 | |
6b4d8d9f | 521 | unsigned long last_moder_packets[MAX_RX_RINGS]; |
c27a02cd | 522 | unsigned long last_moder_tx_packets; |
6b4d8d9f | 523 | unsigned long last_moder_bytes[MAX_RX_RINGS]; |
c27a02cd | 524 | unsigned long last_moder_jiffies; |
6b4d8d9f | 525 | int last_moder_time[MAX_RX_RINGS]; |
c27a02cd YP |
526 | u16 rx_usecs; |
527 | u16 rx_frames; | |
528 | u16 tx_usecs; | |
529 | u16 tx_frames; | |
530 | u32 pkt_rate_low; | |
531 | u16 rx_usecs_low; | |
532 | u32 pkt_rate_high; | |
533 | u16 rx_usecs_high; | |
534 | u16 sample_interval; | |
535 | u16 adaptive_rx_coal; | |
536 | u32 msg_enable; | |
e7c1c2c4 YP |
537 | u32 loopback_ok; |
538 | u32 validate_loopback; | |
c27a02cd YP |
539 | |
540 | struct mlx4_hwq_resources res; | |
541 | int link_state; | |
542 | int last_link_state; | |
543 | bool port_up; | |
544 | int port; | |
545 | int registered; | |
546 | int allocated; | |
547 | int stride; | |
2695bab2 | 548 | unsigned char current_mac[ETH_ALEN + 2]; |
c27a02cd YP |
549 | int mac_index; |
550 | unsigned max_mtu; | |
551 | int base_qpn; | |
08ff3235 | 552 | int cqe_factor; |
b1b6b4da | 553 | int cqe_size; |
c27a02cd YP |
554 | |
555 | struct mlx4_en_rss_map rss_map; | |
4ef2a435 | 556 | __be32 ctrl_flags; |
c27a02cd | 557 | u32 flags; |
d317966b | 558 | u8 num_tx_rings_p_up; |
fbc6daf1 | 559 | u32 tx_work_limit; |
c27a02cd YP |
560 | u32 tx_ring_num; |
561 | u32 rx_ring_num; | |
562 | u32 rx_skb_size; | |
563 | struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; | |
564 | u16 num_frags; | |
565 | u16 log_rx_info; | |
566 | ||
41d942d5 EE |
567 | struct mlx4_en_tx_ring **tx_ring; |
568 | struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; | |
569 | struct mlx4_en_cq **tx_cq; | |
570 | struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; | |
cabdc8ee | 571 | struct mlx4_qp drop_qp; |
0eb74fdd | 572 | struct work_struct rx_mode_task; |
c27a02cd YP |
573 | struct work_struct watchdog_task; |
574 | struct work_struct linkstate_task; | |
575 | struct delayed_work stats_task; | |
b6c39bfc | 576 | struct delayed_work service_task; |
a66132f3 | 577 | #ifdef CONFIG_MLX4_EN_VXLAN |
1b136de1 OG |
578 | struct work_struct vxlan_add_task; |
579 | struct work_struct vxlan_del_task; | |
a66132f3 | 580 | #endif |
c27a02cd YP |
581 | struct mlx4_en_perf_stats pstats; |
582 | struct mlx4_en_pkt_stats pkstats; | |
583 | struct mlx4_en_port_stats port_stats; | |
93ece0c1 | 584 | u64 stats_bitmap; |
6d199937 YP |
585 | struct list_head mc_list; |
586 | struct list_head curr_list; | |
0ff1fb65 | 587 | u64 broadcast_id; |
c27a02cd | 588 | struct mlx4_en_stat_out_mbox hw_stats; |
4c3eb3ca | 589 | int vids[128]; |
14c07b13 | 590 | bool wol; |
ebf8c9aa | 591 | struct device *ddev; |
044ca2a5 | 592 | int base_tx_qpn; |
c07cb4b0 | 593 | struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; |
ec693d47 | 594 | struct hwtstamp_config hwtstamp_config; |
564c274c AV |
595 | |
596 | #ifdef CONFIG_MLX4_EN_DCB | |
597 | struct ieee_ets ets; | |
109d2446 | 598 | u16 maxrate[IEEE_8021QAZ_MAX_TCS]; |
564c274c | 599 | #endif |
1eb8c695 AV |
600 | #ifdef CONFIG_RFS_ACCEL |
601 | spinlock_t filters_lock; | |
602 | int last_filter_id; | |
603 | struct list_head filters; | |
604 | struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; | |
605 | #endif | |
837052d0 | 606 | u64 tunnel_reg_id; |
1b136de1 | 607 | __be16 vxlan_port; |
0fef9d03 AV |
608 | |
609 | u32 pflags; | |
14c07b13 YP |
610 | }; |
611 | ||
612 | enum mlx4_en_wol { | |
613 | MLX4_EN_WOL_MAGIC = (1ULL << 61), | |
614 | MLX4_EN_WOL_ENABLED = (1ULL << 62), | |
c27a02cd YP |
615 | }; |
616 | ||
16a10ffd | 617 | struct mlx4_mac_entry { |
c07cb4b0 | 618 | struct hlist_node hlist; |
16a10ffd YB |
619 | unsigned char mac[ETH_ALEN + 2]; |
620 | u64 reg_id; | |
c07cb4b0 | 621 | struct rcu_head rcu; |
16a10ffd YB |
622 | }; |
623 | ||
b1b6b4da IS |
624 | static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) |
625 | { | |
626 | return buf + idx * cqe_sz; | |
627 | } | |
628 | ||
e0d1095a | 629 | #ifdef CONFIG_NET_RX_BUSY_POLL |
9e77a2b8 AV |
630 | static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) |
631 | { | |
632 | spin_lock_init(&cq->poll_lock); | |
633 | cq->state = MLX4_EN_CQ_STATE_IDLE; | |
634 | } | |
635 | ||
636 | /* called from the device poll rutine to get ownership of a cq */ | |
637 | static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) | |
638 | { | |
639 | int rc = true; | |
640 | spin_lock(&cq->poll_lock); | |
641 | if (cq->state & MLX4_CQ_LOCKED) { | |
642 | WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI); | |
643 | cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD; | |
644 | rc = false; | |
645 | } else | |
646 | /* we don't care if someone yielded */ | |
647 | cq->state = MLX4_EN_CQ_STATE_NAPI; | |
648 | spin_unlock(&cq->poll_lock); | |
649 | return rc; | |
650 | } | |
651 | ||
652 | /* returns true is someone tried to get the cq while napi had it */ | |
653 | static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) | |
654 | { | |
655 | int rc = false; | |
656 | spin_lock(&cq->poll_lock); | |
657 | WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL | | |
658 | MLX4_EN_CQ_STATE_NAPI_YIELD)); | |
659 | ||
660 | if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) | |
661 | rc = true; | |
662 | cq->state = MLX4_EN_CQ_STATE_IDLE; | |
663 | spin_unlock(&cq->poll_lock); | |
664 | return rc; | |
665 | } | |
666 | ||
667 | /* called from mlx4_en_low_latency_poll() */ | |
668 | static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) | |
669 | { | |
670 | int rc = true; | |
671 | spin_lock_bh(&cq->poll_lock); | |
672 | if ((cq->state & MLX4_CQ_LOCKED)) { | |
673 | struct net_device *dev = cq->dev; | |
674 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
41d942d5 | 675 | struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; |
9e77a2b8 AV |
676 | |
677 | cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; | |
678 | rc = false; | |
8501841a | 679 | rx_ring->yields++; |
9e77a2b8 AV |
680 | } else |
681 | /* preserve yield marks */ | |
682 | cq->state |= MLX4_EN_CQ_STATE_POLL; | |
683 | spin_unlock_bh(&cq->poll_lock); | |
684 | return rc; | |
685 | } | |
686 | ||
687 | /* returns true if someone tried to get the cq while it was locked */ | |
688 | static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) | |
689 | { | |
690 | int rc = false; | |
691 | spin_lock_bh(&cq->poll_lock); | |
692 | WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI)); | |
693 | ||
694 | if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) | |
695 | rc = true; | |
696 | cq->state = MLX4_EN_CQ_STATE_IDLE; | |
697 | spin_unlock_bh(&cq->poll_lock); | |
698 | return rc; | |
699 | } | |
700 | ||
701 | /* true if a socket is polling, even if it did not get the lock */ | |
e6a76758 | 702 | static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) |
9e77a2b8 AV |
703 | { |
704 | WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); | |
705 | return cq->state & CQ_USER_PEND; | |
706 | } | |
707 | #else | |
708 | static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) | |
709 | { | |
710 | } | |
711 | ||
712 | static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) | |
713 | { | |
714 | return true; | |
715 | } | |
716 | ||
717 | static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) | |
718 | { | |
719 | return false; | |
720 | } | |
721 | ||
722 | static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) | |
723 | { | |
724 | return false; | |
725 | } | |
726 | ||
727 | static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) | |
728 | { | |
729 | return false; | |
730 | } | |
731 | ||
e6a76758 | 732 | static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) |
9e77a2b8 AV |
733 | { |
734 | return false; | |
735 | } | |
e0d1095a | 736 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
9e77a2b8 | 737 | |
0d9fdaa9 | 738 | #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) |
c27a02cd | 739 | |
79aeaccd YB |
740 | void mlx4_en_update_loopback_state(struct net_device *dev, |
741 | netdev_features_t features); | |
742 | ||
c27a02cd YP |
743 | void mlx4_en_destroy_netdev(struct net_device *dev); |
744 | int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, | |
745 | struct mlx4_en_port_profile *prof); | |
746 | ||
18cc42a3 | 747 | int mlx4_en_start_port(struct net_device *dev); |
3484aac1 | 748 | void mlx4_en_stop_port(struct net_device *dev, int detach); |
18cc42a3 | 749 | |
fe0af03c | 750 | void mlx4_en_free_resources(struct mlx4_en_priv *priv); |
18cc42a3 YP |
751 | int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); |
752 | ||
41d942d5 | 753 | int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, |
163561a4 | 754 | int entries, int ring, enum cq_type mode, int node); |
41d942d5 | 755 | void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); |
76532d0c AG |
756 | int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, |
757 | int cq_idx); | |
c27a02cd YP |
758 | void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); |
759 | int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); | |
760 | int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); | |
761 | ||
c27a02cd | 762 | void mlx4_en_tx_irq(struct mlx4_cq *mcq); |
f663dd9a | 763 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 764 | void *accel_priv, select_queue_fallback_t fallback); |
61357325 | 765 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); |
c27a02cd | 766 | |
41d942d5 EE |
767 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
768 | struct mlx4_en_tx_ring **pring, | |
d03a68f8 IS |
769 | int qpn, u32 size, u16 stride, |
770 | int node, int queue_index); | |
41d942d5 EE |
771 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, |
772 | struct mlx4_en_tx_ring **pring); | |
c27a02cd YP |
773 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, |
774 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 775 | int cq, int user_prio); |
c27a02cd YP |
776 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, |
777 | struct mlx4_en_tx_ring *ring); | |
02512482 | 778 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); |
c27a02cd | 779 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 780 | struct mlx4_en_rx_ring **pring, |
163561a4 | 781 | u32 size, u16 stride, int node); |
c27a02cd | 782 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 783 | struct mlx4_en_rx_ring **pring, |
68355f71 | 784 | u32 size, u16 stride); |
c27a02cd YP |
785 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); |
786 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
787 | struct mlx4_en_rx_ring *ring); | |
788 | int mlx4_en_process_rx_cq(struct net_device *dev, | |
789 | struct mlx4_en_cq *cq, | |
790 | int budget); | |
791 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); | |
0276a330 | 792 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); |
c27a02cd | 793 | void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, |
0e98b523 AV |
794 | int is_tx, int rss, int qpn, int cqn, int user_prio, |
795 | struct mlx4_qp_context *context); | |
966508f7 | 796 | void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); |
c27a02cd YP |
797 | int mlx4_en_map_buffer(struct mlx4_buf *buf); |
798 | void mlx4_en_unmap_buffer(struct mlx4_buf *buf); | |
799 | ||
800 | void mlx4_en_calc_rx_buf(struct net_device *dev); | |
c27a02cd YP |
801 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); |
802 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); | |
cabdc8ee HHZ |
803 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); |
804 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); | |
c27a02cd | 805 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); |
c27a02cd YP |
806 | void mlx4_en_rx_irq(struct mlx4_cq *mcq); |
807 | ||
808 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
f1b553fb | 809 | int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); |
c27a02cd YP |
810 | |
811 | int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); | |
e7c1c2c4 YP |
812 | int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); |
813 | ||
564c274c AV |
814 | #ifdef CONFIG_MLX4_EN_DCB |
815 | extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; | |
540b3a39 | 816 | extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; |
564c274c AV |
817 | #endif |
818 | ||
d317966b AV |
819 | int mlx4_en_setup_tc(struct net_device *dev, u8 up); |
820 | ||
1eb8c695 | 821 | #ifdef CONFIG_RFS_ACCEL |
41d942d5 | 822 | void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); |
1eb8c695 AV |
823 | #endif |
824 | ||
e7c1c2c4 YP |
825 | #define MLX4_EN_NUM_SELF_TEST 5 |
826 | void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); | |
b6c39bfc | 827 | void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); |
c27a02cd YP |
828 | |
829 | /* | |
ec693d47 AV |
830 | * Functions for time stamping |
831 | */ | |
832 | u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); | |
833 | void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, | |
834 | struct skb_shared_hwtstamps *hwts, | |
835 | u64 timestamp); | |
836 | void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); | |
ad7d4eae | 837 | void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); |
ec693d47 AV |
838 | int mlx4_en_timestamp_config(struct net_device *dev, |
839 | int tx_type, | |
840 | int rx_filter); | |
841 | ||
842 | /* Globals | |
c27a02cd YP |
843 | */ |
844 | extern const struct ethtool_ops mlx4_en_ethtool_ops; | |
0a645e80 JP |
845 | |
846 | ||
847 | ||
848 | /* | |
849 | * printk / logging functions | |
850 | */ | |
851 | ||
b9075fa9 | 852 | __printf(3, 4) |
0c87b29c JP |
853 | void en_print(const char *level, const struct mlx4_en_priv *priv, |
854 | const char *format, ...); | |
0a645e80 | 855 | |
1a91de28 JP |
856 | #define en_dbg(mlevel, priv, format, ...) \ |
857 | do { \ | |
858 | if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ | |
859 | en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ | |
0a645e80 | 860 | } while (0) |
1a91de28 JP |
861 | #define en_warn(priv, format, ...) \ |
862 | en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) | |
863 | #define en_err(priv, format, ...) \ | |
864 | en_print(KERN_ERR, priv, format, ##__VA_ARGS__) | |
865 | #define en_info(priv, format, ...) \ | |
866 | en_print(KERN_INFO, priv, format, ##__VA_ARGS__) | |
867 | ||
868 | #define mlx4_err(mdev, format, ...) \ | |
869 | pr_err(DRV_NAME " %s: " format, \ | |
870 | dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) | |
871 | #define mlx4_info(mdev, format, ...) \ | |
872 | pr_info(DRV_NAME " %s: " format, \ | |
873 | dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) | |
874 | #define mlx4_warn(mdev, format, ...) \ | |
875 | pr_warn(DRV_NAME " %s: " format, \ | |
876 | dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) | |
0a645e80 | 877 | |
c27a02cd | 878 | #endif |