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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
225c7b1f | 35 | #include <linux/errno.h> |
ee40fa06 | 36 | #include <linux/export.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
ea51b377 | 38 | #include <linux/kernel.h> |
89dd86db | 39 | #include <linux/vmalloc.h> |
225c7b1f RD |
40 | |
41 | #include <linux/mlx4/cmd.h> | |
42 | ||
43 | #include "mlx4.h" | |
44 | #include "icm.h" | |
45 | ||
225c7b1f RD |
46 | static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order) |
47 | { | |
48 | int o; | |
49 | int m; | |
50 | u32 seg; | |
51 | ||
52 | spin_lock(&buddy->lock); | |
53 | ||
e4044cfc RD |
54 | for (o = order; o <= buddy->max_order; ++o) |
55 | if (buddy->num_free[o]) { | |
56 | m = 1 << (buddy->max_order - o); | |
57 | seg = find_first_bit(buddy->bits[o], m); | |
58 | if (seg < m) | |
59 | goto found; | |
60 | } | |
225c7b1f RD |
61 | |
62 | spin_unlock(&buddy->lock); | |
63 | return -1; | |
64 | ||
65 | found: | |
66 | clear_bit(seg, buddy->bits[o]); | |
e4044cfc | 67 | --buddy->num_free[o]; |
225c7b1f RD |
68 | |
69 | while (o > order) { | |
70 | --o; | |
71 | seg <<= 1; | |
72 | set_bit(seg ^ 1, buddy->bits[o]); | |
e4044cfc | 73 | ++buddy->num_free[o]; |
225c7b1f RD |
74 | } |
75 | ||
76 | spin_unlock(&buddy->lock); | |
77 | ||
78 | seg <<= order; | |
79 | ||
80 | return seg; | |
81 | } | |
82 | ||
83 | static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order) | |
84 | { | |
85 | seg >>= order; | |
86 | ||
87 | spin_lock(&buddy->lock); | |
88 | ||
89 | while (test_bit(seg ^ 1, buddy->bits[order])) { | |
90 | clear_bit(seg ^ 1, buddy->bits[order]); | |
e4044cfc | 91 | --buddy->num_free[order]; |
225c7b1f RD |
92 | seg >>= 1; |
93 | ++order; | |
94 | } | |
95 | ||
96 | set_bit(seg, buddy->bits[order]); | |
e4044cfc | 97 | ++buddy->num_free[order]; |
225c7b1f RD |
98 | |
99 | spin_unlock(&buddy->lock); | |
100 | } | |
101 | ||
e8f9b2ed | 102 | static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order) |
225c7b1f RD |
103 | { |
104 | int i, s; | |
105 | ||
106 | buddy->max_order = max_order; | |
107 | spin_lock_init(&buddy->lock); | |
108 | ||
96f17d59 | 109 | buddy->bits = kcalloc(buddy->max_order + 1, sizeof (long *), |
225c7b1f | 110 | GFP_KERNEL); |
a8312755 | 111 | buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free, |
e4044cfc RD |
112 | GFP_KERNEL); |
113 | if (!buddy->bits || !buddy->num_free) | |
225c7b1f RD |
114 | goto err_out; |
115 | ||
116 | for (i = 0; i <= buddy->max_order; ++i) { | |
117 | s = BITS_TO_LONGS(1 << (buddy->max_order - i)); | |
752ade68 MH |
118 | buddy->bits[i] = kvmalloc_array(s, sizeof(long), GFP_KERNEL | __GFP_ZERO); |
119 | if (!buddy->bits[i]) | |
120 | goto err_out_free; | |
225c7b1f RD |
121 | } |
122 | ||
123 | set_bit(0, buddy->bits[buddy->max_order]); | |
e4044cfc | 124 | buddy->num_free[buddy->max_order] = 1; |
225c7b1f RD |
125 | |
126 | return 0; | |
127 | ||
128 | err_out_free: | |
129 | for (i = 0; i <= buddy->max_order; ++i) | |
914efb02 | 130 | kvfree(buddy->bits[i]); |
225c7b1f | 131 | |
e4044cfc | 132 | err_out: |
225c7b1f | 133 | kfree(buddy->bits); |
e4044cfc | 134 | kfree(buddy->num_free); |
225c7b1f | 135 | |
225c7b1f RD |
136 | return -ENOMEM; |
137 | } | |
138 | ||
139 | static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy) | |
140 | { | |
141 | int i; | |
142 | ||
143 | for (i = 0; i <= buddy->max_order; ++i) | |
914efb02 | 144 | kvfree(buddy->bits[i]); |
225c7b1f RD |
145 | |
146 | kfree(buddy->bits); | |
e4044cfc | 147 | kfree(buddy->num_free); |
225c7b1f RD |
148 | } |
149 | ||
c82e9aa0 | 150 | u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order) |
225c7b1f RD |
151 | { |
152 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
153 | u32 seg; | |
2b8fb286 MA |
154 | int seg_order; |
155 | u32 offset; | |
225c7b1f | 156 | |
2b8fb286 MA |
157 | seg_order = max_t(int, order - log_mtts_per_seg, 0); |
158 | ||
159 | seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, seg_order); | |
225c7b1f RD |
160 | if (seg == -1) |
161 | return -1; | |
162 | ||
2b8fb286 MA |
163 | offset = seg * (1 << log_mtts_per_seg); |
164 | ||
165 | if (mlx4_table_get_range(dev, &mr_table->mtt_table, offset, | |
166 | offset + (1 << order) - 1)) { | |
167 | mlx4_buddy_free(&mr_table->mtt_buddy, seg, seg_order); | |
225c7b1f RD |
168 | return -1; |
169 | } | |
170 | ||
2b8fb286 | 171 | return offset; |
225c7b1f RD |
172 | } |
173 | ||
ea51b377 JM |
174 | static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order) |
175 | { | |
e7dbeba8 | 176 | u64 in_param = 0; |
ea51b377 JM |
177 | u64 out_param; |
178 | int err; | |
179 | ||
180 | if (mlx4_is_mfunc(dev)) { | |
181 | set_param_l(&in_param, order); | |
182 | err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT, | |
183 | RES_OP_RESERVE_AND_MAP, | |
184 | MLX4_CMD_ALLOC_RES, | |
185 | MLX4_CMD_TIME_CLASS_A, | |
186 | MLX4_CMD_WRAPPED); | |
187 | if (err) | |
188 | return -1; | |
189 | return get_param_l(&out_param); | |
190 | } | |
191 | return __mlx4_alloc_mtt_range(dev, order); | |
192 | } | |
193 | ||
225c7b1f RD |
194 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, |
195 | struct mlx4_mtt *mtt) | |
196 | { | |
197 | int i; | |
198 | ||
199 | if (!npages) { | |
200 | mtt->order = -1; | |
201 | mtt->page_shift = MLX4_ICM_PAGE_SHIFT; | |
202 | return 0; | |
203 | } else | |
204 | mtt->page_shift = page_shift; | |
205 | ||
2b8fb286 | 206 | for (mtt->order = 0, i = 1; i < npages; i <<= 1) |
225c7b1f RD |
207 | ++mtt->order; |
208 | ||
2b8fb286 MA |
209 | mtt->offset = mlx4_alloc_mtt_range(dev, mtt->order); |
210 | if (mtt->offset == -1) | |
225c7b1f RD |
211 | return -ENOMEM; |
212 | ||
213 | return 0; | |
214 | } | |
215 | EXPORT_SYMBOL_GPL(mlx4_mtt_init); | |
216 | ||
2b8fb286 | 217 | void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order) |
225c7b1f | 218 | { |
2b8fb286 MA |
219 | u32 first_seg; |
220 | int seg_order; | |
225c7b1f RD |
221 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; |
222 | ||
2b8fb286 MA |
223 | seg_order = max_t(int, order - log_mtts_per_seg, 0); |
224 | first_seg = offset / (1 << log_mtts_per_seg); | |
225 | ||
226 | mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, seg_order); | |
1e27ca69 MA |
227 | mlx4_table_put_range(dev, &mr_table->mtt_table, offset, |
228 | offset + (1 << order) - 1); | |
ea51b377 JM |
229 | } |
230 | ||
2b8fb286 | 231 | static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order) |
ea51b377 | 232 | { |
e7dbeba8 | 233 | u64 in_param = 0; |
ea51b377 JM |
234 | int err; |
235 | ||
236 | if (mlx4_is_mfunc(dev)) { | |
2b8fb286 | 237 | set_param_l(&in_param, offset); |
ea51b377 JM |
238 | set_param_h(&in_param, order); |
239 | err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP, | |
240 | MLX4_CMD_FREE_RES, | |
241 | MLX4_CMD_TIME_CLASS_A, | |
242 | MLX4_CMD_WRAPPED); | |
243 | if (err) | |
1a91de28 JP |
244 | mlx4_warn(dev, "Failed to free mtt range at:%d order:%d\n", |
245 | offset, order); | |
ea51b377 JM |
246 | return; |
247 | } | |
5d4de16c | 248 | __mlx4_free_mtt_range(dev, offset, order); |
ea51b377 JM |
249 | } |
250 | ||
251 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt) | |
252 | { | |
225c7b1f RD |
253 | if (mtt->order < 0) |
254 | return; | |
255 | ||
2b8fb286 | 256 | mlx4_free_mtt_range(dev, mtt->offset, mtt->order); |
225c7b1f RD |
257 | } |
258 | EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup); | |
259 | ||
260 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt) | |
261 | { | |
2b8fb286 | 262 | return (u64) mtt->offset * dev->caps.mtt_entry_sz; |
225c7b1f RD |
263 | } |
264 | EXPORT_SYMBOL_GPL(mlx4_mtt_addr); | |
265 | ||
266 | static u32 hw_index_to_key(u32 ind) | |
267 | { | |
268 | return (ind >> 24) | (ind << 8); | |
269 | } | |
270 | ||
271 | static u32 key_to_hw_index(u32 key) | |
272 | { | |
273 | return (key << 24) | (key >> 8); | |
274 | } | |
275 | ||
276 | static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, | |
277 | int mpt_index) | |
278 | { | |
eb41049f | 279 | return mlx4_cmd(dev, mailbox->dma, mpt_index, |
ea51b377 JM |
280 | 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B, |
281 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
282 | } |
283 | ||
284 | static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, | |
285 | int mpt_index) | |
286 | { | |
287 | return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, | |
f9baff50 JM |
288 | !mailbox, MLX4_CMD_HW2SW_MPT, |
289 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
225c7b1f RD |
290 | } |
291 | ||
4ff0acca | 292 | /* Must protect against concurrent access */ |
e630664c MB |
293 | int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, |
294 | struct mlx4_mpt_entry ***mpt_entry) | |
295 | { | |
296 | int err; | |
297 | int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1); | |
298 | struct mlx4_cmd_mailbox *mailbox = NULL; | |
299 | ||
e630664c MB |
300 | if (mmr->enabled != MLX4_MPT_EN_HW) |
301 | return -EINVAL; | |
302 | ||
303 | err = mlx4_HW2SW_MPT(dev, NULL, key); | |
e630664c MB |
304 | if (err) { |
305 | mlx4_warn(dev, "HW2SW_MPT failed (%d).", err); | |
306 | mlx4_warn(dev, "Most likely the MR has MWs bound to it.\n"); | |
307 | return err; | |
308 | } | |
309 | ||
310 | mmr->enabled = MLX4_MPT_EN_SW; | |
311 | ||
312 | if (!mlx4_is_mfunc(dev)) { | |
313 | **mpt_entry = mlx4_table_find( | |
314 | &mlx4_priv(dev)->mr_table.dmpt_table, | |
315 | key, NULL); | |
316 | } else { | |
317 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
175f8d67 | 318 | if (IS_ERR(mailbox)) |
e630664c MB |
319 | return PTR_ERR(mailbox); |
320 | ||
321 | err = mlx4_cmd_box(dev, 0, mailbox->dma, key, | |
322 | 0, MLX4_CMD_QUERY_MPT, | |
323 | MLX4_CMD_TIME_CLASS_B, | |
324 | MLX4_CMD_WRAPPED); | |
e630664c MB |
325 | if (err) |
326 | goto free_mailbox; | |
327 | ||
328 | *mpt_entry = (struct mlx4_mpt_entry **)&mailbox->buf; | |
329 | } | |
330 | ||
331 | if (!(*mpt_entry) || !(**mpt_entry)) { | |
332 | err = -ENOMEM; | |
333 | goto free_mailbox; | |
334 | } | |
335 | ||
336 | return 0; | |
337 | ||
338 | free_mailbox: | |
339 | mlx4_free_cmd_mailbox(dev, mailbox); | |
340 | return err; | |
341 | } | |
342 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_get_mpt); | |
343 | ||
344 | int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, | |
345 | struct mlx4_mpt_entry **mpt_entry) | |
346 | { | |
347 | int err; | |
348 | ||
349 | if (!mlx4_is_mfunc(dev)) { | |
350 | /* Make sure any changes to this entry are flushed */ | |
351 | wmb(); | |
352 | ||
353 | *(u8 *)(*mpt_entry) = MLX4_MPT_STATUS_HW; | |
354 | ||
355 | /* Make sure the new status is written */ | |
356 | wmb(); | |
357 | ||
358 | err = mlx4_SYNC_TPT(dev); | |
359 | } else { | |
360 | int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1); | |
361 | ||
362 | struct mlx4_cmd_mailbox *mailbox = | |
363 | container_of((void *)mpt_entry, struct mlx4_cmd_mailbox, | |
364 | buf); | |
365 | ||
366 | err = mlx4_SW2HW_MPT(dev, mailbox, key); | |
367 | } | |
368 | ||
4ff0acca MB |
369 | if (!err) { |
370 | mmr->pd = be32_to_cpu((*mpt_entry)->pd_flags) & MLX4_MPT_PD_MASK; | |
e630664c | 371 | mmr->enabled = MLX4_MPT_EN_HW; |
4ff0acca | 372 | } |
e630664c MB |
373 | return err; |
374 | } | |
375 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_write_mpt); | |
376 | ||
377 | void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, | |
378 | struct mlx4_mpt_entry **mpt_entry) | |
379 | { | |
380 | if (mlx4_is_mfunc(dev)) { | |
381 | struct mlx4_cmd_mailbox *mailbox = | |
382 | container_of((void *)mpt_entry, struct mlx4_cmd_mailbox, | |
383 | buf); | |
384 | mlx4_free_cmd_mailbox(dev, mailbox); | |
385 | } | |
386 | } | |
387 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_put_mpt); | |
388 | ||
389 | int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, | |
390 | u32 pdn) | |
391 | { | |
4ff0acca | 392 | u32 pd_flags = be32_to_cpu(mpt_entry->pd_flags) & ~MLX4_MPT_PD_MASK; |
e630664c MB |
393 | /* The wrapper function will put the slave's id here */ |
394 | if (mlx4_is_mfunc(dev)) | |
395 | pd_flags &= ~MLX4_MPT_PD_VF_MASK; | |
4ff0acca MB |
396 | |
397 | mpt_entry->pd_flags = cpu_to_be32(pd_flags | | |
e630664c MB |
398 | (pdn & MLX4_MPT_PD_MASK) |
399 | | MLX4_MPT_PD_FLAG_EN_INV); | |
400 | return 0; | |
401 | } | |
402 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_pd); | |
403 | ||
404 | int mlx4_mr_hw_change_access(struct mlx4_dev *dev, | |
405 | struct mlx4_mpt_entry *mpt_entry, | |
406 | u32 access) | |
407 | { | |
408 | u32 flags = (be32_to_cpu(mpt_entry->flags) & ~MLX4_PERM_MASK) | | |
409 | (access & MLX4_PERM_MASK); | |
410 | ||
411 | mpt_entry->flags = cpu_to_be32(flags); | |
412 | return 0; | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_access); | |
415 | ||
66431a7d | 416 | static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, |
ea51b377 JM |
417 | u64 iova, u64 size, u32 access, int npages, |
418 | int page_shift, struct mlx4_mr *mr) | |
419 | { | |
225c7b1f RD |
420 | mr->iova = iova; |
421 | mr->size = size; | |
422 | mr->pd = pd; | |
423 | mr->access = access; | |
b20e519a | 424 | mr->enabled = MLX4_MPT_DISABLED; |
ea51b377 JM |
425 | mr->key = hw_index_to_key(mridx); |
426 | ||
427 | return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); | |
428 | } | |
ea51b377 JM |
429 | |
430 | static int mlx4_WRITE_MTT(struct mlx4_dev *dev, | |
431 | struct mlx4_cmd_mailbox *mailbox, | |
432 | int num_entries) | |
433 | { | |
434 | return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT, | |
435 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
436 | } | |
437 | ||
b20e519a | 438 | int __mlx4_mpt_reserve(struct mlx4_dev *dev) |
ea51b377 JM |
439 | { |
440 | struct mlx4_priv *priv = mlx4_priv(dev); | |
441 | ||
442 | return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap); | |
443 | } | |
225c7b1f | 444 | |
b20e519a | 445 | static int mlx4_mpt_reserve(struct mlx4_dev *dev) |
ea51b377 JM |
446 | { |
447 | u64 out_param; | |
448 | ||
449 | if (mlx4_is_mfunc(dev)) { | |
450 | if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE, | |
451 | MLX4_CMD_ALLOC_RES, | |
452 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED)) | |
453 | return -1; | |
454 | return get_param_l(&out_param); | |
455 | } | |
b20e519a | 456 | return __mlx4_mpt_reserve(dev); |
ea51b377 JM |
457 | } |
458 | ||
b20e519a | 459 | void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index) |
ea51b377 JM |
460 | { |
461 | struct mlx4_priv *priv = mlx4_priv(dev); | |
462 | ||
7c6d74d2 | 463 | mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index, MLX4_NO_RR); |
ea51b377 JM |
464 | } |
465 | ||
b20e519a | 466 | static void mlx4_mpt_release(struct mlx4_dev *dev, u32 index) |
ea51b377 | 467 | { |
e7dbeba8 | 468 | u64 in_param = 0; |
ea51b377 JM |
469 | |
470 | if (mlx4_is_mfunc(dev)) { | |
471 | set_param_l(&in_param, index); | |
472 | if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE, | |
473 | MLX4_CMD_FREE_RES, | |
474 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED)) | |
475 | mlx4_warn(dev, "Failed to release mr index:%d\n", | |
476 | index); | |
477 | return; | |
478 | } | |
b20e519a | 479 | __mlx4_mpt_release(dev, index); |
ea51b377 JM |
480 | } |
481 | ||
8900b894 | 482 | int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index) |
ea51b377 JM |
483 | { |
484 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
485 | ||
8900b894 | 486 | return mlx4_table_get(dev, &mr_table->dmpt_table, index); |
ea51b377 JM |
487 | } |
488 | ||
8900b894 | 489 | static int mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index) |
ea51b377 | 490 | { |
e7dbeba8 | 491 | u64 param = 0; |
ea51b377 JM |
492 | |
493 | if (mlx4_is_mfunc(dev)) { | |
494 | set_param_l(¶m, index); | |
495 | return mlx4_cmd_imm(dev, param, ¶m, RES_MPT, RES_OP_MAP_ICM, | |
496 | MLX4_CMD_ALLOC_RES, | |
497 | MLX4_CMD_TIME_CLASS_A, | |
498 | MLX4_CMD_WRAPPED); | |
499 | } | |
8900b894 | 500 | return __mlx4_mpt_alloc_icm(dev, index); |
ea51b377 JM |
501 | } |
502 | ||
b20e519a | 503 | void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index) |
ea51b377 JM |
504 | { |
505 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
506 | ||
507 | mlx4_table_put(dev, &mr_table->dmpt_table, index); | |
508 | } | |
509 | ||
b20e519a | 510 | static void mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index) |
ea51b377 | 511 | { |
e7dbeba8 | 512 | u64 in_param = 0; |
ea51b377 JM |
513 | |
514 | if (mlx4_is_mfunc(dev)) { | |
515 | set_param_l(&in_param, index); | |
516 | if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM, | |
517 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
518 | MLX4_CMD_WRAPPED)) | |
519 | mlx4_warn(dev, "Failed to free icm of mr index:%d\n", | |
520 | index); | |
521 | return; | |
522 | } | |
b20e519a | 523 | return __mlx4_mpt_free_icm(dev, index); |
ea51b377 JM |
524 | } |
525 | ||
526 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
527 | int npages, int page_shift, struct mlx4_mr *mr) | |
528 | { | |
529 | u32 index; | |
530 | int err; | |
531 | ||
b20e519a | 532 | index = mlx4_mpt_reserve(dev); |
ea51b377 JM |
533 | if (index == -1) |
534 | return -ENOMEM; | |
535 | ||
536 | err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size, | |
537 | access, npages, page_shift, mr); | |
225c7b1f | 538 | if (err) |
b20e519a | 539 | mlx4_mpt_release(dev, index); |
225c7b1f | 540 | |
225c7b1f RD |
541 | return err; |
542 | } | |
543 | EXPORT_SYMBOL_GPL(mlx4_mr_alloc); | |
544 | ||
61083720 | 545 | static int mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr) |
225c7b1f | 546 | { |
225c7b1f RD |
547 | int err; |
548 | ||
b20e519a | 549 | if (mr->enabled == MLX4_MPT_EN_HW) { |
225c7b1f RD |
550 | err = mlx4_HW2SW_MPT(dev, NULL, |
551 | key_to_hw_index(mr->key) & | |
552 | (dev->caps.num_mpts - 1)); | |
61083720 | 553 | if (err) { |
1a91de28 JP |
554 | mlx4_warn(dev, "HW2SW_MPT failed (%d), MR has MWs bound to it\n", |
555 | err); | |
61083720 SM |
556 | return err; |
557 | } | |
225c7b1f | 558 | |
b20e519a | 559 | mr->enabled = MLX4_MPT_EN_SW; |
ea51b377 | 560 | } |
225c7b1f | 561 | mlx4_mtt_cleanup(dev, &mr->mtt); |
61083720 SM |
562 | |
563 | return 0; | |
ea51b377 | 564 | } |
ea51b377 | 565 | |
61083720 | 566 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr) |
ea51b377 | 567 | { |
61083720 SM |
568 | int ret; |
569 | ||
570 | ret = mlx4_mr_free_reserved(dev, mr); | |
571 | if (ret) | |
572 | return ret; | |
ea51b377 | 573 | if (mr->enabled) |
b20e519a SM |
574 | mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key)); |
575 | mlx4_mpt_release(dev, key_to_hw_index(mr->key)); | |
61083720 SM |
576 | |
577 | return 0; | |
225c7b1f RD |
578 | } |
579 | EXPORT_SYMBOL_GPL(mlx4_mr_free); | |
580 | ||
e630664c MB |
581 | void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr) |
582 | { | |
583 | mlx4_mtt_cleanup(dev, &mr->mtt); | |
a51e0df4 | 584 | mr->mtt.order = -1; |
e630664c MB |
585 | } |
586 | EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_cleanup); | |
587 | ||
588 | int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, | |
589 | u64 iova, u64 size, int npages, | |
590 | int page_shift, struct mlx4_mpt_entry *mpt_entry) | |
591 | { | |
592 | int err; | |
593 | ||
e630664c MB |
594 | err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); |
595 | if (err) | |
596 | return err; | |
597 | ||
b332068c MG |
598 | mpt_entry->start = cpu_to_be64(iova); |
599 | mpt_entry->length = cpu_to_be64(size); | |
600 | mpt_entry->entity_size = cpu_to_be32(page_shift); | |
601 | mpt_entry->flags &= ~(cpu_to_be32(MLX4_MPT_FLAG_FREE | | |
602 | MLX4_MPT_FLAG_SW_OWNS)); | |
e630664c MB |
603 | if (mr->mtt.order < 0) { |
604 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL); | |
605 | mpt_entry->mtt_addr = 0; | |
606 | } else { | |
607 | mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev, | |
608 | &mr->mtt)); | |
609 | if (mr->mtt.page_shift == 0) | |
610 | mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order); | |
611 | } | |
4ff0acca MB |
612 | if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) { |
613 | /* fast register MR in free state */ | |
614 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); | |
615 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG | | |
616 | MLX4_MPT_PD_FLAG_RAE); | |
617 | } else { | |
618 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); | |
619 | } | |
e630664c MB |
620 | mr->enabled = MLX4_MPT_EN_SW; |
621 | ||
622 | return 0; | |
623 | } | |
624 | EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_write); | |
625 | ||
225c7b1f RD |
626 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr) |
627 | { | |
225c7b1f RD |
628 | struct mlx4_cmd_mailbox *mailbox; |
629 | struct mlx4_mpt_entry *mpt_entry; | |
630 | int err; | |
631 | ||
8900b894 | 632 | err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mr->key)); |
225c7b1f RD |
633 | if (err) |
634 | return err; | |
635 | ||
636 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
637 | if (IS_ERR(mailbox)) { | |
638 | err = PTR_ERR(mailbox); | |
639 | goto err_table; | |
640 | } | |
641 | mpt_entry = mailbox->buf; | |
95d04f07 | 642 | mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO | |
225c7b1f RD |
643 | MLX4_MPT_FLAG_REGION | |
644 | mr->access); | |
225c7b1f RD |
645 | |
646 | mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key)); | |
95d04f07 | 647 | mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV); |
225c7b1f RD |
648 | mpt_entry->start = cpu_to_be64(mr->iova); |
649 | mpt_entry->length = cpu_to_be64(mr->size); | |
650 | mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift); | |
95d04f07 | 651 | |
b2d9308a JM |
652 | if (mr->mtt.order < 0) { |
653 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL); | |
2b8fb286 | 654 | mpt_entry->mtt_addr = 0; |
95d04f07 | 655 | } else { |
2b8fb286 MA |
656 | mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev, |
657 | &mr->mtt)); | |
95d04f07 RD |
658 | } |
659 | ||
660 | if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) { | |
661 | /* fast register MR in free state */ | |
662 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); | |
c9257433 VS |
663 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG | |
664 | MLX4_MPT_PD_FLAG_RAE); | |
2b8fb286 | 665 | mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order); |
95d04f07 RD |
666 | } else { |
667 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); | |
668 | } | |
225c7b1f RD |
669 | |
670 | err = mlx4_SW2HW_MPT(dev, mailbox, | |
671 | key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1)); | |
672 | if (err) { | |
673 | mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err); | |
674 | goto err_cmd; | |
675 | } | |
b20e519a | 676 | mr->enabled = MLX4_MPT_EN_HW; |
225c7b1f RD |
677 | |
678 | mlx4_free_cmd_mailbox(dev, mailbox); | |
679 | ||
680 | return 0; | |
681 | ||
682 | err_cmd: | |
683 | mlx4_free_cmd_mailbox(dev, mailbox); | |
684 | ||
685 | err_table: | |
b20e519a | 686 | mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key)); |
225c7b1f RD |
687 | return err; |
688 | } | |
689 | EXPORT_SYMBOL_GPL(mlx4_mr_enable); | |
690 | ||
d7bb58fb JM |
691 | static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
692 | int start_index, int npages, u64 *page_list) | |
225c7b1f | 693 | { |
d7bb58fb JM |
694 | struct mlx4_priv *priv = mlx4_priv(dev); |
695 | __be64 *mtts; | |
696 | dma_addr_t dma_handle; | |
697 | int i; | |
d7bb58fb | 698 | |
2b8fb286 MA |
699 | mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->offset + |
700 | start_index, &dma_handle); | |
d7bb58fb | 701 | |
d7bb58fb JM |
702 | if (!mtts) |
703 | return -ENOMEM; | |
704 | ||
872bf2fb | 705 | dma_sync_single_for_cpu(&dev->persist->pdev->dev, dma_handle, |
e727f5cd RD |
706 | npages * sizeof (u64), DMA_TO_DEVICE); |
707 | ||
d7bb58fb JM |
708 | for (i = 0; i < npages; ++i) |
709 | mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT); | |
710 | ||
872bf2fb | 711 | dma_sync_single_for_device(&dev->persist->pdev->dev, dma_handle, |
e727f5cd | 712 | npages * sizeof (u64), DMA_TO_DEVICE); |
d7bb58fb JM |
713 | |
714 | return 0; | |
225c7b1f RD |
715 | } |
716 | ||
c82e9aa0 | 717 | int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
ea51b377 | 718 | int start_index, int npages, u64 *page_list) |
225c7b1f | 719 | { |
ea51b377 | 720 | int err = 0; |
d7bb58fb | 721 | int chunk; |
2b8fb286 MA |
722 | int mtts_per_page; |
723 | int max_mtts_first_page; | |
724 | ||
725 | /* compute how may mtts fit in the first page */ | |
726 | mtts_per_page = PAGE_SIZE / sizeof(u64); | |
727 | max_mtts_first_page = mtts_per_page - (mtt->offset + start_index) | |
728 | % mtts_per_page; | |
729 | ||
730 | chunk = min_t(int, max_mtts_first_page, npages); | |
225c7b1f | 731 | |
225c7b1f | 732 | while (npages > 0) { |
d7bb58fb | 733 | err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list); |
225c7b1f | 734 | if (err) |
d7bb58fb | 735 | return err; |
d7bb58fb JM |
736 | npages -= chunk; |
737 | start_index += chunk; | |
738 | page_list += chunk; | |
2b8fb286 MA |
739 | |
740 | chunk = min_t(int, mtts_per_page, npages); | |
225c7b1f | 741 | } |
ea51b377 JM |
742 | return err; |
743 | } | |
225c7b1f | 744 | |
ea51b377 JM |
745 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
746 | int start_index, int npages, u64 *page_list) | |
747 | { | |
748 | struct mlx4_cmd_mailbox *mailbox = NULL; | |
749 | __be64 *inbox = NULL; | |
750 | int chunk; | |
751 | int err = 0; | |
752 | int i; | |
753 | ||
754 | if (mtt->order < 0) | |
755 | return -EINVAL; | |
756 | ||
757 | if (mlx4_is_mfunc(dev)) { | |
758 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
759 | if (IS_ERR(mailbox)) | |
760 | return PTR_ERR(mailbox); | |
761 | inbox = mailbox->buf; | |
762 | ||
763 | while (npages > 0) { | |
2b8fb286 MA |
764 | chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) - 2, |
765 | npages); | |
766 | inbox[0] = cpu_to_be64(mtt->offset + start_index); | |
ea51b377 JM |
767 | inbox[1] = 0; |
768 | for (i = 0; i < chunk; ++i) | |
769 | inbox[i + 2] = cpu_to_be64(page_list[i] | | |
770 | MLX4_MTT_FLAG_PRESENT); | |
771 | err = mlx4_WRITE_MTT(dev, mailbox, chunk); | |
772 | if (err) { | |
773 | mlx4_free_cmd_mailbox(dev, mailbox); | |
774 | return err; | |
775 | } | |
776 | ||
777 | npages -= chunk; | |
778 | start_index += chunk; | |
779 | page_list += chunk; | |
780 | } | |
781 | mlx4_free_cmd_mailbox(dev, mailbox); | |
782 | return err; | |
783 | } | |
784 | ||
785 | return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list); | |
225c7b1f RD |
786 | } |
787 | EXPORT_SYMBOL_GPL(mlx4_write_mtt); | |
788 | ||
789 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
8900b894 | 790 | struct mlx4_buf *buf) |
225c7b1f RD |
791 | { |
792 | u64 *page_list; | |
793 | int err; | |
794 | int i; | |
795 | ||
8900b894 | 796 | page_list = kcalloc(buf->npages, sizeof(*page_list), GFP_KERNEL); |
225c7b1f RD |
797 | if (!page_list) |
798 | return -ENOMEM; | |
799 | ||
800 | for (i = 0; i < buf->npages; ++i) | |
801 | if (buf->nbufs == 1) | |
b57aacfa | 802 | page_list[i] = buf->direct.map + (i << buf->page_shift); |
225c7b1f | 803 | else |
b57aacfa | 804 | page_list[i] = buf->page_list[i].map; |
225c7b1f RD |
805 | |
806 | err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list); | |
807 | ||
808 | kfree(page_list); | |
809 | return err; | |
810 | } | |
811 | EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt); | |
812 | ||
804d6a89 SM |
813 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
814 | struct mlx4_mw *mw) | |
815 | { | |
816 | u32 index; | |
817 | ||
818 | if ((type == MLX4_MW_TYPE_1 && | |
819 | !(dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)) || | |
820 | (type == MLX4_MW_TYPE_2 && | |
821 | !(dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN))) | |
423b3aec | 822 | return -EOPNOTSUPP; |
804d6a89 SM |
823 | |
824 | index = mlx4_mpt_reserve(dev); | |
825 | if (index == -1) | |
826 | return -ENOMEM; | |
827 | ||
828 | mw->key = hw_index_to_key(index); | |
829 | mw->pd = pd; | |
830 | mw->type = type; | |
831 | mw->enabled = MLX4_MPT_DISABLED; | |
832 | ||
833 | return 0; | |
834 | } | |
835 | EXPORT_SYMBOL_GPL(mlx4_mw_alloc); | |
836 | ||
837 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw) | |
838 | { | |
839 | struct mlx4_cmd_mailbox *mailbox; | |
840 | struct mlx4_mpt_entry *mpt_entry; | |
841 | int err; | |
842 | ||
8900b894 | 843 | err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mw->key)); |
804d6a89 SM |
844 | if (err) |
845 | return err; | |
846 | ||
847 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
848 | if (IS_ERR(mailbox)) { | |
849 | err = PTR_ERR(mailbox); | |
850 | goto err_table; | |
851 | } | |
852 | mpt_entry = mailbox->buf; | |
853 | ||
804d6a89 SM |
854 | /* Note that the MLX4_MPT_FLAG_REGION bit in mpt_entry->flags is turned |
855 | * off, thus creating a memory window and not a memory region. | |
856 | */ | |
857 | mpt_entry->key = cpu_to_be32(key_to_hw_index(mw->key)); | |
858 | mpt_entry->pd_flags = cpu_to_be32(mw->pd); | |
859 | if (mw->type == MLX4_MW_TYPE_2) { | |
860 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); | |
861 | mpt_entry->qpn = cpu_to_be32(MLX4_MPT_QP_FLAG_BOUND_QP); | |
862 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_EN_INV); | |
863 | } | |
864 | ||
865 | err = mlx4_SW2HW_MPT(dev, mailbox, | |
866 | key_to_hw_index(mw->key) & | |
867 | (dev->caps.num_mpts - 1)); | |
868 | if (err) { | |
869 | mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err); | |
870 | goto err_cmd; | |
871 | } | |
872 | mw->enabled = MLX4_MPT_EN_HW; | |
873 | ||
874 | mlx4_free_cmd_mailbox(dev, mailbox); | |
875 | ||
876 | return 0; | |
877 | ||
878 | err_cmd: | |
879 | mlx4_free_cmd_mailbox(dev, mailbox); | |
880 | ||
881 | err_table: | |
882 | mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key)); | |
883 | return err; | |
884 | } | |
885 | EXPORT_SYMBOL_GPL(mlx4_mw_enable); | |
886 | ||
887 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw) | |
888 | { | |
889 | int err; | |
890 | ||
891 | if (mw->enabled == MLX4_MPT_EN_HW) { | |
892 | err = mlx4_HW2SW_MPT(dev, NULL, | |
893 | key_to_hw_index(mw->key) & | |
894 | (dev->caps.num_mpts - 1)); | |
895 | if (err) | |
896 | mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err); | |
897 | ||
898 | mw->enabled = MLX4_MPT_EN_SW; | |
899 | } | |
900 | if (mw->enabled) | |
901 | mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key)); | |
902 | mlx4_mpt_release(dev, key_to_hw_index(mw->key)); | |
903 | } | |
904 | EXPORT_SYMBOL_GPL(mlx4_mw_free); | |
905 | ||
3d73c288 | 906 | int mlx4_init_mr_table(struct mlx4_dev *dev) |
225c7b1f | 907 | { |
ea51b377 JM |
908 | struct mlx4_priv *priv = mlx4_priv(dev); |
909 | struct mlx4_mr_table *mr_table = &priv->mr_table; | |
225c7b1f RD |
910 | int err; |
911 | ||
ea51b377 JM |
912 | /* Nothing to do for slaves - all MR handling is forwarded |
913 | * to the master */ | |
914 | if (mlx4_is_slave(dev)) | |
915 | return 0; | |
916 | ||
a30f1bc5 JM |
917 | if (!is_power_of_2(dev->caps.num_mpts)) |
918 | return -EINVAL; | |
919 | ||
225c7b1f | 920 | err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts, |
93fc9e1b | 921 | ~0, dev->caps.reserved_mrws, 0); |
225c7b1f RD |
922 | if (err) |
923 | return err; | |
924 | ||
925 | err = mlx4_buddy_init(&mr_table->mtt_buddy, | |
3de819e6 | 926 | ilog2((u32)dev->caps.num_mtts / |
2b8fb286 | 927 | (1 << log_mtts_per_seg))); |
225c7b1f RD |
928 | if (err) |
929 | goto err_buddy; | |
930 | ||
931 | if (dev->caps.reserved_mtts) { | |
ea51b377 JM |
932 | priv->reserved_mtts = |
933 | mlx4_alloc_mtt_range(dev, | |
934 | fls(dev->caps.reserved_mtts - 1)); | |
935 | if (priv->reserved_mtts < 0) { | |
1a91de28 | 936 | mlx4_warn(dev, "MTT table of order %u is too small\n", |
225c7b1f RD |
937 | mr_table->mtt_buddy.max_order); |
938 | err = -ENOMEM; | |
939 | goto err_reserve_mtts; | |
940 | } | |
941 | } | |
942 | ||
943 | return 0; | |
944 | ||
945 | err_reserve_mtts: | |
946 | mlx4_buddy_cleanup(&mr_table->mtt_buddy); | |
947 | ||
948 | err_buddy: | |
949 | mlx4_bitmap_cleanup(&mr_table->mpt_bitmap); | |
950 | ||
951 | return err; | |
952 | } | |
953 | ||
954 | void mlx4_cleanup_mr_table(struct mlx4_dev *dev) | |
955 | { | |
ea51b377 JM |
956 | struct mlx4_priv *priv = mlx4_priv(dev); |
957 | struct mlx4_mr_table *mr_table = &priv->mr_table; | |
225c7b1f | 958 | |
ea51b377 JM |
959 | if (mlx4_is_slave(dev)) |
960 | return; | |
961 | if (priv->reserved_mtts >= 0) | |
962 | mlx4_free_mtt_range(dev, priv->reserved_mtts, | |
963 | fls(dev->caps.reserved_mtts - 1)); | |
225c7b1f RD |
964 | mlx4_buddy_cleanup(&mr_table->mtt_buddy); |
965 | mlx4_bitmap_cleanup(&mr_table->mpt_bitmap); | |
966 | } | |
8ad11fb6 JM |
967 | |
968 | static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list, | |
969 | int npages, u64 iova) | |
970 | { | |
971 | int i, page_mask; | |
972 | ||
973 | if (npages > fmr->max_pages) | |
974 | return -EINVAL; | |
975 | ||
976 | page_mask = (1 << fmr->page_shift) - 1; | |
977 | ||
978 | /* We are getting page lists, so va must be page aligned. */ | |
979 | if (iova & page_mask) | |
980 | return -EINVAL; | |
981 | ||
982 | /* Trust the user not to pass misaligned data in page_list */ | |
983 | if (0) | |
984 | for (i = 0; i < npages; ++i) { | |
985 | if (page_list[i] & ~page_mask) | |
986 | return -EINVAL; | |
987 | } | |
988 | ||
989 | if (fmr->maps >= fmr->max_maps) | |
990 | return -EINVAL; | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
995 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, | |
996 | int npages, u64 iova, u32 *lkey, u32 *rkey) | |
997 | { | |
998 | u32 key; | |
999 | int i, err; | |
1000 | ||
1001 | err = mlx4_check_fmr(fmr, page_list, npages, iova); | |
1002 | if (err) | |
1003 | return err; | |
1004 | ||
1005 | ++fmr->maps; | |
1006 | ||
1007 | key = key_to_hw_index(fmr->mr.key); | |
1008 | key += dev->caps.num_mpts; | |
1009 | *lkey = *rkey = fmr->mr.key = hw_index_to_key(key); | |
1010 | ||
1011 | *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW; | |
1012 | ||
1013 | /* Make sure MPT status is visible before writing MTT entries */ | |
1014 | wmb(); | |
1015 | ||
872bf2fb | 1016 | dma_sync_single_for_cpu(&dev->persist->pdev->dev, fmr->dma_handle, |
e727f5cd RD |
1017 | npages * sizeof(u64), DMA_TO_DEVICE); |
1018 | ||
8ad11fb6 JM |
1019 | for (i = 0; i < npages; ++i) |
1020 | fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT); | |
1021 | ||
872bf2fb | 1022 | dma_sync_single_for_device(&dev->persist->pdev->dev, fmr->dma_handle, |
e727f5cd | 1023 | npages * sizeof(u64), DMA_TO_DEVICE); |
8ad11fb6 JM |
1024 | |
1025 | fmr->mpt->key = cpu_to_be32(key); | |
1026 | fmr->mpt->lkey = cpu_to_be32(key); | |
1027 | fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift)); | |
1028 | fmr->mpt->start = cpu_to_be64(iova); | |
1029 | ||
1030 | /* Make MTT entries are visible before setting MPT status */ | |
1031 | wmb(); | |
1032 | ||
1033 | *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW; | |
1034 | ||
1035 | /* Make sure MPT status is visible before consumer can use FMR */ | |
1036 | wmb(); | |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr); | |
1041 | ||
1042 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1043 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr) | |
1044 | { | |
1045 | struct mlx4_priv *priv = mlx4_priv(dev); | |
8ad11fb6 JM |
1046 | int err = -ENOMEM; |
1047 | ||
a5bbe892 EC |
1048 | if (max_maps > dev->caps.max_fmr_maps) |
1049 | return -EINVAL; | |
1050 | ||
c5057ddc | 1051 | if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32) |
8ad11fb6 JM |
1052 | return -EINVAL; |
1053 | ||
1054 | /* All MTTs must fit in the same page */ | |
1055 | if (max_pages * sizeof *fmr->mtts > PAGE_SIZE) | |
1056 | return -EINVAL; | |
1057 | ||
1058 | fmr->page_shift = page_shift; | |
1059 | fmr->max_pages = max_pages; | |
1060 | fmr->max_maps = max_maps; | |
1061 | fmr->maps = 0; | |
1062 | ||
1063 | err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages, | |
1064 | page_shift, &fmr->mr); | |
1065 | if (err) | |
1066 | return err; | |
1067 | ||
8ad11fb6 | 1068 | fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table, |
2b8fb286 | 1069 | fmr->mr.mtt.offset, |
8ad11fb6 | 1070 | &fmr->dma_handle); |
2b8fb286 | 1071 | |
8ad11fb6 JM |
1072 | if (!fmr->mtts) { |
1073 | err = -ENOMEM; | |
1074 | goto err_free; | |
1075 | } | |
1076 | ||
8ad11fb6 JM |
1077 | return 0; |
1078 | ||
1079 | err_free: | |
61083720 | 1080 | (void) mlx4_mr_free(dev, &fmr->mr); |
8ad11fb6 JM |
1081 | return err; |
1082 | } | |
1083 | EXPORT_SYMBOL_GPL(mlx4_fmr_alloc); | |
1084 | ||
1085 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr) | |
1086 | { | |
11e75a74 JM |
1087 | struct mlx4_priv *priv = mlx4_priv(dev); |
1088 | int err; | |
1089 | ||
1090 | err = mlx4_mr_enable(dev, &fmr->mr); | |
1091 | if (err) | |
1092 | return err; | |
1093 | ||
1094 | fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table, | |
1095 | key_to_hw_index(fmr->mr.key), NULL); | |
1096 | if (!fmr->mpt) | |
1097 | return -ENOMEM; | |
1098 | ||
1099 | return 0; | |
8ad11fb6 JM |
1100 | } |
1101 | EXPORT_SYMBOL_GPL(mlx4_fmr_enable); | |
1102 | ||
1103 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1104 | u32 *lkey, u32 *rkey) | |
1105 | { | |
ea51b377 JM |
1106 | struct mlx4_cmd_mailbox *mailbox; |
1107 | int err; | |
1108 | ||
8ad11fb6 JM |
1109 | if (!fmr->maps) |
1110 | return; | |
1111 | ||
8ad11fb6 JM |
1112 | fmr->maps = 0; |
1113 | ||
ea51b377 JM |
1114 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1115 | if (IS_ERR(mailbox)) { | |
1116 | err = PTR_ERR(mailbox); | |
c20862c8 | 1117 | pr_warn("mlx4_ib: mlx4_alloc_cmd_mailbox failed (%d)\n", err); |
ea51b377 JM |
1118 | return; |
1119 | } | |
1120 | ||
1121 | err = mlx4_HW2SW_MPT(dev, NULL, | |
1122 | key_to_hw_index(fmr->mr.key) & | |
1123 | (dev->caps.num_mpts - 1)); | |
1124 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1125 | if (err) { | |
c20862c8 | 1126 | pr_warn("mlx4_ib: mlx4_HW2SW_MPT failed (%d)\n", err); |
ea51b377 JM |
1127 | return; |
1128 | } | |
b20e519a | 1129 | fmr->mr.enabled = MLX4_MPT_EN_SW; |
8ad11fb6 JM |
1130 | } |
1131 | EXPORT_SYMBOL_GPL(mlx4_fmr_unmap); | |
1132 | ||
1133 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr) | |
1134 | { | |
61083720 SM |
1135 | int ret; |
1136 | ||
8ad11fb6 JM |
1137 | if (fmr->maps) |
1138 | return -EBUSY; | |
1139 | ||
61083720 SM |
1140 | ret = mlx4_mr_free(dev, &fmr->mr); |
1141 | if (ret) | |
1142 | return ret; | |
b20e519a | 1143 | fmr->mr.enabled = MLX4_MPT_DISABLED; |
8ad11fb6 JM |
1144 | |
1145 | return 0; | |
1146 | } | |
1147 | EXPORT_SYMBOL_GPL(mlx4_fmr_free); | |
1148 | ||
1149 | int mlx4_SYNC_TPT(struct mlx4_dev *dev) | |
1150 | { | |
5a031086 JM |
1151 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, |
1152 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
8ad11fb6 JM |
1153 | } |
1154 | EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT); |