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2a2336f8 YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/errno.h> | |
34 | #include <linux/if_ether.h> | |
c59fec20 | 35 | #include <linux/if_vlan.h> |
ee40fa06 | 36 | #include <linux/export.h> |
2a2336f8 YP |
37 | |
38 | #include <linux/mlx4/cmd.h> | |
39 | ||
40 | #include "mlx4.h" | |
41 | ||
42 | #define MLX4_MAC_VALID (1ull << 63) | |
2a2336f8 YP |
43 | |
44 | #define MLX4_VLAN_VALID (1u << 31) | |
45 | #define MLX4_VLAN_MASK 0xfff | |
46 | ||
93ece0c1 EE |
47 | #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL |
48 | #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL | |
49 | #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL | |
50 | #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL | |
51 | ||
2a2336f8 YP |
52 | void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table) |
53 | { | |
54 | int i; | |
55 | ||
56 | mutex_init(&table->mutex); | |
57 | for (i = 0; i < MLX4_MAX_MAC_NUM; i++) { | |
58 | table->entries[i] = 0; | |
59 | table->refs[i] = 0; | |
60 | } | |
61 | table->max = 1 << dev->caps.log_num_macs; | |
62 | table->total = 0; | |
63 | } | |
64 | ||
65 | void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table) | |
66 | { | |
67 | int i; | |
68 | ||
69 | mutex_init(&table->mutex); | |
70 | for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) { | |
71 | table->entries[i] = 0; | |
72 | table->refs[i] = 0; | |
73 | } | |
e72ebf5a | 74 | table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR; |
2a2336f8 YP |
75 | table->total = 0; |
76 | } | |
77 | ||
ffe455ad EE |
78 | static int validate_index(struct mlx4_dev *dev, |
79 | struct mlx4_mac_table *table, int index) | |
80 | { | |
81 | int err = 0; | |
82 | ||
83 | if (index < 0 || index >= table->max || !table->entries[index]) { | |
84 | mlx4_warn(dev, "No valid Mac entry for the given index\n"); | |
85 | err = -EINVAL; | |
86 | } | |
87 | return err; | |
88 | } | |
89 | ||
90 | static int find_index(struct mlx4_dev *dev, | |
91 | struct mlx4_mac_table *table, u64 mac) | |
92 | { | |
93 | int i; | |
94 | ||
95 | for (i = 0; i < MLX4_MAX_MAC_NUM; i++) { | |
96 | if ((mac & MLX4_MAC_MASK) == | |
97 | (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) | |
98 | return i; | |
99 | } | |
100 | /* Mac not found */ | |
101 | return -EINVAL; | |
1679200f YP |
102 | } |
103 | ||
ffe455ad EE |
104 | static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port, |
105 | __be64 *entries) | |
106 | { | |
107 | struct mlx4_cmd_mailbox *mailbox; | |
108 | u32 in_mod; | |
109 | int err; | |
110 | ||
111 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
112 | if (IS_ERR(mailbox)) | |
113 | return PTR_ERR(mailbox); | |
114 | ||
115 | memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE); | |
116 | ||
117 | in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port; | |
0f6740c7 | 118 | |
ffe455ad EE |
119 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, |
120 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
121 | ||
122 | mlx4_free_cmd_mailbox(dev, mailbox); | |
123 | return err; | |
124 | } | |
125 | ||
297e0dad MS |
126 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx) |
127 | { | |
128 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
129 | struct mlx4_mac_table *table = &info->mac_table; | |
130 | int i; | |
131 | ||
132 | for (i = 0; i < MLX4_MAX_MAC_NUM; i++) { | |
133 | if (!table->refs[i]) | |
134 | continue; | |
135 | ||
136 | if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) { | |
137 | *idx = i; | |
138 | return 0; | |
139 | } | |
140 | } | |
141 | ||
142 | return -ENOENT; | |
143 | } | |
144 | EXPORT_SYMBOL_GPL(mlx4_find_cached_mac); | |
145 | ||
ffe455ad EE |
146 | int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac) |
147 | { | |
148 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
149 | struct mlx4_mac_table *table = &info->mac_table; | |
150 | int i, err = 0; | |
151 | int free = -1; | |
152 | ||
153 | mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n", | |
154 | (unsigned long long) mac, port); | |
0f6740c7 | 155 | |
2a2336f8 | 156 | mutex_lock(&table->mutex); |
ffe455ad EE |
157 | for (i = 0; i < MLX4_MAX_MAC_NUM; i++) { |
158 | if (free < 0 && !table->entries[i]) { | |
2a2336f8 YP |
159 | free = i; |
160 | continue; | |
161 | } | |
162 | ||
163 | if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) { | |
6ce71acd RE |
164 | /* MAC already registered, increment ref count */ |
165 | err = i; | |
166 | ++table->refs[i]; | |
2a2336f8 YP |
167 | goto out; |
168 | } | |
169 | } | |
0926f910 | 170 | |
2a2336f8 YP |
171 | mlx4_dbg(dev, "Free MAC index is %d\n", free); |
172 | ||
173 | if (table->total == table->max) { | |
174 | /* No free mac entries */ | |
175 | err = -ENOSPC; | |
176 | goto out; | |
177 | } | |
178 | ||
179 | /* Register new MAC */ | |
2a2336f8 YP |
180 | table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID); |
181 | ||
182 | err = mlx4_set_port_mac_table(dev, port, table->entries); | |
183 | if (unlikely(err)) { | |
ffe455ad EE |
184 | mlx4_err(dev, "Failed adding MAC: 0x%llx\n", |
185 | (unsigned long long) mac); | |
2a2336f8 YP |
186 | table->entries[free] = 0; |
187 | goto out; | |
188 | } | |
6ce71acd | 189 | table->refs[free] = 1; |
ffe455ad | 190 | err = free; |
2a2336f8 YP |
191 | ++table->total; |
192 | out: | |
193 | mutex_unlock(&table->mutex); | |
194 | return err; | |
195 | } | |
ffe455ad | 196 | EXPORT_SYMBOL_GPL(__mlx4_register_mac); |
2a2336f8 | 197 | |
ffe455ad | 198 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac) |
2a2336f8 | 199 | { |
e7dbeba8 | 200 | u64 out_param = 0; |
acddd5dd | 201 | int err = -EINVAL; |
2a2336f8 | 202 | |
ffe455ad | 203 | if (mlx4_is_mfunc(dev)) { |
acddd5dd JM |
204 | if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) { |
205 | err = mlx4_cmd_imm(dev, mac, &out_param, | |
206 | ((u32) port) << 8 | (u32) RES_MAC, | |
207 | RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES, | |
208 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
209 | } | |
210 | if (err && err == -EINVAL && mlx4_is_slave(dev)) { | |
211 | /* retry using old REG_MAC format */ | |
212 | set_param_l(&out_param, port); | |
213 | err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC, | |
214 | RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES, | |
215 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
216 | if (!err) | |
217 | dev->flags |= MLX4_FLAG_OLD_REG_MAC; | |
218 | } | |
ffe455ad EE |
219 | if (err) |
220 | return err; | |
1679200f | 221 | |
ffe455ad | 222 | return get_param_l(&out_param); |
1679200f | 223 | } |
ffe455ad | 224 | return __mlx4_register_mac(dev, port, mac); |
1679200f | 225 | } |
ffe455ad EE |
226 | EXPORT_SYMBOL_GPL(mlx4_register_mac); |
227 | ||
16a10ffd YB |
228 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port) |
229 | { | |
230 | return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] + | |
231 | (port - 1) * (1 << dev->caps.log_num_macs); | |
232 | } | |
233 | EXPORT_SYMBOL_GPL(mlx4_get_base_qpn); | |
1679200f | 234 | |
ffe455ad | 235 | void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac) |
1679200f YP |
236 | { |
237 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
238 | struct mlx4_mac_table *table = &info->mac_table; | |
ffe455ad | 239 | int index; |
1679200f | 240 | |
1679200f | 241 | mutex_lock(&table->mutex); |
6ce71acd | 242 | index = find_index(dev, table, mac); |
1679200f YP |
243 | |
244 | if (validate_index(dev, table, index)) | |
245 | goto out; | |
6ce71acd RE |
246 | if (--table->refs[index]) { |
247 | mlx4_dbg(dev, "Have more references for index %d," | |
248 | "no need to modify mac table\n", index); | |
249 | goto out; | |
250 | } | |
1679200f | 251 | |
ffe455ad EE |
252 | table->entries[index] = 0; |
253 | mlx4_set_port_mac_table(dev, port, table->entries); | |
254 | --table->total; | |
2a2336f8 YP |
255 | out: |
256 | mutex_unlock(&table->mutex); | |
257 | } | |
ffe455ad EE |
258 | EXPORT_SYMBOL_GPL(__mlx4_unregister_mac); |
259 | ||
260 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac) | |
261 | { | |
e7dbeba8 | 262 | u64 out_param = 0; |
ffe455ad EE |
263 | |
264 | if (mlx4_is_mfunc(dev)) { | |
acddd5dd JM |
265 | if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) { |
266 | (void) mlx4_cmd_imm(dev, mac, &out_param, | |
267 | ((u32) port) << 8 | (u32) RES_MAC, | |
268 | RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES, | |
269 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
270 | } else { | |
271 | /* use old unregister mac format */ | |
272 | set_param_l(&out_param, port); | |
273 | (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC, | |
274 | RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES, | |
275 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
276 | } | |
ffe455ad EE |
277 | return; |
278 | } | |
279 | __mlx4_unregister_mac(dev, port, mac); | |
280 | return; | |
281 | } | |
2a2336f8 YP |
282 | EXPORT_SYMBOL_GPL(mlx4_unregister_mac); |
283 | ||
16a10ffd | 284 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac) |
1679200f YP |
285 | { |
286 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
287 | struct mlx4_mac_table *table = &info->mac_table; | |
ffe455ad EE |
288 | int index = qpn - info->base_qpn; |
289 | int err = 0; | |
1679200f | 290 | |
ffe455ad | 291 | /* CX1 doesn't support multi-functions */ |
1679200f YP |
292 | mutex_lock(&table->mutex); |
293 | ||
294 | err = validate_index(dev, table, index); | |
295 | if (err) | |
296 | goto out; | |
297 | ||
298 | table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID); | |
299 | ||
300 | err = mlx4_set_port_mac_table(dev, port, table->entries); | |
301 | if (unlikely(err)) { | |
ffe455ad EE |
302 | mlx4_err(dev, "Failed adding MAC: 0x%llx\n", |
303 | (unsigned long long) new_mac); | |
1679200f YP |
304 | table->entries[index] = 0; |
305 | } | |
306 | out: | |
307 | mutex_unlock(&table->mutex); | |
308 | return err; | |
309 | } | |
16a10ffd | 310 | EXPORT_SYMBOL_GPL(__mlx4_replace_mac); |
ffe455ad | 311 | |
2a2336f8 YP |
312 | static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port, |
313 | __be32 *entries) | |
314 | { | |
315 | struct mlx4_cmd_mailbox *mailbox; | |
316 | u32 in_mod; | |
317 | int err; | |
318 | ||
319 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
320 | if (IS_ERR(mailbox)) | |
321 | return PTR_ERR(mailbox); | |
322 | ||
323 | memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE); | |
324 | in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port; | |
325 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
162226a1 | 326 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
2a2336f8 YP |
327 | |
328 | mlx4_free_cmd_mailbox(dev, mailbox); | |
329 | ||
330 | return err; | |
331 | } | |
332 | ||
4c3eb3ca EC |
333 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx) |
334 | { | |
335 | struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table; | |
336 | int i; | |
337 | ||
338 | for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) { | |
339 | if (table->refs[i] && | |
340 | (vid == (MLX4_VLAN_MASK & | |
341 | be32_to_cpu(table->entries[i])))) { | |
342 | /* VLAN already registered, increase reference count */ | |
343 | *idx = i; | |
344 | return 0; | |
345 | } | |
346 | } | |
347 | ||
348 | return -ENOENT; | |
349 | } | |
350 | EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan); | |
351 | ||
3f7fb021 | 352 | int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, |
ffe455ad | 353 | int *index) |
2a2336f8 YP |
354 | { |
355 | struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table; | |
356 | int i, err = 0; | |
357 | int free = -1; | |
358 | ||
359 | mutex_lock(&table->mutex); | |
e72ebf5a YP |
360 | |
361 | if (table->total == table->max) { | |
362 | /* No free vlan entries */ | |
363 | err = -ENOSPC; | |
364 | goto out; | |
365 | } | |
366 | ||
2a2336f8 YP |
367 | for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) { |
368 | if (free < 0 && (table->refs[i] == 0)) { | |
369 | free = i; | |
370 | continue; | |
371 | } | |
372 | ||
373 | if (table->refs[i] && | |
374 | (vlan == (MLX4_VLAN_MASK & | |
375 | be32_to_cpu(table->entries[i])))) { | |
25985edc | 376 | /* Vlan already registered, increase references count */ |
2a2336f8 YP |
377 | *index = i; |
378 | ++table->refs[i]; | |
379 | goto out; | |
380 | } | |
381 | } | |
382 | ||
0926f910 EC |
383 | if (free < 0) { |
384 | err = -ENOMEM; | |
385 | goto out; | |
386 | } | |
387 | ||
ffe455ad | 388 | /* Register new VLAN */ |
2a2336f8 YP |
389 | table->refs[free] = 1; |
390 | table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID); | |
391 | ||
392 | err = mlx4_set_port_vlan_table(dev, port, table->entries); | |
393 | if (unlikely(err)) { | |
394 | mlx4_warn(dev, "Failed adding vlan: %u\n", vlan); | |
395 | table->refs[free] = 0; | |
396 | table->entries[free] = 0; | |
397 | goto out; | |
398 | } | |
399 | ||
400 | *index = free; | |
401 | ++table->total; | |
402 | out: | |
403 | mutex_unlock(&table->mutex); | |
404 | return err; | |
405 | } | |
ffe455ad EE |
406 | |
407 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index) | |
408 | { | |
e7dbeba8 | 409 | u64 out_param = 0; |
ffe455ad EE |
410 | int err; |
411 | ||
162226a1 JM |
412 | if (vlan > 4095) |
413 | return -EINVAL; | |
414 | ||
ffe455ad | 415 | if (mlx4_is_mfunc(dev)) { |
acddd5dd JM |
416 | err = mlx4_cmd_imm(dev, vlan, &out_param, |
417 | ((u32) port) << 8 | (u32) RES_VLAN, | |
ffe455ad EE |
418 | RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES, |
419 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
420 | if (!err) | |
421 | *index = get_param_l(&out_param); | |
422 | ||
423 | return err; | |
424 | } | |
425 | return __mlx4_register_vlan(dev, port, vlan, index); | |
426 | } | |
2a2336f8 YP |
427 | EXPORT_SYMBOL_GPL(mlx4_register_vlan); |
428 | ||
2009d005 | 429 | void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan) |
2a2336f8 YP |
430 | { |
431 | struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table; | |
2009d005 | 432 | int index; |
2a2336f8 | 433 | |
2009d005 JM |
434 | mutex_lock(&table->mutex); |
435 | if (mlx4_find_cached_vlan(dev, port, vlan, &index)) { | |
436 | mlx4_warn(dev, "vlan 0x%x is not in the vlan table\n", vlan); | |
437 | goto out; | |
2a2336f8 YP |
438 | } |
439 | ||
2009d005 JM |
440 | if (index < MLX4_VLAN_REGULAR) { |
441 | mlx4_warn(dev, "Trying to free special vlan index %d\n", index); | |
2a2336f8 YP |
442 | goto out; |
443 | } | |
2009d005 | 444 | |
2a2336f8 | 445 | if (--table->refs[index]) { |
2009d005 JM |
446 | mlx4_dbg(dev, "Have %d more references for index %d," |
447 | "no need to modify vlan table\n", table->refs[index], | |
448 | index); | |
2a2336f8 YP |
449 | goto out; |
450 | } | |
451 | table->entries[index] = 0; | |
452 | mlx4_set_port_vlan_table(dev, port, table->entries); | |
453 | --table->total; | |
454 | out: | |
455 | mutex_unlock(&table->mutex); | |
456 | } | |
ffe455ad | 457 | |
2009d005 | 458 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan) |
ffe455ad | 459 | { |
162226a1 | 460 | u64 out_param = 0; |
ffe455ad EE |
461 | |
462 | if (mlx4_is_mfunc(dev)) { | |
2009d005 | 463 | (void) mlx4_cmd_imm(dev, vlan, &out_param, |
acddd5dd | 464 | ((u32) port) << 8 | (u32) RES_VLAN, |
162226a1 JM |
465 | RES_OP_RESERVE_AND_MAP, |
466 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
467 | MLX4_CMD_WRAPPED); | |
ffe455ad EE |
468 | return; |
469 | } | |
2009d005 | 470 | __mlx4_unregister_vlan(dev, port, vlan); |
ffe455ad | 471 | } |
2a2336f8 | 472 | EXPORT_SYMBOL_GPL(mlx4_unregister_vlan); |
7ff93f8b | 473 | |
9a5aa622 JM |
474 | int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps) |
475 | { | |
476 | struct mlx4_cmd_mailbox *inmailbox, *outmailbox; | |
477 | u8 *inbuf, *outbuf; | |
478 | int err; | |
479 | ||
480 | inmailbox = mlx4_alloc_cmd_mailbox(dev); | |
481 | if (IS_ERR(inmailbox)) | |
482 | return PTR_ERR(inmailbox); | |
483 | ||
484 | outmailbox = mlx4_alloc_cmd_mailbox(dev); | |
485 | if (IS_ERR(outmailbox)) { | |
486 | mlx4_free_cmd_mailbox(dev, inmailbox); | |
487 | return PTR_ERR(outmailbox); | |
488 | } | |
489 | ||
490 | inbuf = inmailbox->buf; | |
491 | outbuf = outmailbox->buf; | |
9a5aa622 JM |
492 | inbuf[0] = 1; |
493 | inbuf[1] = 1; | |
494 | inbuf[2] = 1; | |
495 | inbuf[3] = 1; | |
496 | *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015); | |
497 | *(__be32 *) (&inbuf[20]) = cpu_to_be32(port); | |
498 | ||
499 | err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3, | |
f9baff50 JM |
500 | MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C, |
501 | MLX4_CMD_NATIVE); | |
9a5aa622 JM |
502 | if (!err) |
503 | *caps = *(__be32 *) (outbuf + 84); | |
504 | mlx4_free_cmd_mailbox(dev, inmailbox); | |
505 | mlx4_free_cmd_mailbox(dev, outmailbox); | |
506 | return err; | |
507 | } | |
9cd59352 | 508 | static struct mlx4_roce_gid_entry zgid_entry; |
9a5aa622 | 509 | |
449fc488 | 510 | int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port) |
b6ffaeff | 511 | { |
449fc488 MB |
512 | int vfs; |
513 | int slave_gid = slave; | |
514 | unsigned i; | |
515 | struct mlx4_slaves_pport slaves_pport; | |
516 | struct mlx4_active_ports actv_ports; | |
517 | unsigned max_port_p_one; | |
518 | ||
b6ffaeff JM |
519 | if (slave == 0) |
520 | return MLX4_ROCE_PF_GIDS; | |
449fc488 MB |
521 | |
522 | /* Slave is a VF */ | |
523 | slaves_pport = mlx4_phys_to_slaves_pport(dev, port); | |
524 | actv_ports = mlx4_get_active_ports(dev, slave); | |
525 | max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) + | |
526 | bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1; | |
527 | ||
528 | for (i = 1; i < max_port_p_one; i++) { | |
529 | struct mlx4_active_ports exclusive_ports; | |
530 | struct mlx4_slaves_pport slaves_pport_actv; | |
531 | bitmap_zero(exclusive_ports.ports, dev->caps.num_ports); | |
532 | set_bit(i - 1, exclusive_ports.ports); | |
533 | if (i == port) | |
534 | continue; | |
535 | slaves_pport_actv = mlx4_phys_to_slaves_pport_actv( | |
536 | dev, &exclusive_ports); | |
537 | slave_gid -= bitmap_weight(slaves_pport_actv.slaves, | |
538 | dev->num_vfs + 1); | |
539 | } | |
540 | vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1; | |
541 | if (slave_gid <= ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) % vfs)) | |
542 | return ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / vfs) + 1; | |
543 | return (MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / vfs; | |
b6ffaeff JM |
544 | } |
545 | ||
449fc488 | 546 | int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port) |
b6ffaeff JM |
547 | { |
548 | int gids; | |
449fc488 MB |
549 | unsigned i; |
550 | int slave_gid = slave; | |
b6ffaeff JM |
551 | int vfs; |
552 | ||
449fc488 MB |
553 | struct mlx4_slaves_pport slaves_pport; |
554 | struct mlx4_active_ports actv_ports; | |
555 | unsigned max_port_p_one; | |
b6ffaeff JM |
556 | |
557 | if (slave == 0) | |
558 | return 0; | |
b6ffaeff | 559 | |
449fc488 MB |
560 | slaves_pport = mlx4_phys_to_slaves_pport(dev, port); |
561 | actv_ports = mlx4_get_active_ports(dev, slave); | |
562 | max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) + | |
563 | bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1; | |
564 | ||
565 | for (i = 1; i < max_port_p_one; i++) { | |
566 | struct mlx4_active_ports exclusive_ports; | |
567 | struct mlx4_slaves_pport slaves_pport_actv; | |
568 | bitmap_zero(exclusive_ports.ports, dev->caps.num_ports); | |
569 | set_bit(i - 1, exclusive_ports.ports); | |
570 | if (i == port) | |
571 | continue; | |
572 | slaves_pport_actv = mlx4_phys_to_slaves_pport_actv( | |
573 | dev, &exclusive_ports); | |
574 | slave_gid -= bitmap_weight(slaves_pport_actv.slaves, | |
575 | dev->num_vfs + 1); | |
576 | } | |
577 | gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS; | |
578 | vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1; | |
579 | if (slave_gid <= gids % vfs) | |
580 | return MLX4_ROCE_PF_GIDS + ((gids / vfs) + 1) * (slave_gid - 1); | |
581 | ||
582 | return MLX4_ROCE_PF_GIDS + (gids % vfs) + | |
583 | ((gids / vfs) * (slave_gid - 1)); | |
b6ffaeff | 584 | } |
449fc488 | 585 | EXPORT_SYMBOL_GPL(mlx4_get_base_gid_ix); |
b6ffaeff | 586 | |
ffe455ad EE |
587 | static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod, |
588 | u8 op_mod, struct mlx4_cmd_mailbox *inbox) | |
589 | { | |
590 | struct mlx4_priv *priv = mlx4_priv(dev); | |
591 | struct mlx4_port_info *port_info; | |
592 | struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master; | |
593 | struct mlx4_slave_state *slave_st = &master->slave_state[slave]; | |
594 | struct mlx4_set_port_rqp_calc_context *qpn_context; | |
595 | struct mlx4_set_port_general_context *gen_context; | |
b6ffaeff | 596 | struct mlx4_roce_gid_entry *gid_entry_tbl, *gid_entry_mbox, *gid_entry_mb1; |
ffe455ad EE |
597 | int reset_qkey_viols; |
598 | int port; | |
599 | int is_eth; | |
b6ffaeff JM |
600 | int num_gids; |
601 | int base; | |
ffe455ad EE |
602 | u32 in_modifier; |
603 | u32 promisc; | |
604 | u16 mtu, prev_mtu; | |
605 | int err; | |
b6ffaeff JM |
606 | int i, j; |
607 | int offset; | |
ffe455ad EE |
608 | __be32 agg_cap_mask; |
609 | __be32 slave_cap_mask; | |
610 | __be32 new_cap_mask; | |
611 | ||
612 | port = in_mod & 0xff; | |
613 | in_modifier = in_mod >> 8; | |
614 | is_eth = op_mod; | |
615 | port_info = &priv->port[port]; | |
616 | ||
617 | /* Slaves cannot perform SET_PORT operations except changing MTU */ | |
618 | if (is_eth) { | |
619 | if (slave != dev->caps.function && | |
9cd59352 JM |
620 | in_modifier != MLX4_SET_PORT_GENERAL && |
621 | in_modifier != MLX4_SET_PORT_GID_TABLE) { | |
ffe455ad EE |
622 | mlx4_warn(dev, "denying SET_PORT for slave:%d\n", |
623 | slave); | |
624 | return -EINVAL; | |
625 | } | |
626 | switch (in_modifier) { | |
627 | case MLX4_SET_PORT_RQP_CALC: | |
628 | qpn_context = inbox->buf; | |
629 | qpn_context->base_qpn = | |
630 | cpu_to_be32(port_info->base_qpn); | |
631 | qpn_context->n_mac = 0x7; | |
632 | promisc = be32_to_cpu(qpn_context->promisc) >> | |
633 | SET_PORT_PROMISC_SHIFT; | |
634 | qpn_context->promisc = cpu_to_be32( | |
635 | promisc << SET_PORT_PROMISC_SHIFT | | |
636 | port_info->base_qpn); | |
637 | promisc = be32_to_cpu(qpn_context->mcast) >> | |
638 | SET_PORT_MC_PROMISC_SHIFT; | |
639 | qpn_context->mcast = cpu_to_be32( | |
640 | promisc << SET_PORT_MC_PROMISC_SHIFT | | |
641 | port_info->base_qpn); | |
642 | break; | |
643 | case MLX4_SET_PORT_GENERAL: | |
644 | gen_context = inbox->buf; | |
645 | /* Mtu is configured as the max MTU among all the | |
646 | * the functions on the port. */ | |
647 | mtu = be16_to_cpu(gen_context->mtu); | |
c59fec20 EE |
648 | mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] + |
649 | ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); | |
ffe455ad EE |
650 | prev_mtu = slave_st->mtu[port]; |
651 | slave_st->mtu[port] = mtu; | |
652 | if (mtu > master->max_mtu[port]) | |
653 | master->max_mtu[port] = mtu; | |
654 | if (mtu < prev_mtu && prev_mtu == | |
655 | master->max_mtu[port]) { | |
656 | slave_st->mtu[port] = mtu; | |
657 | master->max_mtu[port] = mtu; | |
658 | for (i = 0; i < dev->num_slaves; i++) { | |
659 | master->max_mtu[port] = | |
660 | max(master->max_mtu[port], | |
661 | master->slave_state[i].mtu[port]); | |
662 | } | |
663 | } | |
664 | ||
665 | gen_context->mtu = cpu_to_be16(master->max_mtu[port]); | |
666 | break; | |
9cd59352 | 667 | case MLX4_SET_PORT_GID_TABLE: |
b6ffaeff JM |
668 | /* change to MULTIPLE entries: number of guest's gids |
669 | * need a FOR-loop here over number of gids the guest has. | |
670 | * 1. Check no duplicates in gids passed by slave | |
671 | */ | |
449fc488 MB |
672 | num_gids = mlx4_get_slave_num_gids(dev, slave, port); |
673 | base = mlx4_get_base_gid_ix(dev, slave, port); | |
b6ffaeff JM |
674 | gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf); |
675 | for (i = 0; i < num_gids; gid_entry_mbox++, i++) { | |
676 | if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw, | |
677 | sizeof(zgid_entry))) | |
678 | continue; | |
679 | gid_entry_mb1 = gid_entry_mbox + 1; | |
680 | for (j = i + 1; j < num_gids; gid_entry_mb1++, j++) { | |
681 | if (!memcmp(gid_entry_mb1->raw, | |
682 | zgid_entry.raw, sizeof(zgid_entry))) | |
683 | continue; | |
684 | if (!memcmp(gid_entry_mb1->raw, gid_entry_mbox->raw, | |
685 | sizeof(gid_entry_mbox->raw))) { | |
686 | /* found duplicate */ | |
687 | return -EINVAL; | |
9cd59352 JM |
688 | } |
689 | } | |
690 | } | |
b6ffaeff JM |
691 | |
692 | /* 2. Check that do not have duplicates in OTHER | |
693 | * entries in the port GID table | |
694 | */ | |
9cd59352 | 695 | for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) { |
b6ffaeff JM |
696 | if (i >= base && i < base + num_gids) |
697 | continue; /* don't compare to slave's current gids */ | |
698 | gid_entry_tbl = &priv->roce_gids[port - 1][i]; | |
699 | if (!memcmp(gid_entry_tbl->raw, zgid_entry.raw, sizeof(zgid_entry))) | |
700 | continue; | |
701 | gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf); | |
702 | for (j = 0; j < num_gids; gid_entry_mbox++, j++) { | |
703 | if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw, | |
704 | sizeof(zgid_entry))) | |
705 | continue; | |
706 | if (!memcmp(gid_entry_mbox->raw, gid_entry_tbl->raw, | |
707 | sizeof(gid_entry_tbl->raw))) { | |
708 | /* found duplicate */ | |
709 | mlx4_warn(dev, "requested gid entry for slave:%d " | |
710 | "is a duplicate of gid at index %d\n", | |
711 | slave, i); | |
712 | return -EINVAL; | |
713 | } | |
714 | } | |
9cd59352 | 715 | } |
b6ffaeff JM |
716 | |
717 | /* insert slave GIDs with memcpy, starting at slave's base index */ | |
718 | gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf); | |
719 | for (i = 0, offset = base; i < num_gids; gid_entry_mbox++, offset++, i++) | |
720 | memcpy(priv->roce_gids[port - 1][offset].raw, gid_entry_mbox->raw, 16); | |
721 | ||
722 | /* Now, copy roce port gids table to current mailbox for passing to FW */ | |
723 | gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf); | |
724 | for (i = 0; i < MLX4_ROCE_MAX_GIDS; gid_entry_mbox++, i++) | |
725 | memcpy(gid_entry_mbox->raw, priv->roce_gids[port - 1][i].raw, 16); | |
726 | ||
9cd59352 | 727 | break; |
ffe455ad EE |
728 | } |
729 | return mlx4_cmd(dev, inbox->dma, in_mod, op_mod, | |
730 | MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, | |
731 | MLX4_CMD_NATIVE); | |
732 | } | |
733 | ||
734 | /* For IB, we only consider: | |
735 | * - The capability mask, which is set to the aggregate of all | |
736 | * slave function capabilities | |
737 | * - The QKey violatin counter - reset according to each request. | |
738 | */ | |
739 | ||
740 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { | |
741 | reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40; | |
742 | new_cap_mask = ((__be32 *) inbox->buf)[2]; | |
743 | } else { | |
744 | reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1; | |
745 | new_cap_mask = ((__be32 *) inbox->buf)[1]; | |
746 | } | |
747 | ||
efcd235d JM |
748 | /* slave may not set the IS_SM capability for the port */ |
749 | if (slave != mlx4_master_func_num(dev) && | |
750 | (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM)) | |
751 | return -EINVAL; | |
752 | ||
753 | /* No DEV_MGMT in multifunc mode */ | |
754 | if (mlx4_is_mfunc(dev) && | |
755 | (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP)) | |
756 | return -EINVAL; | |
757 | ||
ffe455ad EE |
758 | agg_cap_mask = 0; |
759 | slave_cap_mask = | |
760 | priv->mfunc.master.slave_state[slave].ib_cap_mask[port]; | |
761 | priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask; | |
762 | for (i = 0; i < dev->num_slaves; i++) | |
763 | agg_cap_mask |= | |
764 | priv->mfunc.master.slave_state[i].ib_cap_mask[port]; | |
765 | ||
766 | /* only clear mailbox for guests. Master may be setting | |
767 | * MTU or PKEY table size | |
768 | */ | |
769 | if (slave != dev->caps.function) | |
770 | memset(inbox->buf, 0, 256); | |
771 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { | |
edc4a67e | 772 | *(u8 *) inbox->buf |= !!reset_qkey_viols << 6; |
ffe455ad EE |
773 | ((__be32 *) inbox->buf)[2] = agg_cap_mask; |
774 | } else { | |
edc4a67e | 775 | ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols; |
ffe455ad EE |
776 | ((__be32 *) inbox->buf)[1] = agg_cap_mask; |
777 | } | |
778 | ||
779 | err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT, | |
780 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
781 | if (err) | |
782 | priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = | |
783 | slave_cap_mask; | |
784 | return err; | |
785 | } | |
786 | ||
787 | int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, | |
788 | struct mlx4_vhcr *vhcr, | |
789 | struct mlx4_cmd_mailbox *inbox, | |
790 | struct mlx4_cmd_mailbox *outbox, | |
791 | struct mlx4_cmd_info *cmd) | |
792 | { | |
449fc488 MB |
793 | int port = mlx4_slave_convert_port( |
794 | dev, slave, vhcr->in_modifier & 0xFF); | |
795 | ||
796 | if (port < 0) | |
797 | return -EINVAL; | |
798 | ||
799 | vhcr->in_modifier = (vhcr->in_modifier & ~0xFF) | | |
800 | (port & 0xFF); | |
801 | ||
ffe455ad EE |
802 | return mlx4_common_set_port(dev, slave, vhcr->in_modifier, |
803 | vhcr->op_modifier, inbox); | |
804 | } | |
805 | ||
096335b3 OG |
806 | /* bit locations for set port command with zero op modifier */ |
807 | enum { | |
808 | MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */ | |
809 | MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */ | |
6634961c | 810 | MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20, |
096335b3 OG |
811 | MLX4_CHANGE_PORT_VL_CAP = 21, |
812 | MLX4_CHANGE_PORT_MTU_CAP = 22, | |
813 | }; | |
814 | ||
6634961c | 815 | int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz) |
7ff93f8b YP |
816 | { |
817 | struct mlx4_cmd_mailbox *mailbox; | |
6634961c | 818 | int err, vl_cap, pkey_tbl_flag = 0; |
7ff93f8b | 819 | |
352b09ed RD |
820 | if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) |
821 | return 0; | |
822 | ||
7ff93f8b YP |
823 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
824 | if (IS_ERR(mailbox)) | |
825 | return PTR_ERR(mailbox); | |
826 | ||
793730bf | 827 | ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port]; |
096335b3 | 828 | |
6634961c JM |
829 | if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) { |
830 | pkey_tbl_flag = 1; | |
831 | ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz); | |
832 | } | |
833 | ||
096335b3 OG |
834 | /* IB VL CAP enum isn't used by the firmware, just numerical values */ |
835 | for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) { | |
836 | ((__be32 *) mailbox->buf)[0] = cpu_to_be32( | |
837 | (1 << MLX4_CHANGE_PORT_MTU_CAP) | | |
838 | (1 << MLX4_CHANGE_PORT_VL_CAP) | | |
6634961c | 839 | (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) | |
096335b3 OG |
840 | (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) | |
841 | (vl_cap << MLX4_SET_PORT_VL_CAP)); | |
842 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT, | |
843 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
844 | if (err != -ENOMEM) | |
845 | break; | |
846 | } | |
7ff93f8b YP |
847 | |
848 | mlx4_free_cmd_mailbox(dev, mailbox); | |
849 | return err; | |
850 | } | |
ffe455ad | 851 | |
cb9ffb76 | 852 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
ffe455ad EE |
853 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx) |
854 | { | |
855 | struct mlx4_cmd_mailbox *mailbox; | |
856 | struct mlx4_set_port_general_context *context; | |
857 | int err; | |
858 | u32 in_mod; | |
859 | ||
860 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
861 | if (IS_ERR(mailbox)) | |
862 | return PTR_ERR(mailbox); | |
863 | context = mailbox->buf; | |
ffe455ad EE |
864 | context->flags = SET_PORT_GEN_ALL_VALID; |
865 | context->mtu = cpu_to_be16(mtu); | |
866 | context->pptx = (pptx * (!pfctx)) << 7; | |
867 | context->pfctx = pfctx; | |
868 | context->pprx = (pprx * (!pfcrx)) << 7; | |
869 | context->pfcrx = pfcrx; | |
870 | ||
871 | in_mod = MLX4_SET_PORT_GENERAL << 8 | port; | |
872 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
873 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
874 | ||
875 | mlx4_free_cmd_mailbox(dev, mailbox); | |
876 | return err; | |
877 | } | |
878 | EXPORT_SYMBOL(mlx4_SET_PORT_general); | |
879 | ||
cb9ffb76 | 880 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, |
ffe455ad EE |
881 | u8 promisc) |
882 | { | |
883 | struct mlx4_cmd_mailbox *mailbox; | |
884 | struct mlx4_set_port_rqp_calc_context *context; | |
885 | int err; | |
886 | u32 in_mod; | |
887 | u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ? | |
888 | MCAST_DIRECT : MCAST_DEFAULT; | |
889 | ||
c96d97f4 | 890 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) |
ffe455ad EE |
891 | return 0; |
892 | ||
893 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
894 | if (IS_ERR(mailbox)) | |
895 | return PTR_ERR(mailbox); | |
896 | context = mailbox->buf; | |
ffe455ad EE |
897 | context->base_qpn = cpu_to_be32(base_qpn); |
898 | context->n_mac = dev->caps.log_num_macs; | |
899 | context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT | | |
900 | base_qpn); | |
901 | context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT | | |
902 | base_qpn); | |
903 | context->intra_no_vlan = 0; | |
904 | context->no_vlan = MLX4_NO_VLAN_IDX; | |
905 | context->intra_vlan_miss = 0; | |
906 | context->vlan_miss = MLX4_VLAN_MISS_IDX; | |
907 | ||
908 | in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port; | |
909 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
910 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
911 | ||
912 | mlx4_free_cmd_mailbox(dev, mailbox); | |
913 | return err; | |
914 | } | |
915 | EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc); | |
916 | ||
e5395e92 AV |
917 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc) |
918 | { | |
919 | struct mlx4_cmd_mailbox *mailbox; | |
920 | struct mlx4_set_port_prio2tc_context *context; | |
921 | int err; | |
922 | u32 in_mod; | |
923 | int i; | |
924 | ||
925 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
926 | if (IS_ERR(mailbox)) | |
927 | return PTR_ERR(mailbox); | |
928 | context = mailbox->buf; | |
e5395e92 AV |
929 | for (i = 0; i < MLX4_NUM_UP; i += 2) |
930 | context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1]; | |
931 | ||
932 | in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port; | |
933 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
934 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
935 | ||
936 | mlx4_free_cmd_mailbox(dev, mailbox); | |
937 | return err; | |
938 | } | |
939 | EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC); | |
940 | ||
941 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
942 | u8 *pg, u16 *ratelimit) | |
943 | { | |
944 | struct mlx4_cmd_mailbox *mailbox; | |
945 | struct mlx4_set_port_scheduler_context *context; | |
946 | int err; | |
947 | u32 in_mod; | |
948 | int i; | |
949 | ||
950 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
951 | if (IS_ERR(mailbox)) | |
952 | return PTR_ERR(mailbox); | |
953 | context = mailbox->buf; | |
e5395e92 AV |
954 | |
955 | for (i = 0; i < MLX4_NUM_TC; i++) { | |
956 | struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i]; | |
957 | u16 r = ratelimit && ratelimit[i] ? ratelimit[i] : | |
958 | MLX4_RATELIMIT_DEFAULT; | |
959 | ||
960 | tc->pg = htons(pg[i]); | |
961 | tc->bw_precentage = htons(tc_tx_bw[i]); | |
962 | ||
963 | tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS); | |
964 | tc->max_bw_value = htons(r); | |
965 | } | |
966 | ||
967 | in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port; | |
968 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
969 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
970 | ||
971 | mlx4_free_cmd_mailbox(dev, mailbox); | |
972 | return err; | |
973 | } | |
974 | EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER); | |
975 | ||
7ffdf726 OG |
976 | enum { |
977 | VXLAN_ENABLE_MODIFY = 1 << 7, | |
978 | VXLAN_STEERING_MODIFY = 1 << 6, | |
979 | ||
980 | VXLAN_ENABLE = 1 << 7, | |
981 | }; | |
982 | ||
983 | struct mlx4_set_port_vxlan_context { | |
984 | u32 reserved1; | |
985 | u8 modify_flags; | |
986 | u8 reserved2; | |
987 | u8 enable_flags; | |
988 | u8 steering; | |
989 | }; | |
990 | ||
991 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering) | |
992 | { | |
993 | int err; | |
994 | u32 in_mod; | |
995 | struct mlx4_cmd_mailbox *mailbox; | |
996 | struct mlx4_set_port_vxlan_context *context; | |
997 | ||
998 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
999 | if (IS_ERR(mailbox)) | |
1000 | return PTR_ERR(mailbox); | |
1001 | context = mailbox->buf; | |
1002 | memset(context, 0, sizeof(*context)); | |
1003 | ||
1004 | context->modify_flags = VXLAN_ENABLE_MODIFY | VXLAN_STEERING_MODIFY; | |
1005 | context->enable_flags = VXLAN_ENABLE; | |
1006 | context->steering = steering; | |
1007 | ||
1008 | in_mod = MLX4_SET_PORT_VXLAN << 8 | port; | |
1009 | err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, | |
1010 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
1011 | ||
1012 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1013 | return err; | |
1014 | } | |
1015 | EXPORT_SYMBOL(mlx4_SET_PORT_VXLAN); | |
1016 | ||
ffe455ad EE |
1017 | int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, |
1018 | struct mlx4_vhcr *vhcr, | |
1019 | struct mlx4_cmd_mailbox *inbox, | |
1020 | struct mlx4_cmd_mailbox *outbox, | |
1021 | struct mlx4_cmd_info *cmd) | |
1022 | { | |
1023 | int err = 0; | |
1024 | ||
1025 | return err; | |
1026 | } | |
1027 | ||
1028 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, | |
1029 | u64 mac, u64 clear, u8 mode) | |
1030 | { | |
1031 | return mlx4_cmd(dev, (mac | (clear << 63)), port, mode, | |
1032 | MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B, | |
1033 | MLX4_CMD_WRAPPED); | |
1034 | } | |
1035 | EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR); | |
1036 | ||
1037 | int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, | |
1038 | struct mlx4_vhcr *vhcr, | |
1039 | struct mlx4_cmd_mailbox *inbox, | |
1040 | struct mlx4_cmd_mailbox *outbox, | |
1041 | struct mlx4_cmd_info *cmd) | |
1042 | { | |
1043 | int err = 0; | |
1044 | ||
1045 | return err; | |
1046 | } | |
1047 | ||
1048 | int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, | |
1049 | u32 in_mod, struct mlx4_cmd_mailbox *outbox) | |
1050 | { | |
1051 | return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0, | |
1052 | MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B, | |
1053 | MLX4_CMD_NATIVE); | |
1054 | } | |
1055 | ||
1056 | int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, | |
1057 | struct mlx4_vhcr *vhcr, | |
1058 | struct mlx4_cmd_mailbox *inbox, | |
1059 | struct mlx4_cmd_mailbox *outbox, | |
1060 | struct mlx4_cmd_info *cmd) | |
1061 | { | |
35fb9afb EE |
1062 | if (slave != dev->caps.function) |
1063 | return 0; | |
ffe455ad EE |
1064 | return mlx4_common_dump_eth_stats(dev, slave, |
1065 | vhcr->in_modifier, outbox); | |
1066 | } | |
93ece0c1 EE |
1067 | |
1068 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap) | |
1069 | { | |
1070 | if (!mlx4_is_mfunc(dev)) { | |
1071 | *stats_bitmap = 0; | |
1072 | return; | |
1073 | } | |
1074 | ||
1075 | *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK | | |
1076 | MLX4_STATS_TRAFFIC_DROPS_MASK | | |
1077 | MLX4_STATS_PORT_COUNTERS_MASK); | |
1078 | ||
1079 | if (mlx4_is_master(dev)) | |
1080 | *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK; | |
1081 | } | |
1082 | EXPORT_SYMBOL(mlx4_set_stats_bitmap); | |
6ee51a4e | 1083 | |
9cd59352 JM |
1084 | int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, |
1085 | int *slave_id) | |
6ee51a4e JM |
1086 | { |
1087 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1088 | int i, found_ix = -1; | |
b6ffaeff | 1089 | int vf_gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS; |
449fc488 MB |
1090 | struct mlx4_slaves_pport slaves_pport; |
1091 | unsigned num_vfs; | |
1092 | int slave_gid; | |
6ee51a4e JM |
1093 | |
1094 | if (!mlx4_is_mfunc(dev)) | |
1095 | return -EINVAL; | |
1096 | ||
449fc488 MB |
1097 | slaves_pport = mlx4_phys_to_slaves_pport(dev, port); |
1098 | num_vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1; | |
1099 | ||
6ee51a4e JM |
1100 | for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) { |
1101 | if (!memcmp(priv->roce_gids[port - 1][i].raw, gid, 16)) { | |
1102 | found_ix = i; | |
1103 | break; | |
1104 | } | |
1105 | } | |
1106 | ||
b6ffaeff JM |
1107 | if (found_ix >= 0) { |
1108 | if (found_ix < MLX4_ROCE_PF_GIDS) | |
449fc488 MB |
1109 | slave_gid = 0; |
1110 | else if (found_ix < MLX4_ROCE_PF_GIDS + (vf_gids % num_vfs) * | |
1111 | (vf_gids / num_vfs + 1)) | |
1112 | slave_gid = ((found_ix - MLX4_ROCE_PF_GIDS) / | |
1113 | (vf_gids / num_vfs + 1)) + 1; | |
b6ffaeff | 1114 | else |
449fc488 | 1115 | slave_gid = |
b6ffaeff | 1116 | ((found_ix - MLX4_ROCE_PF_GIDS - |
449fc488 MB |
1117 | ((vf_gids % num_vfs) * ((vf_gids / num_vfs + 1)))) / |
1118 | (vf_gids / num_vfs)) + vf_gids % num_vfs + 1; | |
1119 | ||
1120 | if (slave_gid) { | |
1121 | struct mlx4_active_ports exclusive_ports; | |
1122 | struct mlx4_active_ports actv_ports; | |
1123 | struct mlx4_slaves_pport slaves_pport_actv; | |
1124 | unsigned max_port_p_one; | |
1125 | int num_slaves_before = 1; | |
1126 | ||
1127 | for (i = 1; i < port; i++) { | |
1128 | bitmap_zero(exclusive_ports.ports, dev->caps.num_ports); | |
1129 | set_bit(i, exclusive_ports.ports); | |
1130 | slaves_pport_actv = | |
1131 | mlx4_phys_to_slaves_pport_actv( | |
1132 | dev, &exclusive_ports); | |
1133 | num_slaves_before += bitmap_weight( | |
1134 | slaves_pport_actv.slaves, | |
1135 | dev->num_vfs + 1); | |
1136 | } | |
1137 | ||
1138 | if (slave_gid < num_slaves_before) { | |
1139 | bitmap_zero(exclusive_ports.ports, dev->caps.num_ports); | |
1140 | set_bit(port - 1, exclusive_ports.ports); | |
1141 | slaves_pport_actv = | |
1142 | mlx4_phys_to_slaves_pport_actv( | |
1143 | dev, &exclusive_ports); | |
1144 | slave_gid += bitmap_weight( | |
1145 | slaves_pport_actv.slaves, | |
1146 | dev->num_vfs + 1) - | |
1147 | num_slaves_before; | |
1148 | } | |
1149 | actv_ports = mlx4_get_active_ports(dev, slave_gid); | |
1150 | max_port_p_one = find_first_bit( | |
1151 | actv_ports.ports, dev->caps.num_ports) + | |
1152 | bitmap_weight(actv_ports.ports, | |
1153 | dev->caps.num_ports) + 1; | |
1154 | ||
1155 | for (i = 1; i < max_port_p_one; i++) { | |
1156 | if (i == port) | |
1157 | continue; | |
1158 | bitmap_zero(exclusive_ports.ports, | |
1159 | dev->caps.num_ports); | |
1160 | set_bit(i - 1, exclusive_ports.ports); | |
1161 | slaves_pport_actv = | |
1162 | mlx4_phys_to_slaves_pport_actv( | |
1163 | dev, &exclusive_ports); | |
1164 | slave_gid += bitmap_weight( | |
1165 | slaves_pport_actv.slaves, | |
1166 | dev->num_vfs + 1); | |
1167 | } | |
1168 | } | |
1169 | *slave_id = slave_gid; | |
b6ffaeff | 1170 | } |
6ee51a4e JM |
1171 | |
1172 | return (found_ix >= 0) ? 0 : -EINVAL; | |
1173 | } | |
1174 | EXPORT_SYMBOL(mlx4_get_slave_from_roce_gid); | |
1175 | ||
9cd59352 JM |
1176 | int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, |
1177 | u8 *gid) | |
6ee51a4e JM |
1178 | { |
1179 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1180 | ||
1181 | if (!mlx4_is_master(dev)) | |
1182 | return -EINVAL; | |
1183 | ||
1184 | memcpy(gid, priv->roce_gids[port - 1][slave_id].raw, 16); | |
1185 | return 0; | |
1186 | } | |
1187 | EXPORT_SYMBOL(mlx4_get_roce_gid_from_slave); |