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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
51a379d0 | 4 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
5 | * Copyright (c) 2004 Voltaire, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
5a0e3ad6 | 36 | #include <linux/gfp.h> |
ee40fa06 | 37 | #include <linux/export.h> |
fe9a2603 | 38 | |
225c7b1f RD |
39 | #include <linux/mlx4/cmd.h> |
40 | #include <linux/mlx4/qp.h> | |
41 | ||
42 | #include "mlx4.h" | |
43 | #include "icm.h" | |
44 | ||
ddae0349 EE |
45 | /* QP to support BF should have bits 6,7 cleared */ |
46 | #define MLX4_BF_QP_SKIP_MASK 0xc0 | |
47 | #define MLX4_MAX_BF_QP_RANGE 0x40 | |
48 | ||
225c7b1f RD |
49 | void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type) |
50 | { | |
51 | struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; | |
52 | struct mlx4_qp *qp; | |
53 | ||
54 | spin_lock(&qp_table->lock); | |
55 | ||
56 | qp = __mlx4_qp_lookup(dev, qpn); | |
57 | if (qp) | |
58 | atomic_inc(&qp->refcount); | |
59 | ||
60 | spin_unlock(&qp_table->lock); | |
61 | ||
62 | if (!qp) { | |
fe9a2603 | 63 | mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn); |
225c7b1f RD |
64 | return; |
65 | } | |
66 | ||
67 | qp->event(qp, event_type); | |
68 | ||
69 | if (atomic_dec_and_test(&qp->refcount)) | |
70 | complete(&qp->free); | |
71 | } | |
72 | ||
980e9001 | 73 | /* used for INIT/CLOSE port logic */ |
47605df9 | 74 | static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0) |
fe9a2603 | 75 | { |
47605df9 | 76 | /* this procedure is called after we already know we are on the master */ |
980e9001 | 77 | /* qp0 is either the proxy qp0, or the real qp0 */ |
47605df9 JM |
78 | u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev); |
79 | *proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1; | |
980e9001 | 80 | |
47605df9 JM |
81 | *real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn && |
82 | qp->qpn <= dev->phys_caps.base_sqpn + 1; | |
980e9001 JM |
83 | |
84 | return *real_qp0 || *proxy_qp0; | |
fe9a2603 JM |
85 | } |
86 | ||
87 | static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
88 | enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, | |
89 | struct mlx4_qp_context *context, | |
90 | enum mlx4_qp_optpar optpar, | |
91 | int sqd_event, struct mlx4_qp *qp, int native) | |
225c7b1f RD |
92 | { |
93 | static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = { | |
94 | [MLX4_QP_STATE_RST] = { | |
95 | [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, | |
96 | [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, | |
97 | [MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP, | |
98 | }, | |
99 | [MLX4_QP_STATE_INIT] = { | |
100 | [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, | |
101 | [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, | |
102 | [MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP, | |
103 | [MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP, | |
104 | }, | |
105 | [MLX4_QP_STATE_RTR] = { | |
106 | [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, | |
107 | [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, | |
108 | [MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP, | |
109 | }, | |
110 | [MLX4_QP_STATE_RTS] = { | |
111 | [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, | |
112 | [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, | |
113 | [MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP, | |
114 | [MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP, | |
115 | }, | |
116 | [MLX4_QP_STATE_SQD] = { | |
117 | [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, | |
118 | [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, | |
119 | [MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP, | |
120 | [MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP, | |
121 | }, | |
122 | [MLX4_QP_STATE_SQER] = { | |
123 | [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, | |
124 | [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, | |
125 | [MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP, | |
126 | }, | |
127 | [MLX4_QP_STATE_ERR] = { | |
128 | [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, | |
129 | [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, | |
130 | } | |
131 | }; | |
132 | ||
fe9a2603 | 133 | struct mlx4_priv *priv = mlx4_priv(dev); |
225c7b1f RD |
134 | struct mlx4_cmd_mailbox *mailbox; |
135 | int ret = 0; | |
980e9001 JM |
136 | int real_qp0 = 0; |
137 | int proxy_qp0 = 0; | |
fe9a2603 | 138 | u8 port; |
225c7b1f | 139 | |
9ed87fd3 | 140 | if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE || |
225c7b1f RD |
141 | !op[cur_state][new_state]) |
142 | return -EINVAL; | |
143 | ||
fe9a2603 JM |
144 | if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) { |
145 | ret = mlx4_cmd(dev, 0, qp->qpn, 2, | |
146 | MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native); | |
147 | if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR && | |
148 | cur_state != MLX4_QP_STATE_RST && | |
47605df9 | 149 | is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) { |
fe9a2603 | 150 | port = (qp->qpn & 1) + 1; |
980e9001 JM |
151 | if (proxy_qp0) |
152 | priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0; | |
153 | else | |
154 | priv->mfunc.master.qp0_state[port].qp0_active = 0; | |
fe9a2603 JM |
155 | } |
156 | return ret; | |
157 | } | |
225c7b1f RD |
158 | |
159 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
160 | if (IS_ERR(mailbox)) | |
161 | return PTR_ERR(mailbox); | |
162 | ||
163 | if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) { | |
164 | u64 mtt_addr = mlx4_mtt_addr(dev, mtt); | |
165 | context->mtt_base_addr_h = mtt_addr >> 32; | |
166 | context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); | |
167 | context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; | |
168 | } | |
169 | ||
170 | *(__be32 *) mailbox->buf = cpu_to_be32(optpar); | |
171 | memcpy(mailbox->buf + 8, context, sizeof *context); | |
172 | ||
173 | ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn = | |
174 | cpu_to_be32(qp->qpn); | |
175 | ||
eb41049f | 176 | ret = mlx4_cmd(dev, mailbox->dma, |
fe9a2603 | 177 | qp->qpn | (!!sqd_event << 31), |
225c7b1f | 178 | new_state == MLX4_QP_STATE_RST ? 2 : 0, |
fe9a2603 | 179 | op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native); |
225c7b1f | 180 | |
47605df9 | 181 | if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) { |
980e9001 JM |
182 | port = (qp->qpn & 1) + 1; |
183 | if (cur_state != MLX4_QP_STATE_ERR && | |
184 | cur_state != MLX4_QP_STATE_RST && | |
185 | new_state == MLX4_QP_STATE_ERR) { | |
186 | if (proxy_qp0) | |
187 | priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0; | |
188 | else | |
189 | priv->mfunc.master.qp0_state[port].qp0_active = 0; | |
190 | } else if (new_state == MLX4_QP_STATE_RTR) { | |
191 | if (proxy_qp0) | |
192 | priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1; | |
193 | else | |
194 | priv->mfunc.master.qp0_state[port].qp0_active = 1; | |
195 | } | |
196 | } | |
197 | ||
225c7b1f RD |
198 | mlx4_free_cmd_mailbox(dev, mailbox); |
199 | return ret; | |
200 | } | |
fe9a2603 JM |
201 | |
202 | int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
203 | enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, | |
204 | struct mlx4_qp_context *context, | |
205 | enum mlx4_qp_optpar optpar, | |
206 | int sqd_event, struct mlx4_qp *qp) | |
207 | { | |
208 | return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context, | |
209 | optpar, sqd_event, qp, 0); | |
210 | } | |
225c7b1f RD |
211 | EXPORT_SYMBOL_GPL(mlx4_qp_modify); |
212 | ||
c82e9aa0 | 213 | int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, |
ddae0349 | 214 | int *base, u8 flags) |
a3cdcbfa | 215 | { |
ddae0349 EE |
216 | int bf_qp = !!(flags & (u8)MLX4_RESERVE_ETH_BF_QP); |
217 | ||
a3cdcbfa YP |
218 | struct mlx4_priv *priv = mlx4_priv(dev); |
219 | struct mlx4_qp_table *qp_table = &priv->qp_table; | |
a3cdcbfa | 220 | |
ddae0349 EE |
221 | if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp) |
222 | return -ENOMEM; | |
223 | ||
224 | *base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align, | |
225 | bf_qp ? MLX4_BF_QP_SKIP_MASK : 0); | |
fe9a2603 | 226 | if (*base == -1) |
a3cdcbfa YP |
227 | return -ENOMEM; |
228 | ||
a3cdcbfa YP |
229 | return 0; |
230 | } | |
fe9a2603 | 231 | |
ddae0349 EE |
232 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, |
233 | int *base, u8 flags) | |
fe9a2603 | 234 | { |
e7dbeba8 | 235 | u64 in_param = 0; |
fe9a2603 JM |
236 | u64 out_param; |
237 | int err; | |
238 | ||
ddae0349 EE |
239 | /* Turn off all unsupported QP allocation flags */ |
240 | flags &= dev->caps.alloc_res_qp_mask; | |
241 | ||
fe9a2603 | 242 | if (mlx4_is_mfunc(dev)) { |
ddae0349 | 243 | set_param_l(&in_param, (((u32)flags) << 24) | (u32)cnt); |
fe9a2603 JM |
244 | set_param_h(&in_param, align); |
245 | err = mlx4_cmd_imm(dev, in_param, &out_param, | |
246 | RES_QP, RES_OP_RESERVE, | |
247 | MLX4_CMD_ALLOC_RES, | |
248 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
249 | if (err) | |
250 | return err; | |
251 | ||
252 | *base = get_param_l(&out_param); | |
253 | return 0; | |
254 | } | |
ddae0349 | 255 | return __mlx4_qp_reserve_range(dev, cnt, align, base, flags); |
fe9a2603 | 256 | } |
a3cdcbfa YP |
257 | EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range); |
258 | ||
c82e9aa0 | 259 | void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) |
a3cdcbfa YP |
260 | { |
261 | struct mlx4_priv *priv = mlx4_priv(dev); | |
262 | struct mlx4_qp_table *qp_table = &priv->qp_table; | |
a3cdcbfa | 263 | |
fe9a2603 JM |
264 | if (mlx4_is_qp_reserved(dev, (u32) base_qpn)) |
265 | return; | |
7c6d74d2 | 266 | mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, MLX4_USE_RR); |
a3cdcbfa | 267 | } |
fe9a2603 JM |
268 | |
269 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) | |
270 | { | |
e7dbeba8 | 271 | u64 in_param = 0; |
fe9a2603 JM |
272 | int err; |
273 | ||
274 | if (mlx4_is_mfunc(dev)) { | |
275 | set_param_l(&in_param, base_qpn); | |
276 | set_param_h(&in_param, cnt); | |
277 | err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE, | |
278 | MLX4_CMD_FREE_RES, | |
279 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
280 | if (err) { | |
1a91de28 JP |
281 | mlx4_warn(dev, "Failed to release qp range base:%d cnt:%d\n", |
282 | base_qpn, cnt); | |
fe9a2603 JM |
283 | } |
284 | } else | |
285 | __mlx4_qp_release_range(dev, base_qpn, cnt); | |
286 | } | |
a3cdcbfa YP |
287 | EXPORT_SYMBOL_GPL(mlx4_qp_release_range); |
288 | ||
40f2287b | 289 | int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp) |
225c7b1f RD |
290 | { |
291 | struct mlx4_priv *priv = mlx4_priv(dev); | |
292 | struct mlx4_qp_table *qp_table = &priv->qp_table; | |
293 | int err; | |
294 | ||
40f2287b | 295 | err = mlx4_table_get(dev, &qp_table->qp_table, qpn, gfp); |
225c7b1f RD |
296 | if (err) |
297 | goto err_out; | |
298 | ||
40f2287b | 299 | err = mlx4_table_get(dev, &qp_table->auxc_table, qpn, gfp); |
225c7b1f RD |
300 | if (err) |
301 | goto err_put_qp; | |
302 | ||
40f2287b | 303 | err = mlx4_table_get(dev, &qp_table->altc_table, qpn, gfp); |
225c7b1f RD |
304 | if (err) |
305 | goto err_put_auxc; | |
306 | ||
40f2287b | 307 | err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn, gfp); |
225c7b1f RD |
308 | if (err) |
309 | goto err_put_altc; | |
310 | ||
40f2287b | 311 | err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn, gfp); |
225c7b1f RD |
312 | if (err) |
313 | goto err_put_rdmarc; | |
314 | ||
225c7b1f RD |
315 | return 0; |
316 | ||
225c7b1f | 317 | err_put_rdmarc: |
fe9a2603 | 318 | mlx4_table_put(dev, &qp_table->rdmarc_table, qpn); |
225c7b1f RD |
319 | |
320 | err_put_altc: | |
fe9a2603 | 321 | mlx4_table_put(dev, &qp_table->altc_table, qpn); |
225c7b1f RD |
322 | |
323 | err_put_auxc: | |
fe9a2603 | 324 | mlx4_table_put(dev, &qp_table->auxc_table, qpn); |
225c7b1f RD |
325 | |
326 | err_put_qp: | |
fe9a2603 | 327 | mlx4_table_put(dev, &qp_table->qp_table, qpn); |
225c7b1f RD |
328 | |
329 | err_out: | |
225c7b1f RD |
330 | return err; |
331 | } | |
fe9a2603 | 332 | |
4e2c341b | 333 | static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp) |
fe9a2603 | 334 | { |
e7dbeba8 | 335 | u64 param = 0; |
fe9a2603 JM |
336 | |
337 | if (mlx4_is_mfunc(dev)) { | |
338 | set_param_l(¶m, qpn); | |
339 | return mlx4_cmd_imm(dev, param, ¶m, RES_QP, RES_OP_MAP_ICM, | |
340 | MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A, | |
341 | MLX4_CMD_WRAPPED); | |
342 | } | |
40f2287b | 343 | return __mlx4_qp_alloc_icm(dev, qpn, gfp); |
fe9a2603 JM |
344 | } |
345 | ||
c82e9aa0 | 346 | void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) |
fe9a2603 JM |
347 | { |
348 | struct mlx4_priv *priv = mlx4_priv(dev); | |
349 | struct mlx4_qp_table *qp_table = &priv->qp_table; | |
350 | ||
351 | mlx4_table_put(dev, &qp_table->cmpt_table, qpn); | |
352 | mlx4_table_put(dev, &qp_table->rdmarc_table, qpn); | |
353 | mlx4_table_put(dev, &qp_table->altc_table, qpn); | |
354 | mlx4_table_put(dev, &qp_table->auxc_table, qpn); | |
355 | mlx4_table_put(dev, &qp_table->qp_table, qpn); | |
356 | } | |
357 | ||
358 | static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) | |
359 | { | |
e7dbeba8 | 360 | u64 in_param = 0; |
fe9a2603 JM |
361 | |
362 | if (mlx4_is_mfunc(dev)) { | |
363 | set_param_l(&in_param, qpn); | |
364 | if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM, | |
365 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
366 | MLX4_CMD_WRAPPED)) | |
367 | mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn); | |
368 | } else | |
369 | __mlx4_qp_free_icm(dev, qpn); | |
370 | } | |
371 | ||
40f2287b | 372 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, gfp_t gfp) |
fe9a2603 JM |
373 | { |
374 | struct mlx4_priv *priv = mlx4_priv(dev); | |
375 | struct mlx4_qp_table *qp_table = &priv->qp_table; | |
376 | int err; | |
377 | ||
378 | if (!qpn) | |
379 | return -EINVAL; | |
380 | ||
381 | qp->qpn = qpn; | |
382 | ||
40f2287b | 383 | err = mlx4_qp_alloc_icm(dev, qpn, gfp); |
fe9a2603 JM |
384 | if (err) |
385 | return err; | |
386 | ||
387 | spin_lock_irq(&qp_table->lock); | |
388 | err = radix_tree_insert(&dev->qp_table_tree, qp->qpn & | |
389 | (dev->caps.num_qps - 1), qp); | |
390 | spin_unlock_irq(&qp_table->lock); | |
391 | if (err) | |
392 | goto err_icm; | |
393 | ||
394 | atomic_set(&qp->refcount, 1); | |
395 | init_completion(&qp->free); | |
396 | ||
397 | return 0; | |
398 | ||
399 | err_icm: | |
400 | mlx4_qp_free_icm(dev, qpn); | |
401 | return err; | |
402 | } | |
403 | ||
225c7b1f RD |
404 | EXPORT_SYMBOL_GPL(mlx4_qp_alloc); |
405 | ||
ce8d9e0d | 406 | #define MLX4_UPDATE_QP_SUPPORTED_ATTRS MLX4_UPDATE_QP_SMAC |
09e05c3f | 407 | int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn, |
ce8d9e0d MB |
408 | enum mlx4_update_qp_attr attr, |
409 | struct mlx4_update_qp_params *params) | |
410 | { | |
411 | struct mlx4_cmd_mailbox *mailbox; | |
412 | struct mlx4_update_qp_context *cmd; | |
413 | u64 pri_addr_path_mask = 0; | |
09e05c3f | 414 | u64 qp_mask = 0; |
ce8d9e0d MB |
415 | int err = 0; |
416 | ||
417 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
418 | if (IS_ERR(mailbox)) | |
419 | return PTR_ERR(mailbox); | |
420 | ||
421 | cmd = (struct mlx4_update_qp_context *)mailbox->buf; | |
422 | ||
423 | if (!attr || (attr & ~MLX4_UPDATE_QP_SUPPORTED_ATTRS)) | |
424 | return -EINVAL; | |
425 | ||
426 | if (attr & MLX4_UPDATE_QP_SMAC) { | |
427 | pri_addr_path_mask |= 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX; | |
428 | cmd->qp_context.pri_path.grh_mylmc = params->smac_index; | |
429 | } | |
430 | ||
09e05c3f MB |
431 | if (attr & MLX4_UPDATE_QP_VSD) { |
432 | qp_mask |= 1ULL << MLX4_UPD_QP_MASK_VSD; | |
433 | if (params->flags & MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE) | |
434 | cmd->qp_context.param3 |= cpu_to_be32(MLX4_STRIP_VLAN); | |
435 | } | |
436 | ||
ce8d9e0d | 437 | cmd->primary_addr_path_mask = cpu_to_be64(pri_addr_path_mask); |
09e05c3f | 438 | cmd->qp_mask = cpu_to_be64(qp_mask); |
ce8d9e0d | 439 | |
09e05c3f | 440 | err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0, |
ce8d9e0d MB |
441 | MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A, |
442 | MLX4_CMD_NATIVE); | |
443 | ||
444 | mlx4_free_cmd_mailbox(dev, mailbox); | |
445 | return err; | |
446 | } | |
447 | EXPORT_SYMBOL_GPL(mlx4_update_qp); | |
448 | ||
225c7b1f RD |
449 | void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp) |
450 | { | |
451 | struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; | |
452 | unsigned long flags; | |
453 | ||
454 | spin_lock_irqsave(&qp_table->lock, flags); | |
455 | radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1)); | |
456 | spin_unlock_irqrestore(&qp_table->lock, flags); | |
457 | } | |
458 | EXPORT_SYMBOL_GPL(mlx4_qp_remove); | |
459 | ||
460 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp) | |
461 | { | |
225c7b1f RD |
462 | if (atomic_dec_and_test(&qp->refcount)) |
463 | complete(&qp->free); | |
464 | wait_for_completion(&qp->free); | |
465 | ||
fe9a2603 | 466 | mlx4_qp_free_icm(dev, qp->qpn); |
225c7b1f RD |
467 | } |
468 | EXPORT_SYMBOL_GPL(mlx4_qp_free); | |
469 | ||
470 | static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn) | |
471 | { | |
472 | return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP, | |
f9baff50 | 473 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
225c7b1f RD |
474 | } |
475 | ||
3d73c288 | 476 | int mlx4_init_qp_table(struct mlx4_dev *dev) |
225c7b1f RD |
477 | { |
478 | struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; | |
479 | int err; | |
93fc9e1b | 480 | int reserved_from_top = 0; |
47605df9 | 481 | int k; |
225c7b1f RD |
482 | |
483 | spin_lock_init(&qp_table->lock); | |
484 | INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC); | |
fe9a2603 JM |
485 | if (mlx4_is_slave(dev)) |
486 | return 0; | |
225c7b1f RD |
487 | |
488 | /* | |
489 | * We reserve 2 extra QPs per port for the special QPs. The | |
490 | * block of special QPs must be aligned to a multiple of 8, so | |
491 | * round up. | |
0a1405da SH |
492 | * |
493 | * We also reserve the MSB of the 24-bit QP number to indicate | |
494 | * that a QP is an XRC QP. | |
225c7b1f | 495 | */ |
47605df9 | 496 | dev->phys_caps.base_sqpn = |
93fc9e1b YP |
497 | ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8); |
498 | ||
499 | { | |
500 | int sort[MLX4_NUM_QP_REGION]; | |
501 | int i, j, tmp; | |
502 | int last_base = dev->caps.num_qps; | |
503 | ||
504 | for (i = 1; i < MLX4_NUM_QP_REGION; ++i) | |
505 | sort[i] = i; | |
506 | ||
507 | for (i = MLX4_NUM_QP_REGION; i > 0; --i) { | |
508 | for (j = 2; j < i; ++j) { | |
509 | if (dev->caps.reserved_qps_cnt[sort[j]] > | |
510 | dev->caps.reserved_qps_cnt[sort[j - 1]]) { | |
511 | tmp = sort[j]; | |
512 | sort[j] = sort[j - 1]; | |
513 | sort[j - 1] = tmp; | |
514 | } | |
515 | } | |
516 | } | |
517 | ||
518 | for (i = 1; i < MLX4_NUM_QP_REGION; ++i) { | |
519 | last_base -= dev->caps.reserved_qps_cnt[sort[i]]; | |
520 | dev->caps.reserved_qps_base[sort[i]] = last_base; | |
521 | reserved_from_top += | |
522 | dev->caps.reserved_qps_cnt[sort[i]]; | |
523 | } | |
524 | ||
525 | } | |
526 | ||
e2c76824 JM |
527 | /* Reserve 8 real SQPs in both native and SRIOV modes. |
528 | * In addition, in SRIOV mode, reserve 8 proxy SQPs per function | |
529 | * (for all PFs and VFs), and 8 corresponding tunnel QPs. | |
530 | * Each proxy SQP works opposite its own tunnel QP. | |
531 | * | |
532 | * The QPs are arranged as follows: | |
533 | * a. 8 real SQPs | |
534 | * b. All the proxy SQPs (8 per function) | |
535 | * c. All the tunnel QPs (8 per function) | |
536 | */ | |
537 | ||
225c7b1f | 538 | err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps, |
5a0d0a61 | 539 | (1 << 23) - 1, mlx4_num_reserved_sqps(dev), |
93fc9e1b | 540 | reserved_from_top); |
47605df9 JM |
541 | if (err) |
542 | return err; | |
e2c76824 | 543 | |
e2c76824 | 544 | if (mlx4_is_mfunc(dev)) { |
47605df9 JM |
545 | /* for PPF use */ |
546 | dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8; | |
547 | dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX; | |
548 | ||
549 | /* In mfunc, calculate proxy and tunnel qp offsets for the PF here, | |
550 | * since the PF does not call mlx4_slave_caps */ | |
551 | dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
552 | dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
553 | dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
554 | dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
555 | ||
556 | if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || | |
557 | !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) { | |
558 | err = -ENOMEM; | |
559 | goto err_mem; | |
560 | } | |
e2c76824 | 561 | |
47605df9 JM |
562 | for (k = 0; k < dev->caps.num_ports; k++) { |
563 | dev->caps.qp0_proxy[k] = dev->phys_caps.base_proxy_sqpn + | |
564 | 8 * mlx4_master_func_num(dev) + k; | |
565 | dev->caps.qp0_tunnel[k] = dev->caps.qp0_proxy[k] + 8 * MLX4_MFUNC_MAX; | |
566 | dev->caps.qp1_proxy[k] = dev->phys_caps.base_proxy_sqpn + | |
567 | 8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k; | |
568 | dev->caps.qp1_tunnel[k] = dev->caps.qp1_proxy[k] + 8 * MLX4_MFUNC_MAX; | |
569 | } | |
570 | } | |
571 | ||
572 | ||
573 | err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn); | |
225c7b1f | 574 | if (err) |
47605df9 JM |
575 | goto err_mem; |
576 | return 0; | |
225c7b1f | 577 | |
47605df9 JM |
578 | err_mem: |
579 | kfree(dev->caps.qp0_tunnel); | |
580 | kfree(dev->caps.qp0_proxy); | |
581 | kfree(dev->caps.qp1_tunnel); | |
582 | kfree(dev->caps.qp1_proxy); | |
583 | dev->caps.qp0_tunnel = dev->caps.qp0_proxy = | |
584 | dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL; | |
585 | return err; | |
225c7b1f RD |
586 | } |
587 | ||
588 | void mlx4_cleanup_qp_table(struct mlx4_dev *dev) | |
589 | { | |
fe9a2603 JM |
590 | if (mlx4_is_slave(dev)) |
591 | return; | |
592 | ||
225c7b1f RD |
593 | mlx4_CONF_SPECIAL_QP(dev, 0); |
594 | mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap); | |
595 | } | |
6a775e2b JM |
596 | |
597 | int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, | |
598 | struct mlx4_qp_context *context) | |
599 | { | |
600 | struct mlx4_cmd_mailbox *mailbox; | |
601 | int err; | |
602 | ||
603 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
604 | if (IS_ERR(mailbox)) | |
605 | return PTR_ERR(mailbox); | |
606 | ||
607 | err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0, | |
f9baff50 JM |
608 | MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A, |
609 | MLX4_CMD_WRAPPED); | |
6a775e2b JM |
610 | if (!err) |
611 | memcpy(context, mailbox->buf + 8, sizeof *context); | |
612 | ||
613 | mlx4_free_cmd_mailbox(dev, mailbox); | |
614 | return err; | |
615 | } | |
616 | EXPORT_SYMBOL_GPL(mlx4_qp_query); | |
617 | ||
ed4d3c10 YP |
618 | int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
619 | struct mlx4_qp_context *context, | |
620 | struct mlx4_qp *qp, enum mlx4_qp_state *qp_state) | |
621 | { | |
622 | int err; | |
623 | int i; | |
624 | enum mlx4_qp_state states[] = { | |
625 | MLX4_QP_STATE_RST, | |
626 | MLX4_QP_STATE_INIT, | |
627 | MLX4_QP_STATE_RTR, | |
628 | MLX4_QP_STATE_RTS | |
629 | }; | |
630 | ||
631 | for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { | |
632 | context->flags &= cpu_to_be32(~(0xf << 28)); | |
633 | context->flags |= cpu_to_be32(states[i + 1] << 28); | |
634 | err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1], | |
635 | context, 0, 0, qp); | |
636 | if (err) { | |
1a91de28 | 637 | mlx4_err(dev, "Failed to bring QP to state: %d with error: %d\n", |
ed4d3c10 YP |
638 | states[i + 1], err); |
639 | return err; | |
640 | } | |
641 | ||
642 | *qp_state = states[i + 1]; | |
643 | } | |
644 | ||
645 | return 0; | |
646 | } | |
647 | EXPORT_SYMBOL_GPL(mlx4_qp_to_ready); |