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net/core: Add reading VF statistics through the PF netdevice
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / resource_tracker.c
CommitLineData
c82e9aa0
EC		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
4 * All rights reserved.
5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/sched.h>
37#include <linux/pci.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/io.h>
e143a1ad 41#include <linux/slab.h>
c82e9aa0
EC		 42#include <linux/mlx4/cmd.h>
43#include <linux/mlx4/qp.h>
af22d9de 44#include <linux/if_ether.h>
7fb40f87 45#include <linux/etherdevice.h>
c82e9aa0
EC		 46
47#include "mlx4.h"
48#include "fw.h"
49
50#define MLX4_MAC_VALID (1ull << 63)
9de92c60
EBE		 51#define MLX4_PF_COUNTERS_PER_PORT 2
52#define MLX4_VF_COUNTERS_PER_PORT 1
c82e9aa0
EC		 53
54struct mac_res {
55 struct list_head list;
56 u64 mac;
2f5bb473
JM		 57 int ref_count;
58 u8 smac_index;
c82e9aa0
EC		 59 u8 port;
60};
61
4874080d
JM		 62struct vlan_res {
63 struct list_head list;
64 u16 vlan;
65 int ref_count;
66 int vlan_index;
67 u8 port;
68};
69
c82e9aa0
EC		 70struct res_common {
71 struct list_head list;
4af1c048 72 struct rb_node node;
aa1ec3dd 73 u64 res_id;
c82e9aa0
EC		 74 int owner;
75 int state;
76 int from_state;
77 int to_state;
78 int removing;
79};
80
81enum {
82 RES_ANY_BUSY = 1
83};
84
85struct res_gid {
86 struct list_head list;
87 u8 gid[16];
88 enum mlx4_protocol prot;
9f5b6c63 89 enum mlx4_steer_type steer;
fab1e24a 90 u64 reg_id;
c82e9aa0
EC		 91};
92
93enum res_qp_states {
94 RES_QP_BUSY = RES_ANY_BUSY,
95
96 /* QP number was allocated */
97 RES_QP_RESERVED,
98
99 /* ICM memory for QP context was mapped */
100 RES_QP_MAPPED,
101
102 /* QP is in hw ownership */
103 RES_QP_HW
104};
105
c82e9aa0
EC		 106struct res_qp {
107 struct res_common com;
108 struct res_mtt *mtt;
109 struct res_cq *rcq;
110 struct res_cq *scq;
111 struct res_srq *srq;
112 struct list_head mcg_list;
113 spinlock_t mcg_spl;
114 int local_qpn;
2c473ae7 115 atomic_t ref_count;
b01978ca 116 u32 qpc_flags;
f0f829bf 117 /* saved qp params before VST enforcement in order to restore on VGT */
b01978ca 118 u8 sched_queue;
f0f829bf
RE		 119 __be32 param3;
120 u8 vlan_control;
121 u8 fvl_rx;
122 u8 pri_path_fl;
123 u8 vlan_index;
124 u8 feup;
c82e9aa0
EC		 125};
126
127enum res_mtt_states {
128 RES_MTT_BUSY = RES_ANY_BUSY,
129 RES_MTT_ALLOCATED,
130};
131
132static inline const char *mtt_states_str(enum res_mtt_states state)
133{
134 switch (state) {
135 case RES_MTT_BUSY: return "RES_MTT_BUSY";
136 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
137 default: return "Unknown";
138 }
139}
140
141struct res_mtt {
142 struct res_common com;
143 int order;
144 atomic_t ref_count;
145};
146
147enum res_mpt_states {
148 RES_MPT_BUSY = RES_ANY_BUSY,
149 RES_MPT_RESERVED,
150 RES_MPT_MAPPED,
151 RES_MPT_HW,
152};
153
154struct res_mpt {
155 struct res_common com;
156 struct res_mtt *mtt;
157 int key;
158};
159
160enum res_eq_states {
161 RES_EQ_BUSY = RES_ANY_BUSY,
162 RES_EQ_RESERVED,
163 RES_EQ_HW,
164};
165
166struct res_eq {
167 struct res_common com;
168 struct res_mtt *mtt;
169};
170
171enum res_cq_states {
172 RES_CQ_BUSY = RES_ANY_BUSY,
173 RES_CQ_ALLOCATED,
174 RES_CQ_HW,
175};
176
177struct res_cq {
178 struct res_common com;
179 struct res_mtt *mtt;
180 atomic_t ref_count;
181};
182
183enum res_srq_states {
184 RES_SRQ_BUSY = RES_ANY_BUSY,
185 RES_SRQ_ALLOCATED,
186 RES_SRQ_HW,
187};
188
c82e9aa0
EC		 189struct res_srq {
190 struct res_common com;
191 struct res_mtt *mtt;
192 struct res_cq *cq;
193 atomic_t ref_count;
194};
195
196enum res_counter_states {
197 RES_COUNTER_BUSY = RES_ANY_BUSY,
198 RES_COUNTER_ALLOCATED,
199};
200
c82e9aa0
EC		 201struct res_counter {
202 struct res_common com;
203 int port;
204};
205
ba062d52
JM		 206enum res_xrcdn_states {
207 RES_XRCD_BUSY = RES_ANY_BUSY,
208 RES_XRCD_ALLOCATED,
209};
210
211struct res_xrcdn {
212 struct res_common com;
213 int port;
214};
215
1b9c6b06
HHZ		 216enum res_fs_rule_states {
217 RES_FS_RULE_BUSY = RES_ANY_BUSY,
218 RES_FS_RULE_ALLOCATED,
219};
220
221struct res_fs_rule {
222 struct res_common com;
2c473ae7 223 int qpn;
1b9c6b06
HHZ		 224};
225
4af1c048
HHZ		 226static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
227{
228 struct rb_node *node = root->rb_node;
229
230 while (node) {
231 struct res_common *res = container_of(node, struct res_common,
232 node);
233
234 if (res_id < res->res_id)
235 node = node->rb_left;
236 else if (res_id > res->res_id)
237 node = node->rb_right;
238 else
239 return res;
240 }
241 return NULL;
242}
243
244static int res_tracker_insert(struct rb_root *root, struct res_common *res)
245{
246 struct rb_node **new = &(root->rb_node), *parent = NULL;
247
248 /* Figure out where to put new node */
249 while (*new) {
250 struct res_common *this = container_of(*new, struct res_common,
251 node);
252
253 parent = *new;
254 if (res->res_id < this->res_id)
255 new = &((*new)->rb_left);
256 else if (res->res_id > this->res_id)
257 new = &((*new)->rb_right);
258 else
259 return -EEXIST;
260 }
261
262 /* Add new node and rebalance tree. */
263 rb_link_node(&res->node, parent, new);
264 rb_insert_color(&res->node, root);
265
266 return 0;
267}
268
54679e14
JM		 269enum qp_transition {
270 QP_TRANS_INIT2RTR,
271 QP_TRANS_RTR2RTS,
272 QP_TRANS_RTS2RTS,
273 QP_TRANS_SQERR2RTS,
274 QP_TRANS_SQD2SQD,
275 QP_TRANS_SQD2RTS
276};
277
c82e9aa0 278/* For Debug uses */
95646373 279static const char *resource_str(enum mlx4_resource rt)
c82e9aa0
EC		 280{
281 switch (rt) {
282 case RES_QP: return "RES_QP";
283 case RES_CQ: return "RES_CQ";
284 case RES_SRQ: return "RES_SRQ";
285 case RES_MPT: return "RES_MPT";
286 case RES_MTT: return "RES_MTT";
287 case RES_MAC: return "RES_MAC";
4874080d 288 case RES_VLAN: return "RES_VLAN";
c82e9aa0
EC		 289 case RES_EQ: return "RES_EQ";
290 case RES_COUNTER: return "RES_COUNTER";
1b9c6b06 291 case RES_FS_RULE: return "RES_FS_RULE";
ba062d52 292 case RES_XRCD: return "RES_XRCD";
c82e9aa0
EC		 293 default: return "Unknown resource type !!!";
294 };
295}
296
4874080d 297static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
146f3ef4
JM		 298static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
299 enum mlx4_resource res_type, int count,
300 int port)
301{
302 struct mlx4_priv *priv = mlx4_priv(dev);
303 struct resource_allocator *res_alloc =
304 &priv->mfunc.master.res_tracker.res_alloc[res_type];
305 int err = -EINVAL;
306 int allocated, free, reserved, guaranteed, from_free;
95646373 307 int from_rsvd;
146f3ef4 308
872bf2fb 309 if (slave > dev->persist->num_vfs)
146f3ef4
JM		 310 return -EINVAL;
311
312 spin_lock(&res_alloc->alloc_lock);
313 allocated = (port > 0) ?
872bf2fb
YH		 314 res_alloc->allocated[(port - 1) *
315 (dev->persist->num_vfs + 1) + slave] :
146f3ef4
JM		 316 res_alloc->allocated[slave];
317 free = (port > 0) ? res_alloc->res_port_free[port - 1] :
318 res_alloc->res_free;
319 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
320 res_alloc->res_reserved;
321 guaranteed = res_alloc->guaranteed[slave];
322
95646373
JM		 323 if (allocated + count > res_alloc->quota[slave]) {
324 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
325 slave, port, resource_str(res_type), count,
326 allocated, res_alloc->quota[slave]);
146f3ef4 327 goto out;
95646373 328 }
146f3ef4
JM		 329
330 if (allocated + count <= guaranteed) {
331 err = 0;
95646373 332 from_rsvd = count;
146f3ef4
JM		 333 } else {
334 /* portion may need to be obtained from free area */
335 if (guaranteed - allocated > 0)
336 from_free = count - (guaranteed - allocated);
337 else
338 from_free = count;
339
95646373
JM		 340 from_rsvd = count - from_free;
341
342 if (free - from_free >= reserved)
146f3ef4 343 err = 0;
95646373
JM		 344 else
345 mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
346 slave, port, resource_str(res_type), free,
347 from_free, reserved);
146f3ef4
JM		 348 }
349
350 if (!err) {
351 /* grant the request */
352 if (port > 0) {
872bf2fb
YH		 353 res_alloc->allocated[(port - 1) *
354 (dev->persist->num_vfs + 1) + slave] += count;
146f3ef4 355 res_alloc->res_port_free[port - 1] -= count;
95646373 356 res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
146f3ef4
JM		 357 } else {
358 res_alloc->allocated[slave] += count;
359 res_alloc->res_free -= count;
95646373 360 res_alloc->res_reserved -= from_rsvd;
146f3ef4
JM		 361 }
362 }
363
364out:
365 spin_unlock(&res_alloc->alloc_lock);
366 return err;
367}
368
369static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
370 enum mlx4_resource res_type, int count,
371 int port)
372{
373 struct mlx4_priv *priv = mlx4_priv(dev);
374 struct resource_allocator *res_alloc =
375 &priv->mfunc.master.res_tracker.res_alloc[res_type];
95646373 376 int allocated, guaranteed, from_rsvd;
146f3ef4 377
872bf2fb 378 if (slave > dev->persist->num_vfs)
146f3ef4
JM		 379 return;
380
381 spin_lock(&res_alloc->alloc_lock);
95646373
JM		 382
383 allocated = (port > 0) ?
872bf2fb
YH		 384 res_alloc->allocated[(port - 1) *
385 (dev->persist->num_vfs + 1) + slave] :
95646373
JM		 386 res_alloc->allocated[slave];
387 guaranteed = res_alloc->guaranteed[slave];
388
389 if (allocated - count >= guaranteed) {
390 from_rsvd = 0;
391 } else {
392 /* portion may need to be returned to reserved area */
393 if (allocated - guaranteed > 0)
394 from_rsvd = count - (allocated - guaranteed);
395 else
396 from_rsvd = count;
397 }
398
146f3ef4 399 if (port > 0) {
872bf2fb
YH		 400 res_alloc->allocated[(port - 1) *
401 (dev->persist->num_vfs + 1) + slave] -= count;
146f3ef4 402 res_alloc->res_port_free[port - 1] += count;
95646373 403 res_alloc->res_port_rsvd[port - 1] += from_rsvd;
146f3ef4
JM		 404 } else {
405 res_alloc->allocated[slave] -= count;
406 res_alloc->res_free += count;
95646373 407 res_alloc->res_reserved += from_rsvd;
146f3ef4
JM		 408 }
409
410 spin_unlock(&res_alloc->alloc_lock);
411 return;
412}
413
5a0d0a61
JM		 414static inline void initialize_res_quotas(struct mlx4_dev *dev,
415 struct resource_allocator *res_alloc,
416 enum mlx4_resource res_type,
417 int vf, int num_instances)
418{
872bf2fb
YH		 419 res_alloc->guaranteed[vf] = num_instances /
420 (2 * (dev->persist->num_vfs + 1));
5a0d0a61
JM		 421 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
422 if (vf == mlx4_master_func_num(dev)) {
423 res_alloc->res_free = num_instances;
424 if (res_type == RES_MTT) {
425 /* reserved mtts will be taken out of the PF allocation */
426 res_alloc->res_free += dev->caps.reserved_mtts;
427 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
428 res_alloc->quota[vf] += dev->caps.reserved_mtts;
429 }
430 }
431}
432
433void mlx4_init_quotas(struct mlx4_dev *dev)
434{
435 struct mlx4_priv *priv = mlx4_priv(dev);
436 int pf;
437
438 /* quotas for VFs are initialized in mlx4_slave_cap */
439 if (mlx4_is_slave(dev))
440 return;
441
442 if (!mlx4_is_mfunc(dev)) {
443 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
444 mlx4_num_reserved_sqps(dev);
445 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
446 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
447 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
448 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
449 return;
450 }
451
452 pf = mlx4_master_func_num(dev);
453 dev->quotas.qp =
454 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
455 dev->quotas.cq =
456 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
457 dev->quotas.srq =
458 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
459 dev->quotas.mtt =
460 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
461 dev->quotas.mpt =
462 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
463}
9de92c60
EBE		 464
465static int get_max_gauranteed_vfs_counter(struct mlx4_dev *dev)
466{
467 /* reduce the sink counter */
468 return (dev->caps.max_counters - 1 -
469 (MLX4_PF_COUNTERS_PER_PORT * MLX4_MAX_PORTS))
470 / MLX4_MAX_PORTS;
471}
472
c82e9aa0
EC		 473int mlx4_init_resource_tracker(struct mlx4_dev *dev)
474{
475 struct mlx4_priv *priv = mlx4_priv(dev);
5a0d0a61 476 int i, j;
c82e9aa0 477 int t;
9de92c60 478 int max_vfs_guarantee_counter = get_max_gauranteed_vfs_counter(dev);
c82e9aa0
EC		 479
480 priv->mfunc.master.res_tracker.slave_list =
481 kzalloc(dev->num_slaves * sizeof(struct slave_list),
482 GFP_KERNEL);
483 if (!priv->mfunc.master.res_tracker.slave_list)
484 return -ENOMEM;
485
486 for (i = 0 ; i < dev->num_slaves; i++) {
487 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
488 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
489 slave_list[i].res_list[t]);
490 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
491 }
492
493 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
494 dev->num_slaves);
495 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
4af1c048 496 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
c82e9aa0 497
5a0d0a61
JM		 498 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
499 struct resource_allocator *res_alloc =
500 &priv->mfunc.master.res_tracker.res_alloc[i];
872bf2fb
YH		 501 res_alloc->quota = kmalloc((dev->persist->num_vfs + 1) *
502 sizeof(int), GFP_KERNEL);
503 res_alloc->guaranteed = kmalloc((dev->persist->num_vfs + 1) *
504 sizeof(int), GFP_KERNEL);
5a0d0a61
JM		 505 if (i == RES_MAC || i == RES_VLAN)
506 res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
872bf2fb
YH		 507 (dev->persist->num_vfs
508 + 1) *
509 sizeof(int), GFP_KERNEL);
5a0d0a61 510 else
872bf2fb
YH		 511 res_alloc->allocated = kzalloc((dev->persist->
512 num_vfs + 1) *
513 sizeof(int), GFP_KERNEL);
9de92c60
EBE		 514 /* Reduce the sink counter */
515 if (i == RES_COUNTER)
516 res_alloc->res_free = dev->caps.max_counters - 1;
5a0d0a61
JM		 517
518 if (!res_alloc->quota || !res_alloc->guaranteed ||
519 !res_alloc->allocated)
520 goto no_mem_err;
521
146f3ef4 522 spin_lock_init(&res_alloc->alloc_lock);
872bf2fb 523 for (t = 0; t < dev->persist->num_vfs + 1; t++) {
449fc488
MB		 524 struct mlx4_active_ports actv_ports =
525 mlx4_get_active_ports(dev, t);
5a0d0a61
JM		 526 switch (i) {
527 case RES_QP:
528 initialize_res_quotas(dev, res_alloc, RES_QP,
529 t, dev->caps.num_qps -
530 dev->caps.reserved_qps -
531 mlx4_num_reserved_sqps(dev));
532 break;
533 case RES_CQ:
534 initialize_res_quotas(dev, res_alloc, RES_CQ,
535 t, dev->caps.num_cqs -
536 dev->caps.reserved_cqs);
537 break;
538 case RES_SRQ:
539 initialize_res_quotas(dev, res_alloc, RES_SRQ,
540 t, dev->caps.num_srqs -
541 dev->caps.reserved_srqs);
542 break;
543 case RES_MPT:
544 initialize_res_quotas(dev, res_alloc, RES_MPT,
545 t, dev->caps.num_mpts -
546 dev->caps.reserved_mrws);
547 break;
548 case RES_MTT:
549 initialize_res_quotas(dev, res_alloc, RES_MTT,
550 t, dev->caps.num_mtts -
551 dev->caps.reserved_mtts);
552 break;
553 case RES_MAC:
554 if (t == mlx4_master_func_num(dev)) {
449fc488
MB		 555 int max_vfs_pport = 0;
556 /* Calculate the max vfs per port for */
557 /* both ports. */
558 for (j = 0; j < dev->caps.num_ports;
559 j++) {
560 struct mlx4_slaves_pport slaves_pport =
561 mlx4_phys_to_slaves_pport(dev, j + 1);
562 unsigned current_slaves =
563 bitmap_weight(slaves_pport.slaves,
564 dev->caps.num_ports) - 1;
565 if (max_vfs_pport < current_slaves)
566 max_vfs_pport =
567 current_slaves;
568 }
569 res_alloc->quota[t] =
570 MLX4_MAX_MAC_NUM -
571 2 * max_vfs_pport;
5a0d0a61
JM		 572 res_alloc->guaranteed[t] = 2;
573 for (j = 0; j < MLX4_MAX_PORTS; j++)
449fc488
MB		 574 res_alloc->res_port_free[j] =
575 MLX4_MAX_MAC_NUM;
5a0d0a61
JM		 576 } else {
577 res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
578 res_alloc->guaranteed[t] = 2;
579 }
580 break;
581 case RES_VLAN:
582 if (t == mlx4_master_func_num(dev)) {
583 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
584 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
585 for (j = 0; j < MLX4_MAX_PORTS; j++)
586 res_alloc->res_port_free[j] =
587 res_alloc->quota[t];
588 } else {
589 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
590 res_alloc->guaranteed[t] = 0;
591 }
592 break;
593 case RES_COUNTER:
594 res_alloc->quota[t] = dev->caps.max_counters;
5a0d0a61 595 if (t == mlx4_master_func_num(dev))
9de92c60
EBE		 596 res_alloc->guaranteed[t] =
597 MLX4_PF_COUNTERS_PER_PORT *
598 MLX4_MAX_PORTS;
599 else if (t <= max_vfs_guarantee_counter)
600 res_alloc->guaranteed[t] =
601 MLX4_VF_COUNTERS_PER_PORT *
602 MLX4_MAX_PORTS;
603 else
604 res_alloc->guaranteed[t] = 0;
605 res_alloc->res_free -= res_alloc->guaranteed[t];
5a0d0a61
JM		 606 break;
607 default:
608 break;
609 }
610 if (i == RES_MAC || i == RES_VLAN) {
449fc488
MB		 611 for (j = 0; j < dev->caps.num_ports; j++)
612 if (test_bit(j, actv_ports.ports))
613 res_alloc->res_port_rsvd[j] +=
614 res_alloc->guaranteed[t];
5a0d0a61
JM		 615 } else {
616 res_alloc->res_reserved += res_alloc->guaranteed[t];
617 }
618 }
619 }
c82e9aa0 620 spin_lock_init(&priv->mfunc.master.res_tracker.lock);
5a0d0a61
JM		 621 return 0;
622
623no_mem_err:
624 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
625 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
626 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
627 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
628 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
629 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
630 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
631 }
632 return -ENOMEM;
c82e9aa0
EC		 633}
634
b8924951
JM		 635void mlx4_free_resource_tracker(struct mlx4_dev *dev,
636 enum mlx4_res_tracker_free_type type)
c82e9aa0
EC		 637{
638 struct mlx4_priv *priv = mlx4_priv(dev);
639 int i;
640
641 if (priv->mfunc.master.res_tracker.slave_list) {
4874080d
JM		 642 if (type != RES_TR_FREE_STRUCTS_ONLY) {
643 for (i = 0; i < dev->num_slaves; i++) {
b8924951
JM		 644 if (type == RES_TR_FREE_ALL ||
645 dev->caps.function != i)
646 mlx4_delete_all_resources_for_slave(dev, i);
4874080d
JM		 647 }
648 /* free master's vlans */
649 i = dev->caps.function;
111c6094 650 mlx4_reset_roce_gids(dev, i);
4874080d
JM		 651 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
652 rem_slave_vlans(dev, i);
653 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
654 }
b8924951
JM		 655
656 if (type != RES_TR_FREE_SLAVES_ONLY) {
5a0d0a61
JM		 657 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
658 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
659 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
660 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
661 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
662 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
663 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
664 }
b8924951
JM		 665 kfree(priv->mfunc.master.res_tracker.slave_list);
666 priv->mfunc.master.res_tracker.slave_list = NULL;
667 }
c82e9aa0
EC		 668 }
669}
670
54679e14
JM		 671static void update_pkey_index(struct mlx4_dev *dev, int slave,
672 struct mlx4_cmd_mailbox *inbox)
c82e9aa0 673{
54679e14
JM		 674 u8 sched = *(u8 *)(inbox->buf + 64);
675 u8 orig_index = *(u8 *)(inbox->buf + 35);
676 u8 new_index;
677 struct mlx4_priv *priv = mlx4_priv(dev);
678 int port;
679
680 port = (sched >> 6 & 1) + 1;
681
682 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
683 *(u8 *)(inbox->buf + 35) = new_index;
54679e14
JM		 684}
685
686static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
687 u8 slave)
688{
689 struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
690 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
691 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
b6ffaeff 692 int port;
c82e9aa0 693
b6ffaeff
JM		 694 if (MLX4_QP_ST_UD == ts) {
695 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
696 if (mlx4_is_eth(dev, port))
449fc488
MB		 697 qp_ctx->pri_path.mgid_index =
698 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
b6ffaeff
JM		 699 else
700 qp_ctx->pri_path.mgid_index = slave | 0x80;
701
702 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
703 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
704 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
705 if (mlx4_is_eth(dev, port)) {
449fc488
MB		 706 qp_ctx->pri_path.mgid_index +=
707 mlx4_get_base_gid_ix(dev, slave, port);
b6ffaeff
JM		 708 qp_ctx->pri_path.mgid_index &= 0x7f;
709 } else {
710 qp_ctx->pri_path.mgid_index = slave & 0x7F;
711 }
712 }
713 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
714 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
715 if (mlx4_is_eth(dev, port)) {
449fc488
MB		 716 qp_ctx->alt_path.mgid_index +=
717 mlx4_get_base_gid_ix(dev, slave, port);
b6ffaeff
JM		 718 qp_ctx->alt_path.mgid_index &= 0x7f;
719 } else {
720 qp_ctx->alt_path.mgid_index = slave & 0x7F;
721 }
722 }
54679e14 723 }
c82e9aa0
EC		 724}
725
68230242
EBE		 726static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
727 u8 slave, int port);
728
3f7fb021
RE		 729static int update_vport_qp_param(struct mlx4_dev *dev,
730 struct mlx4_cmd_mailbox *inbox,
b01978ca 731 u8 slave, u32 qpn)
3f7fb021
RE		 732{
733 struct mlx4_qp_context *qpc = inbox->buf + 8;
734 struct mlx4_vport_oper_state *vp_oper;
735 struct mlx4_priv *priv;
09e05c3f 736 u32 qp_type;
f5956faf 737 int port, err = 0;
3f7fb021
RE		 738
739 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
740 priv = mlx4_priv(dev);
741 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
09e05c3f 742 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3f7fb021 743
68230242
EBE		 744 err = handle_counter(dev, qpc, slave, port);
745 if (err)
746 goto out;
747
3f7fb021 748 if (MLX4_VGT != vp_oper->state.default_vlan) {
b01978ca
JM		 749 /* the reserved QPs (special, proxy, tunnel)
750 * do not operate over vlans
751 */
752 if (mlx4_is_qp_reserved(dev, qpn))
753 return 0;
754
09e05c3f
MB		 755 /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */
756 if (qp_type == MLX4_QP_ST_UD ||
757 (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) {
758 if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) {
759 *(__be32 *)inbox->buf =
760 cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) |
761 MLX4_QP_OPTPAR_VLAN_STRIPPING);
762 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
763 } else {
764 struct mlx4_update_qp_params params = {.flags = 0};
765
f5956faf
OG		 766 err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, &params);
767 if (err)
768 goto out;
09e05c3f
MB		 769 }
770 }
0a6eac24
RE		 771
772 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
773 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
774 qpc->pri_path.vlan_control =
775 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
776 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
777 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
778 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
779 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
780 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
781 } else if (0 != vp_oper->state.default_vlan) {
7677fc96
RE		 782 qpc->pri_path.vlan_control =
783 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
784 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
785 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
786 } else { /* priority tagged */
787 qpc->pri_path.vlan_control =
788 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
789 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
790 }
791
792 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
3f7fb021 793 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
7677fc96
RE		 794 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
795 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
3f7fb021
RE		 796 qpc->pri_path.sched_queue &= 0xC7;
797 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
08068cd5 798 qpc->qos_vport = vp_oper->state.qos_vport;
3f7fb021 799 }
e6b6a231 800 if (vp_oper->state.spoofchk) {
7677fc96 801 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
e6b6a231 802 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
e6b6a231 803 }
f5956faf
OG		 804out:
805 return err;
3f7fb021
RE		 806}
807
c82e9aa0
EC		 808static int mpt_mask(struct mlx4_dev *dev)
809{
810 return dev->caps.num_mpts - 1;
811}
812
1e3f7b32 813static void *find_res(struct mlx4_dev *dev, u64 res_id,
c82e9aa0
EC		 814 enum mlx4_resource type)
815{
816 struct mlx4_priv *priv = mlx4_priv(dev);
817
4af1c048
HHZ		 818 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
819 res_id);
c82e9aa0
EC		 820}
821
aa1ec3dd 822static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
c82e9aa0
EC		 823 enum mlx4_resource type,
824 void *res)
825{
826 struct res_common *r;
827 int err = 0;
828
829 spin_lock_irq(mlx4_tlock(dev));
830 r = find_res(dev, res_id, type);
831 if (!r) {
832 err = -ENONET;
833 goto exit;
834 }
835
836 if (r->state == RES_ANY_BUSY) {
837 err = -EBUSY;
838 goto exit;
839 }
840
841 if (r->owner != slave) {
842 err = -EPERM;
843 goto exit;
844 }
845
846 r->from_state = r->state;
847 r->state = RES_ANY_BUSY;
c82e9aa0
EC		 848
849 if (res)
850 *((struct res_common **)res) = r;
851
852exit:
853 spin_unlock_irq(mlx4_tlock(dev));
854 return err;
855}
856
857int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
858 enum mlx4_resource type,
aa1ec3dd 859 u64 res_id, int *slave)
c82e9aa0
EC		 860{
861
862 struct res_common *r;
863 int err = -ENOENT;
864 int id = res_id;
865
866 if (type == RES_QP)
867 id &= 0x7fffff;
996b0541 868 spin_lock(mlx4_tlock(dev));
c82e9aa0
EC		 869
870 r = find_res(dev, id, type);
871 if (r) {
872 *slave = r->owner;
873 err = 0;
874 }
996b0541 875 spin_unlock(mlx4_tlock(dev));
c82e9aa0
EC		 876
877 return err;
878}
879
aa1ec3dd 880static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
c82e9aa0
EC		 881 enum mlx4_resource type)
882{
883 struct res_common *r;
884
885 spin_lock_irq(mlx4_tlock(dev));
886 r = find_res(dev, res_id, type);
887 if (r)
888 r->state = r->from_state;
889 spin_unlock_irq(mlx4_tlock(dev));
890}
891
68230242
EBE		 892static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
893 u64 in_param, u64 *out_param, int port);
894
895static int handle_existing_counter(struct mlx4_dev *dev, u8 slave, int port,
896 int counter_index)
897{
898 struct res_common *r;
899 struct res_counter *counter;
900 int ret = 0;
901
902 if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
903 return ret;
904
905 spin_lock_irq(mlx4_tlock(dev));
906 r = find_res(dev, counter_index, RES_COUNTER);
907 if (!r || r->owner != slave)
908 ret = -EINVAL;
909 counter = container_of(r, struct res_counter, com);
910 if (!counter->port)
911 counter->port = port;
912
913 spin_unlock_irq(mlx4_tlock(dev));
914 return ret;
915}
916
917static int handle_unexisting_counter(struct mlx4_dev *dev,
918 struct mlx4_qp_context *qpc, u8 slave,
919 int port)
920{
921 struct mlx4_priv *priv = mlx4_priv(dev);
922 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
923 struct res_common *tmp;
924 struct res_counter *counter;
925 u64 counter_idx = MLX4_SINK_COUNTER_INDEX(dev);
926 int err = 0;
927
928 spin_lock_irq(mlx4_tlock(dev));
929 list_for_each_entry(tmp,
930 &tracker->slave_list[slave].res_list[RES_COUNTER],
931 list) {
932 counter = container_of(tmp, struct res_counter, com);
933 if (port == counter->port) {
934 qpc->pri_path.counter_index = counter->com.res_id;
935 spin_unlock_irq(mlx4_tlock(dev));
936 return 0;
937 }
938 }
939 spin_unlock_irq(mlx4_tlock(dev));
940
941 /* No existing counter, need to allocate a new counter */
942 err = counter_alloc_res(dev, slave, RES_OP_RESERVE, 0, 0, &counter_idx,
943 port);
944 if (err == -ENOENT) {
945 err = 0;
946 } else if (err && err != -ENOSPC) {
947 mlx4_err(dev, "%s: failed to create new counter for slave %d err %d\n",
948 __func__, slave, err);
949 } else {
950 qpc->pri_path.counter_index = counter_idx;
951 mlx4_dbg(dev, "%s: alloc new counter for slave %d index %d\n",
952 __func__, slave, qpc->pri_path.counter_index);
953 err = 0;
954 }
955
956 return err;
957}
958
959static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
960 u8 slave, int port)
961{
962 if (qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX(dev))
963 return handle_existing_counter(dev, slave, port,
964 qpc->pri_path.counter_index);
965
966 return handle_unexisting_counter(dev, qpc, slave, port);
967}
968
c82e9aa0
EC		 969static struct res_common *alloc_qp_tr(int id)
970{
971 struct res_qp *ret;
972
973 ret = kzalloc(sizeof *ret, GFP_KERNEL);
974 if (!ret)
975 return NULL;
976
977 ret->com.res_id = id;
978 ret->com.state = RES_QP_RESERVED;
2531188b 979 ret->local_qpn = id;
c82e9aa0
EC		 980 INIT_LIST_HEAD(&ret->mcg_list);
981 spin_lock_init(&ret->mcg_spl);
2c473ae7 982 atomic_set(&ret->ref_count, 0);
c82e9aa0
EC		 983
984 return &ret->com;
985}
986
987static struct res_common *alloc_mtt_tr(int id, int order)
988{
989 struct res_mtt *ret;
990
991 ret = kzalloc(sizeof *ret, GFP_KERNEL);
992 if (!ret)
993 return NULL;
994
995 ret->com.res_id = id;
996 ret->order = order;
997 ret->com.state = RES_MTT_ALLOCATED;
998 atomic_set(&ret->ref_count, 0);
999
1000 return &ret->com;
1001}
1002
1003static struct res_common *alloc_mpt_tr(int id, int key)
1004{
1005 struct res_mpt *ret;
1006
1007 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1008 if (!ret)
1009 return NULL;
1010
1011 ret->com.res_id = id;
1012 ret->com.state = RES_MPT_RESERVED;
1013 ret->key = key;
1014
1015 return &ret->com;
1016}
1017
1018static struct res_common *alloc_eq_tr(int id)
1019{
1020 struct res_eq *ret;
1021
1022 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1023 if (!ret)
1024 return NULL;
1025
1026 ret->com.res_id = id;
1027 ret->com.state = RES_EQ_RESERVED;
1028
1029 return &ret->com;
1030}
1031
1032static struct res_common *alloc_cq_tr(int id)
1033{
1034 struct res_cq *ret;
1035
1036 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1037 if (!ret)
1038 return NULL;
1039
1040 ret->com.res_id = id;
1041 ret->com.state = RES_CQ_ALLOCATED;
1042 atomic_set(&ret->ref_count, 0);
1043
1044 return &ret->com;
1045}
1046
1047static struct res_common *alloc_srq_tr(int id)
1048{
1049 struct res_srq *ret;
1050
1051 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1052 if (!ret)
1053 return NULL;
1054
1055 ret->com.res_id = id;
1056 ret->com.state = RES_SRQ_ALLOCATED;
1057 atomic_set(&ret->ref_count, 0);
1058
1059 return &ret->com;
1060}
1061
9de92c60 1062static struct res_common *alloc_counter_tr(int id, int port)
c82e9aa0
EC		 1063{
1064 struct res_counter *ret;
1065
1066 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1067 if (!ret)
1068 return NULL;
1069
1070 ret->com.res_id = id;
1071 ret->com.state = RES_COUNTER_ALLOCATED;
9de92c60 1072 ret->port = port;
c82e9aa0
EC		 1073
1074 return &ret->com;
1075}
1076
ba062d52
JM		 1077static struct res_common *alloc_xrcdn_tr(int id)
1078{
1079 struct res_xrcdn *ret;
1080
1081 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1082 if (!ret)
1083 return NULL;
1084
1085 ret->com.res_id = id;
1086 ret->com.state = RES_XRCD_ALLOCATED;
1087
1088 return &ret->com;
1089}
1090
2c473ae7 1091static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
1b9c6b06
HHZ		 1092{
1093 struct res_fs_rule *ret;
1094
1095 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1096 if (!ret)
1097 return NULL;
1098
1099 ret->com.res_id = id;
1100 ret->com.state = RES_FS_RULE_ALLOCATED;
2c473ae7 1101 ret->qpn = qpn;
1b9c6b06
HHZ		 1102 return &ret->com;
1103}
1104
aa1ec3dd 1105static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
c82e9aa0
EC		 1106 int extra)
1107{
1108 struct res_common *ret;
1109
1110 switch (type) {
1111 case RES_QP:
1112 ret = alloc_qp_tr(id);
1113 break;
1114 case RES_MPT:
1115 ret = alloc_mpt_tr(id, extra);
1116 break;
1117 case RES_MTT:
1118 ret = alloc_mtt_tr(id, extra);
1119 break;
1120 case RES_EQ:
1121 ret = alloc_eq_tr(id);
1122 break;
1123 case RES_CQ:
1124 ret = alloc_cq_tr(id);
1125 break;
1126 case RES_SRQ:
1127 ret = alloc_srq_tr(id);
1128 break;
1129 case RES_MAC:
c20862c8 1130 pr_err("implementation missing\n");
c82e9aa0
EC		 1131 return NULL;
1132 case RES_COUNTER:
9de92c60 1133 ret = alloc_counter_tr(id, extra);
c82e9aa0 1134 break;
ba062d52
JM		 1135 case RES_XRCD:
1136 ret = alloc_xrcdn_tr(id);
1137 break;
1b9c6b06 1138 case RES_FS_RULE:
2c473ae7 1139 ret = alloc_fs_rule_tr(id, extra);
1b9c6b06 1140 break;
c82e9aa0
EC		 1141 default:
1142 return NULL;
1143 }
1144 if (ret)
1145 ret->owner = slave;
1146
1147 return ret;
1148}
1149
aa1ec3dd 1150static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
c82e9aa0
EC		 1151 enum mlx4_resource type, int extra)
1152{
1153 int i;
1154 int err;
1155 struct mlx4_priv *priv = mlx4_priv(dev);
1156 struct res_common **res_arr;
1157 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4af1c048 1158 struct rb_root *root = &tracker->res_tree[type];
c82e9aa0
EC		 1159
1160 res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
1161 if (!res_arr)
1162 return -ENOMEM;
1163
1164 for (i = 0; i < count; ++i) {
1165 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1166 if (!res_arr[i]) {
1167 for (--i; i >= 0; --i)
1168 kfree(res_arr[i]);
1169
1170 kfree(res_arr);
1171 return -ENOMEM;
1172 }
1173 }
1174
1175 spin_lock_irq(mlx4_tlock(dev));
1176 for (i = 0; i < count; ++i) {
1177 if (find_res(dev, base + i, type)) {
1178 err = -EEXIST;
1179 goto undo;
1180 }
4af1c048 1181 err = res_tracker_insert(root, res_arr[i]);
c82e9aa0
EC		 1182 if (err)
1183 goto undo;
1184 list_add_tail(&res_arr[i]->list,
1185 &tracker->slave_list[slave].res_list[type]);
1186 }
1187 spin_unlock_irq(mlx4_tlock(dev));
1188 kfree(res_arr);
1189
1190 return 0;
1191
1192undo:
1193 for (--i; i >= base; --i)
4af1c048 1194 rb_erase(&res_arr[i]->node, root);
c82e9aa0
EC		 1195
1196 spin_unlock_irq(mlx4_tlock(dev));
1197
1198 for (i = 0; i < count; ++i)
1199 kfree(res_arr[i]);
1200
1201 kfree(res_arr);
1202
1203 return err;
1204}
1205
1206static int remove_qp_ok(struct res_qp *res)
1207{
2c473ae7
HHZ		 1208 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1209 !list_empty(&res->mcg_list)) {
1210 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1211 res->com.state, atomic_read(&res->ref_count));
c82e9aa0 1212 return -EBUSY;
2c473ae7 1213 } else if (res->com.state != RES_QP_RESERVED) {
c82e9aa0 1214 return -EPERM;
2c473ae7 1215 }
c82e9aa0
EC		 1216
1217 return 0;
1218}
1219
1220static int remove_mtt_ok(struct res_mtt *res, int order)
1221{
1222 if (res->com.state == RES_MTT_BUSY ||
1223 atomic_read(&res->ref_count)) {
c20862c8
AV		 1224 pr_devel("%s-%d: state %s, ref_count %d\n",
1225 __func__, __LINE__,
1226 mtt_states_str(res->com.state),
1227 atomic_read(&res->ref_count));
c82e9aa0
EC		 1228 return -EBUSY;
1229 } else if (res->com.state != RES_MTT_ALLOCATED)
1230 return -EPERM;
1231 else if (res->order != order)
1232 return -EINVAL;
1233
1234 return 0;
1235}
1236
1237static int remove_mpt_ok(struct res_mpt *res)
1238{
1239 if (res->com.state == RES_MPT_BUSY)
1240 return -EBUSY;
1241 else if (res->com.state != RES_MPT_RESERVED)
1242 return -EPERM;
1243
1244 return 0;
1245}
1246
1247static int remove_eq_ok(struct res_eq *res)
1248{
1249 if (res->com.state == RES_MPT_BUSY)
1250 return -EBUSY;
1251 else if (res->com.state != RES_MPT_RESERVED)
1252 return -EPERM;
1253
1254 return 0;
1255}
1256
1257static int remove_counter_ok(struct res_counter *res)
1258{
1259 if (res->com.state == RES_COUNTER_BUSY)
1260 return -EBUSY;
1261 else if (res->com.state != RES_COUNTER_ALLOCATED)
1262 return -EPERM;
1263
1264 return 0;
1265}
1266
ba062d52
JM		 1267static int remove_xrcdn_ok(struct res_xrcdn *res)
1268{
1269 if (res->com.state == RES_XRCD_BUSY)
1270 return -EBUSY;
1271 else if (res->com.state != RES_XRCD_ALLOCATED)
1272 return -EPERM;
1273
1274 return 0;
1275}
1276
1b9c6b06
HHZ		 1277static int remove_fs_rule_ok(struct res_fs_rule *res)
1278{
1279 if (res->com.state == RES_FS_RULE_BUSY)
1280 return -EBUSY;
1281 else if (res->com.state != RES_FS_RULE_ALLOCATED)
1282 return -EPERM;
1283
1284 return 0;
1285}
1286
c82e9aa0
EC		 1287static int remove_cq_ok(struct res_cq *res)
1288{
1289 if (res->com.state == RES_CQ_BUSY)
1290 return -EBUSY;
1291 else if (res->com.state != RES_CQ_ALLOCATED)
1292 return -EPERM;
1293
1294 return 0;
1295}
1296
1297static int remove_srq_ok(struct res_srq *res)
1298{
1299 if (res->com.state == RES_SRQ_BUSY)
1300 return -EBUSY;
1301 else if (res->com.state != RES_SRQ_ALLOCATED)
1302 return -EPERM;
1303
1304 return 0;
1305}
1306
1307static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1308{
1309 switch (type) {
1310 case RES_QP:
1311 return remove_qp_ok((struct res_qp *)res);
1312 case RES_CQ:
1313 return remove_cq_ok((struct res_cq *)res);
1314 case RES_SRQ:
1315 return remove_srq_ok((struct res_srq *)res);
1316 case RES_MPT:
1317 return remove_mpt_ok((struct res_mpt *)res);
1318 case RES_MTT:
1319 return remove_mtt_ok((struct res_mtt *)res, extra);
1320 case RES_MAC:
1321 return -ENOSYS;
1322 case RES_EQ:
1323 return remove_eq_ok((struct res_eq *)res);
1324 case RES_COUNTER:
1325 return remove_counter_ok((struct res_counter *)res);
ba062d52
JM		 1326 case RES_XRCD:
1327 return remove_xrcdn_ok((struct res_xrcdn *)res);
1b9c6b06
HHZ		 1328 case RES_FS_RULE:
1329 return remove_fs_rule_ok((struct res_fs_rule *)res);
c82e9aa0
EC		 1330 default:
1331 return -EINVAL;
1332 }
1333}
1334
aa1ec3dd 1335static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
c82e9aa0
EC		 1336 enum mlx4_resource type, int extra)
1337{
aa1ec3dd 1338 u64 i;
c82e9aa0
EC		 1339 int err;
1340 struct mlx4_priv *priv = mlx4_priv(dev);
1341 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1342 struct res_common *r;
1343
1344 spin_lock_irq(mlx4_tlock(dev));
1345 for (i = base; i < base + count; ++i) {
4af1c048 1346 r = res_tracker_lookup(&tracker->res_tree[type], i);
c82e9aa0
EC		 1347 if (!r) {
1348 err = -ENOENT;
1349 goto out;
1350 }
1351 if (r->owner != slave) {
1352 err = -EPERM;
1353 goto out;
1354 }
1355 err = remove_ok(r, type, extra);
1356 if (err)
1357 goto out;
1358 }
1359
1360 for (i = base; i < base + count; ++i) {
4af1c048
HHZ		 1361 r = res_tracker_lookup(&tracker->res_tree[type], i);
1362 rb_erase(&r->node, &tracker->res_tree[type]);
c82e9aa0
EC		 1363 list_del(&r->list);
1364 kfree(r);
1365 }
1366 err = 0;
1367
1368out:
1369 spin_unlock_irq(mlx4_tlock(dev));
1370
1371 return err;
1372}
1373
1374static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1375 enum res_qp_states state, struct res_qp **qp,
1376 int alloc)
1377{
1378 struct mlx4_priv *priv = mlx4_priv(dev);
1379 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1380 struct res_qp *r;
1381 int err = 0;
1382
1383 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1384 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
c82e9aa0
EC		 1385 if (!r)
1386 err = -ENOENT;
1387 else if (r->com.owner != slave)
1388 err = -EPERM;
1389 else {
1390 switch (state) {
1391 case RES_QP_BUSY:
aa1ec3dd 1392 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
c82e9aa0
EC		 1393 __func__, r->com.res_id);
1394 err = -EBUSY;
1395 break;
1396
1397 case RES_QP_RESERVED:
1398 if (r->com.state == RES_QP_MAPPED && !alloc)
1399 break;
1400
aa1ec3dd 1401 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
c82e9aa0
EC		 1402 err = -EINVAL;
1403 break;
1404
1405 case RES_QP_MAPPED:
1406 if ((r->com.state == RES_QP_RESERVED && alloc) ||
1407 r->com.state == RES_QP_HW)
1408 break;
1409 else {
aa1ec3dd 1410 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
c82e9aa0
EC		 1411 r->com.res_id);
1412 err = -EINVAL;
1413 }
1414
1415 break;
1416
1417 case RES_QP_HW:
1418 if (r->com.state != RES_QP_MAPPED)
1419 err = -EINVAL;
1420 break;
1421 default:
1422 err = -EINVAL;
1423 }
1424
1425 if (!err) {
1426 r->com.from_state = r->com.state;
1427 r->com.to_state = state;
1428 r->com.state = RES_QP_BUSY;
1429 if (qp)
64699336 1430 *qp = r;
c82e9aa0
EC		 1431 }
1432 }
1433
1434 spin_unlock_irq(mlx4_tlock(dev));
1435
1436 return err;
1437}
1438
1439static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1440 enum res_mpt_states state, struct res_mpt **mpt)
1441{
1442 struct mlx4_priv *priv = mlx4_priv(dev);
1443 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1444 struct res_mpt *r;
1445 int err = 0;
1446
1447 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1448 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
c82e9aa0
EC		 1449 if (!r)
1450 err = -ENOENT;
1451 else if (r->com.owner != slave)
1452 err = -EPERM;
1453 else {
1454 switch (state) {
1455 case RES_MPT_BUSY:
1456 err = -EINVAL;
1457 break;
1458
1459 case RES_MPT_RESERVED:
1460 if (r->com.state != RES_MPT_MAPPED)
1461 err = -EINVAL;
1462 break;
1463
1464 case RES_MPT_MAPPED:
1465 if (r->com.state != RES_MPT_RESERVED &&
1466 r->com.state != RES_MPT_HW)
1467 err = -EINVAL;
1468 break;
1469
1470 case RES_MPT_HW:
1471 if (r->com.state != RES_MPT_MAPPED)
1472 err = -EINVAL;
1473 break;
1474 default:
1475 err = -EINVAL;
1476 }
1477
1478 if (!err) {
1479 r->com.from_state = r->com.state;
1480 r->com.to_state = state;
1481 r->com.state = RES_MPT_BUSY;
1482 if (mpt)
64699336 1483 *mpt = r;
c82e9aa0
EC		 1484 }
1485 }
1486
1487 spin_unlock_irq(mlx4_tlock(dev));
1488
1489 return err;
1490}
1491
1492static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1493 enum res_eq_states state, struct res_eq **eq)
1494{
1495 struct mlx4_priv *priv = mlx4_priv(dev);
1496 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1497 struct res_eq *r;
1498 int err = 0;
1499
1500 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1501 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
c82e9aa0
EC		 1502 if (!r)
1503 err = -ENOENT;
1504 else if (r->com.owner != slave)
1505 err = -EPERM;
1506 else {
1507 switch (state) {
1508 case RES_EQ_BUSY:
1509 err = -EINVAL;
1510 break;
1511
1512 case RES_EQ_RESERVED:
1513 if (r->com.state != RES_EQ_HW)
1514 err = -EINVAL;
1515 break;
1516
1517 case RES_EQ_HW:
1518 if (r->com.state != RES_EQ_RESERVED)
1519 err = -EINVAL;
1520 break;
1521
1522 default:
1523 err = -EINVAL;
1524 }
1525
1526 if (!err) {
1527 r->com.from_state = r->com.state;
1528 r->com.to_state = state;
1529 r->com.state = RES_EQ_BUSY;
1530 if (eq)
1531 *eq = r;
1532 }
1533 }
1534
1535 spin_unlock_irq(mlx4_tlock(dev));
1536
1537 return err;
1538}
1539
1540static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1541 enum res_cq_states state, struct res_cq **cq)
1542{
1543 struct mlx4_priv *priv = mlx4_priv(dev);
1544 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1545 struct res_cq *r;
1546 int err;
1547
1548 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1549 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
c9218a9e 1550 if (!r) {
c82e9aa0 1551 err = -ENOENT;
c9218a9e 1552 } else if (r->com.owner != slave) {
c82e9aa0 1553 err = -EPERM;
c9218a9e
PB		 1554 } else if (state == RES_CQ_ALLOCATED) {
1555 if (r->com.state != RES_CQ_HW)
c82e9aa0 1556 err = -EINVAL;
c9218a9e
PB		 1557 else if (atomic_read(&r->ref_count))
1558 err = -EBUSY;
1559 else
1560 err = 0;
1561 } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1562 err = -EINVAL;
1563 } else {
1564 err = 0;
1565 }
c82e9aa0 1566
c9218a9e
PB		 1567 if (!err) {
1568 r->com.from_state = r->com.state;
1569 r->com.to_state = state;
1570 r->com.state = RES_CQ_BUSY;
1571 if (cq)
1572 *cq = r;
c82e9aa0
EC		 1573 }
1574
1575 spin_unlock_irq(mlx4_tlock(dev));
1576
1577 return err;
1578}
1579
1580static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
f088cbb8 1581 enum res_srq_states state, struct res_srq **srq)
c82e9aa0
EC		 1582{
1583 struct mlx4_priv *priv = mlx4_priv(dev);
1584 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1585 struct res_srq *r;
1586 int err = 0;
1587
1588 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1589 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
f088cbb8 1590 if (!r) {
c82e9aa0 1591 err = -ENOENT;
f088cbb8 1592 } else if (r->com.owner != slave) {
c82e9aa0 1593 err = -EPERM;
f088cbb8
PB		 1594 } else if (state == RES_SRQ_ALLOCATED) {
1595 if (r->com.state != RES_SRQ_HW)
c82e9aa0 1596 err = -EINVAL;
f088cbb8
PB		 1597 else if (atomic_read(&r->ref_count))
1598 err = -EBUSY;
1599 } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1600 err = -EINVAL;
1601 }
c82e9aa0 1602
f088cbb8
PB		 1603 if (!err) {
1604 r->com.from_state = r->com.state;
1605 r->com.to_state = state;
1606 r->com.state = RES_SRQ_BUSY;
1607 if (srq)
1608 *srq = r;
c82e9aa0
EC		 1609 }
1610
1611 spin_unlock_irq(mlx4_tlock(dev));
1612
1613 return err;
1614}
1615
1616static void res_abort_move(struct mlx4_dev *dev, int slave,
1617 enum mlx4_resource type, int id)
1618{
1619 struct mlx4_priv *priv = mlx4_priv(dev);
1620 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1621 struct res_common *r;
1622
1623 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1624 r = res_tracker_lookup(&tracker->res_tree[type], id);
c82e9aa0
EC		 1625 if (r && (r->owner == slave))
1626 r->state = r->from_state;
1627 spin_unlock_irq(mlx4_tlock(dev));
1628}
1629
1630static void res_end_move(struct mlx4_dev *dev, int slave,
1631 enum mlx4_resource type, int id)
1632{
1633 struct mlx4_priv *priv = mlx4_priv(dev);
1634 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1635 struct res_common *r;
1636
1637 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1638 r = res_tracker_lookup(&tracker->res_tree[type], id);
c82e9aa0
EC		 1639 if (r && (r->owner == slave))
1640 r->state = r->to_state;
1641 spin_unlock_irq(mlx4_tlock(dev));
1642}
1643
1644static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1645{
e2c76824
JM		 1646 return mlx4_is_qp_reserved(dev, qpn) &&
1647 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
c82e9aa0
EC		 1648}
1649
54679e14
JM		 1650static int fw_reserved(struct mlx4_dev *dev, int qpn)
1651{
1652 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
c82e9aa0
EC		 1653}
1654
1655static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1656 u64 in_param, u64 *out_param)
1657{
1658 int err;
1659 int count;
1660 int align;
1661 int base;
1662 int qpn;
ddae0349 1663 u8 flags;
c82e9aa0
EC		 1664
1665 switch (op) {
1666 case RES_OP_RESERVE:
2d5c57d7 1667 count = get_param_l(&in_param) & 0xffffff;
ddae0349
EE		 1668 /* Turn off all unsupported QP allocation flags that the
1669 * slave tries to set.
1670 */
1671 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
c82e9aa0 1672 align = get_param_h(&in_param);
146f3ef4 1673 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 1674 if (err)
1675 return err;
1676
ddae0349 1677 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
146f3ef4
JM		 1678 if (err) {
1679 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1680 return err;
1681 }
1682
c82e9aa0
EC		 1683 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1684 if (err) {
146f3ef4 1685 mlx4_release_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 1686 __mlx4_qp_release_range(dev, base, count);
1687 return err;
1688 }
1689 set_param_l(out_param, base);
1690 break;
1691 case RES_OP_MAP_ICM:
1692 qpn = get_param_l(&in_param) & 0x7fffff;
1693 if (valid_reserved(dev, slave, qpn)) {
1694 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1695 if (err)
1696 return err;
1697 }
1698
1699 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1700 NULL, 1);
1701 if (err)
1702 return err;
1703
54679e14 1704 if (!fw_reserved(dev, qpn)) {
40f2287b 1705 err = __mlx4_qp_alloc_icm(dev, qpn, GFP_KERNEL);
c82e9aa0
EC		 1706 if (err) {
1707 res_abort_move(dev, slave, RES_QP, qpn);
1708 return err;
1709 }
1710 }
1711
1712 res_end_move(dev, slave, RES_QP, qpn);
1713 break;
1714
1715 default:
1716 err = -EINVAL;
1717 break;
1718 }
1719 return err;
1720}
1721
1722static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1723 u64 in_param, u64 *out_param)
1724{
1725 int err = -EINVAL;
1726 int base;
1727 int order;
1728
1729 if (op != RES_OP_RESERVE_AND_MAP)
1730 return err;
1731
1732 order = get_param_l(&in_param);
146f3ef4
JM		 1733
1734 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1735 if (err)
1736 return err;
1737
c82e9aa0 1738 base = __mlx4_alloc_mtt_range(dev, order);
146f3ef4
JM		 1739 if (base == -1) {
1740 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 1741 return -ENOMEM;
146f3ef4 1742 }
c82e9aa0
EC		 1743
1744 err = add_res_range(dev, slave, base, 1, RES_MTT, order);
146f3ef4
JM		 1745 if (err) {
1746 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 1747 __mlx4_free_mtt_range(dev, base, order);
146f3ef4 1748 } else {
c82e9aa0 1749 set_param_l(out_param, base);
146f3ef4 1750 }
c82e9aa0
EC		 1751
1752 return err;
1753}
1754
1755static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1756 u64 in_param, u64 *out_param)
1757{
1758 int err = -EINVAL;
1759 int index;
1760 int id;
1761 struct res_mpt *mpt;
1762
1763 switch (op) {
1764 case RES_OP_RESERVE:
146f3ef4
JM		 1765 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1766 if (err)
1767 break;
1768
b20e519a 1769 index = __mlx4_mpt_reserve(dev);
146f3ef4
JM		 1770 if (index == -1) {
1771 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
c82e9aa0 1772 break;
146f3ef4 1773 }
c82e9aa0
EC		 1774 id = index & mpt_mask(dev);
1775
1776 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1777 if (err) {
146f3ef4 1778 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
b20e519a 1779 __mlx4_mpt_release(dev, index);
c82e9aa0
EC		 1780 break;
1781 }
1782 set_param_l(out_param, index);
1783 break;
1784 case RES_OP_MAP_ICM:
1785 index = get_param_l(&in_param);
1786 id = index & mpt_mask(dev);
1787 err = mr_res_start_move_to(dev, slave, id,
1788 RES_MPT_MAPPED, &mpt);
1789 if (err)
1790 return err;
1791
40f2287b 1792 err = __mlx4_mpt_alloc_icm(dev, mpt->key, GFP_KERNEL);
c82e9aa0
EC		 1793 if (err) {
1794 res_abort_move(dev, slave, RES_MPT, id);
1795 return err;
1796 }
1797
1798 res_end_move(dev, slave, RES_MPT, id);
1799 break;
1800 }
1801 return err;
1802}
1803
1804static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1805 u64 in_param, u64 *out_param)
1806{
1807 int cqn;
1808 int err;
1809
1810 switch (op) {
1811 case RES_OP_RESERVE_AND_MAP:
146f3ef4 1812 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 1813 if (err)
1814 break;
1815
146f3ef4
JM		 1816 err = __mlx4_cq_alloc_icm(dev, &cqn);
1817 if (err) {
1818 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1819 break;
1820 }
1821
c82e9aa0
EC		 1822 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1823 if (err) {
146f3ef4 1824 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 1825 __mlx4_cq_free_icm(dev, cqn);
1826 break;
1827 }
1828
1829 set_param_l(out_param, cqn);
1830 break;
1831
1832 default:
1833 err = -EINVAL;
1834 }
1835
1836 return err;
1837}
1838
1839static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1840 u64 in_param, u64 *out_param)
1841{
1842 int srqn;
1843 int err;
1844
1845 switch (op) {
1846 case RES_OP_RESERVE_AND_MAP:
146f3ef4 1847 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 1848 if (err)
1849 break;
1850
146f3ef4
JM		 1851 err = __mlx4_srq_alloc_icm(dev, &srqn);
1852 if (err) {
1853 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1854 break;
1855 }
1856
c82e9aa0
EC		 1857 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1858 if (err) {
146f3ef4 1859 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 1860 __mlx4_srq_free_icm(dev, srqn);
1861 break;
1862 }
1863
1864 set_param_l(out_param, srqn);
1865 break;
1866
1867 default:
1868 err = -EINVAL;
1869 }
1870
1871 return err;
1872}
1873
2f5bb473
JM		 1874static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1875 u8 smac_index, u64 *mac)
1876{
1877 struct mlx4_priv *priv = mlx4_priv(dev);
1878 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1879 struct list_head *mac_list =
1880 &tracker->slave_list[slave].res_list[RES_MAC];
1881 struct mac_res *res, *tmp;
1882
1883 list_for_each_entry_safe(res, tmp, mac_list, list) {
1884 if (res->smac_index == smac_index && res->port == (u8) port) {
1885 *mac = res->mac;
1886 return 0;
1887 }
1888 }
1889 return -ENOENT;
1890}
1891
1892static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
c82e9aa0
EC		 1893{
1894 struct mlx4_priv *priv = mlx4_priv(dev);
1895 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2f5bb473
JM		 1896 struct list_head *mac_list =
1897 &tracker->slave_list[slave].res_list[RES_MAC];
1898 struct mac_res *res, *tmp;
1899
1900 list_for_each_entry_safe(res, tmp, mac_list, list) {
1901 if (res->mac == mac && res->port == (u8) port) {
1902 /* mac found. update ref count */
1903 ++res->ref_count;
1904 return 0;
1905 }
1906 }
c82e9aa0 1907
146f3ef4
JM		 1908 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1909 return -EINVAL;
c82e9aa0 1910 res = kzalloc(sizeof *res, GFP_KERNEL);
146f3ef4
JM		 1911 if (!res) {
1912 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
c82e9aa0 1913 return -ENOMEM;
146f3ef4 1914 }
c82e9aa0
EC		 1915 res->mac = mac;
1916 res->port = (u8) port;
2f5bb473
JM		 1917 res->smac_index = smac_index;
1918 res->ref_count = 1;
c82e9aa0
EC		 1919 list_add_tail(&res->list,
1920 &tracker->slave_list[slave].res_list[RES_MAC]);
1921 return 0;
1922}
1923
1924static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1925 int port)
1926{
1927 struct mlx4_priv *priv = mlx4_priv(dev);
1928 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1929 struct list_head *mac_list =
1930 &tracker->slave_list[slave].res_list[RES_MAC];
1931 struct mac_res *res, *tmp;
1932
1933 list_for_each_entry_safe(res, tmp, mac_list, list) {
1934 if (res->mac == mac && res->port == (u8) port) {
2f5bb473
JM		 1935 if (!--res->ref_count) {
1936 list_del(&res->list);
1937 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1938 kfree(res);
1939 }
c82e9aa0
EC		 1940 break;
1941 }
1942 }
1943}
1944
1945static void rem_slave_macs(struct mlx4_dev *dev, int slave)
1946{
1947 struct mlx4_priv *priv = mlx4_priv(dev);
1948 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1949 struct list_head *mac_list =
1950 &tracker->slave_list[slave].res_list[RES_MAC];
1951 struct mac_res *res, *tmp;
2f5bb473 1952 int i;
c82e9aa0
EC		 1953
1954 list_for_each_entry_safe(res, tmp, mac_list, list) {
1955 list_del(&res->list);
2f5bb473
JM		 1956 /* dereference the mac the num times the slave referenced it */
1957 for (i = 0; i < res->ref_count; i++)
1958 __mlx4_unregister_mac(dev, res->port, res->mac);
146f3ef4 1959 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
c82e9aa0
EC		 1960 kfree(res);
1961 }
1962}
1963
1964static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 1965 u64 in_param, u64 *out_param, int in_port)
c82e9aa0
EC		 1966{
1967 int err = -EINVAL;
1968 int port;
1969 u64 mac;
2f5bb473 1970 u8 smac_index;
c82e9aa0
EC		 1971
1972 if (op != RES_OP_RESERVE_AND_MAP)
1973 return err;
1974
acddd5dd 1975 port = !in_port ? get_param_l(out_param) : in_port;
449fc488
MB		 1976 port = mlx4_slave_convert_port(
1977 dev, slave, port);
1978
1979 if (port < 0)
1980 return -EINVAL;
c82e9aa0
EC		 1981 mac = in_param;
1982
1983 err = __mlx4_register_mac(dev, port, mac);
1984 if (err >= 0) {
2f5bb473 1985 smac_index = err;
c82e9aa0
EC		 1986 set_param_l(out_param, err);
1987 err = 0;
1988 }
1989
1990 if (!err) {
2f5bb473 1991 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
c82e9aa0
EC		 1992 if (err)
1993 __mlx4_unregister_mac(dev, port, mac);
1994 }
1995 return err;
1996}
1997
4874080d
JM		 1998static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1999 int port, int vlan_index)
ffe455ad 2000{
4874080d
JM		 2001 struct mlx4_priv *priv = mlx4_priv(dev);
2002 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2003 struct list_head *vlan_list =
2004 &tracker->slave_list[slave].res_list[RES_VLAN];
2005 struct vlan_res *res, *tmp;
2006
2007 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2008 if (res->vlan == vlan && res->port == (u8) port) {
2009 /* vlan found. update ref count */
2010 ++res->ref_count;
2011 return 0;
2012 }
2013 }
2014
146f3ef4
JM		 2015 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
2016 return -EINVAL;
4874080d 2017 res = kzalloc(sizeof(*res), GFP_KERNEL);
146f3ef4
JM		 2018 if (!res) {
2019 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
4874080d 2020 return -ENOMEM;
146f3ef4 2021 }
4874080d
JM		 2022 res->vlan = vlan;
2023 res->port = (u8) port;
2024 res->vlan_index = vlan_index;
2025 res->ref_count = 1;
2026 list_add_tail(&res->list,
2027 &tracker->slave_list[slave].res_list[RES_VLAN]);
ffe455ad
EE		 2028 return 0;
2029}
2030
4874080d
JM		 2031
2032static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2033 int port)
2034{
2035 struct mlx4_priv *priv = mlx4_priv(dev);
2036 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2037 struct list_head *vlan_list =
2038 &tracker->slave_list[slave].res_list[RES_VLAN];
2039 struct vlan_res *res, *tmp;
2040
2041 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2042 if (res->vlan == vlan && res->port == (u8) port) {
2043 if (!--res->ref_count) {
2044 list_del(&res->list);
146f3ef4
JM		 2045 mlx4_release_resource(dev, slave, RES_VLAN,
2046 1, port);
4874080d
JM		 2047 kfree(res);
2048 }
2049 break;
2050 }
2051 }
2052}
2053
2054static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
2055{
2056 struct mlx4_priv *priv = mlx4_priv(dev);
2057 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2058 struct list_head *vlan_list =
2059 &tracker->slave_list[slave].res_list[RES_VLAN];
2060 struct vlan_res *res, *tmp;
2061 int i;
2062
2063 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2064 list_del(&res->list);
2065 /* dereference the vlan the num times the slave referenced it */
2066 for (i = 0; i < res->ref_count; i++)
2067 __mlx4_unregister_vlan(dev, res->port, res->vlan);
146f3ef4 2068 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
4874080d
JM		 2069 kfree(res);
2070 }
2071}
2072
2073static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2c957ff2 2074 u64 in_param, u64 *out_param, int in_port)
4874080d 2075{
2c957ff2
JM		 2076 struct mlx4_priv *priv = mlx4_priv(dev);
2077 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
4874080d
JM		 2078 int err;
2079 u16 vlan;
2080 int vlan_index;
2c957ff2
JM		 2081 int port;
2082
2083 port = !in_port ? get_param_l(out_param) : in_port;
4874080d
JM		 2084
2085 if (!port || op != RES_OP_RESERVE_AND_MAP)
2086 return -EINVAL;
2087
449fc488
MB		 2088 port = mlx4_slave_convert_port(
2089 dev, slave, port);
2090
2091 if (port < 0)
2092 return -EINVAL;
2c957ff2
JM		 2093 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
2094 if (!in_port && port > 0 && port <= dev->caps.num_ports) {
2095 slave_state[slave].old_vlan_api = true;
2096 return 0;
2097 }
2098
4874080d
JM		 2099 vlan = (u16) in_param;
2100
2101 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
2102 if (!err) {
2103 set_param_l(out_param, (u32) vlan_index);
2104 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
2105 if (err)
2106 __mlx4_unregister_vlan(dev, port, vlan);
2107 }
2108 return err;
2109}
2110
ba062d52 2111static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
68230242 2112 u64 in_param, u64 *out_param, int port)
ba062d52
JM		 2113{
2114 u32 index;
2115 int err;
2116
2117 if (op != RES_OP_RESERVE)
2118 return -EINVAL;
2119
146f3ef4 2120 err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 2121 if (err)
2122 return err;
2123
146f3ef4
JM		 2124 err = __mlx4_counter_alloc(dev, &index);
2125 if (err) {
2126 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2127 return err;
2128 }
2129
68230242 2130 err = add_res_range(dev, slave, index, 1, RES_COUNTER, port);
146f3ef4 2131 if (err) {
ba062d52 2132 __mlx4_counter_free(dev, index);
146f3ef4
JM		 2133 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2134 } else {
ba062d52 2135 set_param_l(out_param, index);
146f3ef4 2136 }
ba062d52
JM		 2137
2138 return err;
2139}
2140
2141static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2142 u64 in_param, u64 *out_param)
2143{
2144 u32 xrcdn;
2145 int err;
2146
2147 if (op != RES_OP_RESERVE)
2148 return -EINVAL;
2149
2150 err = __mlx4_xrcd_alloc(dev, &xrcdn);
2151 if (err)
2152 return err;
2153
2154 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2155 if (err)
2156 __mlx4_xrcd_free(dev, xrcdn);
2157 else
2158 set_param_l(out_param, xrcdn);
2159
2160 return err;
2161}
2162
c82e9aa0
EC		 2163int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2164 struct mlx4_vhcr *vhcr,
2165 struct mlx4_cmd_mailbox *inbox,
2166 struct mlx4_cmd_mailbox *outbox,
2167 struct mlx4_cmd_info *cmd)
2168{
2169 int err;
2170 int alop = vhcr->op_modifier;
2171
acddd5dd 2172 switch (vhcr->in_modifier & 0xFF) {
c82e9aa0
EC		 2173 case RES_QP:
2174 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2175 vhcr->in_param, &vhcr->out_param);
2176 break;
2177
2178 case RES_MTT:
2179 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2180 vhcr->in_param, &vhcr->out_param);
2181 break;
2182
2183 case RES_MPT:
2184 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2185 vhcr->in_param, &vhcr->out_param);
2186 break;
2187
2188 case RES_CQ:
2189 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2190 vhcr->in_param, &vhcr->out_param);
2191 break;
2192
2193 case RES_SRQ:
2194 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2195 vhcr->in_param, &vhcr->out_param);
2196 break;
2197
2198 case RES_MAC:
2199 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2200 vhcr->in_param, &vhcr->out_param,
2201 (vhcr->in_modifier >> 8) & 0xFF);
c82e9aa0
EC		 2202 break;
2203
ffe455ad
EE		 2204 case RES_VLAN:
2205 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2206 vhcr->in_param, &vhcr->out_param,
2207 (vhcr->in_modifier >> 8) & 0xFF);
ffe455ad
EE		 2208 break;
2209
ba062d52
JM		 2210 case RES_COUNTER:
2211 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
68230242 2212 vhcr->in_param, &vhcr->out_param, 0);
ba062d52
JM		 2213 break;
2214
2215 case RES_XRCD:
2216 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2217 vhcr->in_param, &vhcr->out_param);
2218 break;
2219
c82e9aa0
EC		 2220 default:
2221 err = -EINVAL;
2222 break;
2223 }
2224
2225 return err;
2226}
2227
2228static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2229 u64 in_param)
2230{
2231 int err;
2232 int count;
2233 int base;
2234 int qpn;
2235
2236 switch (op) {
2237 case RES_OP_RESERVE:
2238 base = get_param_l(&in_param) & 0x7fffff;
2239 count = get_param_h(&in_param);
2240 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2241 if (err)
2242 break;
146f3ef4 2243 mlx4_release_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 2244 __mlx4_qp_release_range(dev, base, count);
2245 break;
2246 case RES_OP_MAP_ICM:
2247 qpn = get_param_l(&in_param) & 0x7fffff;
2248 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2249 NULL, 0);
2250 if (err)
2251 return err;
2252
54679e14 2253 if (!fw_reserved(dev, qpn))
c82e9aa0
EC		 2254 __mlx4_qp_free_icm(dev, qpn);
2255
2256 res_end_move(dev, slave, RES_QP, qpn);
2257
2258 if (valid_reserved(dev, slave, qpn))
2259 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2260 break;
2261 default:
2262 err = -EINVAL;
2263 break;
2264 }
2265 return err;
2266}
2267
2268static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2269 u64 in_param, u64 *out_param)
2270{
2271 int err = -EINVAL;
2272 int base;
2273 int order;
2274
2275 if (op != RES_OP_RESERVE_AND_MAP)
2276 return err;
2277
2278 base = get_param_l(&in_param);
2279 order = get_param_h(&in_param);
2280 err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
146f3ef4
JM		 2281 if (!err) {
2282 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 2283 __mlx4_free_mtt_range(dev, base, order);
146f3ef4 2284 }
c82e9aa0
EC		 2285 return err;
2286}
2287
2288static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2289 u64 in_param)
2290{
2291 int err = -EINVAL;
2292 int index;
2293 int id;
2294 struct res_mpt *mpt;
2295
2296 switch (op) {
2297 case RES_OP_RESERVE:
2298 index = get_param_l(&in_param);
2299 id = index & mpt_mask(dev);
2300 err = get_res(dev, slave, id, RES_MPT, &mpt);
2301 if (err)
2302 break;
2303 index = mpt->key;
2304 put_res(dev, slave, id, RES_MPT);
2305
2306 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2307 if (err)
2308 break;
146f3ef4 2309 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
b20e519a 2310 __mlx4_mpt_release(dev, index);
c82e9aa0
EC		 2311 break;
2312 case RES_OP_MAP_ICM:
2313 index = get_param_l(&in_param);
2314 id = index & mpt_mask(dev);
2315 err = mr_res_start_move_to(dev, slave, id,
2316 RES_MPT_RESERVED, &mpt);
2317 if (err)
2318 return err;
2319
b20e519a 2320 __mlx4_mpt_free_icm(dev, mpt->key);
c82e9aa0
EC		 2321 res_end_move(dev, slave, RES_MPT, id);
2322 return err;
2323 break;
2324 default:
2325 err = -EINVAL;
2326 break;
2327 }
2328 return err;
2329}
2330
2331static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2332 u64 in_param, u64 *out_param)
2333{
2334 int cqn;
2335 int err;
2336
2337 switch (op) {
2338 case RES_OP_RESERVE_AND_MAP:
2339 cqn = get_param_l(&in_param);
2340 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2341 if (err)
2342 break;
2343
146f3ef4 2344 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 2345 __mlx4_cq_free_icm(dev, cqn);
2346 break;
2347
2348 default:
2349 err = -EINVAL;
2350 break;
2351 }
2352
2353 return err;
2354}
2355
2356static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2357 u64 in_param, u64 *out_param)
2358{
2359 int srqn;
2360 int err;
2361
2362 switch (op) {
2363 case RES_OP_RESERVE_AND_MAP:
2364 srqn = get_param_l(&in_param);
2365 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2366 if (err)
2367 break;
2368
146f3ef4 2369 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 2370 __mlx4_srq_free_icm(dev, srqn);
2371 break;
2372
2373 default:
2374 err = -EINVAL;
2375 break;
2376 }
2377
2378 return err;
2379}
2380
2381static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2382 u64 in_param, u64 *out_param, int in_port)
c82e9aa0
EC		 2383{
2384 int port;
2385 int err = 0;
2386
2387 switch (op) {
2388 case RES_OP_RESERVE_AND_MAP:
acddd5dd 2389 port = !in_port ? get_param_l(out_param) : in_port;
449fc488
MB		 2390 port = mlx4_slave_convert_port(
2391 dev, slave, port);
2392
2393 if (port < 0)
2394 return -EINVAL;
c82e9aa0
EC		 2395 mac_del_from_slave(dev, slave, in_param, port);
2396 __mlx4_unregister_mac(dev, port, in_param);
2397 break;
2398 default:
2399 err = -EINVAL;
2400 break;
2401 }
2402
2403 return err;
2404
2405}
2406
ffe455ad 2407static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2408 u64 in_param, u64 *out_param, int port)
ffe455ad 2409{
2c957ff2
JM		 2410 struct mlx4_priv *priv = mlx4_priv(dev);
2411 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
4874080d
JM		 2412 int err = 0;
2413
449fc488
MB		 2414 port = mlx4_slave_convert_port(
2415 dev, slave, port);
2416
2417 if (port < 0)
2418 return -EINVAL;
4874080d
JM		 2419 switch (op) {
2420 case RES_OP_RESERVE_AND_MAP:
2c957ff2
JM		 2421 if (slave_state[slave].old_vlan_api)
2422 return 0;
4874080d
JM		 2423 if (!port)
2424 return -EINVAL;
2425 vlan_del_from_slave(dev, slave, in_param, port);
2426 __mlx4_unregister_vlan(dev, port, in_param);
2427 break;
2428 default:
2429 err = -EINVAL;
2430 break;
2431 }
2432
2433 return err;
ffe455ad
EE		 2434}
2435
ba062d52
JM		 2436static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2437 u64 in_param, u64 *out_param)
2438{
2439 int index;
2440 int err;
2441
2442 if (op != RES_OP_RESERVE)
2443 return -EINVAL;
2444
2445 index = get_param_l(&in_param);
9de92c60
EBE		 2446 if (index == MLX4_SINK_COUNTER_INDEX(dev))
2447 return 0;
2448
ba062d52
JM		 2449 err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2450 if (err)
2451 return err;
2452
2453 __mlx4_counter_free(dev, index);
146f3ef4 2454 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 2455
2456 return err;
2457}
2458
2459static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2460 u64 in_param, u64 *out_param)
2461{
2462 int xrcdn;
2463 int err;
2464
2465 if (op != RES_OP_RESERVE)
2466 return -EINVAL;
2467
2468 xrcdn = get_param_l(&in_param);
2469 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2470 if (err)
2471 return err;
2472
2473 __mlx4_xrcd_free(dev, xrcdn);
2474
2475 return err;
2476}
2477
c82e9aa0
EC		 2478int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2479 struct mlx4_vhcr *vhcr,
2480 struct mlx4_cmd_mailbox *inbox,
2481 struct mlx4_cmd_mailbox *outbox,
2482 struct mlx4_cmd_info *cmd)
2483{
2484 int err = -EINVAL;
2485 int alop = vhcr->op_modifier;
2486
acddd5dd 2487 switch (vhcr->in_modifier & 0xFF) {
c82e9aa0
EC		 2488 case RES_QP:
2489 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2490 vhcr->in_param);
2491 break;
2492
2493 case RES_MTT:
2494 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2495 vhcr->in_param, &vhcr->out_param);
2496 break;
2497
2498 case RES_MPT:
2499 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2500 vhcr->in_param);
2501 break;
2502
2503 case RES_CQ:
2504 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2505 vhcr->in_param, &vhcr->out_param);
2506 break;
2507
2508 case RES_SRQ:
2509 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2510 vhcr->in_param, &vhcr->out_param);
2511 break;
2512
2513 case RES_MAC:
2514 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2515 vhcr->in_param, &vhcr->out_param,
2516 (vhcr->in_modifier >> 8) & 0xFF);
c82e9aa0
EC		 2517 break;
2518
ffe455ad
EE		 2519 case RES_VLAN:
2520 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2521 vhcr->in_param, &vhcr->out_param,
2522 (vhcr->in_modifier >> 8) & 0xFF);
ffe455ad
EE		 2523 break;
2524
ba062d52
JM		 2525 case RES_COUNTER:
2526 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2527 vhcr->in_param, &vhcr->out_param);
2528 break;
2529
2530 case RES_XRCD:
2531 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2532 vhcr->in_param, &vhcr->out_param);
2533
c82e9aa0
EC		 2534 default:
2535 break;
2536 }
2537 return err;
2538}
2539
2540/* ugly but other choices are uglier */
2541static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2542{
2543 return (be32_to_cpu(mpt->flags) >> 9) & 1;
2544}
2545
2b8fb286 2546static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
c82e9aa0 2547{
2b8fb286 2548 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
c82e9aa0
EC		 2549}
2550
2551static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2552{
2553 return be32_to_cpu(mpt->mtt_sz);
2554}
2555
cc1ade94
SM		 2556static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2557{
2558 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2559}
2560
2561static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2562{
2563 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2564}
2565
2566static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2567{
2568 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2569}
2570
2571static int mr_is_region(struct mlx4_mpt_entry *mpt)
2572{
2573 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2574}
2575
2b8fb286 2576static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
c82e9aa0
EC		 2577{
2578 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2579}
2580
2b8fb286 2581static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
c82e9aa0
EC		 2582{
2583 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2584}
2585
2586static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2587{
2588 int page_shift = (qpc->log_page_size & 0x3f) + 12;
2589 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2590 int log_sq_sride = qpc->sq_size_stride & 7;
2591 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2592 int log_rq_stride = qpc->rq_size_stride & 7;
2593 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2594 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
5c5f3f0a
YH		 2595 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2596 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
c82e9aa0
EC		 2597 int sq_size;
2598 int rq_size;
2599 int total_pages;
2600 int total_mem;
2601 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2602
2603 sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2604 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2605 total_mem = sq_size + rq_size;
2606 total_pages =
2607 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
2608 page_shift);
2609
2610 return total_pages;
2611}
2612
c82e9aa0
EC		 2613static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2614 int size, struct res_mtt *mtt)
2615{
2b8fb286
MA		 2616 int res_start = mtt->com.res_id;
2617 int res_size = (1 << mtt->order);
c82e9aa0
EC		 2618
2619 if (start < res_start || start + size > res_start + res_size)
2620 return -EPERM;
2621 return 0;
2622}
2623
2624int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2625 struct mlx4_vhcr *vhcr,
2626 struct mlx4_cmd_mailbox *inbox,
2627 struct mlx4_cmd_mailbox *outbox,
2628 struct mlx4_cmd_info *cmd)
2629{
2630 int err;
2631 int index = vhcr->in_modifier;
2632 struct res_mtt *mtt;
2633 struct res_mpt *mpt;
2b8fb286 2634 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2635 int phys;
2636 int id;
cc1ade94
SM		 2637 u32 pd;
2638 int pd_slave;
c82e9aa0
EC		 2639
2640 id = index & mpt_mask(dev);
2641 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2642 if (err)
2643 return err;
2644
cc1ade94
SM		 2645 /* Disable memory windows for VFs. */
2646 if (!mr_is_region(inbox->buf)) {
2647 err = -EPERM;
2648 goto ex_abort;
2649 }
2650
2651 /* Make sure that the PD bits related to the slave id are zeros. */
2652 pd = mr_get_pd(inbox->buf);
2653 pd_slave = (pd >> 17) & 0x7f;
b332068c 2654 if (pd_slave != 0 && --pd_slave != slave) {
cc1ade94
SM		 2655 err = -EPERM;
2656 goto ex_abort;
2657 }
2658
2659 if (mr_is_fmr(inbox->buf)) {
2660 /* FMR and Bind Enable are forbidden in slave devices. */
2661 if (mr_is_bind_enabled(inbox->buf)) {
2662 err = -EPERM;
2663 goto ex_abort;
2664 }
2665 /* FMR and Memory Windows are also forbidden. */
2666 if (!mr_is_region(inbox->buf)) {
2667 err = -EPERM;
2668 goto ex_abort;
2669 }
2670 }
2671
c82e9aa0
EC		 2672 phys = mr_phys_mpt(inbox->buf);
2673 if (!phys) {
2b8fb286 2674 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2675 if (err)
2676 goto ex_abort;
2677
2678 err = check_mtt_range(dev, slave, mtt_base,
2679 mr_get_mtt_size(inbox->buf), mtt);
2680 if (err)
2681 goto ex_put;
2682
2683 mpt->mtt = mtt;
2684 }
2685
c82e9aa0
EC		 2686 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2687 if (err)
2688 goto ex_put;
2689
2690 if (!phys) {
2691 atomic_inc(&mtt->ref_count);
2692 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2693 }
2694
2695 res_end_move(dev, slave, RES_MPT, id);
2696 return 0;
2697
2698ex_put:
2699 if (!phys)
2700 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2701ex_abort:
2702 res_abort_move(dev, slave, RES_MPT, id);
2703
2704 return err;
2705}
2706
2707int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2708 struct mlx4_vhcr *vhcr,
2709 struct mlx4_cmd_mailbox *inbox,
2710 struct mlx4_cmd_mailbox *outbox,
2711 struct mlx4_cmd_info *cmd)
2712{
2713 int err;
2714 int index = vhcr->in_modifier;
2715 struct res_mpt *mpt;
2716 int id;
2717
2718 id = index & mpt_mask(dev);
2719 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2720 if (err)
2721 return err;
2722
2723 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2724 if (err)
2725 goto ex_abort;
2726
2727 if (mpt->mtt)
2728 atomic_dec(&mpt->mtt->ref_count);
2729
2730 res_end_move(dev, slave, RES_MPT, id);
2731 return 0;
2732
2733ex_abort:
2734 res_abort_move(dev, slave, RES_MPT, id);
2735
2736 return err;
2737}
2738
2739int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2740 struct mlx4_vhcr *vhcr,
2741 struct mlx4_cmd_mailbox *inbox,
2742 struct mlx4_cmd_mailbox *outbox,
2743 struct mlx4_cmd_info *cmd)
2744{
2745 int err;
2746 int index = vhcr->in_modifier;
2747 struct res_mpt *mpt;
2748 int id;
2749
2750 id = index & mpt_mask(dev);
2751 err = get_res(dev, slave, id, RES_MPT, &mpt);
2752 if (err)
2753 return err;
2754
e630664c
MB		 2755 if (mpt->com.from_state == RES_MPT_MAPPED) {
2756 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
2757 * that, the VF must read the MPT. But since the MPT entry memory is not
2758 * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
2759 * entry contents. To guarantee that the MPT cannot be changed, the driver
2760 * must perform HW2SW_MPT before this query and return the MPT entry to HW
2761 * ownership fofollowing the change. The change here allows the VF to
2762 * perform QUERY_MPT also when the entry is in SW ownership.
2763 */
2764 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
2765 &mlx4_priv(dev)->mr_table.dmpt_table,
2766 mpt->key, NULL);
2767
2768 if (NULL == mpt_entry || NULL == outbox->buf) {
2769 err = -EINVAL;
2770 goto out;
2771 }
2772
2773 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
2774
2775 err = 0;
2776 } else if (mpt->com.from_state == RES_MPT_HW) {
2777 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2778 } else {
c82e9aa0
EC		 2779 err = -EBUSY;
2780 goto out;
2781 }
2782
c82e9aa0
EC		 2783
2784out:
2785 put_res(dev, slave, id, RES_MPT);
2786 return err;
2787}
2788
2789static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2790{
2791 return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2792}
2793
2794static int qp_get_scqn(struct mlx4_qp_context *qpc)
2795{
2796 return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2797}
2798
2799static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2800{
2801 return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2802}
2803
54679e14
JM		 2804static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2805 struct mlx4_qp_context *context)
2806{
2807 u32 qpn = vhcr->in_modifier & 0xffffff;
2808 u32 qkey = 0;
2809
2810 if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2811 return;
2812
2813 /* adjust qkey in qp context */
2814 context->qkey = cpu_to_be32(qkey);
2815}
2816
e5dfbf9a
OG		 2817static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
2818 struct mlx4_qp_context *qpc,
2819 struct mlx4_cmd_mailbox *inbox);
2820
c82e9aa0
EC		 2821int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2822 struct mlx4_vhcr *vhcr,
2823 struct mlx4_cmd_mailbox *inbox,
2824 struct mlx4_cmd_mailbox *outbox,
2825 struct mlx4_cmd_info *cmd)
2826{
2827 int err;
2828 int qpn = vhcr->in_modifier & 0x7fffff;
2829 struct res_mtt *mtt;
2830 struct res_qp *qp;
2831 struct mlx4_qp_context *qpc = inbox->buf + 8;
2b8fb286 2832 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2833 int mtt_size = qp_get_mtt_size(qpc);
2834 struct res_cq *rcq;
2835 struct res_cq *scq;
2836 int rcqn = qp_get_rcqn(qpc);
2837 int scqn = qp_get_scqn(qpc);
2838 u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2839 int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2840 struct res_srq *srq;
2841 int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2842
e5dfbf9a
OG		 2843 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
2844 if (err)
2845 return err;
2846
c82e9aa0
EC		 2847 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2848 if (err)
2849 return err;
2850 qp->local_qpn = local_qpn;
b01978ca 2851 qp->sched_queue = 0;
f0f829bf
RE		 2852 qp->param3 = 0;
2853 qp->vlan_control = 0;
2854 qp->fvl_rx = 0;
2855 qp->pri_path_fl = 0;
2856 qp->vlan_index = 0;
2857 qp->feup = 0;
b01978ca 2858 qp->qpc_flags = be32_to_cpu(qpc->flags);
c82e9aa0 2859
2b8fb286 2860 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2861 if (err)
2862 goto ex_abort;
2863
2864 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2865 if (err)
2866 goto ex_put_mtt;
2867
c82e9aa0
EC		 2868 err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2869 if (err)
2870 goto ex_put_mtt;
2871
2872 if (scqn != rcqn) {
2873 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2874 if (err)
2875 goto ex_put_rcq;
2876 } else
2877 scq = rcq;
2878
2879 if (use_srq) {
2880 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2881 if (err)
2882 goto ex_put_scq;
2883 }
2884
54679e14
JM		 2885 adjust_proxy_tun_qkey(dev, vhcr, qpc);
2886 update_pkey_index(dev, slave, inbox);
c82e9aa0
EC		 2887 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2888 if (err)
2889 goto ex_put_srq;
2890 atomic_inc(&mtt->ref_count);
2891 qp->mtt = mtt;
2892 atomic_inc(&rcq->ref_count);
2893 qp->rcq = rcq;
2894 atomic_inc(&scq->ref_count);
2895 qp->scq = scq;
2896
2897 if (scqn != rcqn)
2898 put_res(dev, slave, scqn, RES_CQ);
2899
2900 if (use_srq) {
2901 atomic_inc(&srq->ref_count);
2902 put_res(dev, slave, srqn, RES_SRQ);
2903 qp->srq = srq;
2904 }
2905 put_res(dev, slave, rcqn, RES_CQ);
2b8fb286 2906 put_res(dev, slave, mtt_base, RES_MTT);
c82e9aa0
EC		 2907 res_end_move(dev, slave, RES_QP, qpn);
2908
2909 return 0;
2910
2911ex_put_srq:
2912 if (use_srq)
2913 put_res(dev, slave, srqn, RES_SRQ);
2914ex_put_scq:
2915 if (scqn != rcqn)
2916 put_res(dev, slave, scqn, RES_CQ);
2917ex_put_rcq:
2918 put_res(dev, slave, rcqn, RES_CQ);
2919ex_put_mtt:
2b8fb286 2920 put_res(dev, slave, mtt_base, RES_MTT);
c82e9aa0
EC		 2921ex_abort:
2922 res_abort_move(dev, slave, RES_QP, qpn);
2923
2924 return err;
2925}
2926
2b8fb286 2927static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
c82e9aa0
EC		 2928{
2929 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
2930}
2931
2932static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
2933{
2934 int log_eq_size = eqc->log_eq_size & 0x1f;
2935 int page_shift = (eqc->log_page_size & 0x3f) + 12;
2936
2937 if (log_eq_size + 5 < page_shift)
2938 return 1;
2939
2940 return 1 << (log_eq_size + 5 - page_shift);
2941}
2942
2b8fb286 2943static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
c82e9aa0
EC		 2944{
2945 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
2946}
2947
2948static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
2949{
2950 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
2951 int page_shift = (cqc->log_page_size & 0x3f) + 12;
2952
2953 if (log_cq_size + 5 < page_shift)
2954 return 1;
2955
2956 return 1 << (log_cq_size + 5 - page_shift);
2957}
2958
2959int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2960 struct mlx4_vhcr *vhcr,
2961 struct mlx4_cmd_mailbox *inbox,
2962 struct mlx4_cmd_mailbox *outbox,
2963 struct mlx4_cmd_info *cmd)
2964{
2965 int err;
2966 int eqn = vhcr->in_modifier;
2d3c7397 2967 int res_id = (slave << 10) | eqn;
c82e9aa0 2968 struct mlx4_eq_context *eqc = inbox->buf;
2b8fb286 2969 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2970 int mtt_size = eq_get_mtt_size(eqc);
2971 struct res_eq *eq;
2972 struct res_mtt *mtt;
2973
2974 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2975 if (err)
2976 return err;
2977 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
2978 if (err)
2979 goto out_add;
2980
2b8fb286 2981 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2982 if (err)
2983 goto out_move;
2984
2985 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2986 if (err)
2987 goto out_put;
2988
2989 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2990 if (err)
2991 goto out_put;
2992
2993 atomic_inc(&mtt->ref_count);
2994 eq->mtt = mtt;
2995 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2996 res_end_move(dev, slave, RES_EQ, res_id);
2997 return 0;
2998
2999out_put:
3000 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3001out_move:
3002 res_abort_move(dev, slave, RES_EQ, res_id);
3003out_add:
3004 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3005 return err;
3006}
3007
d475c95b
MB		 3008int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
3009 struct mlx4_vhcr *vhcr,
3010 struct mlx4_cmd_mailbox *inbox,
3011 struct mlx4_cmd_mailbox *outbox,
3012 struct mlx4_cmd_info *cmd)
3013{
3014 int err;
3015 u8 get = vhcr->op_modifier;
3016
3017 if (get != 1)
3018 return -EPERM;
3019
3020 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3021
3022 return err;
3023}
3024
c82e9aa0
EC		 3025static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
3026 int len, struct res_mtt **res)
3027{
3028 struct mlx4_priv *priv = mlx4_priv(dev);
3029 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3030 struct res_mtt *mtt;
3031 int err = -EINVAL;
3032
3033 spin_lock_irq(mlx4_tlock(dev));
3034 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
3035 com.list) {
3036 if (!check_mtt_range(dev, slave, start, len, mtt)) {
3037 *res = mtt;
3038 mtt->com.from_state = mtt->com.state;
3039 mtt->com.state = RES_MTT_BUSY;
3040 err = 0;
3041 break;
3042 }
3043 }
3044 spin_unlock_irq(mlx4_tlock(dev));
3045
3046 return err;
3047}
3048
54679e14 3049static int verify_qp_parameters(struct mlx4_dev *dev,
99ec41d0 3050 struct mlx4_vhcr *vhcr,
54679e14
JM		 3051 struct mlx4_cmd_mailbox *inbox,
3052 enum qp_transition transition, u8 slave)
3053{
3054 u32 qp_type;
99ec41d0 3055 u32 qpn;
54679e14
JM		 3056 struct mlx4_qp_context *qp_ctx;
3057 enum mlx4_qp_optpar optpar;
b6ffaeff
JM		 3058 int port;
3059 int num_gids;
54679e14
JM		 3060
3061 qp_ctx = inbox->buf + 8;
3062 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
3063 optpar = be32_to_cpu(*(__be32 *) inbox->buf);
3064
fc31e256 3065 if (slave != mlx4_master_func_num(dev)) {
53f33ae2 3066 qp_ctx->params2 &= ~MLX4_QP_BIT_FPP;
fc31e256
OG		 3067 /* setting QP rate-limit is disallowed for VFs */
3068 if (qp_ctx->rate_limit_params)
3069 return -EPERM;
3070 }
53f33ae2 3071
54679e14
JM		 3072 switch (qp_type) {
3073 case MLX4_QP_ST_RC:
b6ffaeff 3074 case MLX4_QP_ST_XRC:
54679e14
JM		 3075 case MLX4_QP_ST_UC:
3076 switch (transition) {
3077 case QP_TRANS_INIT2RTR:
3078 case QP_TRANS_RTR2RTS:
3079 case QP_TRANS_RTS2RTS:
3080 case QP_TRANS_SQD2SQD:
3081 case QP_TRANS_SQD2RTS:
3082 if (slave != mlx4_master_func_num(dev))
b6ffaeff
JM		 3083 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
3084 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3085 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
449fc488 3086 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 3087 else
3088 num_gids = 1;
3089 if (qp_ctx->pri_path.mgid_index >= num_gids)
54679e14 3090 return -EINVAL;
b6ffaeff
JM		 3091 }
3092 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3093 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
3094 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
449fc488 3095 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 3096 else
3097 num_gids = 1;
3098 if (qp_ctx->alt_path.mgid_index >= num_gids)
54679e14 3099 return -EINVAL;
b6ffaeff 3100 }
54679e14
JM		 3101 break;
3102 default:
3103 break;
3104 }
165cb465 3105 break;
54679e14 3106
165cb465
RD		 3107 case MLX4_QP_ST_MLX:
3108 qpn = vhcr->in_modifier & 0x7fffff;
3109 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3110 if (transition == QP_TRANS_INIT2RTR &&
3111 slave != mlx4_master_func_num(dev) &&
3112 mlx4_is_qp_reserved(dev, qpn) &&
3113 !mlx4_vf_smi_enabled(dev, slave, port)) {
3114 /* only enabled VFs may create MLX proxy QPs */
3115 mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
3116 __func__, slave, port);
3117 return -EPERM;
3118 }
54679e14 3119 break;
165cb465 3120
54679e14
JM		 3121 default:
3122 break;
3123 }
3124
3125 return 0;
3126}
3127
c82e9aa0
EC		 3128int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
3129 struct mlx4_vhcr *vhcr,
3130 struct mlx4_cmd_mailbox *inbox,
3131 struct mlx4_cmd_mailbox *outbox,
3132 struct mlx4_cmd_info *cmd)
3133{
3134 struct mlx4_mtt mtt;
3135 __be64 *page_list = inbox->buf;
3136 u64 *pg_list = (u64 *)page_list;
3137 int i;
3138 struct res_mtt *rmtt = NULL;
3139 int start = be64_to_cpu(page_list[0]);
3140 int npages = vhcr->in_modifier;
3141 int err;
3142
3143 err = get_containing_mtt(dev, slave, start, npages, &rmtt);
3144 if (err)
3145 return err;
3146
3147 /* Call the SW implementation of write_mtt:
3148 * - Prepare a dummy mtt struct
dbedd44e 3149 * - Translate inbox contents to simple addresses in host endianness */
2b8fb286
MA		 3150 mtt.offset = 0; /* TBD this is broken but I don't handle it since
3151 we don't really use it */
c82e9aa0
EC		 3152 mtt.order = 0;
3153 mtt.page_shift = 0;
3154 for (i = 0; i < npages; ++i)
3155 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
3156
3157 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
3158 ((u64 *)page_list + 2));
3159
3160 if (rmtt)
3161 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
3162
3163 return err;
3164}
3165
3166int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3167 struct mlx4_vhcr *vhcr,
3168 struct mlx4_cmd_mailbox *inbox,
3169 struct mlx4_cmd_mailbox *outbox,
3170 struct mlx4_cmd_info *cmd)
3171{
3172 int eqn = vhcr->in_modifier;
2d3c7397 3173 int res_id = eqn | (slave << 10);
c82e9aa0
EC		 3174 struct res_eq *eq;
3175 int err;
3176
3177 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
3178 if (err)
3179 return err;
3180
3181 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
3182 if (err)
3183 goto ex_abort;
3184
3185 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3186 if (err)
3187 goto ex_put;
3188
3189 atomic_dec(&eq->mtt->ref_count);
3190 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3191 res_end_move(dev, slave, RES_EQ, res_id);
3192 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3193
3194 return 0;
3195
3196ex_put:
3197 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3198ex_abort:
3199 res_abort_move(dev, slave, RES_EQ, res_id);
3200
3201 return err;
3202}
3203
3204int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
3205{
3206 struct mlx4_priv *priv = mlx4_priv(dev);
3207 struct mlx4_slave_event_eq_info *event_eq;
3208 struct mlx4_cmd_mailbox *mailbox;
3209 u32 in_modifier = 0;
3210 int err;
3211 int res_id;
3212 struct res_eq *req;
3213
3214 if (!priv->mfunc.master.slave_state)
3215 return -EINVAL;
3216
bffb023a
JM		 3217 /* check for slave valid, slave not PF, and slave active */
3218 if (slave < 0 || slave > dev->persist->num_vfs ||
3219 slave == dev->caps.function ||
3220 !priv->mfunc.master.slave_state[slave].active)
3221 return 0;
3222
803143fb 3223 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
c82e9aa0
EC		 3224
3225 /* Create the event only if the slave is registered */
803143fb 3226 if (event_eq->eqn < 0)
c82e9aa0
EC		 3227 return 0;
3228
3229 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
2d3c7397 3230 res_id = (slave << 10) | event_eq->eqn;
c82e9aa0
EC		 3231 err = get_res(dev, slave, res_id, RES_EQ, &req);
3232 if (err)
3233 goto unlock;
3234
3235 if (req->com.from_state != RES_EQ_HW) {
3236 err = -EINVAL;
3237 goto put;
3238 }
3239
3240 mailbox = mlx4_alloc_cmd_mailbox(dev);
3241 if (IS_ERR(mailbox)) {
3242 err = PTR_ERR(mailbox);
3243 goto put;
3244 }
3245
3246 if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3247 ++event_eq->token;
3248 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3249 }
3250
3251 memcpy(mailbox->buf, (u8 *) eqe, 28);
3252
2d3c7397 3253 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0x3ff) << 16);
c82e9aa0
EC		 3254
3255 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3256 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3257 MLX4_CMD_NATIVE);
3258
3259 put_res(dev, slave, res_id, RES_EQ);
3260 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3261 mlx4_free_cmd_mailbox(dev, mailbox);
3262 return err;
3263
3264put:
3265 put_res(dev, slave, res_id, RES_EQ);
3266
3267unlock:
3268 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3269 return err;
3270}
3271
3272int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3273 struct mlx4_vhcr *vhcr,
3274 struct mlx4_cmd_mailbox *inbox,
3275 struct mlx4_cmd_mailbox *outbox,
3276 struct mlx4_cmd_info *cmd)
3277{
3278 int eqn = vhcr->in_modifier;
2d3c7397 3279 int res_id = eqn | (slave << 10);
c82e9aa0
EC		 3280 struct res_eq *eq;
3281 int err;
3282
3283 err = get_res(dev, slave, res_id, RES_EQ, &eq);
3284 if (err)
3285 return err;
3286
3287 if (eq->com.from_state != RES_EQ_HW) {
3288 err = -EINVAL;
3289 goto ex_put;
3290 }
3291
3292 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3293
3294ex_put:
3295 put_res(dev, slave, res_id, RES_EQ);
3296 return err;
3297}
3298
3299int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3300 struct mlx4_vhcr *vhcr,
3301 struct mlx4_cmd_mailbox *inbox,
3302 struct mlx4_cmd_mailbox *outbox,
3303 struct mlx4_cmd_info *cmd)
3304{
3305 int err;
3306 int cqn = vhcr->in_modifier;
3307 struct mlx4_cq_context *cqc = inbox->buf;
2b8fb286 3308 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
c1c52db1 3309 struct res_cq *cq = NULL;
c82e9aa0
EC		 3310 struct res_mtt *mtt;
3311
3312 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3313 if (err)
3314 return err;
2b8fb286 3315 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3316 if (err)
3317 goto out_move;
3318 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3319 if (err)
3320 goto out_put;
3321 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3322 if (err)
3323 goto out_put;
3324 atomic_inc(&mtt->ref_count);
3325 cq->mtt = mtt;
3326 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3327 res_end_move(dev, slave, RES_CQ, cqn);
3328 return 0;
3329
3330out_put:
3331 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3332out_move:
3333 res_abort_move(dev, slave, RES_CQ, cqn);
3334 return err;
3335}
3336
3337int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3338 struct mlx4_vhcr *vhcr,
3339 struct mlx4_cmd_mailbox *inbox,
3340 struct mlx4_cmd_mailbox *outbox,
3341 struct mlx4_cmd_info *cmd)
3342{
3343 int err;
3344 int cqn = vhcr->in_modifier;
c1c52db1 3345 struct res_cq *cq = NULL;
c82e9aa0
EC		 3346
3347 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3348 if (err)
3349 return err;
3350 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3351 if (err)
3352 goto out_move;
3353 atomic_dec(&cq->mtt->ref_count);
3354 res_end_move(dev, slave, RES_CQ, cqn);
3355 return 0;
3356
3357out_move:
3358 res_abort_move(dev, slave, RES_CQ, cqn);
3359 return err;
3360}
3361
3362int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3363 struct mlx4_vhcr *vhcr,
3364 struct mlx4_cmd_mailbox *inbox,
3365 struct mlx4_cmd_mailbox *outbox,
3366 struct mlx4_cmd_info *cmd)
3367{
3368 int cqn = vhcr->in_modifier;
3369 struct res_cq *cq;
3370 int err;
3371
3372 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3373 if (err)
3374 return err;
3375
3376 if (cq->com.from_state != RES_CQ_HW)
3377 goto ex_put;
3378
3379 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3380ex_put:
3381 put_res(dev, slave, cqn, RES_CQ);
3382
3383 return err;
3384}
3385
3386static int handle_resize(struct mlx4_dev *dev, int slave,
3387 struct mlx4_vhcr *vhcr,
3388 struct mlx4_cmd_mailbox *inbox,
3389 struct mlx4_cmd_mailbox *outbox,
3390 struct mlx4_cmd_info *cmd,
3391 struct res_cq *cq)
3392{
3393 int err;
3394 struct res_mtt *orig_mtt;
3395 struct res_mtt *mtt;
3396 struct mlx4_cq_context *cqc = inbox->buf;
2b8fb286 3397 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3398
3399 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3400 if (err)
3401 return err;
3402
3403 if (orig_mtt != cq->mtt) {
3404 err = -EINVAL;
3405 goto ex_put;
3406 }
3407
2b8fb286 3408 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3409 if (err)
3410 goto ex_put;
3411
3412 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3413 if (err)
3414 goto ex_put1;
3415 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3416 if (err)
3417 goto ex_put1;
3418 atomic_dec(&orig_mtt->ref_count);
3419 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3420 atomic_inc(&mtt->ref_count);
3421 cq->mtt = mtt;
3422 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3423 return 0;
3424
3425ex_put1:
3426 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3427ex_put:
3428 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3429
3430 return err;
3431
3432}
3433
3434int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3435 struct mlx4_vhcr *vhcr,
3436 struct mlx4_cmd_mailbox *inbox,
3437 struct mlx4_cmd_mailbox *outbox,
3438 struct mlx4_cmd_info *cmd)
3439{
3440 int cqn = vhcr->in_modifier;
3441 struct res_cq *cq;
3442 int err;
3443
3444 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3445 if (err)
3446 return err;
3447
3448 if (cq->com.from_state != RES_CQ_HW)
3449 goto ex_put;
3450
3451 if (vhcr->op_modifier == 0) {
3452 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
dcf353b1 3453 goto ex_put;
c82e9aa0
EC		 3454 }
3455
3456 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3457ex_put:
3458 put_res(dev, slave, cqn, RES_CQ);
3459
3460 return err;
3461}
3462
c82e9aa0
EC		 3463static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3464{
3465 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3466 int log_rq_stride = srqc->logstride & 7;
3467 int page_shift = (srqc->log_page_size & 0x3f) + 12;
3468
3469 if (log_srq_size + log_rq_stride + 4 < page_shift)
3470 return 1;
3471
3472 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3473}
3474
3475int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3476 struct mlx4_vhcr *vhcr,
3477 struct mlx4_cmd_mailbox *inbox,
3478 struct mlx4_cmd_mailbox *outbox,
3479 struct mlx4_cmd_info *cmd)
3480{
3481 int err;
3482 int srqn = vhcr->in_modifier;
3483 struct res_mtt *mtt;
c1c52db1 3484 struct res_srq *srq = NULL;
c82e9aa0 3485 struct mlx4_srq_context *srqc = inbox->buf;
2b8fb286 3486 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3487
3488 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3489 return -EINVAL;
3490
3491 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3492 if (err)
3493 return err;
2b8fb286 3494 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3495 if (err)
3496 goto ex_abort;
3497 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3498 mtt);
3499 if (err)
3500 goto ex_put_mtt;
3501
c82e9aa0
EC		 3502 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3503 if (err)
3504 goto ex_put_mtt;
3505
3506 atomic_inc(&mtt->ref_count);
3507 srq->mtt = mtt;
3508 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3509 res_end_move(dev, slave, RES_SRQ, srqn);
3510 return 0;
3511
3512ex_put_mtt:
3513 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3514ex_abort:
3515 res_abort_move(dev, slave, RES_SRQ, srqn);
3516
3517 return err;
3518}
3519
3520int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3521 struct mlx4_vhcr *vhcr,
3522 struct mlx4_cmd_mailbox *inbox,
3523 struct mlx4_cmd_mailbox *outbox,
3524 struct mlx4_cmd_info *cmd)
3525{
3526 int err;
3527 int srqn = vhcr->in_modifier;
c1c52db1 3528 struct res_srq *srq = NULL;
c82e9aa0
EC		 3529
3530 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3531 if (err)
3532 return err;
3533 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3534 if (err)
3535 goto ex_abort;
3536 atomic_dec(&srq->mtt->ref_count);
3537 if (srq->cq)
3538 atomic_dec(&srq->cq->ref_count);
3539 res_end_move(dev, slave, RES_SRQ, srqn);
3540
3541 return 0;
3542
3543ex_abort:
3544 res_abort_move(dev, slave, RES_SRQ, srqn);
3545
3546 return err;
3547}
3548
3549int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3550 struct mlx4_vhcr *vhcr,
3551 struct mlx4_cmd_mailbox *inbox,
3552 struct mlx4_cmd_mailbox *outbox,
3553 struct mlx4_cmd_info *cmd)
3554{
3555 int err;
3556 int srqn = vhcr->in_modifier;
3557 struct res_srq *srq;
3558
3559 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3560 if (err)
3561 return err;
3562 if (srq->com.from_state != RES_SRQ_HW) {
3563 err = -EBUSY;
3564 goto out;
3565 }
3566 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3567out:
3568 put_res(dev, slave, srqn, RES_SRQ);
3569 return err;
3570}
3571
3572int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3573 struct mlx4_vhcr *vhcr,
3574 struct mlx4_cmd_mailbox *inbox,
3575 struct mlx4_cmd_mailbox *outbox,
3576 struct mlx4_cmd_info *cmd)
3577{
3578 int err;
3579 int srqn = vhcr->in_modifier;
3580 struct res_srq *srq;
3581
3582 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3583 if (err)
3584 return err;
3585
3586 if (srq->com.from_state != RES_SRQ_HW) {
3587 err = -EBUSY;
3588 goto out;
3589 }
3590
3591 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3592out:
3593 put_res(dev, slave, srqn, RES_SRQ);
3594 return err;
3595}
3596
3597int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3598 struct mlx4_vhcr *vhcr,
3599 struct mlx4_cmd_mailbox *inbox,
3600 struct mlx4_cmd_mailbox *outbox,
3601 struct mlx4_cmd_info *cmd)
3602{
3603 int err;
3604 int qpn = vhcr->in_modifier & 0x7fffff;
3605 struct res_qp *qp;
3606
3607 err = get_res(dev, slave, qpn, RES_QP, &qp);
3608 if (err)
3609 return err;
3610 if (qp->com.from_state != RES_QP_HW) {
3611 err = -EBUSY;
3612 goto out;
3613 }
3614
3615 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3616out:
3617 put_res(dev, slave, qpn, RES_QP);
3618 return err;
3619}
3620
54679e14
JM		 3621int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3622 struct mlx4_vhcr *vhcr,
3623 struct mlx4_cmd_mailbox *inbox,
3624 struct mlx4_cmd_mailbox *outbox,
3625 struct mlx4_cmd_info *cmd)
3626{
3627 struct mlx4_qp_context *context = inbox->buf + 8;
3628 adjust_proxy_tun_qkey(dev, vhcr, context);
3629 update_pkey_index(dev, slave, inbox);
3630 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3631}
3632
449fc488
MB		 3633static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3634 struct mlx4_qp_context *qpc,
3635 struct mlx4_cmd_mailbox *inbox)
3636{
3637 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3638 u8 pri_sched_queue;
3639 int port = mlx4_slave_convert_port(
3640 dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3641
3642 if (port < 0)
3643 return -EINVAL;
3644
3645 pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3646 ((port & 1) << 6);
3647
f40e99e9
OG		 3648 if (optpar & (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | MLX4_QP_OPTPAR_SCHED_QUEUE) ||
3649 qpc->pri_path.sched_queue || mlx4_is_eth(dev, port + 1)) {
449fc488
MB		 3650 qpc->pri_path.sched_queue = pri_sched_queue;
3651 }
3652
3653 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3654 port = mlx4_slave_convert_port(
3655 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3656 + 1) - 1;
3657 if (port < 0)
3658 return -EINVAL;
3659 qpc->alt_path.sched_queue =
3660 (qpc->alt_path.sched_queue & ~(1 << 6)) |
3661 (port & 1) << 6;
3662 }
3663 return 0;
3664}
3665
2f5bb473
JM		 3666static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3667 struct mlx4_qp_context *qpc,
3668 struct mlx4_cmd_mailbox *inbox)
3669{
3670 u64 mac;
3671 int port;
3672 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3673 u8 sched = *(u8 *)(inbox->buf + 64);
3674 u8 smac_ix;
3675
3676 port = (sched >> 6 & 1) + 1;
3677 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3678 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3679 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3680 return -ENOENT;
3681 }
3682 return 0;
3683}
3684
c82e9aa0
EC		 3685int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3686 struct mlx4_vhcr *vhcr,
3687 struct mlx4_cmd_mailbox *inbox,
3688 struct mlx4_cmd_mailbox *outbox,
3689 struct mlx4_cmd_info *cmd)
3690{
54679e14 3691 int err;
c82e9aa0 3692 struct mlx4_qp_context *qpc = inbox->buf + 8;
b01978ca
JM		 3693 int qpn = vhcr->in_modifier & 0x7fffff;
3694 struct res_qp *qp;
3695 u8 orig_sched_queue;
f0f829bf
RE		 3696 __be32 orig_param3 = qpc->param3;
3697 u8 orig_vlan_control = qpc->pri_path.vlan_control;
3698 u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3699 u8 orig_pri_path_fl = qpc->pri_path.fl;
3700 u8 orig_vlan_index = qpc->pri_path.vlan_index;
3701 u8 orig_feup = qpc->pri_path.feup;
c82e9aa0 3702
449fc488
MB		 3703 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3704 if (err)
3705 return err;
99ec41d0 3706 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
54679e14
JM		 3707 if (err)
3708 return err;
3709
2f5bb473
JM		 3710 if (roce_verify_mac(dev, slave, qpc, inbox))
3711 return -EINVAL;
3712
54679e14
JM		 3713 update_pkey_index(dev, slave, inbox);
3714 update_gid(dev, inbox, (u8)slave);
3715 adjust_proxy_tun_qkey(dev, vhcr, qpc);
b01978ca
JM		 3716 orig_sched_queue = qpc->pri_path.sched_queue;
3717 err = update_vport_qp_param(dev, inbox, slave, qpn);
3f7fb021
RE		 3718 if (err)
3719 return err;
54679e14 3720
b01978ca
JM		 3721 err = get_res(dev, slave, qpn, RES_QP, &qp);
3722 if (err)
3723 return err;
3724 if (qp->com.from_state != RES_QP_HW) {
3725 err = -EBUSY;
3726 goto out;
3727 }
3728
3729 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3730out:
3731 /* if no error, save sched queue value passed in by VF. This is
3732 * essentially the QOS value provided by the VF. This will be useful
3733 * if we allow dynamic changes from VST back to VGT
3734 */
f0f829bf 3735 if (!err) {
b01978ca 3736 qp->sched_queue = orig_sched_queue;
f0f829bf
RE		 3737 qp->param3 = orig_param3;
3738 qp->vlan_control = orig_vlan_control;
3739 qp->fvl_rx = orig_fvl_rx;
3740 qp->pri_path_fl = orig_pri_path_fl;
3741 qp->vlan_index = orig_vlan_index;
3742 qp->feup = orig_feup;
3743 }
b01978ca
JM		 3744 put_res(dev, slave, qpn, RES_QP);
3745 return err;
54679e14
JM		 3746}
3747
3748int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3749 struct mlx4_vhcr *vhcr,
3750 struct mlx4_cmd_mailbox *inbox,
3751 struct mlx4_cmd_mailbox *outbox,
3752 struct mlx4_cmd_info *cmd)
3753{
3754 int err;
3755 struct mlx4_qp_context *context = inbox->buf + 8;
3756
449fc488
MB		 3757 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3758 if (err)
3759 return err;
99ec41d0 3760 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
54679e14
JM		 3761 if (err)
3762 return err;
3763
3764 update_pkey_index(dev, slave, inbox);
3765 update_gid(dev, inbox, (u8)slave);
3766 adjust_proxy_tun_qkey(dev, vhcr, context);
3767 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3768}
3769
3770int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3771 struct mlx4_vhcr *vhcr,
3772 struct mlx4_cmd_mailbox *inbox,
3773 struct mlx4_cmd_mailbox *outbox,
3774 struct mlx4_cmd_info *cmd)
3775{
3776 int err;
3777 struct mlx4_qp_context *context = inbox->buf + 8;
3778
449fc488
MB		 3779 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3780 if (err)
3781 return err;
99ec41d0 3782 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
54679e14
JM		 3783 if (err)
3784 return err;
3785
3786 update_pkey_index(dev, slave, inbox);
3787 update_gid(dev, inbox, (u8)slave);
3788 adjust_proxy_tun_qkey(dev, vhcr, context);
3789 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3790}
3791
3792
3793int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3794 struct mlx4_vhcr *vhcr,
3795 struct mlx4_cmd_mailbox *inbox,
3796 struct mlx4_cmd_mailbox *outbox,
3797 struct mlx4_cmd_info *cmd)
3798{
3799 struct mlx4_qp_context *context = inbox->buf + 8;
449fc488
MB		 3800 int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3801 if (err)
3802 return err;
54679e14
JM		 3803 adjust_proxy_tun_qkey(dev, vhcr, context);
3804 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3805}
3806
3807int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3808 struct mlx4_vhcr *vhcr,
3809 struct mlx4_cmd_mailbox *inbox,
3810 struct mlx4_cmd_mailbox *outbox,
3811 struct mlx4_cmd_info *cmd)
3812{
3813 int err;
3814 struct mlx4_qp_context *context = inbox->buf + 8;
3815
449fc488
MB		 3816 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3817 if (err)
3818 return err;
99ec41d0 3819 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
54679e14
JM		 3820 if (err)
3821 return err;
3822
3823 adjust_proxy_tun_qkey(dev, vhcr, context);
3824 update_gid(dev, inbox, (u8)slave);
3825 update_pkey_index(dev, slave, inbox);
3826 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3827}
3828
3829int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3830 struct mlx4_vhcr *vhcr,
3831 struct mlx4_cmd_mailbox *inbox,
3832 struct mlx4_cmd_mailbox *outbox,
3833 struct mlx4_cmd_info *cmd)
3834{
3835 int err;
3836 struct mlx4_qp_context *context = inbox->buf + 8;
3837
449fc488
MB		 3838 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3839 if (err)
3840 return err;
99ec41d0 3841 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
54679e14
JM		 3842 if (err)
3843 return err;
c82e9aa0 3844
54679e14
JM		 3845 adjust_proxy_tun_qkey(dev, vhcr, context);
3846 update_gid(dev, inbox, (u8)slave);
3847 update_pkey_index(dev, slave, inbox);
c82e9aa0
EC		 3848 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3849}
3850
3851int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3852 struct mlx4_vhcr *vhcr,
3853 struct mlx4_cmd_mailbox *inbox,
3854 struct mlx4_cmd_mailbox *outbox,
3855 struct mlx4_cmd_info *cmd)
3856{
3857 int err;
3858 int qpn = vhcr->in_modifier & 0x7fffff;
3859 struct res_qp *qp;
3860
3861 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3862 if (err)
3863 return err;
3864 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3865 if (err)
3866 goto ex_abort;
3867
3868 atomic_dec(&qp->mtt->ref_count);
3869 atomic_dec(&qp->rcq->ref_count);
3870 atomic_dec(&qp->scq->ref_count);
3871 if (qp->srq)
3872 atomic_dec(&qp->srq->ref_count);
3873 res_end_move(dev, slave, RES_QP, qpn);
3874 return 0;
3875
3876ex_abort:
3877 res_abort_move(dev, slave, RES_QP, qpn);
3878
3879 return err;
3880}
3881
3882static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3883 struct res_qp *rqp, u8 *gid)
3884{
3885 struct res_gid *res;
3886
3887 list_for_each_entry(res, &rqp->mcg_list, list) {
3888 if (!memcmp(res->gid, gid, 16))
3889 return res;
3890 }
3891 return NULL;
3892}
3893
3894static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
9f5b6c63 3895 u8 *gid, enum mlx4_protocol prot,
fab1e24a 3896 enum mlx4_steer_type steer, u64 reg_id)
c82e9aa0
EC		 3897{
3898 struct res_gid *res;
3899 int err;
3900
3901 res = kzalloc(sizeof *res, GFP_KERNEL);
3902 if (!res)
3903 return -ENOMEM;
3904
3905 spin_lock_irq(&rqp->mcg_spl);
3906 if (find_gid(dev, slave, rqp, gid)) {
3907 kfree(res);
3908 err = -EEXIST;
3909 } else {
3910 memcpy(res->gid, gid, 16);
3911 res->prot = prot;
9f5b6c63 3912 res->steer = steer;
fab1e24a 3913 res->reg_id = reg_id;
c82e9aa0
EC		 3914 list_add_tail(&res->list, &rqp->mcg_list);
3915 err = 0;
3916 }
3917 spin_unlock_irq(&rqp->mcg_spl);
3918
3919 return err;
3920}
3921
3922static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
9f5b6c63 3923 u8 *gid, enum mlx4_protocol prot,
fab1e24a 3924 enum mlx4_steer_type steer, u64 *reg_id)
c82e9aa0
EC		 3925{
3926 struct res_gid *res;
3927 int err;
3928
3929 spin_lock_irq(&rqp->mcg_spl);
3930 res = find_gid(dev, slave, rqp, gid);
9f5b6c63 3931 if (!res || res->prot != prot || res->steer != steer)
c82e9aa0
EC		 3932 err = -EINVAL;
3933 else {
fab1e24a 3934 *reg_id = res->reg_id;
c82e9aa0
EC		 3935 list_del(&res->list);
3936 kfree(res);
3937 err = 0;
3938 }
3939 spin_unlock_irq(&rqp->mcg_spl);
3940
3941 return err;
3942}
3943
449fc488
MB		 3944static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
3945 u8 gid[16], int block_loopback, enum mlx4_protocol prot,
fab1e24a
HHZ		 3946 enum mlx4_steer_type type, u64 *reg_id)
3947{
3948 switch (dev->caps.steering_mode) {
449fc488
MB		 3949 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
3950 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
3951 if (port < 0)
3952 return port;
3953 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
fab1e24a
HHZ		 3954 block_loopback, prot,
3955 reg_id);
449fc488 3956 }
fab1e24a 3957 case MLX4_STEERING_MODE_B0:
449fc488
MB		 3958 if (prot == MLX4_PROT_ETH) {
3959 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
3960 if (port < 0)
3961 return port;
3962 gid[5] = port;
3963 }
fab1e24a
HHZ		 3964 return mlx4_qp_attach_common(dev, qp, gid,
3965 block_loopback, prot, type);
3966 default:
3967 return -EINVAL;
3968 }
3969}
3970
449fc488
MB		 3971static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
3972 u8 gid[16], enum mlx4_protocol prot,
3973 enum mlx4_steer_type type, u64 reg_id)
fab1e24a
HHZ		 3974{
3975 switch (dev->caps.steering_mode) {
3976 case MLX4_STEERING_MODE_DEVICE_MANAGED:
3977 return mlx4_flow_detach(dev, reg_id);
3978 case MLX4_STEERING_MODE_B0:
3979 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
3980 default:
3981 return -EINVAL;
3982 }
3983}
3984
531d9014
JM		 3985static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
3986 u8 *gid, enum mlx4_protocol prot)
3987{
3988 int real_port;
3989
3990 if (prot != MLX4_PROT_ETH)
3991 return 0;
3992
3993 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
3994 dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
3995 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
3996 if (real_port < 0)
3997 return -EINVAL;
3998 gid[5] = real_port;
3999 }
4000
4001 return 0;
4002}
4003
c82e9aa0
EC		 4004int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4005 struct mlx4_vhcr *vhcr,
4006 struct mlx4_cmd_mailbox *inbox,
4007 struct mlx4_cmd_mailbox *outbox,
4008 struct mlx4_cmd_info *cmd)
4009{
4010 struct mlx4_qp qp; /* dummy for calling attach/detach */
4011 u8 *gid = inbox->buf;
4012 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
162344ed 4013 int err;
c82e9aa0
EC		 4014 int qpn;
4015 struct res_qp *rqp;
fab1e24a 4016 u64 reg_id = 0;
c82e9aa0
EC		 4017 int attach = vhcr->op_modifier;
4018 int block_loopback = vhcr->in_modifier >> 31;
4019 u8 steer_type_mask = 2;
75c6062c 4020 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
c82e9aa0
EC		 4021
4022 qpn = vhcr->in_modifier & 0xffffff;
4023 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4024 if (err)
4025 return err;
4026
4027 qp.qpn = qpn;
4028 if (attach) {
449fc488 4029 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
fab1e24a
HHZ		 4030 type, &reg_id);
4031 if (err) {
4032 pr_err("Fail to attach rule to qp 0x%x\n", qpn);
c82e9aa0 4033 goto ex_put;
fab1e24a
HHZ		 4034 }
4035 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
c82e9aa0 4036 if (err)
fab1e24a 4037 goto ex_detach;
c82e9aa0 4038 } else {
531d9014
JM		 4039 err = mlx4_adjust_port(dev, slave, gid, prot);
4040 if (err)
4041 goto ex_put;
4042
fab1e24a 4043 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
c82e9aa0
EC		 4044 if (err)
4045 goto ex_put;
c82e9aa0 4046
fab1e24a
HHZ		 4047 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
4048 if (err)
4049 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
4050 qpn, reg_id);
4051 }
c82e9aa0 4052 put_res(dev, slave, qpn, RES_QP);
fab1e24a 4053 return err;
c82e9aa0 4054
fab1e24a
HHZ		 4055ex_detach:
4056 qp_detach(dev, &qp, gid, prot, type, reg_id);
c82e9aa0
EC		 4057ex_put:
4058 put_res(dev, slave, qpn, RES_QP);
c82e9aa0
EC		 4059 return err;
4060}
4061
7fb40f87
HHZ		 4062/*
4063 * MAC validation for Flow Steering rules.
4064 * VF can attach rules only with a mac address which is assigned to it.
4065 */
4066static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
4067 struct list_head *rlist)
4068{
4069 struct mac_res *res, *tmp;
4070 __be64 be_mac;
4071
4072 /* make sure it isn't multicast or broadcast mac*/
4073 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
4074 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4075 list_for_each_entry_safe(res, tmp, rlist, list) {
4076 be_mac = cpu_to_be64(res->mac << 16);
c0623e58 4077 if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
7fb40f87
HHZ		 4078 return 0;
4079 }
4080 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
4081 eth_header->eth.dst_mac, slave);
4082 return -EINVAL;
4083 }
4084 return 0;
4085}
4086
48564135
MB		 4087static void handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
4088 struct _rule_hw *eth_header)
4089{
4090 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
4091 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4092 struct mlx4_net_trans_rule_hw_eth *eth =
4093 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
4094 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
4095 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
4096 next_rule->rsvd == 0;
4097
4098 if (last_rule)
4099 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
4100 }
4101}
4102
7fb40f87
HHZ		 4103/*
4104 * In case of missing eth header, append eth header with a MAC address
4105 * assigned to the VF.
4106 */
4107static int add_eth_header(struct mlx4_dev *dev, int slave,
4108 struct mlx4_cmd_mailbox *inbox,
4109 struct list_head *rlist, int header_id)
4110{
4111 struct mac_res *res, *tmp;
4112 u8 port;
4113 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4114 struct mlx4_net_trans_rule_hw_eth *eth_header;
4115 struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
4116 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
4117 __be64 be_mac = 0;
4118 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
4119
4120 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
015465f8 4121 port = ctrl->port;
7fb40f87
HHZ		 4122 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
4123
4124 /* Clear a space in the inbox for eth header */
4125 switch (header_id) {
4126 case MLX4_NET_TRANS_RULE_ID_IPV4:
4127 ip_header =
4128 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
4129 memmove(ip_header, eth_header,
4130 sizeof(*ip_header) + sizeof(*l4_header));
4131 break;
4132 case MLX4_NET_TRANS_RULE_ID_TCP:
4133 case MLX4_NET_TRANS_RULE_ID_UDP:
4134 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
4135 (eth_header + 1);
4136 memmove(l4_header, eth_header, sizeof(*l4_header));
4137 break;
4138 default:
4139 return -EINVAL;
4140 }
4141 list_for_each_entry_safe(res, tmp, rlist, list) {
4142 if (port == res->port) {
4143 be_mac = cpu_to_be64(res->mac << 16);
4144 break;
4145 }
4146 }
4147 if (!be_mac) {
1a91de28 4148 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
7fb40f87
HHZ		 4149 port);
4150 return -EINVAL;
4151 }
4152
4153 memset(eth_header, 0, sizeof(*eth_header));
4154 eth_header->size = sizeof(*eth_header) >> 2;
4155 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
4156 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
4157 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
4158
4159 return 0;
4160
4161}
4162
ce8d9e0d
MB		 4163#define MLX4_UPD_QP_PATH_MASK_SUPPORTED (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)
4164int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
4165 struct mlx4_vhcr *vhcr,
4166 struct mlx4_cmd_mailbox *inbox,
4167 struct mlx4_cmd_mailbox *outbox,
4168 struct mlx4_cmd_info *cmd_info)
4169{
4170 int err;
4171 u32 qpn = vhcr->in_modifier & 0xffffff;
4172 struct res_qp *rqp;
4173 u64 mac;
4174 unsigned port;
4175 u64 pri_addr_path_mask;
4176 struct mlx4_update_qp_context *cmd;
4177 int smac_index;
4178
4179 cmd = (struct mlx4_update_qp_context *)inbox->buf;
4180
4181 pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
4182 if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
4183 (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
4184 return -EPERM;
4185
4186 /* Just change the smac for the QP */
4187 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4188 if (err) {
4189 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
4190 return err;
4191 }
4192
4193 port = (rqp->sched_queue >> 6 & 1) + 1;
b7834758
MB		 4194
4195 if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
4196 smac_index = cmd->qp_context.pri_path.grh_mylmc;
4197 err = mac_find_smac_ix_in_slave(dev, slave, port,
4198 smac_index, &mac);
4199
4200 if (err) {
4201 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
4202 qpn, smac_index);
4203 goto err_mac;
4204 }
ce8d9e0d
MB		 4205 }
4206
4207 err = mlx4_cmd(dev, inbox->dma,
4208 vhcr->in_modifier, 0,
4209 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
4210 MLX4_CMD_NATIVE);
4211 if (err) {
4212 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
4213 goto err_mac;
4214 }
4215
4216err_mac:
4217 put_res(dev, slave, qpn, RES_QP);
4218 return err;
4219}
4220
8fcfb4db
HHZ		 4221int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4222 struct mlx4_vhcr *vhcr,
4223 struct mlx4_cmd_mailbox *inbox,
4224 struct mlx4_cmd_mailbox *outbox,
4225 struct mlx4_cmd_info *cmd)
4226{
7fb40f87
HHZ		 4227
4228 struct mlx4_priv *priv = mlx4_priv(dev);
4229 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4230 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
1b9c6b06 4231 int err;
a9c01e7a 4232 int qpn;
2c473ae7 4233 struct res_qp *rqp;
7fb40f87
HHZ		 4234 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4235 struct _rule_hw *rule_header;
4236 int header_id;
1b9c6b06 4237
0ff1fb65
HHZ		 4238 if (dev->caps.steering_mode !=
4239 MLX4_STEERING_MODE_DEVICE_MANAGED)
4240 return -EOPNOTSUPP;
1b9c6b06 4241
7fb40f87 4242 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
449fc488
MB		 4243 ctrl->port = mlx4_slave_convert_port(dev, slave, ctrl->port);
4244 if (ctrl->port <= 0)
4245 return -EINVAL;
a9c01e7a 4246 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
2c473ae7 4247 err = get_res(dev, slave, qpn, RES_QP, &rqp);
a9c01e7a 4248 if (err) {
1a91de28 4249 pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
a9c01e7a
HHZ		 4250 return err;
4251 }
7fb40f87
HHZ		 4252 rule_header = (struct _rule_hw *)(ctrl + 1);
4253 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
4254
48564135
MB		 4255 if (header_id == MLX4_NET_TRANS_RULE_ID_ETH)
4256 handle_eth_header_mcast_prio(ctrl, rule_header);
4257
4258 if (slave == dev->caps.function)
4259 goto execute;
4260
7fb40f87
HHZ		 4261 switch (header_id) {
4262 case MLX4_NET_TRANS_RULE_ID_ETH:
a9c01e7a
HHZ		 4263 if (validate_eth_header_mac(slave, rule_header, rlist)) {
4264 err = -EINVAL;
4265 goto err_put;
4266 }
7fb40f87 4267 break;
60396683
JM		 4268 case MLX4_NET_TRANS_RULE_ID_IB:
4269 break;
7fb40f87
HHZ		 4270 case MLX4_NET_TRANS_RULE_ID_IPV4:
4271 case MLX4_NET_TRANS_RULE_ID_TCP:
4272 case MLX4_NET_TRANS_RULE_ID_UDP:
1a91de28 4273 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
a9c01e7a
HHZ		 4274 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4275 err = -EINVAL;
4276 goto err_put;
4277 }
7fb40f87
HHZ		 4278 vhcr->in_modifier +=
4279 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4280 break;
4281 default:
1a91de28 4282 pr_err("Corrupted mailbox\n");
a9c01e7a
HHZ		 4283 err = -EINVAL;
4284 goto err_put;
7fb40f87
HHZ		 4285 }
4286
48564135 4287execute:
1b9c6b06
HHZ		 4288 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4289 vhcr->in_modifier, 0,
4290 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4291 MLX4_CMD_NATIVE);
4292 if (err)
a9c01e7a 4293 goto err_put;
1b9c6b06 4294
2c473ae7 4295 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
1b9c6b06 4296 if (err) {
1a91de28 4297 mlx4_err(dev, "Fail to add flow steering resources\n");
1b9c6b06
HHZ		 4298 /* detach rule*/
4299 mlx4_cmd(dev, vhcr->out_param, 0, 0,
2065b38b 4300 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1b9c6b06 4301 MLX4_CMD_NATIVE);
2c473ae7 4302 goto err_put;
1b9c6b06 4303 }
2c473ae7 4304 atomic_inc(&rqp->ref_count);
a9c01e7a
HHZ		 4305err_put:
4306 put_res(dev, slave, qpn, RES_QP);
1b9c6b06 4307 return err;
8fcfb4db
HHZ		 4308}
4309
4310int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4311 struct mlx4_vhcr *vhcr,
4312 struct mlx4_cmd_mailbox *inbox,
4313 struct mlx4_cmd_mailbox *outbox,
4314 struct mlx4_cmd_info *cmd)
4315{
1b9c6b06 4316 int err;
2c473ae7
HHZ		 4317 struct res_qp *rqp;
4318 struct res_fs_rule *rrule;
1b9c6b06 4319
0ff1fb65
HHZ		 4320 if (dev->caps.steering_mode !=
4321 MLX4_STEERING_MODE_DEVICE_MANAGED)
4322 return -EOPNOTSUPP;
1b9c6b06 4323
2c473ae7
HHZ		 4324 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4325 if (err)
4326 return err;
4327 /* Release the rule form busy state before removal */
4328 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4329 err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
4330 if (err)
4331 return err;
4332
1b9c6b06
HHZ		 4333 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4334 if (err) {
1a91de28 4335 mlx4_err(dev, "Fail to remove flow steering resources\n");
2c473ae7 4336 goto out;
1b9c6b06
HHZ		 4337 }
4338
4339 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4340 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4341 MLX4_CMD_NATIVE);
2c473ae7
HHZ		 4342 if (!err)
4343 atomic_dec(&rqp->ref_count);
4344out:
4345 put_res(dev, slave, rrule->qpn, RES_QP);
1b9c6b06 4346 return err;
8fcfb4db
HHZ		 4347}
4348
c82e9aa0
EC		 4349enum {
4350 BUSY_MAX_RETRIES = 10
4351};
4352
4353int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4354 struct mlx4_vhcr *vhcr,
4355 struct mlx4_cmd_mailbox *inbox,
4356 struct mlx4_cmd_mailbox *outbox,
4357 struct mlx4_cmd_info *cmd)
4358{
4359 int err;
4360 int index = vhcr->in_modifier & 0xffff;
4361
4362 err = get_res(dev, slave, index, RES_COUNTER, NULL);
4363 if (err)
4364 return err;
4365
4366 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4367 put_res(dev, slave, index, RES_COUNTER);
4368 return err;
4369}
4370
4371static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4372{
4373 struct res_gid *rgid;
4374 struct res_gid *tmp;
c82e9aa0
EC		 4375 struct mlx4_qp qp; /* dummy for calling attach/detach */
4376
4377 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
fab1e24a
HHZ		 4378 switch (dev->caps.steering_mode) {
4379 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4380 mlx4_flow_detach(dev, rgid->reg_id);
4381 break;
4382 case MLX4_STEERING_MODE_B0:
4383 qp.qpn = rqp->local_qpn;
4384 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4385 rgid->prot, rgid->steer);
4386 break;
4387 }
c82e9aa0
EC		 4388 list_del(&rgid->list);
4389 kfree(rgid);
4390 }
4391}
4392
4393static int _move_all_busy(struct mlx4_dev *dev, int slave,
4394 enum mlx4_resource type, int print)
4395{
4396 struct mlx4_priv *priv = mlx4_priv(dev);
4397 struct mlx4_resource_tracker *tracker =
4398 &priv->mfunc.master.res_tracker;
4399 struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4400 struct res_common *r;
4401 struct res_common *tmp;
4402 int busy;
4403
4404 busy = 0;
4405 spin_lock_irq(mlx4_tlock(dev));
4406 list_for_each_entry_safe(r, tmp, rlist, list) {
4407 if (r->owner == slave) {
4408 if (!r->removing) {
4409 if (r->state == RES_ANY_BUSY) {
4410 if (print)
4411 mlx4_dbg(dev,
aa1ec3dd 4412 "%s id 0x%llx is busy\n",
95646373 4413 resource_str(type),
c82e9aa0
EC		 4414 r->res_id);
4415 ++busy;
4416 } else {
4417 r->from_state = r->state;
4418 r->state = RES_ANY_BUSY;
4419 r->removing = 1;
4420 }
4421 }
4422 }
4423 }
4424 spin_unlock_irq(mlx4_tlock(dev));
4425
4426 return busy;
4427}
4428
4429static int move_all_busy(struct mlx4_dev *dev, int slave,
4430 enum mlx4_resource type)
4431{
4432 unsigned long begin;
4433 int busy;
4434
4435 begin = jiffies;
4436 do {
4437 busy = _move_all_busy(dev, slave, type, 0);
4438 if (time_after(jiffies, begin + 5 * HZ))
4439 break;
4440 if (busy)
4441 cond_resched();
4442 } while (busy);
4443
4444 if (busy)
4445 busy = _move_all_busy(dev, slave, type, 1);
4446
4447 return busy;
4448}
4449static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4450{
4451 struct mlx4_priv *priv = mlx4_priv(dev);
4452 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4453 struct list_head *qp_list =
4454 &tracker->slave_list[slave].res_list[RES_QP];
4455 struct res_qp *qp;
4456 struct res_qp *tmp;
4457 int state;
4458 u64 in_param;
4459 int qpn;
4460 int err;
4461
4462 err = move_all_busy(dev, slave, RES_QP);
4463 if (err)
1a91de28
JP		 4464 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
4465 slave);
c82e9aa0
EC		 4466
4467 spin_lock_irq(mlx4_tlock(dev));
4468 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4469 spin_unlock_irq(mlx4_tlock(dev));
4470 if (qp->com.owner == slave) {
4471 qpn = qp->com.res_id;
4472 detach_qp(dev, slave, qp);
4473 state = qp->com.from_state;
4474 while (state != 0) {
4475 switch (state) {
4476 case RES_QP_RESERVED:
4477 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4478 rb_erase(&qp->com.node,
4479 &tracker->res_tree[RES_QP]);
c82e9aa0
EC		 4480 list_del(&qp->com.list);
4481 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4482 if (!valid_reserved(dev, slave, qpn)) {
4483 __mlx4_qp_release_range(dev, qpn, 1);
4484 mlx4_release_resource(dev, slave,
4485 RES_QP, 1, 0);
4486 }
c82e9aa0
EC		 4487 kfree(qp);
4488 state = 0;
4489 break;
4490 case RES_QP_MAPPED:
4491 if (!valid_reserved(dev, slave, qpn))
4492 __mlx4_qp_free_icm(dev, qpn);
4493 state = RES_QP_RESERVED;
4494 break;
4495 case RES_QP_HW:
4496 in_param = slave;
4497 err = mlx4_cmd(dev, in_param,
4498 qp->local_qpn, 2,
4499 MLX4_CMD_2RST_QP,
4500 MLX4_CMD_TIME_CLASS_A,
4501 MLX4_CMD_NATIVE);
4502 if (err)
1a91de28
JP		 4503 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
4504 slave, qp->local_qpn);
c82e9aa0
EC		 4505 atomic_dec(&qp->rcq->ref_count);
4506 atomic_dec(&qp->scq->ref_count);
4507 atomic_dec(&qp->mtt->ref_count);
4508 if (qp->srq)
4509 atomic_dec(&qp->srq->ref_count);
4510 state = RES_QP_MAPPED;
4511 break;
4512 default:
4513 state = 0;
4514 }
4515 }
4516 }
4517 spin_lock_irq(mlx4_tlock(dev));
4518 }
4519 spin_unlock_irq(mlx4_tlock(dev));
4520}
4521
4522static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4523{
4524 struct mlx4_priv *priv = mlx4_priv(dev);
4525 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4526 struct list_head *srq_list =
4527 &tracker->slave_list[slave].res_list[RES_SRQ];
4528 struct res_srq *srq;
4529 struct res_srq *tmp;
4530 int state;
4531 u64 in_param;
4532 LIST_HEAD(tlist);
4533 int srqn;
4534 int err;
4535
4536 err = move_all_busy(dev, slave, RES_SRQ);
4537 if (err)
1a91de28
JP		 4538 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
4539 slave);
c82e9aa0
EC		 4540
4541 spin_lock_irq(mlx4_tlock(dev));
4542 list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4543 spin_unlock_irq(mlx4_tlock(dev));
4544 if (srq->com.owner == slave) {
4545 srqn = srq->com.res_id;
4546 state = srq->com.from_state;
4547 while (state != 0) {
4548 switch (state) {
4549 case RES_SRQ_ALLOCATED:
4550 __mlx4_srq_free_icm(dev, srqn);
4551 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4552 rb_erase(&srq->com.node,
4553 &tracker->res_tree[RES_SRQ]);
c82e9aa0
EC		 4554 list_del(&srq->com.list);
4555 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4556 mlx4_release_resource(dev, slave,
4557 RES_SRQ, 1, 0);
c82e9aa0
EC		 4558 kfree(srq);
4559 state = 0;
4560 break;
4561
4562 case RES_SRQ_HW:
4563 in_param = slave;
4564 err = mlx4_cmd(dev, in_param, srqn, 1,
4565 MLX4_CMD_HW2SW_SRQ,
4566 MLX4_CMD_TIME_CLASS_A,
4567 MLX4_CMD_NATIVE);
4568 if (err)
1a91de28 4569 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
c82e9aa0
EC		 4570 slave, srqn);
4571
4572 atomic_dec(&srq->mtt->ref_count);
4573 if (srq->cq)
4574 atomic_dec(&srq->cq->ref_count);
4575 state = RES_SRQ_ALLOCATED;
4576 break;
4577
4578 default:
4579 state = 0;
4580 }
4581 }
4582 }
4583 spin_lock_irq(mlx4_tlock(dev));
4584 }
4585 spin_unlock_irq(mlx4_tlock(dev));
4586}
4587
4588static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4589{
4590 struct mlx4_priv *priv = mlx4_priv(dev);
4591 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4592 struct list_head *cq_list =
4593 &tracker->slave_list[slave].res_list[RES_CQ];
4594 struct res_cq *cq;
4595 struct res_cq *tmp;
4596 int state;
4597 u64 in_param;
4598 LIST_HEAD(tlist);
4599 int cqn;
4600 int err;
4601
4602 err = move_all_busy(dev, slave, RES_CQ);
4603 if (err)
1a91de28
JP		 4604 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
4605 slave);
c82e9aa0
EC		 4606
4607 spin_lock_irq(mlx4_tlock(dev));
4608 list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4609 spin_unlock_irq(mlx4_tlock(dev));
4610 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4611 cqn = cq->com.res_id;
4612 state = cq->com.from_state;
4613 while (state != 0) {
4614 switch (state) {
4615 case RES_CQ_ALLOCATED:
4616 __mlx4_cq_free_icm(dev, cqn);
4617 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4618 rb_erase(&cq->com.node,
4619 &tracker->res_tree[RES_CQ]);
c82e9aa0
EC		 4620 list_del(&cq->com.list);
4621 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4622 mlx4_release_resource(dev, slave,
4623 RES_CQ, 1, 0);
c82e9aa0
EC		 4624 kfree(cq);
4625 state = 0;
4626 break;
4627
4628 case RES_CQ_HW:
4629 in_param = slave;
4630 err = mlx4_cmd(dev, in_param, cqn, 1,
4631 MLX4_CMD_HW2SW_CQ,
4632 MLX4_CMD_TIME_CLASS_A,
4633 MLX4_CMD_NATIVE);
4634 if (err)
1a91de28 4635 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
c82e9aa0
EC		 4636 slave, cqn);
4637 atomic_dec(&cq->mtt->ref_count);
4638 state = RES_CQ_ALLOCATED;
4639 break;
4640
4641 default:
4642 state = 0;
4643 }
4644 }
4645 }
4646 spin_lock_irq(mlx4_tlock(dev));
4647 }
4648 spin_unlock_irq(mlx4_tlock(dev));
4649}
4650
4651static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4652{
4653 struct mlx4_priv *priv = mlx4_priv(dev);
4654 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4655 struct list_head *mpt_list =
4656 &tracker->slave_list[slave].res_list[RES_MPT];
4657 struct res_mpt *mpt;
4658 struct res_mpt *tmp;
4659 int state;
4660 u64 in_param;
4661 LIST_HEAD(tlist);
4662 int mptn;
4663 int err;
4664
4665 err = move_all_busy(dev, slave, RES_MPT);
4666 if (err)
1a91de28
JP		 4667 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
4668 slave);
c82e9aa0
EC		 4669
4670 spin_lock_irq(mlx4_tlock(dev));
4671 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4672 spin_unlock_irq(mlx4_tlock(dev));
4673 if (mpt->com.owner == slave) {
4674 mptn = mpt->com.res_id;
4675 state = mpt->com.from_state;
4676 while (state != 0) {
4677 switch (state) {
4678 case RES_MPT_RESERVED:
b20e519a 4679 __mlx4_mpt_release(dev, mpt->key);
c82e9aa0 4680 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4681 rb_erase(&mpt->com.node,
4682 &tracker->res_tree[RES_MPT]);
c82e9aa0
EC		 4683 list_del(&mpt->com.list);
4684 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4685 mlx4_release_resource(dev, slave,
4686 RES_MPT, 1, 0);
c82e9aa0
EC		 4687 kfree(mpt);
4688 state = 0;
4689 break;
4690
4691 case RES_MPT_MAPPED:
b20e519a 4692 __mlx4_mpt_free_icm(dev, mpt->key);
c82e9aa0
EC		 4693 state = RES_MPT_RESERVED;
4694 break;
4695
4696 case RES_MPT_HW:
4697 in_param = slave;
4698 err = mlx4_cmd(dev, in_param, mptn, 0,
4699 MLX4_CMD_HW2SW_MPT,
4700 MLX4_CMD_TIME_CLASS_A,
4701 MLX4_CMD_NATIVE);
4702 if (err)
1a91de28 4703 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
c82e9aa0
EC		 4704 slave, mptn);
4705 if (mpt->mtt)
4706 atomic_dec(&mpt->mtt->ref_count);
4707 state = RES_MPT_MAPPED;
4708 break;
4709 default:
4710 state = 0;
4711 }
4712 }
4713 }
4714 spin_lock_irq(mlx4_tlock(dev));
4715 }
4716 spin_unlock_irq(mlx4_tlock(dev));
4717}
4718
4719static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4720{
4721 struct mlx4_priv *priv = mlx4_priv(dev);
4722 struct mlx4_resource_tracker *tracker =
4723 &priv->mfunc.master.res_tracker;
4724 struct list_head *mtt_list =
4725 &tracker->slave_list[slave].res_list[RES_MTT];
4726 struct res_mtt *mtt;
4727 struct res_mtt *tmp;
4728 int state;
4729 LIST_HEAD(tlist);
4730 int base;
4731 int err;
4732
4733 err = move_all_busy(dev, slave, RES_MTT);
4734 if (err)
1a91de28
JP		 4735 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n",
4736 slave);
c82e9aa0
EC		 4737
4738 spin_lock_irq(mlx4_tlock(dev));
4739 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4740 spin_unlock_irq(mlx4_tlock(dev));
4741 if (mtt->com.owner == slave) {
4742 base = mtt->com.res_id;
4743 state = mtt->com.from_state;
4744 while (state != 0) {
4745 switch (state) {
4746 case RES_MTT_ALLOCATED:
4747 __mlx4_free_mtt_range(dev, base,
4748 mtt->order);
4749 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4750 rb_erase(&mtt->com.node,
4751 &tracker->res_tree[RES_MTT]);
c82e9aa0
EC		 4752 list_del(&mtt->com.list);
4753 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4754 mlx4_release_resource(dev, slave, RES_MTT,
4755 1 << mtt->order, 0);
c82e9aa0
EC		 4756 kfree(mtt);
4757 state = 0;
4758 break;
4759
4760 default:
4761 state = 0;
4762 }
4763 }
4764 }
4765 spin_lock_irq(mlx4_tlock(dev));
4766 }
4767 spin_unlock_irq(mlx4_tlock(dev));
4768}
4769
1b9c6b06
HHZ		 4770static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
4771{
4772 struct mlx4_priv *priv = mlx4_priv(dev);
4773 struct mlx4_resource_tracker *tracker =
4774 &priv->mfunc.master.res_tracker;
4775 struct list_head *fs_rule_list =
4776 &tracker->slave_list[slave].res_list[RES_FS_RULE];
4777 struct res_fs_rule *fs_rule;
4778 struct res_fs_rule *tmp;
4779 int state;
4780 u64 base;
4781 int err;
4782
4783 err = move_all_busy(dev, slave, RES_FS_RULE);
4784 if (err)
4785 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
4786 slave);
4787
4788 spin_lock_irq(mlx4_tlock(dev));
4789 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
4790 spin_unlock_irq(mlx4_tlock(dev));
4791 if (fs_rule->com.owner == slave) {
4792 base = fs_rule->com.res_id;
4793 state = fs_rule->com.from_state;
4794 while (state != 0) {
4795 switch (state) {
4796 case RES_FS_RULE_ALLOCATED:
4797 /* detach rule */
4798 err = mlx4_cmd(dev, base, 0, 0,
4799 MLX4_QP_FLOW_STEERING_DETACH,
4800 MLX4_CMD_TIME_CLASS_A,
4801 MLX4_CMD_NATIVE);
4802
4803 spin_lock_irq(mlx4_tlock(dev));
4804 rb_erase(&fs_rule->com.node,
4805 &tracker->res_tree[RES_FS_RULE]);
4806 list_del(&fs_rule->com.list);
4807 spin_unlock_irq(mlx4_tlock(dev));
4808 kfree(fs_rule);
4809 state = 0;
4810 break;
4811
4812 default:
4813 state = 0;
4814 }
4815 }
4816 }
4817 spin_lock_irq(mlx4_tlock(dev));
4818 }
4819 spin_unlock_irq(mlx4_tlock(dev));
4820}
4821
c82e9aa0
EC		 4822static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
4823{
4824 struct mlx4_priv *priv = mlx4_priv(dev);
4825 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4826 struct list_head *eq_list =
4827 &tracker->slave_list[slave].res_list[RES_EQ];
4828 struct res_eq *eq;
4829 struct res_eq *tmp;
4830 int err;
4831 int state;
4832 LIST_HEAD(tlist);
4833 int eqn;
c82e9aa0
EC		 4834
4835 err = move_all_busy(dev, slave, RES_EQ);
4836 if (err)
1a91de28
JP		 4837 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
4838 slave);
c82e9aa0
EC		 4839
4840 spin_lock_irq(mlx4_tlock(dev));
4841 list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
4842 spin_unlock_irq(mlx4_tlock(dev));
4843 if (eq->com.owner == slave) {
4844 eqn = eq->com.res_id;
4845 state = eq->com.from_state;
4846 while (state != 0) {
4847 switch (state) {
4848 case RES_EQ_RESERVED:
4849 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4850 rb_erase(&eq->com.node,
4851 &tracker->res_tree[RES_EQ]);
c82e9aa0
EC		 4852 list_del(&eq->com.list);
4853 spin_unlock_irq(mlx4_tlock(dev));
4854 kfree(eq);
4855 state = 0;
4856 break;
4857
4858 case RES_EQ_HW:
2d3c7397 4859 err = mlx4_cmd(dev, slave, eqn & 0x3ff,
30a5da5b
JM		 4860 1, MLX4_CMD_HW2SW_EQ,
4861 MLX4_CMD_TIME_CLASS_A,
4862 MLX4_CMD_NATIVE);
eb71d0d6 4863 if (err)
1a91de28 4864 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
2d3c7397 4865 slave, eqn & 0x3ff);
eb71d0d6
JM		 4866 atomic_dec(&eq->mtt->ref_count);
4867 state = RES_EQ_RESERVED;
c82e9aa0
EC		 4868 break;
4869
4870 default:
4871 state = 0;
4872 }
4873 }
4874 }
4875 spin_lock_irq(mlx4_tlock(dev));
4876 }
4877 spin_unlock_irq(mlx4_tlock(dev));
4878}
4879
ba062d52
JM		 4880static void rem_slave_counters(struct mlx4_dev *dev, int slave)
4881{
4882 struct mlx4_priv *priv = mlx4_priv(dev);
4883 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4884 struct list_head *counter_list =
4885 &tracker->slave_list[slave].res_list[RES_COUNTER];
4886 struct res_counter *counter;
4887 struct res_counter *tmp;
4888 int err;
4889 int index;
4890
4891 err = move_all_busy(dev, slave, RES_COUNTER);
4892 if (err)
1a91de28
JP		 4893 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
4894 slave);
ba062d52
JM		 4895
4896 spin_lock_irq(mlx4_tlock(dev));
4897 list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
4898 if (counter->com.owner == slave) {
4899 index = counter->com.res_id;
4af1c048
HHZ		 4900 rb_erase(&counter->com.node,
4901 &tracker->res_tree[RES_COUNTER]);
ba062d52
JM		 4902 list_del(&counter->com.list);
4903 kfree(counter);
4904 __mlx4_counter_free(dev, index);
146f3ef4 4905 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 4906 }
4907 }
4908 spin_unlock_irq(mlx4_tlock(dev));
4909}
4910
4911static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
4912{
4913 struct mlx4_priv *priv = mlx4_priv(dev);
4914 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4915 struct list_head *xrcdn_list =
4916 &tracker->slave_list[slave].res_list[RES_XRCD];
4917 struct res_xrcdn *xrcd;
4918 struct res_xrcdn *tmp;
4919 int err;
4920 int xrcdn;
4921
4922 err = move_all_busy(dev, slave, RES_XRCD);
4923 if (err)
1a91de28
JP		 4924 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
4925 slave);
ba062d52
JM		 4926
4927 spin_lock_irq(mlx4_tlock(dev));
4928 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
4929 if (xrcd->com.owner == slave) {
4930 xrcdn = xrcd->com.res_id;
4af1c048 4931 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
ba062d52
JM		 4932 list_del(&xrcd->com.list);
4933 kfree(xrcd);
4934 __mlx4_xrcd_free(dev, xrcdn);
4935 }
4936 }
4937 spin_unlock_irq(mlx4_tlock(dev));
4938}
4939
c82e9aa0
EC		 4940void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
4941{
4942 struct mlx4_priv *priv = mlx4_priv(dev);
111c6094 4943 mlx4_reset_roce_gids(dev, slave);
c82e9aa0 4944 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4874080d 4945 rem_slave_vlans(dev, slave);
c82e9aa0 4946 rem_slave_macs(dev, slave);
80cb0021 4947 rem_slave_fs_rule(dev, slave);
c82e9aa0
EC		 4948 rem_slave_qps(dev, slave);
4949 rem_slave_srqs(dev, slave);
4950 rem_slave_cqs(dev, slave);
4951 rem_slave_mrs(dev, slave);
4952 rem_slave_eqs(dev, slave);
4953 rem_slave_mtts(dev, slave);
ba062d52
JM		 4954 rem_slave_counters(dev, slave);
4955 rem_slave_xrcdns(dev, slave);
c82e9aa0
EC		 4956 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4957}
b01978ca
JM		 4958
4959void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
4960{
4961 struct mlx4_vf_immed_vlan_work *work =
4962 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
4963 struct mlx4_cmd_mailbox *mailbox;
4964 struct mlx4_update_qp_context *upd_context;
4965 struct mlx4_dev *dev = &work->priv->dev;
4966 struct mlx4_resource_tracker *tracker =
4967 &work->priv->mfunc.master.res_tracker;
4968 struct list_head *qp_list =
4969 &tracker->slave_list[work->slave].res_list[RES_QP];
4970 struct res_qp *qp;
4971 struct res_qp *tmp;
f0f829bf
RE		 4972 u64 qp_path_mask_vlan_ctrl =
4973 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
b01978ca
JM		 4974 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
4975 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
4976 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
4977 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
f0f829bf
RE		 4978 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
4979
4980 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
4981 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
4982 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
4983 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
4984 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
4985 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
b01978ca
JM		 4986 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
4987
4988 int err;
4989 int port, errors = 0;
4990 u8 vlan_control;
4991
4992 if (mlx4_is_slave(dev)) {
4993 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
4994 work->slave);
4995 goto out;
4996 }
4997
4998 mailbox = mlx4_alloc_cmd_mailbox(dev);
4999 if (IS_ERR(mailbox))
5000 goto out;
0a6eac24
RE		 5001 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
5002 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5003 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
5004 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
5005 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5006 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
5007 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5008 else if (!work->vlan_id)
b01978ca
JM		 5009 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5010 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5011 else
5012 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5013 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5014 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
5015
5016 upd_context = mailbox->buf;
311be98a 5017 upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
b01978ca
JM		 5018
5019 spin_lock_irq(mlx4_tlock(dev));
5020 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
5021 spin_unlock_irq(mlx4_tlock(dev));
5022 if (qp->com.owner == work->slave) {
5023 if (qp->com.from_state != RES_QP_HW ||
5024 !qp->sched_queue || /* no INIT2RTR trans yet */
5025 mlx4_is_qp_reserved(dev, qp->local_qpn) ||
5026 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
5027 spin_lock_irq(mlx4_tlock(dev));
5028 continue;
5029 }
5030 port = (qp->sched_queue >> 6 & 1) + 1;
5031 if (port != work->port) {
5032 spin_lock_irq(mlx4_tlock(dev));
5033 continue;
5034 }
f0f829bf
RE		 5035 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
5036 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
5037 else
5038 upd_context->primary_addr_path_mask =
5039 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
5040 if (work->vlan_id == MLX4_VGT) {
5041 upd_context->qp_context.param3 = qp->param3;
5042 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
5043 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
5044 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
5045 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
5046 upd_context->qp_context.pri_path.feup = qp->feup;
5047 upd_context->qp_context.pri_path.sched_queue =
5048 qp->sched_queue;
5049 } else {
5050 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
5051 upd_context->qp_context.pri_path.vlan_control = vlan_control;
5052 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
5053 upd_context->qp_context.pri_path.fvl_rx =
5054 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
5055 upd_context->qp_context.pri_path.fl =
5056 qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
5057 upd_context->qp_context.pri_path.feup =
5058 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
5059 upd_context->qp_context.pri_path.sched_queue =
5060 qp->sched_queue & 0xC7;
5061 upd_context->qp_context.pri_path.sched_queue |=
5062 ((work->qos & 0x7) << 3);
08068cd5
IS		 5063 upd_context->qp_mask |=
5064 cpu_to_be64(1ULL <<
5065 MLX4_UPD_QP_MASK_QOS_VPP);
5066 upd_context->qp_context.qos_vport =
5067 work->qos_vport;
f0f829bf 5068 }
b01978ca
JM		 5069
5070 err = mlx4_cmd(dev, mailbox->dma,
5071 qp->local_qpn & 0xffffff,
5072 0, MLX4_CMD_UPDATE_QP,
5073 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
5074 if (err) {
1a91de28
JP		 5075 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
5076 work->slave, port, qp->local_qpn, err);
b01978ca
JM		 5077 errors++;
5078 }
5079 }
5080 spin_lock_irq(mlx4_tlock(dev));
5081 }
5082 spin_unlock_irq(mlx4_tlock(dev));
5083 mlx4_free_cmd_mailbox(dev, mailbox);
5084
5085 if (errors)
5086 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
5087 errors, work->slave, work->port);
5088
5089 /* unregister previous vlan_id if needed and we had no errors
5090 * while updating the QPs
5091 */
5092 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
5093 NO_INDX != work->orig_vlan_ix)
5094 __mlx4_unregister_vlan(&work->priv->dev, work->port,
2009d005 5095 work->orig_vlan_id);
b01978ca
JM		 5096out:
5097 kfree(work);
5098 return;
5099}
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