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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / resource_tracker.c
CommitLineData
c82e9aa0
EC		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
4 * All rights reserved.
5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/sched.h>
37#include <linux/pci.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/io.h>
e143a1ad 41#include <linux/slab.h>
c82e9aa0
EC		 42#include <linux/mlx4/cmd.h>
43#include <linux/mlx4/qp.h>
af22d9de 44#include <linux/if_ether.h>
7fb40f87 45#include <linux/etherdevice.h>
c82e9aa0
EC		 46
47#include "mlx4.h"
48#include "fw.h"
49
50#define MLX4_MAC_VALID (1ull << 63)
c82e9aa0
EC		 51
52struct mac_res {
53 struct list_head list;
54 u64 mac;
2f5bb473
JM		 55 int ref_count;
56 u8 smac_index;
c82e9aa0
EC		 57 u8 port;
58};
59
4874080d
JM		 60struct vlan_res {
61 struct list_head list;
62 u16 vlan;
63 int ref_count;
64 int vlan_index;
65 u8 port;
66};
67
c82e9aa0
EC		 68struct res_common {
69 struct list_head list;
4af1c048 70 struct rb_node node;
aa1ec3dd 71 u64 res_id;
c82e9aa0
EC		 72 int owner;
73 int state;
74 int from_state;
75 int to_state;
76 int removing;
77};
78
79enum {
80 RES_ANY_BUSY = 1
81};
82
83struct res_gid {
84 struct list_head list;
85 u8 gid[16];
86 enum mlx4_protocol prot;
9f5b6c63 87 enum mlx4_steer_type steer;
fab1e24a 88 u64 reg_id;
c82e9aa0
EC		 89};
90
91enum res_qp_states {
92 RES_QP_BUSY = RES_ANY_BUSY,
93
94 /* QP number was allocated */
95 RES_QP_RESERVED,
96
97 /* ICM memory for QP context was mapped */
98 RES_QP_MAPPED,
99
100 /* QP is in hw ownership */
101 RES_QP_HW
102};
103
c82e9aa0
EC		 104struct res_qp {
105 struct res_common com;
106 struct res_mtt *mtt;
107 struct res_cq *rcq;
108 struct res_cq *scq;
109 struct res_srq *srq;
110 struct list_head mcg_list;
111 spinlock_t mcg_spl;
112 int local_qpn;
2c473ae7 113 atomic_t ref_count;
b01978ca 114 u32 qpc_flags;
f0f829bf 115 /* saved qp params before VST enforcement in order to restore on VGT */
b01978ca 116 u8 sched_queue;
f0f829bf
RE		 117 __be32 param3;
118 u8 vlan_control;
119 u8 fvl_rx;
120 u8 pri_path_fl;
121 u8 vlan_index;
122 u8 feup;
c82e9aa0
EC		 123};
124
125enum res_mtt_states {
126 RES_MTT_BUSY = RES_ANY_BUSY,
127 RES_MTT_ALLOCATED,
128};
129
130static inline const char *mtt_states_str(enum res_mtt_states state)
131{
132 switch (state) {
133 case RES_MTT_BUSY: return "RES_MTT_BUSY";
134 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
135 default: return "Unknown";
136 }
137}
138
139struct res_mtt {
140 struct res_common com;
141 int order;
142 atomic_t ref_count;
143};
144
145enum res_mpt_states {
146 RES_MPT_BUSY = RES_ANY_BUSY,
147 RES_MPT_RESERVED,
148 RES_MPT_MAPPED,
149 RES_MPT_HW,
150};
151
152struct res_mpt {
153 struct res_common com;
154 struct res_mtt *mtt;
155 int key;
156};
157
158enum res_eq_states {
159 RES_EQ_BUSY = RES_ANY_BUSY,
160 RES_EQ_RESERVED,
161 RES_EQ_HW,
162};
163
164struct res_eq {
165 struct res_common com;
166 struct res_mtt *mtt;
167};
168
169enum res_cq_states {
170 RES_CQ_BUSY = RES_ANY_BUSY,
171 RES_CQ_ALLOCATED,
172 RES_CQ_HW,
173};
174
175struct res_cq {
176 struct res_common com;
177 struct res_mtt *mtt;
178 atomic_t ref_count;
179};
180
181enum res_srq_states {
182 RES_SRQ_BUSY = RES_ANY_BUSY,
183 RES_SRQ_ALLOCATED,
184 RES_SRQ_HW,
185};
186
c82e9aa0
EC		 187struct res_srq {
188 struct res_common com;
189 struct res_mtt *mtt;
190 struct res_cq *cq;
191 atomic_t ref_count;
192};
193
194enum res_counter_states {
195 RES_COUNTER_BUSY = RES_ANY_BUSY,
196 RES_COUNTER_ALLOCATED,
197};
198
c82e9aa0
EC		 199struct res_counter {
200 struct res_common com;
201 int port;
202};
203
ba062d52
JM		 204enum res_xrcdn_states {
205 RES_XRCD_BUSY = RES_ANY_BUSY,
206 RES_XRCD_ALLOCATED,
207};
208
209struct res_xrcdn {
210 struct res_common com;
211 int port;
212};
213
1b9c6b06
HHZ		 214enum res_fs_rule_states {
215 RES_FS_RULE_BUSY = RES_ANY_BUSY,
216 RES_FS_RULE_ALLOCATED,
217};
218
219struct res_fs_rule {
220 struct res_common com;
2c473ae7 221 int qpn;
1b9c6b06
HHZ		 222};
223
b6ffaeff
JM		 224static int mlx4_is_eth(struct mlx4_dev *dev, int port)
225{
226 return dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
227}
228
4af1c048
HHZ		 229static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
230{
231 struct rb_node *node = root->rb_node;
232
233 while (node) {
234 struct res_common *res = container_of(node, struct res_common,
235 node);
236
237 if (res_id < res->res_id)
238 node = node->rb_left;
239 else if (res_id > res->res_id)
240 node = node->rb_right;
241 else
242 return res;
243 }
244 return NULL;
245}
246
247static int res_tracker_insert(struct rb_root *root, struct res_common *res)
248{
249 struct rb_node **new = &(root->rb_node), *parent = NULL;
250
251 /* Figure out where to put new node */
252 while (*new) {
253 struct res_common *this = container_of(*new, struct res_common,
254 node);
255
256 parent = *new;
257 if (res->res_id < this->res_id)
258 new = &((*new)->rb_left);
259 else if (res->res_id > this->res_id)
260 new = &((*new)->rb_right);
261 else
262 return -EEXIST;
263 }
264
265 /* Add new node and rebalance tree. */
266 rb_link_node(&res->node, parent, new);
267 rb_insert_color(&res->node, root);
268
269 return 0;
270}
271
54679e14
JM		 272enum qp_transition {
273 QP_TRANS_INIT2RTR,
274 QP_TRANS_RTR2RTS,
275 QP_TRANS_RTS2RTS,
276 QP_TRANS_SQERR2RTS,
277 QP_TRANS_SQD2SQD,
278 QP_TRANS_SQD2RTS
279};
280
c82e9aa0 281/* For Debug uses */
95646373 282static const char *resource_str(enum mlx4_resource rt)
c82e9aa0
EC		 283{
284 switch (rt) {
285 case RES_QP: return "RES_QP";
286 case RES_CQ: return "RES_CQ";
287 case RES_SRQ: return "RES_SRQ";
288 case RES_MPT: return "RES_MPT";
289 case RES_MTT: return "RES_MTT";
290 case RES_MAC: return "RES_MAC";
4874080d 291 case RES_VLAN: return "RES_VLAN";
c82e9aa0
EC		 292 case RES_EQ: return "RES_EQ";
293 case RES_COUNTER: return "RES_COUNTER";
1b9c6b06 294 case RES_FS_RULE: return "RES_FS_RULE";
ba062d52 295 case RES_XRCD: return "RES_XRCD";
c82e9aa0
EC		 296 default: return "Unknown resource type !!!";
297 };
298}
299
4874080d 300static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
146f3ef4
JM		 301static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
302 enum mlx4_resource res_type, int count,
303 int port)
304{
305 struct mlx4_priv *priv = mlx4_priv(dev);
306 struct resource_allocator *res_alloc =
307 &priv->mfunc.master.res_tracker.res_alloc[res_type];
308 int err = -EINVAL;
309 int allocated, free, reserved, guaranteed, from_free;
95646373 310 int from_rsvd;
146f3ef4 311
872bf2fb 312 if (slave > dev->persist->num_vfs)
146f3ef4
JM		 313 return -EINVAL;
314
315 spin_lock(&res_alloc->alloc_lock);
316 allocated = (port > 0) ?
872bf2fb
YH		 317 res_alloc->allocated[(port - 1) *
318 (dev->persist->num_vfs + 1) + slave] :
146f3ef4
JM		 319 res_alloc->allocated[slave];
320 free = (port > 0) ? res_alloc->res_port_free[port - 1] :
321 res_alloc->res_free;
322 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
323 res_alloc->res_reserved;
324 guaranteed = res_alloc->guaranteed[slave];
325
95646373
JM		 326 if (allocated + count > res_alloc->quota[slave]) {
327 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
328 slave, port, resource_str(res_type), count,
329 allocated, res_alloc->quota[slave]);
146f3ef4 330 goto out;
95646373 331 }
146f3ef4
JM		 332
333 if (allocated + count <= guaranteed) {
334 err = 0;
95646373 335 from_rsvd = count;
146f3ef4
JM		 336 } else {
337 /* portion may need to be obtained from free area */
338 if (guaranteed - allocated > 0)
339 from_free = count - (guaranteed - allocated);
340 else
341 from_free = count;
342
95646373
JM		 343 from_rsvd = count - from_free;
344
345 if (free - from_free >= reserved)
146f3ef4 346 err = 0;
95646373
JM		 347 else
348 mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
349 slave, port, resource_str(res_type), free,
350 from_free, reserved);
146f3ef4
JM		 351 }
352
353 if (!err) {
354 /* grant the request */
355 if (port > 0) {
872bf2fb
YH		 356 res_alloc->allocated[(port - 1) *
357 (dev->persist->num_vfs + 1) + slave] += count;
146f3ef4 358 res_alloc->res_port_free[port - 1] -= count;
95646373 359 res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
146f3ef4
JM		 360 } else {
361 res_alloc->allocated[slave] += count;
362 res_alloc->res_free -= count;
95646373 363 res_alloc->res_reserved -= from_rsvd;
146f3ef4
JM		 364 }
365 }
366
367out:
368 spin_unlock(&res_alloc->alloc_lock);
369 return err;
370}
371
372static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
373 enum mlx4_resource res_type, int count,
374 int port)
375{
376 struct mlx4_priv *priv = mlx4_priv(dev);
377 struct resource_allocator *res_alloc =
378 &priv->mfunc.master.res_tracker.res_alloc[res_type];
95646373 379 int allocated, guaranteed, from_rsvd;
146f3ef4 380
872bf2fb 381 if (slave > dev->persist->num_vfs)
146f3ef4
JM		 382 return;
383
384 spin_lock(&res_alloc->alloc_lock);
95646373
JM		 385
386 allocated = (port > 0) ?
872bf2fb
YH		 387 res_alloc->allocated[(port - 1) *
388 (dev->persist->num_vfs + 1) + slave] :
95646373
JM		 389 res_alloc->allocated[slave];
390 guaranteed = res_alloc->guaranteed[slave];
391
392 if (allocated - count >= guaranteed) {
393 from_rsvd = 0;
394 } else {
395 /* portion may need to be returned to reserved area */
396 if (allocated - guaranteed > 0)
397 from_rsvd = count - (allocated - guaranteed);
398 else
399 from_rsvd = count;
400 }
401
146f3ef4 402 if (port > 0) {
872bf2fb
YH		 403 res_alloc->allocated[(port - 1) *
404 (dev->persist->num_vfs + 1) + slave] -= count;
146f3ef4 405 res_alloc->res_port_free[port - 1] += count;
95646373 406 res_alloc->res_port_rsvd[port - 1] += from_rsvd;
146f3ef4
JM		 407 } else {
408 res_alloc->allocated[slave] -= count;
409 res_alloc->res_free += count;
95646373 410 res_alloc->res_reserved += from_rsvd;
146f3ef4
JM		 411 }
412
413 spin_unlock(&res_alloc->alloc_lock);
414 return;
415}
416
5a0d0a61
JM		 417static inline void initialize_res_quotas(struct mlx4_dev *dev,
418 struct resource_allocator *res_alloc,
419 enum mlx4_resource res_type,
420 int vf, int num_instances)
421{
872bf2fb
YH		 422 res_alloc->guaranteed[vf] = num_instances /
423 (2 * (dev->persist->num_vfs + 1));
5a0d0a61
JM		 424 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
425 if (vf == mlx4_master_func_num(dev)) {
426 res_alloc->res_free = num_instances;
427 if (res_type == RES_MTT) {
428 /* reserved mtts will be taken out of the PF allocation */
429 res_alloc->res_free += dev->caps.reserved_mtts;
430 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
431 res_alloc->quota[vf] += dev->caps.reserved_mtts;
432 }
433 }
434}
435
436void mlx4_init_quotas(struct mlx4_dev *dev)
437{
438 struct mlx4_priv *priv = mlx4_priv(dev);
439 int pf;
440
441 /* quotas for VFs are initialized in mlx4_slave_cap */
442 if (mlx4_is_slave(dev))
443 return;
444
445 if (!mlx4_is_mfunc(dev)) {
446 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
447 mlx4_num_reserved_sqps(dev);
448 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
449 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
450 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
451 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
452 return;
453 }
454
455 pf = mlx4_master_func_num(dev);
456 dev->quotas.qp =
457 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
458 dev->quotas.cq =
459 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
460 dev->quotas.srq =
461 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
462 dev->quotas.mtt =
463 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
464 dev->quotas.mpt =
465 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
466}
c82e9aa0
EC		 467int mlx4_init_resource_tracker(struct mlx4_dev *dev)
468{
469 struct mlx4_priv *priv = mlx4_priv(dev);
5a0d0a61 470 int i, j;
c82e9aa0
EC		 471 int t;
472
473 priv->mfunc.master.res_tracker.slave_list =
474 kzalloc(dev->num_slaves * sizeof(struct slave_list),
475 GFP_KERNEL);
476 if (!priv->mfunc.master.res_tracker.slave_list)
477 return -ENOMEM;
478
479 for (i = 0 ; i < dev->num_slaves; i++) {
480 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
481 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
482 slave_list[i].res_list[t]);
483 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
484 }
485
486 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
487 dev->num_slaves);
488 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
4af1c048 489 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
c82e9aa0 490
5a0d0a61
JM		 491 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
492 struct resource_allocator *res_alloc =
493 &priv->mfunc.master.res_tracker.res_alloc[i];
872bf2fb
YH		 494 res_alloc->quota = kmalloc((dev->persist->num_vfs + 1) *
495 sizeof(int), GFP_KERNEL);
496 res_alloc->guaranteed = kmalloc((dev->persist->num_vfs + 1) *
497 sizeof(int), GFP_KERNEL);
5a0d0a61
JM		 498 if (i == RES_MAC || i == RES_VLAN)
499 res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
872bf2fb
YH		 500 (dev->persist->num_vfs
501 + 1) *
502 sizeof(int), GFP_KERNEL);
5a0d0a61 503 else
872bf2fb
YH		 504 res_alloc->allocated = kzalloc((dev->persist->
505 num_vfs + 1) *
506 sizeof(int), GFP_KERNEL);
5a0d0a61
JM		 507
508 if (!res_alloc->quota || !res_alloc->guaranteed ||
509 !res_alloc->allocated)
510 goto no_mem_err;
511
146f3ef4 512 spin_lock_init(&res_alloc->alloc_lock);
872bf2fb 513 for (t = 0; t < dev->persist->num_vfs + 1; t++) {
449fc488
MB		 514 struct mlx4_active_ports actv_ports =
515 mlx4_get_active_ports(dev, t);
5a0d0a61
JM		 516 switch (i) {
517 case RES_QP:
518 initialize_res_quotas(dev, res_alloc, RES_QP,
519 t, dev->caps.num_qps -
520 dev->caps.reserved_qps -
521 mlx4_num_reserved_sqps(dev));
522 break;
523 case RES_CQ:
524 initialize_res_quotas(dev, res_alloc, RES_CQ,
525 t, dev->caps.num_cqs -
526 dev->caps.reserved_cqs);
527 break;
528 case RES_SRQ:
529 initialize_res_quotas(dev, res_alloc, RES_SRQ,
530 t, dev->caps.num_srqs -
531 dev->caps.reserved_srqs);
532 break;
533 case RES_MPT:
534 initialize_res_quotas(dev, res_alloc, RES_MPT,
535 t, dev->caps.num_mpts -
536 dev->caps.reserved_mrws);
537 break;
538 case RES_MTT:
539 initialize_res_quotas(dev, res_alloc, RES_MTT,
540 t, dev->caps.num_mtts -
541 dev->caps.reserved_mtts);
542 break;
543 case RES_MAC:
544 if (t == mlx4_master_func_num(dev)) {
449fc488
MB		 545 int max_vfs_pport = 0;
546 /* Calculate the max vfs per port for */
547 /* both ports. */
548 for (j = 0; j < dev->caps.num_ports;
549 j++) {
550 struct mlx4_slaves_pport slaves_pport =
551 mlx4_phys_to_slaves_pport(dev, j + 1);
552 unsigned current_slaves =
553 bitmap_weight(slaves_pport.slaves,
554 dev->caps.num_ports) - 1;
555 if (max_vfs_pport < current_slaves)
556 max_vfs_pport =
557 current_slaves;
558 }
559 res_alloc->quota[t] =
560 MLX4_MAX_MAC_NUM -
561 2 * max_vfs_pport;
5a0d0a61
JM		 562 res_alloc->guaranteed[t] = 2;
563 for (j = 0; j < MLX4_MAX_PORTS; j++)
449fc488
MB		 564 res_alloc->res_port_free[j] =
565 MLX4_MAX_MAC_NUM;
5a0d0a61
JM		 566 } else {
567 res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
568 res_alloc->guaranteed[t] = 2;
569 }
570 break;
571 case RES_VLAN:
572 if (t == mlx4_master_func_num(dev)) {
573 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
574 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
575 for (j = 0; j < MLX4_MAX_PORTS; j++)
576 res_alloc->res_port_free[j] =
577 res_alloc->quota[t];
578 } else {
579 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
580 res_alloc->guaranteed[t] = 0;
581 }
582 break;
583 case RES_COUNTER:
584 res_alloc->quota[t] = dev->caps.max_counters;
585 res_alloc->guaranteed[t] = 0;
586 if (t == mlx4_master_func_num(dev))
587 res_alloc->res_free = res_alloc->quota[t];
588 break;
589 default:
590 break;
591 }
592 if (i == RES_MAC || i == RES_VLAN) {
449fc488
MB		 593 for (j = 0; j < dev->caps.num_ports; j++)
594 if (test_bit(j, actv_ports.ports))
595 res_alloc->res_port_rsvd[j] +=
596 res_alloc->guaranteed[t];
5a0d0a61
JM		 597 } else {
598 res_alloc->res_reserved += res_alloc->guaranteed[t];
599 }
600 }
601 }
c82e9aa0 602 spin_lock_init(&priv->mfunc.master.res_tracker.lock);
5a0d0a61
JM		 603 return 0;
604
605no_mem_err:
606 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
607 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
608 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
609 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
610 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
611 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
612 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
613 }
614 return -ENOMEM;
c82e9aa0
EC		 615}
616
b8924951
JM		 617void mlx4_free_resource_tracker(struct mlx4_dev *dev,
618 enum mlx4_res_tracker_free_type type)
c82e9aa0
EC		 619{
620 struct mlx4_priv *priv = mlx4_priv(dev);
621 int i;
622
623 if (priv->mfunc.master.res_tracker.slave_list) {
4874080d
JM		 624 if (type != RES_TR_FREE_STRUCTS_ONLY) {
625 for (i = 0; i < dev->num_slaves; i++) {
b8924951
JM		 626 if (type == RES_TR_FREE_ALL ||
627 dev->caps.function != i)
628 mlx4_delete_all_resources_for_slave(dev, i);
4874080d
JM		 629 }
630 /* free master's vlans */
631 i = dev->caps.function;
111c6094 632 mlx4_reset_roce_gids(dev, i);
4874080d
JM		 633 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
634 rem_slave_vlans(dev, i);
635 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
636 }
b8924951
JM		 637
638 if (type != RES_TR_FREE_SLAVES_ONLY) {
5a0d0a61
JM		 639 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
640 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
641 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
642 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
643 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
644 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
645 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
646 }
b8924951
JM		 647 kfree(priv->mfunc.master.res_tracker.slave_list);
648 priv->mfunc.master.res_tracker.slave_list = NULL;
649 }
c82e9aa0
EC		 650 }
651}
652
54679e14
JM		 653static void update_pkey_index(struct mlx4_dev *dev, int slave,
654 struct mlx4_cmd_mailbox *inbox)
c82e9aa0 655{
54679e14
JM		 656 u8 sched = *(u8 *)(inbox->buf + 64);
657 u8 orig_index = *(u8 *)(inbox->buf + 35);
658 u8 new_index;
659 struct mlx4_priv *priv = mlx4_priv(dev);
660 int port;
661
662 port = (sched >> 6 & 1) + 1;
663
664 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
665 *(u8 *)(inbox->buf + 35) = new_index;
54679e14
JM		 666}
667
668static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
669 u8 slave)
670{
671 struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
672 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
673 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
b6ffaeff 674 int port;
c82e9aa0 675
b6ffaeff
JM		 676 if (MLX4_QP_ST_UD == ts) {
677 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
678 if (mlx4_is_eth(dev, port))
449fc488
MB		 679 qp_ctx->pri_path.mgid_index =
680 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
b6ffaeff
JM		 681 else
682 qp_ctx->pri_path.mgid_index = slave | 0x80;
683
684 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
685 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
686 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
687 if (mlx4_is_eth(dev, port)) {
449fc488
MB		 688 qp_ctx->pri_path.mgid_index +=
689 mlx4_get_base_gid_ix(dev, slave, port);
b6ffaeff
JM		 690 qp_ctx->pri_path.mgid_index &= 0x7f;
691 } else {
692 qp_ctx->pri_path.mgid_index = slave & 0x7F;
693 }
694 }
695 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
696 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
697 if (mlx4_is_eth(dev, port)) {
449fc488
MB		 698 qp_ctx->alt_path.mgid_index +=
699 mlx4_get_base_gid_ix(dev, slave, port);
b6ffaeff
JM		 700 qp_ctx->alt_path.mgid_index &= 0x7f;
701 } else {
702 qp_ctx->alt_path.mgid_index = slave & 0x7F;
703 }
704 }
54679e14 705 }
c82e9aa0
EC		 706}
707
3f7fb021
RE		 708static int update_vport_qp_param(struct mlx4_dev *dev,
709 struct mlx4_cmd_mailbox *inbox,
b01978ca 710 u8 slave, u32 qpn)
3f7fb021
RE		 711{
712 struct mlx4_qp_context *qpc = inbox->buf + 8;
713 struct mlx4_vport_oper_state *vp_oper;
714 struct mlx4_priv *priv;
09e05c3f 715 u32 qp_type;
f5956faf 716 int port, err = 0;
3f7fb021
RE		 717
718 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
719 priv = mlx4_priv(dev);
720 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
09e05c3f 721 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3f7fb021
RE		 722
723 if (MLX4_VGT != vp_oper->state.default_vlan) {
b01978ca
JM		 724 /* the reserved QPs (special, proxy, tunnel)
725 * do not operate over vlans
726 */
727 if (mlx4_is_qp_reserved(dev, qpn))
728 return 0;
729
09e05c3f
MB		 730 /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */
731 if (qp_type == MLX4_QP_ST_UD ||
732 (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) {
733 if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) {
734 *(__be32 *)inbox->buf =
735 cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) |
736 MLX4_QP_OPTPAR_VLAN_STRIPPING);
737 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
738 } else {
739 struct mlx4_update_qp_params params = {.flags = 0};
740
f5956faf
OG		 741 err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, &params);
742 if (err)
743 goto out;
09e05c3f
MB		 744 }
745 }
0a6eac24
RE		 746
747 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
748 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
749 qpc->pri_path.vlan_control =
750 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
751 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
752 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
753 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
754 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
755 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
756 } else if (0 != vp_oper->state.default_vlan) {
7677fc96
RE		 757 qpc->pri_path.vlan_control =
758 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
759 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
760 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
761 } else { /* priority tagged */
762 qpc->pri_path.vlan_control =
763 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
764 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
765 }
766
767 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
3f7fb021 768 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
7677fc96
RE		 769 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
770 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
3f7fb021
RE		 771 qpc->pri_path.sched_queue &= 0xC7;
772 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
3f7fb021 773 }
e6b6a231 774 if (vp_oper->state.spoofchk) {
7677fc96 775 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
e6b6a231 776 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
e6b6a231 777 }
f5956faf
OG		 778out:
779 return err;
3f7fb021
RE		 780}
781
c82e9aa0
EC		 782static int mpt_mask(struct mlx4_dev *dev)
783{
784 return dev->caps.num_mpts - 1;
785}
786
1e3f7b32 787static void *find_res(struct mlx4_dev *dev, u64 res_id,
c82e9aa0
EC		 788 enum mlx4_resource type)
789{
790 struct mlx4_priv *priv = mlx4_priv(dev);
791
4af1c048
HHZ		 792 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
793 res_id);
c82e9aa0
EC		 794}
795
aa1ec3dd 796static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
c82e9aa0
EC		 797 enum mlx4_resource type,
798 void *res)
799{
800 struct res_common *r;
801 int err = 0;
802
803 spin_lock_irq(mlx4_tlock(dev));
804 r = find_res(dev, res_id, type);
805 if (!r) {
806 err = -ENONET;
807 goto exit;
808 }
809
810 if (r->state == RES_ANY_BUSY) {
811 err = -EBUSY;
812 goto exit;
813 }
814
815 if (r->owner != slave) {
816 err = -EPERM;
817 goto exit;
818 }
819
820 r->from_state = r->state;
821 r->state = RES_ANY_BUSY;
c82e9aa0
EC		 822
823 if (res)
824 *((struct res_common **)res) = r;
825
826exit:
827 spin_unlock_irq(mlx4_tlock(dev));
828 return err;
829}
830
831int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
832 enum mlx4_resource type,
aa1ec3dd 833 u64 res_id, int *slave)
c82e9aa0
EC		 834{
835
836 struct res_common *r;
837 int err = -ENOENT;
838 int id = res_id;
839
840 if (type == RES_QP)
841 id &= 0x7fffff;
996b0541 842 spin_lock(mlx4_tlock(dev));
c82e9aa0
EC		 843
844 r = find_res(dev, id, type);
845 if (r) {
846 *slave = r->owner;
847 err = 0;
848 }
996b0541 849 spin_unlock(mlx4_tlock(dev));
c82e9aa0
EC		 850
851 return err;
852}
853
aa1ec3dd 854static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
c82e9aa0
EC		 855 enum mlx4_resource type)
856{
857 struct res_common *r;
858
859 spin_lock_irq(mlx4_tlock(dev));
860 r = find_res(dev, res_id, type);
861 if (r)
862 r->state = r->from_state;
863 spin_unlock_irq(mlx4_tlock(dev));
864}
865
866static struct res_common *alloc_qp_tr(int id)
867{
868 struct res_qp *ret;
869
870 ret = kzalloc(sizeof *ret, GFP_KERNEL);
871 if (!ret)
872 return NULL;
873
874 ret->com.res_id = id;
875 ret->com.state = RES_QP_RESERVED;
2531188b 876 ret->local_qpn = id;
c82e9aa0
EC		 877 INIT_LIST_HEAD(&ret->mcg_list);
878 spin_lock_init(&ret->mcg_spl);
2c473ae7 879 atomic_set(&ret->ref_count, 0);
c82e9aa0
EC		 880
881 return &ret->com;
882}
883
884static struct res_common *alloc_mtt_tr(int id, int order)
885{
886 struct res_mtt *ret;
887
888 ret = kzalloc(sizeof *ret, GFP_KERNEL);
889 if (!ret)
890 return NULL;
891
892 ret->com.res_id = id;
893 ret->order = order;
894 ret->com.state = RES_MTT_ALLOCATED;
895 atomic_set(&ret->ref_count, 0);
896
897 return &ret->com;
898}
899
900static struct res_common *alloc_mpt_tr(int id, int key)
901{
902 struct res_mpt *ret;
903
904 ret = kzalloc(sizeof *ret, GFP_KERNEL);
905 if (!ret)
906 return NULL;
907
908 ret->com.res_id = id;
909 ret->com.state = RES_MPT_RESERVED;
910 ret->key = key;
911
912 return &ret->com;
913}
914
915static struct res_common *alloc_eq_tr(int id)
916{
917 struct res_eq *ret;
918
919 ret = kzalloc(sizeof *ret, GFP_KERNEL);
920 if (!ret)
921 return NULL;
922
923 ret->com.res_id = id;
924 ret->com.state = RES_EQ_RESERVED;
925
926 return &ret->com;
927}
928
929static struct res_common *alloc_cq_tr(int id)
930{
931 struct res_cq *ret;
932
933 ret = kzalloc(sizeof *ret, GFP_KERNEL);
934 if (!ret)
935 return NULL;
936
937 ret->com.res_id = id;
938 ret->com.state = RES_CQ_ALLOCATED;
939 atomic_set(&ret->ref_count, 0);
940
941 return &ret->com;
942}
943
944static struct res_common *alloc_srq_tr(int id)
945{
946 struct res_srq *ret;
947
948 ret = kzalloc(sizeof *ret, GFP_KERNEL);
949 if (!ret)
950 return NULL;
951
952 ret->com.res_id = id;
953 ret->com.state = RES_SRQ_ALLOCATED;
954 atomic_set(&ret->ref_count, 0);
955
956 return &ret->com;
957}
958
959static struct res_common *alloc_counter_tr(int id)
960{
961 struct res_counter *ret;
962
963 ret = kzalloc(sizeof *ret, GFP_KERNEL);
964 if (!ret)
965 return NULL;
966
967 ret->com.res_id = id;
968 ret->com.state = RES_COUNTER_ALLOCATED;
969
970 return &ret->com;
971}
972
ba062d52
JM		 973static struct res_common *alloc_xrcdn_tr(int id)
974{
975 struct res_xrcdn *ret;
976
977 ret = kzalloc(sizeof *ret, GFP_KERNEL);
978 if (!ret)
979 return NULL;
980
981 ret->com.res_id = id;
982 ret->com.state = RES_XRCD_ALLOCATED;
983
984 return &ret->com;
985}
986
2c473ae7 987static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
1b9c6b06
HHZ		 988{
989 struct res_fs_rule *ret;
990
991 ret = kzalloc(sizeof *ret, GFP_KERNEL);
992 if (!ret)
993 return NULL;
994
995 ret->com.res_id = id;
996 ret->com.state = RES_FS_RULE_ALLOCATED;
2c473ae7 997 ret->qpn = qpn;
1b9c6b06
HHZ		 998 return &ret->com;
999}
1000
aa1ec3dd 1001static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
c82e9aa0
EC		 1002 int extra)
1003{
1004 struct res_common *ret;
1005
1006 switch (type) {
1007 case RES_QP:
1008 ret = alloc_qp_tr(id);
1009 break;
1010 case RES_MPT:
1011 ret = alloc_mpt_tr(id, extra);
1012 break;
1013 case RES_MTT:
1014 ret = alloc_mtt_tr(id, extra);
1015 break;
1016 case RES_EQ:
1017 ret = alloc_eq_tr(id);
1018 break;
1019 case RES_CQ:
1020 ret = alloc_cq_tr(id);
1021 break;
1022 case RES_SRQ:
1023 ret = alloc_srq_tr(id);
1024 break;
1025 case RES_MAC:
c20862c8 1026 pr_err("implementation missing\n");
c82e9aa0
EC		 1027 return NULL;
1028 case RES_COUNTER:
1029 ret = alloc_counter_tr(id);
1030 break;
ba062d52
JM		 1031 case RES_XRCD:
1032 ret = alloc_xrcdn_tr(id);
1033 break;
1b9c6b06 1034 case RES_FS_RULE:
2c473ae7 1035 ret = alloc_fs_rule_tr(id, extra);
1b9c6b06 1036 break;
c82e9aa0
EC		 1037 default:
1038 return NULL;
1039 }
1040 if (ret)
1041 ret->owner = slave;
1042
1043 return ret;
1044}
1045
aa1ec3dd 1046static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
c82e9aa0
EC		 1047 enum mlx4_resource type, int extra)
1048{
1049 int i;
1050 int err;
1051 struct mlx4_priv *priv = mlx4_priv(dev);
1052 struct res_common **res_arr;
1053 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4af1c048 1054 struct rb_root *root = &tracker->res_tree[type];
c82e9aa0
EC		 1055
1056 res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
1057 if (!res_arr)
1058 return -ENOMEM;
1059
1060 for (i = 0; i < count; ++i) {
1061 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1062 if (!res_arr[i]) {
1063 for (--i; i >= 0; --i)
1064 kfree(res_arr[i]);
1065
1066 kfree(res_arr);
1067 return -ENOMEM;
1068 }
1069 }
1070
1071 spin_lock_irq(mlx4_tlock(dev));
1072 for (i = 0; i < count; ++i) {
1073 if (find_res(dev, base + i, type)) {
1074 err = -EEXIST;
1075 goto undo;
1076 }
4af1c048 1077 err = res_tracker_insert(root, res_arr[i]);
c82e9aa0
EC		 1078 if (err)
1079 goto undo;
1080 list_add_tail(&res_arr[i]->list,
1081 &tracker->slave_list[slave].res_list[type]);
1082 }
1083 spin_unlock_irq(mlx4_tlock(dev));
1084 kfree(res_arr);
1085
1086 return 0;
1087
1088undo:
1089 for (--i; i >= base; --i)
4af1c048 1090 rb_erase(&res_arr[i]->node, root);
c82e9aa0
EC		 1091
1092 spin_unlock_irq(mlx4_tlock(dev));
1093
1094 for (i = 0; i < count; ++i)
1095 kfree(res_arr[i]);
1096
1097 kfree(res_arr);
1098
1099 return err;
1100}
1101
1102static int remove_qp_ok(struct res_qp *res)
1103{
2c473ae7
HHZ		 1104 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1105 !list_empty(&res->mcg_list)) {
1106 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1107 res->com.state, atomic_read(&res->ref_count));
c82e9aa0 1108 return -EBUSY;
2c473ae7 1109 } else if (res->com.state != RES_QP_RESERVED) {
c82e9aa0 1110 return -EPERM;
2c473ae7 1111 }
c82e9aa0
EC		 1112
1113 return 0;
1114}
1115
1116static int remove_mtt_ok(struct res_mtt *res, int order)
1117{
1118 if (res->com.state == RES_MTT_BUSY ||
1119 atomic_read(&res->ref_count)) {
c20862c8
AV		 1120 pr_devel("%s-%d: state %s, ref_count %d\n",
1121 __func__, __LINE__,
1122 mtt_states_str(res->com.state),
1123 atomic_read(&res->ref_count));
c82e9aa0
EC		 1124 return -EBUSY;
1125 } else if (res->com.state != RES_MTT_ALLOCATED)
1126 return -EPERM;
1127 else if (res->order != order)
1128 return -EINVAL;
1129
1130 return 0;
1131}
1132
1133static int remove_mpt_ok(struct res_mpt *res)
1134{
1135 if (res->com.state == RES_MPT_BUSY)
1136 return -EBUSY;
1137 else if (res->com.state != RES_MPT_RESERVED)
1138 return -EPERM;
1139
1140 return 0;
1141}
1142
1143static int remove_eq_ok(struct res_eq *res)
1144{
1145 if (res->com.state == RES_MPT_BUSY)
1146 return -EBUSY;
1147 else if (res->com.state != RES_MPT_RESERVED)
1148 return -EPERM;
1149
1150 return 0;
1151}
1152
1153static int remove_counter_ok(struct res_counter *res)
1154{
1155 if (res->com.state == RES_COUNTER_BUSY)
1156 return -EBUSY;
1157 else if (res->com.state != RES_COUNTER_ALLOCATED)
1158 return -EPERM;
1159
1160 return 0;
1161}
1162
ba062d52
JM		 1163static int remove_xrcdn_ok(struct res_xrcdn *res)
1164{
1165 if (res->com.state == RES_XRCD_BUSY)
1166 return -EBUSY;
1167 else if (res->com.state != RES_XRCD_ALLOCATED)
1168 return -EPERM;
1169
1170 return 0;
1171}
1172
1b9c6b06
HHZ		 1173static int remove_fs_rule_ok(struct res_fs_rule *res)
1174{
1175 if (res->com.state == RES_FS_RULE_BUSY)
1176 return -EBUSY;
1177 else if (res->com.state != RES_FS_RULE_ALLOCATED)
1178 return -EPERM;
1179
1180 return 0;
1181}
1182
c82e9aa0
EC		 1183static int remove_cq_ok(struct res_cq *res)
1184{
1185 if (res->com.state == RES_CQ_BUSY)
1186 return -EBUSY;
1187 else if (res->com.state != RES_CQ_ALLOCATED)
1188 return -EPERM;
1189
1190 return 0;
1191}
1192
1193static int remove_srq_ok(struct res_srq *res)
1194{
1195 if (res->com.state == RES_SRQ_BUSY)
1196 return -EBUSY;
1197 else if (res->com.state != RES_SRQ_ALLOCATED)
1198 return -EPERM;
1199
1200 return 0;
1201}
1202
1203static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1204{
1205 switch (type) {
1206 case RES_QP:
1207 return remove_qp_ok((struct res_qp *)res);
1208 case RES_CQ:
1209 return remove_cq_ok((struct res_cq *)res);
1210 case RES_SRQ:
1211 return remove_srq_ok((struct res_srq *)res);
1212 case RES_MPT:
1213 return remove_mpt_ok((struct res_mpt *)res);
1214 case RES_MTT:
1215 return remove_mtt_ok((struct res_mtt *)res, extra);
1216 case RES_MAC:
1217 return -ENOSYS;
1218 case RES_EQ:
1219 return remove_eq_ok((struct res_eq *)res);
1220 case RES_COUNTER:
1221 return remove_counter_ok((struct res_counter *)res);
ba062d52
JM		 1222 case RES_XRCD:
1223 return remove_xrcdn_ok((struct res_xrcdn *)res);
1b9c6b06
HHZ		 1224 case RES_FS_RULE:
1225 return remove_fs_rule_ok((struct res_fs_rule *)res);
c82e9aa0
EC		 1226 default:
1227 return -EINVAL;
1228 }
1229}
1230
aa1ec3dd 1231static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
c82e9aa0
EC		 1232 enum mlx4_resource type, int extra)
1233{
aa1ec3dd 1234 u64 i;
c82e9aa0
EC		 1235 int err;
1236 struct mlx4_priv *priv = mlx4_priv(dev);
1237 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1238 struct res_common *r;
1239
1240 spin_lock_irq(mlx4_tlock(dev));
1241 for (i = base; i < base + count; ++i) {
4af1c048 1242 r = res_tracker_lookup(&tracker->res_tree[type], i);
c82e9aa0
EC		 1243 if (!r) {
1244 err = -ENOENT;
1245 goto out;
1246 }
1247 if (r->owner != slave) {
1248 err = -EPERM;
1249 goto out;
1250 }
1251 err = remove_ok(r, type, extra);
1252 if (err)
1253 goto out;
1254 }
1255
1256 for (i = base; i < base + count; ++i) {
4af1c048
HHZ		 1257 r = res_tracker_lookup(&tracker->res_tree[type], i);
1258 rb_erase(&r->node, &tracker->res_tree[type]);
c82e9aa0
EC		 1259 list_del(&r->list);
1260 kfree(r);
1261 }
1262 err = 0;
1263
1264out:
1265 spin_unlock_irq(mlx4_tlock(dev));
1266
1267 return err;
1268}
1269
1270static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1271 enum res_qp_states state, struct res_qp **qp,
1272 int alloc)
1273{
1274 struct mlx4_priv *priv = mlx4_priv(dev);
1275 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1276 struct res_qp *r;
1277 int err = 0;
1278
1279 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1280 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
c82e9aa0
EC		 1281 if (!r)
1282 err = -ENOENT;
1283 else if (r->com.owner != slave)
1284 err = -EPERM;
1285 else {
1286 switch (state) {
1287 case RES_QP_BUSY:
aa1ec3dd 1288 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
c82e9aa0
EC		 1289 __func__, r->com.res_id);
1290 err = -EBUSY;
1291 break;
1292
1293 case RES_QP_RESERVED:
1294 if (r->com.state == RES_QP_MAPPED && !alloc)
1295 break;
1296
aa1ec3dd 1297 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
c82e9aa0
EC		 1298 err = -EINVAL;
1299 break;
1300
1301 case RES_QP_MAPPED:
1302 if ((r->com.state == RES_QP_RESERVED && alloc) ||
1303 r->com.state == RES_QP_HW)
1304 break;
1305 else {
aa1ec3dd 1306 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
c82e9aa0
EC		 1307 r->com.res_id);
1308 err = -EINVAL;
1309 }
1310
1311 break;
1312
1313 case RES_QP_HW:
1314 if (r->com.state != RES_QP_MAPPED)
1315 err = -EINVAL;
1316 break;
1317 default:
1318 err = -EINVAL;
1319 }
1320
1321 if (!err) {
1322 r->com.from_state = r->com.state;
1323 r->com.to_state = state;
1324 r->com.state = RES_QP_BUSY;
1325 if (qp)
64699336 1326 *qp = r;
c82e9aa0
EC		 1327 }
1328 }
1329
1330 spin_unlock_irq(mlx4_tlock(dev));
1331
1332 return err;
1333}
1334
1335static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1336 enum res_mpt_states state, struct res_mpt **mpt)
1337{
1338 struct mlx4_priv *priv = mlx4_priv(dev);
1339 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1340 struct res_mpt *r;
1341 int err = 0;
1342
1343 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1344 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
c82e9aa0
EC		 1345 if (!r)
1346 err = -ENOENT;
1347 else if (r->com.owner != slave)
1348 err = -EPERM;
1349 else {
1350 switch (state) {
1351 case RES_MPT_BUSY:
1352 err = -EINVAL;
1353 break;
1354
1355 case RES_MPT_RESERVED:
1356 if (r->com.state != RES_MPT_MAPPED)
1357 err = -EINVAL;
1358 break;
1359
1360 case RES_MPT_MAPPED:
1361 if (r->com.state != RES_MPT_RESERVED &&
1362 r->com.state != RES_MPT_HW)
1363 err = -EINVAL;
1364 break;
1365
1366 case RES_MPT_HW:
1367 if (r->com.state != RES_MPT_MAPPED)
1368 err = -EINVAL;
1369 break;
1370 default:
1371 err = -EINVAL;
1372 }
1373
1374 if (!err) {
1375 r->com.from_state = r->com.state;
1376 r->com.to_state = state;
1377 r->com.state = RES_MPT_BUSY;
1378 if (mpt)
64699336 1379 *mpt = r;
c82e9aa0
EC		 1380 }
1381 }
1382
1383 spin_unlock_irq(mlx4_tlock(dev));
1384
1385 return err;
1386}
1387
1388static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1389 enum res_eq_states state, struct res_eq **eq)
1390{
1391 struct mlx4_priv *priv = mlx4_priv(dev);
1392 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1393 struct res_eq *r;
1394 int err = 0;
1395
1396 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1397 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
c82e9aa0
EC		 1398 if (!r)
1399 err = -ENOENT;
1400 else if (r->com.owner != slave)
1401 err = -EPERM;
1402 else {
1403 switch (state) {
1404 case RES_EQ_BUSY:
1405 err = -EINVAL;
1406 break;
1407
1408 case RES_EQ_RESERVED:
1409 if (r->com.state != RES_EQ_HW)
1410 err = -EINVAL;
1411 break;
1412
1413 case RES_EQ_HW:
1414 if (r->com.state != RES_EQ_RESERVED)
1415 err = -EINVAL;
1416 break;
1417
1418 default:
1419 err = -EINVAL;
1420 }
1421
1422 if (!err) {
1423 r->com.from_state = r->com.state;
1424 r->com.to_state = state;
1425 r->com.state = RES_EQ_BUSY;
1426 if (eq)
1427 *eq = r;
1428 }
1429 }
1430
1431 spin_unlock_irq(mlx4_tlock(dev));
1432
1433 return err;
1434}
1435
1436static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1437 enum res_cq_states state, struct res_cq **cq)
1438{
1439 struct mlx4_priv *priv = mlx4_priv(dev);
1440 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1441 struct res_cq *r;
1442 int err;
1443
1444 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1445 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
c9218a9e 1446 if (!r) {
c82e9aa0 1447 err = -ENOENT;
c9218a9e 1448 } else if (r->com.owner != slave) {
c82e9aa0 1449 err = -EPERM;
c9218a9e
PB		 1450 } else if (state == RES_CQ_ALLOCATED) {
1451 if (r->com.state != RES_CQ_HW)
c82e9aa0 1452 err = -EINVAL;
c9218a9e
PB		 1453 else if (atomic_read(&r->ref_count))
1454 err = -EBUSY;
1455 else
1456 err = 0;
1457 } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1458 err = -EINVAL;
1459 } else {
1460 err = 0;
1461 }
c82e9aa0 1462
c9218a9e
PB		 1463 if (!err) {
1464 r->com.from_state = r->com.state;
1465 r->com.to_state = state;
1466 r->com.state = RES_CQ_BUSY;
1467 if (cq)
1468 *cq = r;
c82e9aa0
EC		 1469 }
1470
1471 spin_unlock_irq(mlx4_tlock(dev));
1472
1473 return err;
1474}
1475
1476static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
f088cbb8 1477 enum res_srq_states state, struct res_srq **srq)
c82e9aa0
EC		 1478{
1479 struct mlx4_priv *priv = mlx4_priv(dev);
1480 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1481 struct res_srq *r;
1482 int err = 0;
1483
1484 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1485 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
f088cbb8 1486 if (!r) {
c82e9aa0 1487 err = -ENOENT;
f088cbb8 1488 } else if (r->com.owner != slave) {
c82e9aa0 1489 err = -EPERM;
f088cbb8
PB		 1490 } else if (state == RES_SRQ_ALLOCATED) {
1491 if (r->com.state != RES_SRQ_HW)
c82e9aa0 1492 err = -EINVAL;
f088cbb8
PB		 1493 else if (atomic_read(&r->ref_count))
1494 err = -EBUSY;
1495 } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1496 err = -EINVAL;
1497 }
c82e9aa0 1498
f088cbb8
PB		 1499 if (!err) {
1500 r->com.from_state = r->com.state;
1501 r->com.to_state = state;
1502 r->com.state = RES_SRQ_BUSY;
1503 if (srq)
1504 *srq = r;
c82e9aa0
EC		 1505 }
1506
1507 spin_unlock_irq(mlx4_tlock(dev));
1508
1509 return err;
1510}
1511
1512static void res_abort_move(struct mlx4_dev *dev, int slave,
1513 enum mlx4_resource type, int id)
1514{
1515 struct mlx4_priv *priv = mlx4_priv(dev);
1516 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1517 struct res_common *r;
1518
1519 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1520 r = res_tracker_lookup(&tracker->res_tree[type], id);
c82e9aa0
EC		 1521 if (r && (r->owner == slave))
1522 r->state = r->from_state;
1523 spin_unlock_irq(mlx4_tlock(dev));
1524}
1525
1526static void res_end_move(struct mlx4_dev *dev, int slave,
1527 enum mlx4_resource type, int id)
1528{
1529 struct mlx4_priv *priv = mlx4_priv(dev);
1530 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1531 struct res_common *r;
1532
1533 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1534 r = res_tracker_lookup(&tracker->res_tree[type], id);
c82e9aa0
EC		 1535 if (r && (r->owner == slave))
1536 r->state = r->to_state;
1537 spin_unlock_irq(mlx4_tlock(dev));
1538}
1539
1540static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1541{
e2c76824
JM		 1542 return mlx4_is_qp_reserved(dev, qpn) &&
1543 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
c82e9aa0
EC		 1544}
1545
54679e14
JM		 1546static int fw_reserved(struct mlx4_dev *dev, int qpn)
1547{
1548 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
c82e9aa0
EC		 1549}
1550
1551static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1552 u64 in_param, u64 *out_param)
1553{
1554 int err;
1555 int count;
1556 int align;
1557 int base;
1558 int qpn;
ddae0349 1559 u8 flags;
c82e9aa0
EC		 1560
1561 switch (op) {
1562 case RES_OP_RESERVE:
2d5c57d7 1563 count = get_param_l(&in_param) & 0xffffff;
ddae0349
EE		 1564 /* Turn off all unsupported QP allocation flags that the
1565 * slave tries to set.
1566 */
1567 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
c82e9aa0 1568 align = get_param_h(&in_param);
146f3ef4 1569 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 1570 if (err)
1571 return err;
1572
ddae0349 1573 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
146f3ef4
JM		 1574 if (err) {
1575 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1576 return err;
1577 }
1578
c82e9aa0
EC		 1579 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1580 if (err) {
146f3ef4 1581 mlx4_release_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 1582 __mlx4_qp_release_range(dev, base, count);
1583 return err;
1584 }
1585 set_param_l(out_param, base);
1586 break;
1587 case RES_OP_MAP_ICM:
1588 qpn = get_param_l(&in_param) & 0x7fffff;
1589 if (valid_reserved(dev, slave, qpn)) {
1590 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1591 if (err)
1592 return err;
1593 }
1594
1595 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1596 NULL, 1);
1597 if (err)
1598 return err;
1599
54679e14 1600 if (!fw_reserved(dev, qpn)) {
40f2287b 1601 err = __mlx4_qp_alloc_icm(dev, qpn, GFP_KERNEL);
c82e9aa0
EC		 1602 if (err) {
1603 res_abort_move(dev, slave, RES_QP, qpn);
1604 return err;
1605 }
1606 }
1607
1608 res_end_move(dev, slave, RES_QP, qpn);
1609 break;
1610
1611 default:
1612 err = -EINVAL;
1613 break;
1614 }
1615 return err;
1616}
1617
1618static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1619 u64 in_param, u64 *out_param)
1620{
1621 int err = -EINVAL;
1622 int base;
1623 int order;
1624
1625 if (op != RES_OP_RESERVE_AND_MAP)
1626 return err;
1627
1628 order = get_param_l(&in_param);
146f3ef4
JM		 1629
1630 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1631 if (err)
1632 return err;
1633
c82e9aa0 1634 base = __mlx4_alloc_mtt_range(dev, order);
146f3ef4
JM		 1635 if (base == -1) {
1636 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 1637 return -ENOMEM;
146f3ef4 1638 }
c82e9aa0
EC		 1639
1640 err = add_res_range(dev, slave, base, 1, RES_MTT, order);
146f3ef4
JM		 1641 if (err) {
1642 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 1643 __mlx4_free_mtt_range(dev, base, order);
146f3ef4 1644 } else {
c82e9aa0 1645 set_param_l(out_param, base);
146f3ef4 1646 }
c82e9aa0
EC		 1647
1648 return err;
1649}
1650
1651static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1652 u64 in_param, u64 *out_param)
1653{
1654 int err = -EINVAL;
1655 int index;
1656 int id;
1657 struct res_mpt *mpt;
1658
1659 switch (op) {
1660 case RES_OP_RESERVE:
146f3ef4
JM		 1661 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1662 if (err)
1663 break;
1664
b20e519a 1665 index = __mlx4_mpt_reserve(dev);
146f3ef4
JM		 1666 if (index == -1) {
1667 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
c82e9aa0 1668 break;
146f3ef4 1669 }
c82e9aa0
EC		 1670 id = index & mpt_mask(dev);
1671
1672 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1673 if (err) {
146f3ef4 1674 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
b20e519a 1675 __mlx4_mpt_release(dev, index);
c82e9aa0
EC		 1676 break;
1677 }
1678 set_param_l(out_param, index);
1679 break;
1680 case RES_OP_MAP_ICM:
1681 index = get_param_l(&in_param);
1682 id = index & mpt_mask(dev);
1683 err = mr_res_start_move_to(dev, slave, id,
1684 RES_MPT_MAPPED, &mpt);
1685 if (err)
1686 return err;
1687
40f2287b 1688 err = __mlx4_mpt_alloc_icm(dev, mpt->key, GFP_KERNEL);
c82e9aa0
EC		 1689 if (err) {
1690 res_abort_move(dev, slave, RES_MPT, id);
1691 return err;
1692 }
1693
1694 res_end_move(dev, slave, RES_MPT, id);
1695 break;
1696 }
1697 return err;
1698}
1699
1700static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1701 u64 in_param, u64 *out_param)
1702{
1703 int cqn;
1704 int err;
1705
1706 switch (op) {
1707 case RES_OP_RESERVE_AND_MAP:
146f3ef4 1708 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 1709 if (err)
1710 break;
1711
146f3ef4
JM		 1712 err = __mlx4_cq_alloc_icm(dev, &cqn);
1713 if (err) {
1714 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1715 break;
1716 }
1717
c82e9aa0
EC		 1718 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1719 if (err) {
146f3ef4 1720 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 1721 __mlx4_cq_free_icm(dev, cqn);
1722 break;
1723 }
1724
1725 set_param_l(out_param, cqn);
1726 break;
1727
1728 default:
1729 err = -EINVAL;
1730 }
1731
1732 return err;
1733}
1734
1735static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1736 u64 in_param, u64 *out_param)
1737{
1738 int srqn;
1739 int err;
1740
1741 switch (op) {
1742 case RES_OP_RESERVE_AND_MAP:
146f3ef4 1743 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 1744 if (err)
1745 break;
1746
146f3ef4
JM		 1747 err = __mlx4_srq_alloc_icm(dev, &srqn);
1748 if (err) {
1749 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1750 break;
1751 }
1752
c82e9aa0
EC		 1753 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1754 if (err) {
146f3ef4 1755 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 1756 __mlx4_srq_free_icm(dev, srqn);
1757 break;
1758 }
1759
1760 set_param_l(out_param, srqn);
1761 break;
1762
1763 default:
1764 err = -EINVAL;
1765 }
1766
1767 return err;
1768}
1769
2f5bb473
JM		 1770static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1771 u8 smac_index, u64 *mac)
1772{
1773 struct mlx4_priv *priv = mlx4_priv(dev);
1774 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1775 struct list_head *mac_list =
1776 &tracker->slave_list[slave].res_list[RES_MAC];
1777 struct mac_res *res, *tmp;
1778
1779 list_for_each_entry_safe(res, tmp, mac_list, list) {
1780 if (res->smac_index == smac_index && res->port == (u8) port) {
1781 *mac = res->mac;
1782 return 0;
1783 }
1784 }
1785 return -ENOENT;
1786}
1787
1788static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
c82e9aa0
EC		 1789{
1790 struct mlx4_priv *priv = mlx4_priv(dev);
1791 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2f5bb473
JM		 1792 struct list_head *mac_list =
1793 &tracker->slave_list[slave].res_list[RES_MAC];
1794 struct mac_res *res, *tmp;
1795
1796 list_for_each_entry_safe(res, tmp, mac_list, list) {
1797 if (res->mac == mac && res->port == (u8) port) {
1798 /* mac found. update ref count */
1799 ++res->ref_count;
1800 return 0;
1801 }
1802 }
c82e9aa0 1803
146f3ef4
JM		 1804 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1805 return -EINVAL;
c82e9aa0 1806 res = kzalloc(sizeof *res, GFP_KERNEL);
146f3ef4
JM		 1807 if (!res) {
1808 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
c82e9aa0 1809 return -ENOMEM;
146f3ef4 1810 }
c82e9aa0
EC		 1811 res->mac = mac;
1812 res->port = (u8) port;
2f5bb473
JM		 1813 res->smac_index = smac_index;
1814 res->ref_count = 1;
c82e9aa0
EC		 1815 list_add_tail(&res->list,
1816 &tracker->slave_list[slave].res_list[RES_MAC]);
1817 return 0;
1818}
1819
1820static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1821 int port)
1822{
1823 struct mlx4_priv *priv = mlx4_priv(dev);
1824 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1825 struct list_head *mac_list =
1826 &tracker->slave_list[slave].res_list[RES_MAC];
1827 struct mac_res *res, *tmp;
1828
1829 list_for_each_entry_safe(res, tmp, mac_list, list) {
1830 if (res->mac == mac && res->port == (u8) port) {
2f5bb473
JM		 1831 if (!--res->ref_count) {
1832 list_del(&res->list);
1833 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1834 kfree(res);
1835 }
c82e9aa0
EC		 1836 break;
1837 }
1838 }
1839}
1840
1841static void rem_slave_macs(struct mlx4_dev *dev, int slave)
1842{
1843 struct mlx4_priv *priv = mlx4_priv(dev);
1844 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1845 struct list_head *mac_list =
1846 &tracker->slave_list[slave].res_list[RES_MAC];
1847 struct mac_res *res, *tmp;
2f5bb473 1848 int i;
c82e9aa0
EC		 1849
1850 list_for_each_entry_safe(res, tmp, mac_list, list) {
1851 list_del(&res->list);
2f5bb473
JM		 1852 /* dereference the mac the num times the slave referenced it */
1853 for (i = 0; i < res->ref_count; i++)
1854 __mlx4_unregister_mac(dev, res->port, res->mac);
146f3ef4 1855 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
c82e9aa0
EC		 1856 kfree(res);
1857 }
1858}
1859
1860static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 1861 u64 in_param, u64 *out_param, int in_port)
c82e9aa0
EC		 1862{
1863 int err = -EINVAL;
1864 int port;
1865 u64 mac;
2f5bb473 1866 u8 smac_index;
c82e9aa0
EC		 1867
1868 if (op != RES_OP_RESERVE_AND_MAP)
1869 return err;
1870
acddd5dd 1871 port = !in_port ? get_param_l(out_param) : in_port;
449fc488
MB		 1872 port = mlx4_slave_convert_port(
1873 dev, slave, port);
1874
1875 if (port < 0)
1876 return -EINVAL;
c82e9aa0
EC		 1877 mac = in_param;
1878
1879 err = __mlx4_register_mac(dev, port, mac);
1880 if (err >= 0) {
2f5bb473 1881 smac_index = err;
c82e9aa0
EC		 1882 set_param_l(out_param, err);
1883 err = 0;
1884 }
1885
1886 if (!err) {
2f5bb473 1887 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
c82e9aa0
EC		 1888 if (err)
1889 __mlx4_unregister_mac(dev, port, mac);
1890 }
1891 return err;
1892}
1893
4874080d
JM		 1894static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1895 int port, int vlan_index)
ffe455ad 1896{
4874080d
JM		 1897 struct mlx4_priv *priv = mlx4_priv(dev);
1898 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1899 struct list_head *vlan_list =
1900 &tracker->slave_list[slave].res_list[RES_VLAN];
1901 struct vlan_res *res, *tmp;
1902
1903 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1904 if (res->vlan == vlan && res->port == (u8) port) {
1905 /* vlan found. update ref count */
1906 ++res->ref_count;
1907 return 0;
1908 }
1909 }
1910
146f3ef4
JM		 1911 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
1912 return -EINVAL;
4874080d 1913 res = kzalloc(sizeof(*res), GFP_KERNEL);
146f3ef4
JM		 1914 if (!res) {
1915 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
4874080d 1916 return -ENOMEM;
146f3ef4 1917 }
4874080d
JM		 1918 res->vlan = vlan;
1919 res->port = (u8) port;
1920 res->vlan_index = vlan_index;
1921 res->ref_count = 1;
1922 list_add_tail(&res->list,
1923 &tracker->slave_list[slave].res_list[RES_VLAN]);
ffe455ad
EE		 1924 return 0;
1925}
1926
4874080d
JM		 1927
1928static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1929 int port)
1930{
1931 struct mlx4_priv *priv = mlx4_priv(dev);
1932 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1933 struct list_head *vlan_list =
1934 &tracker->slave_list[slave].res_list[RES_VLAN];
1935 struct vlan_res *res, *tmp;
1936
1937 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1938 if (res->vlan == vlan && res->port == (u8) port) {
1939 if (!--res->ref_count) {
1940 list_del(&res->list);
146f3ef4
JM		 1941 mlx4_release_resource(dev, slave, RES_VLAN,
1942 1, port);
4874080d
JM		 1943 kfree(res);
1944 }
1945 break;
1946 }
1947 }
1948}
1949
1950static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
1951{
1952 struct mlx4_priv *priv = mlx4_priv(dev);
1953 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1954 struct list_head *vlan_list =
1955 &tracker->slave_list[slave].res_list[RES_VLAN];
1956 struct vlan_res *res, *tmp;
1957 int i;
1958
1959 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1960 list_del(&res->list);
1961 /* dereference the vlan the num times the slave referenced it */
1962 for (i = 0; i < res->ref_count; i++)
1963 __mlx4_unregister_vlan(dev, res->port, res->vlan);
146f3ef4 1964 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
4874080d
JM		 1965 kfree(res);
1966 }
1967}
1968
1969static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2c957ff2 1970 u64 in_param, u64 *out_param, int in_port)
4874080d 1971{
2c957ff2
JM		 1972 struct mlx4_priv *priv = mlx4_priv(dev);
1973 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
4874080d
JM		 1974 int err;
1975 u16 vlan;
1976 int vlan_index;
2c957ff2
JM		 1977 int port;
1978
1979 port = !in_port ? get_param_l(out_param) : in_port;
4874080d
JM		 1980
1981 if (!port || op != RES_OP_RESERVE_AND_MAP)
1982 return -EINVAL;
1983
449fc488
MB		 1984 port = mlx4_slave_convert_port(
1985 dev, slave, port);
1986
1987 if (port < 0)
1988 return -EINVAL;
2c957ff2
JM		 1989 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
1990 if (!in_port && port > 0 && port <= dev->caps.num_ports) {
1991 slave_state[slave].old_vlan_api = true;
1992 return 0;
1993 }
1994
4874080d
JM		 1995 vlan = (u16) in_param;
1996
1997 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
1998 if (!err) {
1999 set_param_l(out_param, (u32) vlan_index);
2000 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
2001 if (err)
2002 __mlx4_unregister_vlan(dev, port, vlan);
2003 }
2004 return err;
2005}
2006
ba062d52
JM		 2007static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2008 u64 in_param, u64 *out_param)
2009{
2010 u32 index;
2011 int err;
2012
2013 if (op != RES_OP_RESERVE)
2014 return -EINVAL;
2015
146f3ef4 2016 err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 2017 if (err)
2018 return err;
2019
146f3ef4
JM		 2020 err = __mlx4_counter_alloc(dev, &index);
2021 if (err) {
2022 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2023 return err;
2024 }
2025
ba062d52 2026 err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
146f3ef4 2027 if (err) {
ba062d52 2028 __mlx4_counter_free(dev, index);
146f3ef4
JM		 2029 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2030 } else {
ba062d52 2031 set_param_l(out_param, index);
146f3ef4 2032 }
ba062d52
JM		 2033
2034 return err;
2035}
2036
2037static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2038 u64 in_param, u64 *out_param)
2039{
2040 u32 xrcdn;
2041 int err;
2042
2043 if (op != RES_OP_RESERVE)
2044 return -EINVAL;
2045
2046 err = __mlx4_xrcd_alloc(dev, &xrcdn);
2047 if (err)
2048 return err;
2049
2050 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2051 if (err)
2052 __mlx4_xrcd_free(dev, xrcdn);
2053 else
2054 set_param_l(out_param, xrcdn);
2055
2056 return err;
2057}
2058
c82e9aa0
EC		 2059int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2060 struct mlx4_vhcr *vhcr,
2061 struct mlx4_cmd_mailbox *inbox,
2062 struct mlx4_cmd_mailbox *outbox,
2063 struct mlx4_cmd_info *cmd)
2064{
2065 int err;
2066 int alop = vhcr->op_modifier;
2067
acddd5dd 2068 switch (vhcr->in_modifier & 0xFF) {
c82e9aa0
EC		 2069 case RES_QP:
2070 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2071 vhcr->in_param, &vhcr->out_param);
2072 break;
2073
2074 case RES_MTT:
2075 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2076 vhcr->in_param, &vhcr->out_param);
2077 break;
2078
2079 case RES_MPT:
2080 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2081 vhcr->in_param, &vhcr->out_param);
2082 break;
2083
2084 case RES_CQ:
2085 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2086 vhcr->in_param, &vhcr->out_param);
2087 break;
2088
2089 case RES_SRQ:
2090 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2091 vhcr->in_param, &vhcr->out_param);
2092 break;
2093
2094 case RES_MAC:
2095 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2096 vhcr->in_param, &vhcr->out_param,
2097 (vhcr->in_modifier >> 8) & 0xFF);
c82e9aa0
EC		 2098 break;
2099
ffe455ad
EE		 2100 case RES_VLAN:
2101 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2102 vhcr->in_param, &vhcr->out_param,
2103 (vhcr->in_modifier >> 8) & 0xFF);
ffe455ad
EE		 2104 break;
2105
ba062d52
JM		 2106 case RES_COUNTER:
2107 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
2108 vhcr->in_param, &vhcr->out_param);
2109 break;
2110
2111 case RES_XRCD:
2112 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2113 vhcr->in_param, &vhcr->out_param);
2114 break;
2115
c82e9aa0
EC		 2116 default:
2117 err = -EINVAL;
2118 break;
2119 }
2120
2121 return err;
2122}
2123
2124static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2125 u64 in_param)
2126{
2127 int err;
2128 int count;
2129 int base;
2130 int qpn;
2131
2132 switch (op) {
2133 case RES_OP_RESERVE:
2134 base = get_param_l(&in_param) & 0x7fffff;
2135 count = get_param_h(&in_param);
2136 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2137 if (err)
2138 break;
146f3ef4 2139 mlx4_release_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 2140 __mlx4_qp_release_range(dev, base, count);
2141 break;
2142 case RES_OP_MAP_ICM:
2143 qpn = get_param_l(&in_param) & 0x7fffff;
2144 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2145 NULL, 0);
2146 if (err)
2147 return err;
2148
54679e14 2149 if (!fw_reserved(dev, qpn))
c82e9aa0
EC		 2150 __mlx4_qp_free_icm(dev, qpn);
2151
2152 res_end_move(dev, slave, RES_QP, qpn);
2153
2154 if (valid_reserved(dev, slave, qpn))
2155 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2156 break;
2157 default:
2158 err = -EINVAL;
2159 break;
2160 }
2161 return err;
2162}
2163
2164static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2165 u64 in_param, u64 *out_param)
2166{
2167 int err = -EINVAL;
2168 int base;
2169 int order;
2170
2171 if (op != RES_OP_RESERVE_AND_MAP)
2172 return err;
2173
2174 base = get_param_l(&in_param);
2175 order = get_param_h(&in_param);
2176 err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
146f3ef4
JM		 2177 if (!err) {
2178 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 2179 __mlx4_free_mtt_range(dev, base, order);
146f3ef4 2180 }
c82e9aa0
EC		 2181 return err;
2182}
2183
2184static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2185 u64 in_param)
2186{
2187 int err = -EINVAL;
2188 int index;
2189 int id;
2190 struct res_mpt *mpt;
2191
2192 switch (op) {
2193 case RES_OP_RESERVE:
2194 index = get_param_l(&in_param);
2195 id = index & mpt_mask(dev);
2196 err = get_res(dev, slave, id, RES_MPT, &mpt);
2197 if (err)
2198 break;
2199 index = mpt->key;
2200 put_res(dev, slave, id, RES_MPT);
2201
2202 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2203 if (err)
2204 break;
146f3ef4 2205 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
b20e519a 2206 __mlx4_mpt_release(dev, index);
c82e9aa0
EC		 2207 break;
2208 case RES_OP_MAP_ICM:
2209 index = get_param_l(&in_param);
2210 id = index & mpt_mask(dev);
2211 err = mr_res_start_move_to(dev, slave, id,
2212 RES_MPT_RESERVED, &mpt);
2213 if (err)
2214 return err;
2215
b20e519a 2216 __mlx4_mpt_free_icm(dev, mpt->key);
c82e9aa0
EC		 2217 res_end_move(dev, slave, RES_MPT, id);
2218 return err;
2219 break;
2220 default:
2221 err = -EINVAL;
2222 break;
2223 }
2224 return err;
2225}
2226
2227static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2228 u64 in_param, u64 *out_param)
2229{
2230 int cqn;
2231 int err;
2232
2233 switch (op) {
2234 case RES_OP_RESERVE_AND_MAP:
2235 cqn = get_param_l(&in_param);
2236 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2237 if (err)
2238 break;
2239
146f3ef4 2240 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 2241 __mlx4_cq_free_icm(dev, cqn);
2242 break;
2243
2244 default:
2245 err = -EINVAL;
2246 break;
2247 }
2248
2249 return err;
2250}
2251
2252static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2253 u64 in_param, u64 *out_param)
2254{
2255 int srqn;
2256 int err;
2257
2258 switch (op) {
2259 case RES_OP_RESERVE_AND_MAP:
2260 srqn = get_param_l(&in_param);
2261 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2262 if (err)
2263 break;
2264
146f3ef4 2265 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 2266 __mlx4_srq_free_icm(dev, srqn);
2267 break;
2268
2269 default:
2270 err = -EINVAL;
2271 break;
2272 }
2273
2274 return err;
2275}
2276
2277static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2278 u64 in_param, u64 *out_param, int in_port)
c82e9aa0
EC		 2279{
2280 int port;
2281 int err = 0;
2282
2283 switch (op) {
2284 case RES_OP_RESERVE_AND_MAP:
acddd5dd 2285 port = !in_port ? get_param_l(out_param) : in_port;
449fc488
MB		 2286 port = mlx4_slave_convert_port(
2287 dev, slave, port);
2288
2289 if (port < 0)
2290 return -EINVAL;
c82e9aa0
EC		 2291 mac_del_from_slave(dev, slave, in_param, port);
2292 __mlx4_unregister_mac(dev, port, in_param);
2293 break;
2294 default:
2295 err = -EINVAL;
2296 break;
2297 }
2298
2299 return err;
2300
2301}
2302
ffe455ad 2303static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2304 u64 in_param, u64 *out_param, int port)
ffe455ad 2305{
2c957ff2
JM		 2306 struct mlx4_priv *priv = mlx4_priv(dev);
2307 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
4874080d
JM		 2308 int err = 0;
2309
449fc488
MB		 2310 port = mlx4_slave_convert_port(
2311 dev, slave, port);
2312
2313 if (port < 0)
2314 return -EINVAL;
4874080d
JM		 2315 switch (op) {
2316 case RES_OP_RESERVE_AND_MAP:
2c957ff2
JM		 2317 if (slave_state[slave].old_vlan_api)
2318 return 0;
4874080d
JM		 2319 if (!port)
2320 return -EINVAL;
2321 vlan_del_from_slave(dev, slave, in_param, port);
2322 __mlx4_unregister_vlan(dev, port, in_param);
2323 break;
2324 default:
2325 err = -EINVAL;
2326 break;
2327 }
2328
2329 return err;
ffe455ad
EE		 2330}
2331
ba062d52
JM		 2332static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2333 u64 in_param, u64 *out_param)
2334{
2335 int index;
2336 int err;
2337
2338 if (op != RES_OP_RESERVE)
2339 return -EINVAL;
2340
2341 index = get_param_l(&in_param);
2342 err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2343 if (err)
2344 return err;
2345
2346 __mlx4_counter_free(dev, index);
146f3ef4 2347 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 2348
2349 return err;
2350}
2351
2352static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2353 u64 in_param, u64 *out_param)
2354{
2355 int xrcdn;
2356 int err;
2357
2358 if (op != RES_OP_RESERVE)
2359 return -EINVAL;
2360
2361 xrcdn = get_param_l(&in_param);
2362 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2363 if (err)
2364 return err;
2365
2366 __mlx4_xrcd_free(dev, xrcdn);
2367
2368 return err;
2369}
2370
c82e9aa0
EC		 2371int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2372 struct mlx4_vhcr *vhcr,
2373 struct mlx4_cmd_mailbox *inbox,
2374 struct mlx4_cmd_mailbox *outbox,
2375 struct mlx4_cmd_info *cmd)
2376{
2377 int err = -EINVAL;
2378 int alop = vhcr->op_modifier;
2379
acddd5dd 2380 switch (vhcr->in_modifier & 0xFF) {
c82e9aa0
EC		 2381 case RES_QP:
2382 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2383 vhcr->in_param);
2384 break;
2385
2386 case RES_MTT:
2387 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2388 vhcr->in_param, &vhcr->out_param);
2389 break;
2390
2391 case RES_MPT:
2392 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2393 vhcr->in_param);
2394 break;
2395
2396 case RES_CQ:
2397 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2398 vhcr->in_param, &vhcr->out_param);
2399 break;
2400
2401 case RES_SRQ:
2402 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2403 vhcr->in_param, &vhcr->out_param);
2404 break;
2405
2406 case RES_MAC:
2407 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2408 vhcr->in_param, &vhcr->out_param,
2409 (vhcr->in_modifier >> 8) & 0xFF);
c82e9aa0
EC		 2410 break;
2411
ffe455ad
EE		 2412 case RES_VLAN:
2413 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2414 vhcr->in_param, &vhcr->out_param,
2415 (vhcr->in_modifier >> 8) & 0xFF);
ffe455ad
EE		 2416 break;
2417
ba062d52
JM		 2418 case RES_COUNTER:
2419 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2420 vhcr->in_param, &vhcr->out_param);
2421 break;
2422
2423 case RES_XRCD:
2424 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2425 vhcr->in_param, &vhcr->out_param);
2426
c82e9aa0
EC		 2427 default:
2428 break;
2429 }
2430 return err;
2431}
2432
2433/* ugly but other choices are uglier */
2434static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2435{
2436 return (be32_to_cpu(mpt->flags) >> 9) & 1;
2437}
2438
2b8fb286 2439static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
c82e9aa0 2440{
2b8fb286 2441 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
c82e9aa0
EC		 2442}
2443
2444static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2445{
2446 return be32_to_cpu(mpt->mtt_sz);
2447}
2448
cc1ade94
SM		 2449static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2450{
2451 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2452}
2453
2454static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2455{
2456 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2457}
2458
2459static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2460{
2461 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2462}
2463
2464static int mr_is_region(struct mlx4_mpt_entry *mpt)
2465{
2466 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2467}
2468
2b8fb286 2469static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
c82e9aa0
EC		 2470{
2471 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2472}
2473
2b8fb286 2474static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
c82e9aa0
EC		 2475{
2476 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2477}
2478
2479static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2480{
2481 int page_shift = (qpc->log_page_size & 0x3f) + 12;
2482 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2483 int log_sq_sride = qpc->sq_size_stride & 7;
2484 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2485 int log_rq_stride = qpc->rq_size_stride & 7;
2486 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2487 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
5c5f3f0a
YH		 2488 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2489 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
c82e9aa0
EC		 2490 int sq_size;
2491 int rq_size;
2492 int total_pages;
2493 int total_mem;
2494 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2495
2496 sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2497 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2498 total_mem = sq_size + rq_size;
2499 total_pages =
2500 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
2501 page_shift);
2502
2503 return total_pages;
2504}
2505
c82e9aa0
EC		 2506static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2507 int size, struct res_mtt *mtt)
2508{
2b8fb286
MA		 2509 int res_start = mtt->com.res_id;
2510 int res_size = (1 << mtt->order);
c82e9aa0
EC		 2511
2512 if (start < res_start || start + size > res_start + res_size)
2513 return -EPERM;
2514 return 0;
2515}
2516
2517int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2518 struct mlx4_vhcr *vhcr,
2519 struct mlx4_cmd_mailbox *inbox,
2520 struct mlx4_cmd_mailbox *outbox,
2521 struct mlx4_cmd_info *cmd)
2522{
2523 int err;
2524 int index = vhcr->in_modifier;
2525 struct res_mtt *mtt;
2526 struct res_mpt *mpt;
2b8fb286 2527 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2528 int phys;
2529 int id;
cc1ade94
SM		 2530 u32 pd;
2531 int pd_slave;
c82e9aa0
EC		 2532
2533 id = index & mpt_mask(dev);
2534 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2535 if (err)
2536 return err;
2537
cc1ade94
SM		 2538 /* Disable memory windows for VFs. */
2539 if (!mr_is_region(inbox->buf)) {
2540 err = -EPERM;
2541 goto ex_abort;
2542 }
2543
2544 /* Make sure that the PD bits related to the slave id are zeros. */
2545 pd = mr_get_pd(inbox->buf);
2546 pd_slave = (pd >> 17) & 0x7f;
b332068c 2547 if (pd_slave != 0 && --pd_slave != slave) {
cc1ade94
SM		 2548 err = -EPERM;
2549 goto ex_abort;
2550 }
2551
2552 if (mr_is_fmr(inbox->buf)) {
2553 /* FMR and Bind Enable are forbidden in slave devices. */
2554 if (mr_is_bind_enabled(inbox->buf)) {
2555 err = -EPERM;
2556 goto ex_abort;
2557 }
2558 /* FMR and Memory Windows are also forbidden. */
2559 if (!mr_is_region(inbox->buf)) {
2560 err = -EPERM;
2561 goto ex_abort;
2562 }
2563 }
2564
c82e9aa0
EC		 2565 phys = mr_phys_mpt(inbox->buf);
2566 if (!phys) {
2b8fb286 2567 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2568 if (err)
2569 goto ex_abort;
2570
2571 err = check_mtt_range(dev, slave, mtt_base,
2572 mr_get_mtt_size(inbox->buf), mtt);
2573 if (err)
2574 goto ex_put;
2575
2576 mpt->mtt = mtt;
2577 }
2578
c82e9aa0
EC		 2579 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2580 if (err)
2581 goto ex_put;
2582
2583 if (!phys) {
2584 atomic_inc(&mtt->ref_count);
2585 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2586 }
2587
2588 res_end_move(dev, slave, RES_MPT, id);
2589 return 0;
2590
2591ex_put:
2592 if (!phys)
2593 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2594ex_abort:
2595 res_abort_move(dev, slave, RES_MPT, id);
2596
2597 return err;
2598}
2599
2600int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2601 struct mlx4_vhcr *vhcr,
2602 struct mlx4_cmd_mailbox *inbox,
2603 struct mlx4_cmd_mailbox *outbox,
2604 struct mlx4_cmd_info *cmd)
2605{
2606 int err;
2607 int index = vhcr->in_modifier;
2608 struct res_mpt *mpt;
2609 int id;
2610
2611 id = index & mpt_mask(dev);
2612 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2613 if (err)
2614 return err;
2615
2616 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2617 if (err)
2618 goto ex_abort;
2619
2620 if (mpt->mtt)
2621 atomic_dec(&mpt->mtt->ref_count);
2622
2623 res_end_move(dev, slave, RES_MPT, id);
2624 return 0;
2625
2626ex_abort:
2627 res_abort_move(dev, slave, RES_MPT, id);
2628
2629 return err;
2630}
2631
2632int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2633 struct mlx4_vhcr *vhcr,
2634 struct mlx4_cmd_mailbox *inbox,
2635 struct mlx4_cmd_mailbox *outbox,
2636 struct mlx4_cmd_info *cmd)
2637{
2638 int err;
2639 int index = vhcr->in_modifier;
2640 struct res_mpt *mpt;
2641 int id;
2642
2643 id = index & mpt_mask(dev);
2644 err = get_res(dev, slave, id, RES_MPT, &mpt);
2645 if (err)
2646 return err;
2647
e630664c
MB		 2648 if (mpt->com.from_state == RES_MPT_MAPPED) {
2649 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
2650 * that, the VF must read the MPT. But since the MPT entry memory is not
2651 * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
2652 * entry contents. To guarantee that the MPT cannot be changed, the driver
2653 * must perform HW2SW_MPT before this query and return the MPT entry to HW
2654 * ownership fofollowing the change. The change here allows the VF to
2655 * perform QUERY_MPT also when the entry is in SW ownership.
2656 */
2657 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
2658 &mlx4_priv(dev)->mr_table.dmpt_table,
2659 mpt->key, NULL);
2660
2661 if (NULL == mpt_entry || NULL == outbox->buf) {
2662 err = -EINVAL;
2663 goto out;
2664 }
2665
2666 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
2667
2668 err = 0;
2669 } else if (mpt->com.from_state == RES_MPT_HW) {
2670 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2671 } else {
c82e9aa0
EC		 2672 err = -EBUSY;
2673 goto out;
2674 }
2675
c82e9aa0
EC		 2676
2677out:
2678 put_res(dev, slave, id, RES_MPT);
2679 return err;
2680}
2681
2682static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2683{
2684 return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2685}
2686
2687static int qp_get_scqn(struct mlx4_qp_context *qpc)
2688{
2689 return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2690}
2691
2692static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2693{
2694 return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2695}
2696
54679e14
JM		 2697static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2698 struct mlx4_qp_context *context)
2699{
2700 u32 qpn = vhcr->in_modifier & 0xffffff;
2701 u32 qkey = 0;
2702
2703 if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2704 return;
2705
2706 /* adjust qkey in qp context */
2707 context->qkey = cpu_to_be32(qkey);
2708}
2709
c82e9aa0
EC		 2710int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2711 struct mlx4_vhcr *vhcr,
2712 struct mlx4_cmd_mailbox *inbox,
2713 struct mlx4_cmd_mailbox *outbox,
2714 struct mlx4_cmd_info *cmd)
2715{
2716 int err;
2717 int qpn = vhcr->in_modifier & 0x7fffff;
2718 struct res_mtt *mtt;
2719 struct res_qp *qp;
2720 struct mlx4_qp_context *qpc = inbox->buf + 8;
2b8fb286 2721 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2722 int mtt_size = qp_get_mtt_size(qpc);
2723 struct res_cq *rcq;
2724 struct res_cq *scq;
2725 int rcqn = qp_get_rcqn(qpc);
2726 int scqn = qp_get_scqn(qpc);
2727 u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2728 int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2729 struct res_srq *srq;
2730 int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2731
2732 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2733 if (err)
2734 return err;
2735 qp->local_qpn = local_qpn;
b01978ca 2736 qp->sched_queue = 0;
f0f829bf
RE		 2737 qp->param3 = 0;
2738 qp->vlan_control = 0;
2739 qp->fvl_rx = 0;
2740 qp->pri_path_fl = 0;
2741 qp->vlan_index = 0;
2742 qp->feup = 0;
b01978ca 2743 qp->qpc_flags = be32_to_cpu(qpc->flags);
c82e9aa0 2744
2b8fb286 2745 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2746 if (err)
2747 goto ex_abort;
2748
2749 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2750 if (err)
2751 goto ex_put_mtt;
2752
c82e9aa0
EC		 2753 err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2754 if (err)
2755 goto ex_put_mtt;
2756
2757 if (scqn != rcqn) {
2758 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2759 if (err)
2760 goto ex_put_rcq;
2761 } else
2762 scq = rcq;
2763
2764 if (use_srq) {
2765 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2766 if (err)
2767 goto ex_put_scq;
2768 }
2769
54679e14
JM		 2770 adjust_proxy_tun_qkey(dev, vhcr, qpc);
2771 update_pkey_index(dev, slave, inbox);
c82e9aa0
EC		 2772 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2773 if (err)
2774 goto ex_put_srq;
2775 atomic_inc(&mtt->ref_count);
2776 qp->mtt = mtt;
2777 atomic_inc(&rcq->ref_count);
2778 qp->rcq = rcq;
2779 atomic_inc(&scq->ref_count);
2780 qp->scq = scq;
2781
2782 if (scqn != rcqn)
2783 put_res(dev, slave, scqn, RES_CQ);
2784
2785 if (use_srq) {
2786 atomic_inc(&srq->ref_count);
2787 put_res(dev, slave, srqn, RES_SRQ);
2788 qp->srq = srq;
2789 }
2790 put_res(dev, slave, rcqn, RES_CQ);
2b8fb286 2791 put_res(dev, slave, mtt_base, RES_MTT);
c82e9aa0
EC		 2792 res_end_move(dev, slave, RES_QP, qpn);
2793
2794 return 0;
2795
2796ex_put_srq:
2797 if (use_srq)
2798 put_res(dev, slave, srqn, RES_SRQ);
2799ex_put_scq:
2800 if (scqn != rcqn)
2801 put_res(dev, slave, scqn, RES_CQ);
2802ex_put_rcq:
2803 put_res(dev, slave, rcqn, RES_CQ);
2804ex_put_mtt:
2b8fb286 2805 put_res(dev, slave, mtt_base, RES_MTT);
c82e9aa0
EC		 2806ex_abort:
2807 res_abort_move(dev, slave, RES_QP, qpn);
2808
2809 return err;
2810}
2811
2b8fb286 2812static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
c82e9aa0
EC		 2813{
2814 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
2815}
2816
2817static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
2818{
2819 int log_eq_size = eqc->log_eq_size & 0x1f;
2820 int page_shift = (eqc->log_page_size & 0x3f) + 12;
2821
2822 if (log_eq_size + 5 < page_shift)
2823 return 1;
2824
2825 return 1 << (log_eq_size + 5 - page_shift);
2826}
2827
2b8fb286 2828static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
c82e9aa0
EC		 2829{
2830 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
2831}
2832
2833static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
2834{
2835 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
2836 int page_shift = (cqc->log_page_size & 0x3f) + 12;
2837
2838 if (log_cq_size + 5 < page_shift)
2839 return 1;
2840
2841 return 1 << (log_cq_size + 5 - page_shift);
2842}
2843
2844int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2845 struct mlx4_vhcr *vhcr,
2846 struct mlx4_cmd_mailbox *inbox,
2847 struct mlx4_cmd_mailbox *outbox,
2848 struct mlx4_cmd_info *cmd)
2849{
2850 int err;
2851 int eqn = vhcr->in_modifier;
2852 int res_id = (slave << 8) | eqn;
2853 struct mlx4_eq_context *eqc = inbox->buf;
2b8fb286 2854 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2855 int mtt_size = eq_get_mtt_size(eqc);
2856 struct res_eq *eq;
2857 struct res_mtt *mtt;
2858
2859 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2860 if (err)
2861 return err;
2862 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
2863 if (err)
2864 goto out_add;
2865
2b8fb286 2866 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2867 if (err)
2868 goto out_move;
2869
2870 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2871 if (err)
2872 goto out_put;
2873
2874 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2875 if (err)
2876 goto out_put;
2877
2878 atomic_inc(&mtt->ref_count);
2879 eq->mtt = mtt;
2880 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2881 res_end_move(dev, slave, RES_EQ, res_id);
2882 return 0;
2883
2884out_put:
2885 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2886out_move:
2887 res_abort_move(dev, slave, RES_EQ, res_id);
2888out_add:
2889 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2890 return err;
2891}
2892
d475c95b
MB		 2893int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
2894 struct mlx4_vhcr *vhcr,
2895 struct mlx4_cmd_mailbox *inbox,
2896 struct mlx4_cmd_mailbox *outbox,
2897 struct mlx4_cmd_info *cmd)
2898{
2899 int err;
2900 u8 get = vhcr->op_modifier;
2901
2902 if (get != 1)
2903 return -EPERM;
2904
2905 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2906
2907 return err;
2908}
2909
c82e9aa0
EC		 2910static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
2911 int len, struct res_mtt **res)
2912{
2913 struct mlx4_priv *priv = mlx4_priv(dev);
2914 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2915 struct res_mtt *mtt;
2916 int err = -EINVAL;
2917
2918 spin_lock_irq(mlx4_tlock(dev));
2919 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
2920 com.list) {
2921 if (!check_mtt_range(dev, slave, start, len, mtt)) {
2922 *res = mtt;
2923 mtt->com.from_state = mtt->com.state;
2924 mtt->com.state = RES_MTT_BUSY;
2925 err = 0;
2926 break;
2927 }
2928 }
2929 spin_unlock_irq(mlx4_tlock(dev));
2930
2931 return err;
2932}
2933
54679e14 2934static int verify_qp_parameters(struct mlx4_dev *dev,
99ec41d0 2935 struct mlx4_vhcr *vhcr,
54679e14
JM		 2936 struct mlx4_cmd_mailbox *inbox,
2937 enum qp_transition transition, u8 slave)
2938{
2939 u32 qp_type;
99ec41d0 2940 u32 qpn;
54679e14
JM		 2941 struct mlx4_qp_context *qp_ctx;
2942 enum mlx4_qp_optpar optpar;
b6ffaeff
JM		 2943 int port;
2944 int num_gids;
54679e14
JM		 2945
2946 qp_ctx = inbox->buf + 8;
2947 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
2948 optpar = be32_to_cpu(*(__be32 *) inbox->buf);
2949
53f33ae2
MS		 2950 if (slave != mlx4_master_func_num(dev))
2951 qp_ctx->params2 &= ~MLX4_QP_BIT_FPP;
2952
54679e14
JM		 2953 switch (qp_type) {
2954 case MLX4_QP_ST_RC:
b6ffaeff 2955 case MLX4_QP_ST_XRC:
54679e14
JM		 2956 case MLX4_QP_ST_UC:
2957 switch (transition) {
2958 case QP_TRANS_INIT2RTR:
2959 case QP_TRANS_RTR2RTS:
2960 case QP_TRANS_RTS2RTS:
2961 case QP_TRANS_SQD2SQD:
2962 case QP_TRANS_SQD2RTS:
2963 if (slave != mlx4_master_func_num(dev))
b6ffaeff
JM		 2964 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
2965 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
2966 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
449fc488 2967 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 2968 else
2969 num_gids = 1;
2970 if (qp_ctx->pri_path.mgid_index >= num_gids)
54679e14 2971 return -EINVAL;
b6ffaeff
JM		 2972 }
2973 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
2974 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
2975 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
449fc488 2976 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 2977 else
2978 num_gids = 1;
2979 if (qp_ctx->alt_path.mgid_index >= num_gids)
54679e14 2980 return -EINVAL;
b6ffaeff 2981 }
54679e14
JM		 2982 break;
2983 default:
2984 break;
2985 }
165cb465 2986 break;
54679e14 2987
165cb465
RD		 2988 case MLX4_QP_ST_MLX:
2989 qpn = vhcr->in_modifier & 0x7fffff;
2990 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
2991 if (transition == QP_TRANS_INIT2RTR &&
2992 slave != mlx4_master_func_num(dev) &&
2993 mlx4_is_qp_reserved(dev, qpn) &&
2994 !mlx4_vf_smi_enabled(dev, slave, port)) {
2995 /* only enabled VFs may create MLX proxy QPs */
2996 mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
2997 __func__, slave, port);
2998 return -EPERM;
2999 }
54679e14 3000 break;
165cb465 3001
54679e14
JM		 3002 default:
3003 break;
3004 }
3005
3006 return 0;
3007}
3008
c82e9aa0
EC		 3009int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
3010 struct mlx4_vhcr *vhcr,
3011 struct mlx4_cmd_mailbox *inbox,
3012 struct mlx4_cmd_mailbox *outbox,
3013 struct mlx4_cmd_info *cmd)
3014{
3015 struct mlx4_mtt mtt;
3016 __be64 *page_list = inbox->buf;
3017 u64 *pg_list = (u64 *)page_list;
3018 int i;
3019 struct res_mtt *rmtt = NULL;
3020 int start = be64_to_cpu(page_list[0]);
3021 int npages = vhcr->in_modifier;
3022 int err;
3023
3024 err = get_containing_mtt(dev, slave, start, npages, &rmtt);
3025 if (err)
3026 return err;
3027
3028 /* Call the SW implementation of write_mtt:
3029 * - Prepare a dummy mtt struct
3030 * - Translate inbox contents to simple addresses in host endianess */
2b8fb286
MA		 3031 mtt.offset = 0; /* TBD this is broken but I don't handle it since
3032 we don't really use it */
c82e9aa0
EC		 3033 mtt.order = 0;
3034 mtt.page_shift = 0;
3035 for (i = 0; i < npages; ++i)
3036 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
3037
3038 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
3039 ((u64 *)page_list + 2));
3040
3041 if (rmtt)
3042 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
3043
3044 return err;
3045}
3046
3047int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3048 struct mlx4_vhcr *vhcr,
3049 struct mlx4_cmd_mailbox *inbox,
3050 struct mlx4_cmd_mailbox *outbox,
3051 struct mlx4_cmd_info *cmd)
3052{
3053 int eqn = vhcr->in_modifier;
3054 int res_id = eqn | (slave << 8);
3055 struct res_eq *eq;
3056 int err;
3057
3058 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
3059 if (err)
3060 return err;
3061
3062 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
3063 if (err)
3064 goto ex_abort;
3065
3066 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3067 if (err)
3068 goto ex_put;
3069
3070 atomic_dec(&eq->mtt->ref_count);
3071 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3072 res_end_move(dev, slave, RES_EQ, res_id);
3073 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3074
3075 return 0;
3076
3077ex_put:
3078 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3079ex_abort:
3080 res_abort_move(dev, slave, RES_EQ, res_id);
3081
3082 return err;
3083}
3084
3085int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
3086{
3087 struct mlx4_priv *priv = mlx4_priv(dev);
3088 struct mlx4_slave_event_eq_info *event_eq;
3089 struct mlx4_cmd_mailbox *mailbox;
3090 u32 in_modifier = 0;
3091 int err;
3092 int res_id;
3093 struct res_eq *req;
3094
3095 if (!priv->mfunc.master.slave_state)
3096 return -EINVAL;
3097
803143fb 3098 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
c82e9aa0
EC		 3099
3100 /* Create the event only if the slave is registered */
803143fb 3101 if (event_eq->eqn < 0)
c82e9aa0
EC		 3102 return 0;
3103
3104 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3105 res_id = (slave << 8) | event_eq->eqn;
3106 err = get_res(dev, slave, res_id, RES_EQ, &req);
3107 if (err)
3108 goto unlock;
3109
3110 if (req->com.from_state != RES_EQ_HW) {
3111 err = -EINVAL;
3112 goto put;
3113 }
3114
3115 mailbox = mlx4_alloc_cmd_mailbox(dev);
3116 if (IS_ERR(mailbox)) {
3117 err = PTR_ERR(mailbox);
3118 goto put;
3119 }
3120
3121 if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3122 ++event_eq->token;
3123 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3124 }
3125
3126 memcpy(mailbox->buf, (u8 *) eqe, 28);
3127
3128 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
3129
3130 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3131 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3132 MLX4_CMD_NATIVE);
3133
3134 put_res(dev, slave, res_id, RES_EQ);
3135 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3136 mlx4_free_cmd_mailbox(dev, mailbox);
3137 return err;
3138
3139put:
3140 put_res(dev, slave, res_id, RES_EQ);
3141
3142unlock:
3143 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3144 return err;
3145}
3146
3147int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3148 struct mlx4_vhcr *vhcr,
3149 struct mlx4_cmd_mailbox *inbox,
3150 struct mlx4_cmd_mailbox *outbox,
3151 struct mlx4_cmd_info *cmd)
3152{
3153 int eqn = vhcr->in_modifier;
3154 int res_id = eqn | (slave << 8);
3155 struct res_eq *eq;
3156 int err;
3157
3158 err = get_res(dev, slave, res_id, RES_EQ, &eq);
3159 if (err)
3160 return err;
3161
3162 if (eq->com.from_state != RES_EQ_HW) {
3163 err = -EINVAL;
3164 goto ex_put;
3165 }
3166
3167 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3168
3169ex_put:
3170 put_res(dev, slave, res_id, RES_EQ);
3171 return err;
3172}
3173
3174int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3175 struct mlx4_vhcr *vhcr,
3176 struct mlx4_cmd_mailbox *inbox,
3177 struct mlx4_cmd_mailbox *outbox,
3178 struct mlx4_cmd_info *cmd)
3179{
3180 int err;
3181 int cqn = vhcr->in_modifier;
3182 struct mlx4_cq_context *cqc = inbox->buf;
2b8fb286 3183 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3184 struct res_cq *cq;
3185 struct res_mtt *mtt;
3186
3187 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3188 if (err)
3189 return err;
2b8fb286 3190 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3191 if (err)
3192 goto out_move;
3193 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3194 if (err)
3195 goto out_put;
3196 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3197 if (err)
3198 goto out_put;
3199 atomic_inc(&mtt->ref_count);
3200 cq->mtt = mtt;
3201 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3202 res_end_move(dev, slave, RES_CQ, cqn);
3203 return 0;
3204
3205out_put:
3206 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3207out_move:
3208 res_abort_move(dev, slave, RES_CQ, cqn);
3209 return err;
3210}
3211
3212int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3213 struct mlx4_vhcr *vhcr,
3214 struct mlx4_cmd_mailbox *inbox,
3215 struct mlx4_cmd_mailbox *outbox,
3216 struct mlx4_cmd_info *cmd)
3217{
3218 int err;
3219 int cqn = vhcr->in_modifier;
3220 struct res_cq *cq;
3221
3222 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3223 if (err)
3224 return err;
3225 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3226 if (err)
3227 goto out_move;
3228 atomic_dec(&cq->mtt->ref_count);
3229 res_end_move(dev, slave, RES_CQ, cqn);
3230 return 0;
3231
3232out_move:
3233 res_abort_move(dev, slave, RES_CQ, cqn);
3234 return err;
3235}
3236
3237int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3238 struct mlx4_vhcr *vhcr,
3239 struct mlx4_cmd_mailbox *inbox,
3240 struct mlx4_cmd_mailbox *outbox,
3241 struct mlx4_cmd_info *cmd)
3242{
3243 int cqn = vhcr->in_modifier;
3244 struct res_cq *cq;
3245 int err;
3246
3247 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3248 if (err)
3249 return err;
3250
3251 if (cq->com.from_state != RES_CQ_HW)
3252 goto ex_put;
3253
3254 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3255ex_put:
3256 put_res(dev, slave, cqn, RES_CQ);
3257
3258 return err;
3259}
3260
3261static int handle_resize(struct mlx4_dev *dev, int slave,
3262 struct mlx4_vhcr *vhcr,
3263 struct mlx4_cmd_mailbox *inbox,
3264 struct mlx4_cmd_mailbox *outbox,
3265 struct mlx4_cmd_info *cmd,
3266 struct res_cq *cq)
3267{
3268 int err;
3269 struct res_mtt *orig_mtt;
3270 struct res_mtt *mtt;
3271 struct mlx4_cq_context *cqc = inbox->buf;
2b8fb286 3272 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3273
3274 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3275 if (err)
3276 return err;
3277
3278 if (orig_mtt != cq->mtt) {
3279 err = -EINVAL;
3280 goto ex_put;
3281 }
3282
2b8fb286 3283 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3284 if (err)
3285 goto ex_put;
3286
3287 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3288 if (err)
3289 goto ex_put1;
3290 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3291 if (err)
3292 goto ex_put1;
3293 atomic_dec(&orig_mtt->ref_count);
3294 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3295 atomic_inc(&mtt->ref_count);
3296 cq->mtt = mtt;
3297 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3298 return 0;
3299
3300ex_put1:
3301 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3302ex_put:
3303 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3304
3305 return err;
3306
3307}
3308
3309int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3310 struct mlx4_vhcr *vhcr,
3311 struct mlx4_cmd_mailbox *inbox,
3312 struct mlx4_cmd_mailbox *outbox,
3313 struct mlx4_cmd_info *cmd)
3314{
3315 int cqn = vhcr->in_modifier;
3316 struct res_cq *cq;
3317 int err;
3318
3319 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3320 if (err)
3321 return err;
3322
3323 if (cq->com.from_state != RES_CQ_HW)
3324 goto ex_put;
3325
3326 if (vhcr->op_modifier == 0) {
3327 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
dcf353b1 3328 goto ex_put;
c82e9aa0
EC		 3329 }
3330
3331 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3332ex_put:
3333 put_res(dev, slave, cqn, RES_CQ);
3334
3335 return err;
3336}
3337
c82e9aa0
EC		 3338static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3339{
3340 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3341 int log_rq_stride = srqc->logstride & 7;
3342 int page_shift = (srqc->log_page_size & 0x3f) + 12;
3343
3344 if (log_srq_size + log_rq_stride + 4 < page_shift)
3345 return 1;
3346
3347 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3348}
3349
3350int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3351 struct mlx4_vhcr *vhcr,
3352 struct mlx4_cmd_mailbox *inbox,
3353 struct mlx4_cmd_mailbox *outbox,
3354 struct mlx4_cmd_info *cmd)
3355{
3356 int err;
3357 int srqn = vhcr->in_modifier;
3358 struct res_mtt *mtt;
3359 struct res_srq *srq;
3360 struct mlx4_srq_context *srqc = inbox->buf;
2b8fb286 3361 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3362
3363 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3364 return -EINVAL;
3365
3366 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3367 if (err)
3368 return err;
2b8fb286 3369 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3370 if (err)
3371 goto ex_abort;
3372 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3373 mtt);
3374 if (err)
3375 goto ex_put_mtt;
3376
c82e9aa0
EC		 3377 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3378 if (err)
3379 goto ex_put_mtt;
3380
3381 atomic_inc(&mtt->ref_count);
3382 srq->mtt = mtt;
3383 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3384 res_end_move(dev, slave, RES_SRQ, srqn);
3385 return 0;
3386
3387ex_put_mtt:
3388 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3389ex_abort:
3390 res_abort_move(dev, slave, RES_SRQ, srqn);
3391
3392 return err;
3393}
3394
3395int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3396 struct mlx4_vhcr *vhcr,
3397 struct mlx4_cmd_mailbox *inbox,
3398 struct mlx4_cmd_mailbox *outbox,
3399 struct mlx4_cmd_info *cmd)
3400{
3401 int err;
3402 int srqn = vhcr->in_modifier;
3403 struct res_srq *srq;
3404
3405 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3406 if (err)
3407 return err;
3408 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3409 if (err)
3410 goto ex_abort;
3411 atomic_dec(&srq->mtt->ref_count);
3412 if (srq->cq)
3413 atomic_dec(&srq->cq->ref_count);
3414 res_end_move(dev, slave, RES_SRQ, srqn);
3415
3416 return 0;
3417
3418ex_abort:
3419 res_abort_move(dev, slave, RES_SRQ, srqn);
3420
3421 return err;
3422}
3423
3424int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3425 struct mlx4_vhcr *vhcr,
3426 struct mlx4_cmd_mailbox *inbox,
3427 struct mlx4_cmd_mailbox *outbox,
3428 struct mlx4_cmd_info *cmd)
3429{
3430 int err;
3431 int srqn = vhcr->in_modifier;
3432 struct res_srq *srq;
3433
3434 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3435 if (err)
3436 return err;
3437 if (srq->com.from_state != RES_SRQ_HW) {
3438 err = -EBUSY;
3439 goto out;
3440 }
3441 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3442out:
3443 put_res(dev, slave, srqn, RES_SRQ);
3444 return err;
3445}
3446
3447int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3448 struct mlx4_vhcr *vhcr,
3449 struct mlx4_cmd_mailbox *inbox,
3450 struct mlx4_cmd_mailbox *outbox,
3451 struct mlx4_cmd_info *cmd)
3452{
3453 int err;
3454 int srqn = vhcr->in_modifier;
3455 struct res_srq *srq;
3456
3457 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3458 if (err)
3459 return err;
3460
3461 if (srq->com.from_state != RES_SRQ_HW) {
3462 err = -EBUSY;
3463 goto out;
3464 }
3465
3466 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3467out:
3468 put_res(dev, slave, srqn, RES_SRQ);
3469 return err;
3470}
3471
3472int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3473 struct mlx4_vhcr *vhcr,
3474 struct mlx4_cmd_mailbox *inbox,
3475 struct mlx4_cmd_mailbox *outbox,
3476 struct mlx4_cmd_info *cmd)
3477{
3478 int err;
3479 int qpn = vhcr->in_modifier & 0x7fffff;
3480 struct res_qp *qp;
3481
3482 err = get_res(dev, slave, qpn, RES_QP, &qp);
3483 if (err)
3484 return err;
3485 if (qp->com.from_state != RES_QP_HW) {
3486 err = -EBUSY;
3487 goto out;
3488 }
3489
3490 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3491out:
3492 put_res(dev, slave, qpn, RES_QP);
3493 return err;
3494}
3495
54679e14
JM		 3496int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3497 struct mlx4_vhcr *vhcr,
3498 struct mlx4_cmd_mailbox *inbox,
3499 struct mlx4_cmd_mailbox *outbox,
3500 struct mlx4_cmd_info *cmd)
3501{
3502 struct mlx4_qp_context *context = inbox->buf + 8;
3503 adjust_proxy_tun_qkey(dev, vhcr, context);
3504 update_pkey_index(dev, slave, inbox);
3505 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3506}
3507
449fc488
MB		 3508static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3509 struct mlx4_qp_context *qpc,
3510 struct mlx4_cmd_mailbox *inbox)
3511{
3512 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3513 u8 pri_sched_queue;
3514 int port = mlx4_slave_convert_port(
3515 dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3516
3517 if (port < 0)
3518 return -EINVAL;
3519
3520 pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3521 ((port & 1) << 6);
3522
3523 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH ||
3524 mlx4_is_eth(dev, port + 1)) {
3525 qpc->pri_path.sched_queue = pri_sched_queue;
3526 }
3527
3528 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3529 port = mlx4_slave_convert_port(
3530 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3531 + 1) - 1;
3532 if (port < 0)
3533 return -EINVAL;
3534 qpc->alt_path.sched_queue =
3535 (qpc->alt_path.sched_queue & ~(1 << 6)) |
3536 (port & 1) << 6;
3537 }
3538 return 0;
3539}
3540
2f5bb473
JM		 3541static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3542 struct mlx4_qp_context *qpc,
3543 struct mlx4_cmd_mailbox *inbox)
3544{
3545 u64 mac;
3546 int port;
3547 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3548 u8 sched = *(u8 *)(inbox->buf + 64);
3549 u8 smac_ix;
3550
3551 port = (sched >> 6 & 1) + 1;
3552 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3553 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3554 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3555 return -ENOENT;
3556 }
3557 return 0;
3558}
3559
c82e9aa0
EC		 3560int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3561 struct mlx4_vhcr *vhcr,
3562 struct mlx4_cmd_mailbox *inbox,
3563 struct mlx4_cmd_mailbox *outbox,
3564 struct mlx4_cmd_info *cmd)
3565{
54679e14 3566 int err;
c82e9aa0 3567 struct mlx4_qp_context *qpc = inbox->buf + 8;
b01978ca
JM		 3568 int qpn = vhcr->in_modifier & 0x7fffff;
3569 struct res_qp *qp;
3570 u8 orig_sched_queue;
f0f829bf
RE		 3571 __be32 orig_param3 = qpc->param3;
3572 u8 orig_vlan_control = qpc->pri_path.vlan_control;
3573 u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3574 u8 orig_pri_path_fl = qpc->pri_path.fl;
3575 u8 orig_vlan_index = qpc->pri_path.vlan_index;
3576 u8 orig_feup = qpc->pri_path.feup;
c82e9aa0 3577
449fc488
MB		 3578 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3579 if (err)
3580 return err;
99ec41d0 3581 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
54679e14
JM		 3582 if (err)
3583 return err;
3584
2f5bb473
JM		 3585 if (roce_verify_mac(dev, slave, qpc, inbox))
3586 return -EINVAL;
3587
54679e14
JM		 3588 update_pkey_index(dev, slave, inbox);
3589 update_gid(dev, inbox, (u8)slave);
3590 adjust_proxy_tun_qkey(dev, vhcr, qpc);
b01978ca
JM		 3591 orig_sched_queue = qpc->pri_path.sched_queue;
3592 err = update_vport_qp_param(dev, inbox, slave, qpn);
3f7fb021
RE		 3593 if (err)
3594 return err;
54679e14 3595
b01978ca
JM		 3596 err = get_res(dev, slave, qpn, RES_QP, &qp);
3597 if (err)
3598 return err;
3599 if (qp->com.from_state != RES_QP_HW) {
3600 err = -EBUSY;
3601 goto out;
3602 }
3603
3604 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3605out:
3606 /* if no error, save sched queue value passed in by VF. This is
3607 * essentially the QOS value provided by the VF. This will be useful
3608 * if we allow dynamic changes from VST back to VGT
3609 */
f0f829bf 3610 if (!err) {
b01978ca 3611 qp->sched_queue = orig_sched_queue;
f0f829bf
RE		 3612 qp->param3 = orig_param3;
3613 qp->vlan_control = orig_vlan_control;
3614 qp->fvl_rx = orig_fvl_rx;
3615 qp->pri_path_fl = orig_pri_path_fl;
3616 qp->vlan_index = orig_vlan_index;
3617 qp->feup = orig_feup;
3618 }
b01978ca
JM		 3619 put_res(dev, slave, qpn, RES_QP);
3620 return err;
54679e14
JM		 3621}
3622
3623int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3624 struct mlx4_vhcr *vhcr,
3625 struct mlx4_cmd_mailbox *inbox,
3626 struct mlx4_cmd_mailbox *outbox,
3627 struct mlx4_cmd_info *cmd)
3628{
3629 int err;
3630 struct mlx4_qp_context *context = inbox->buf + 8;
3631
449fc488
MB		 3632 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3633 if (err)
3634 return err;
99ec41d0 3635 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
54679e14
JM		 3636 if (err)
3637 return err;
3638
3639 update_pkey_index(dev, slave, inbox);
3640 update_gid(dev, inbox, (u8)slave);
3641 adjust_proxy_tun_qkey(dev, vhcr, context);
3642 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3643}
3644
3645int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3646 struct mlx4_vhcr *vhcr,
3647 struct mlx4_cmd_mailbox *inbox,
3648 struct mlx4_cmd_mailbox *outbox,
3649 struct mlx4_cmd_info *cmd)
3650{
3651 int err;
3652 struct mlx4_qp_context *context = inbox->buf + 8;
3653
449fc488
MB		 3654 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3655 if (err)
3656 return err;
99ec41d0 3657 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
54679e14
JM		 3658 if (err)
3659 return err;
3660
3661 update_pkey_index(dev, slave, inbox);
3662 update_gid(dev, inbox, (u8)slave);
3663 adjust_proxy_tun_qkey(dev, vhcr, context);
3664 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3665}
3666
3667
3668int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3669 struct mlx4_vhcr *vhcr,
3670 struct mlx4_cmd_mailbox *inbox,
3671 struct mlx4_cmd_mailbox *outbox,
3672 struct mlx4_cmd_info *cmd)
3673{
3674 struct mlx4_qp_context *context = inbox->buf + 8;
449fc488
MB		 3675 int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3676 if (err)
3677 return err;
54679e14
JM		 3678 adjust_proxy_tun_qkey(dev, vhcr, context);
3679 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3680}
3681
3682int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3683 struct mlx4_vhcr *vhcr,
3684 struct mlx4_cmd_mailbox *inbox,
3685 struct mlx4_cmd_mailbox *outbox,
3686 struct mlx4_cmd_info *cmd)
3687{
3688 int err;
3689 struct mlx4_qp_context *context = inbox->buf + 8;
3690
449fc488
MB		 3691 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3692 if (err)
3693 return err;
99ec41d0 3694 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
54679e14
JM		 3695 if (err)
3696 return err;
3697
3698 adjust_proxy_tun_qkey(dev, vhcr, context);
3699 update_gid(dev, inbox, (u8)slave);
3700 update_pkey_index(dev, slave, inbox);
3701 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3702}
3703
3704int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3705 struct mlx4_vhcr *vhcr,
3706 struct mlx4_cmd_mailbox *inbox,
3707 struct mlx4_cmd_mailbox *outbox,
3708 struct mlx4_cmd_info *cmd)
3709{
3710 int err;
3711 struct mlx4_qp_context *context = inbox->buf + 8;
3712
449fc488
MB		 3713 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3714 if (err)
3715 return err;
99ec41d0 3716 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
54679e14
JM		 3717 if (err)
3718 return err;
c82e9aa0 3719
54679e14
JM		 3720 adjust_proxy_tun_qkey(dev, vhcr, context);
3721 update_gid(dev, inbox, (u8)slave);
3722 update_pkey_index(dev, slave, inbox);
c82e9aa0
EC		 3723 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3724}
3725
3726int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3727 struct mlx4_vhcr *vhcr,
3728 struct mlx4_cmd_mailbox *inbox,
3729 struct mlx4_cmd_mailbox *outbox,
3730 struct mlx4_cmd_info *cmd)
3731{
3732 int err;
3733 int qpn = vhcr->in_modifier & 0x7fffff;
3734 struct res_qp *qp;
3735
3736 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3737 if (err)
3738 return err;
3739 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3740 if (err)
3741 goto ex_abort;
3742
3743 atomic_dec(&qp->mtt->ref_count);
3744 atomic_dec(&qp->rcq->ref_count);
3745 atomic_dec(&qp->scq->ref_count);
3746 if (qp->srq)
3747 atomic_dec(&qp->srq->ref_count);
3748 res_end_move(dev, slave, RES_QP, qpn);
3749 return 0;
3750
3751ex_abort:
3752 res_abort_move(dev, slave, RES_QP, qpn);
3753
3754 return err;
3755}
3756
3757static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3758 struct res_qp *rqp, u8 *gid)
3759{
3760 struct res_gid *res;
3761
3762 list_for_each_entry(res, &rqp->mcg_list, list) {
3763 if (!memcmp(res->gid, gid, 16))
3764 return res;
3765 }
3766 return NULL;
3767}
3768
3769static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
9f5b6c63 3770 u8 *gid, enum mlx4_protocol prot,
fab1e24a 3771 enum mlx4_steer_type steer, u64 reg_id)
c82e9aa0
EC		 3772{
3773 struct res_gid *res;
3774 int err;
3775
3776 res = kzalloc(sizeof *res, GFP_KERNEL);
3777 if (!res)
3778 return -ENOMEM;
3779
3780 spin_lock_irq(&rqp->mcg_spl);
3781 if (find_gid(dev, slave, rqp, gid)) {
3782 kfree(res);
3783 err = -EEXIST;
3784 } else {
3785 memcpy(res->gid, gid, 16);
3786 res->prot = prot;
9f5b6c63 3787 res->steer = steer;
fab1e24a 3788 res->reg_id = reg_id;
c82e9aa0
EC		 3789 list_add_tail(&res->list, &rqp->mcg_list);
3790 err = 0;
3791 }
3792 spin_unlock_irq(&rqp->mcg_spl);
3793
3794 return err;
3795}
3796
3797static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
9f5b6c63 3798 u8 *gid, enum mlx4_protocol prot,
fab1e24a 3799 enum mlx4_steer_type steer, u64 *reg_id)
c82e9aa0
EC		 3800{
3801 struct res_gid *res;
3802 int err;
3803
3804 spin_lock_irq(&rqp->mcg_spl);
3805 res = find_gid(dev, slave, rqp, gid);
9f5b6c63 3806 if (!res || res->prot != prot || res->steer != steer)
c82e9aa0
EC		 3807 err = -EINVAL;
3808 else {
fab1e24a 3809 *reg_id = res->reg_id;
c82e9aa0
EC		 3810 list_del(&res->list);
3811 kfree(res);
3812 err = 0;
3813 }
3814 spin_unlock_irq(&rqp->mcg_spl);
3815
3816 return err;
3817}
3818
449fc488
MB		 3819static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
3820 u8 gid[16], int block_loopback, enum mlx4_protocol prot,
fab1e24a
HHZ		 3821 enum mlx4_steer_type type, u64 *reg_id)
3822{
3823 switch (dev->caps.steering_mode) {
449fc488
MB		 3824 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
3825 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
3826 if (port < 0)
3827 return port;
3828 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
fab1e24a
HHZ		 3829 block_loopback, prot,
3830 reg_id);
449fc488 3831 }
fab1e24a 3832 case MLX4_STEERING_MODE_B0:
449fc488
MB		 3833 if (prot == MLX4_PROT_ETH) {
3834 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
3835 if (port < 0)
3836 return port;
3837 gid[5] = port;
3838 }
fab1e24a
HHZ		 3839 return mlx4_qp_attach_common(dev, qp, gid,
3840 block_loopback, prot, type);
3841 default:
3842 return -EINVAL;
3843 }
3844}
3845
449fc488
MB		 3846static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
3847 u8 gid[16], enum mlx4_protocol prot,
3848 enum mlx4_steer_type type, u64 reg_id)
fab1e24a
HHZ		 3849{
3850 switch (dev->caps.steering_mode) {
3851 case MLX4_STEERING_MODE_DEVICE_MANAGED:
3852 return mlx4_flow_detach(dev, reg_id);
3853 case MLX4_STEERING_MODE_B0:
3854 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
3855 default:
3856 return -EINVAL;
3857 }
3858}
3859
531d9014
JM		 3860static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
3861 u8 *gid, enum mlx4_protocol prot)
3862{
3863 int real_port;
3864
3865 if (prot != MLX4_PROT_ETH)
3866 return 0;
3867
3868 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
3869 dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
3870 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
3871 if (real_port < 0)
3872 return -EINVAL;
3873 gid[5] = real_port;
3874 }
3875
3876 return 0;
3877}
3878
c82e9aa0
EC		 3879int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
3880 struct mlx4_vhcr *vhcr,
3881 struct mlx4_cmd_mailbox *inbox,
3882 struct mlx4_cmd_mailbox *outbox,
3883 struct mlx4_cmd_info *cmd)
3884{
3885 struct mlx4_qp qp; /* dummy for calling attach/detach */
3886 u8 *gid = inbox->buf;
3887 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
162344ed 3888 int err;
c82e9aa0
EC		 3889 int qpn;
3890 struct res_qp *rqp;
fab1e24a 3891 u64 reg_id = 0;
c82e9aa0
EC		 3892 int attach = vhcr->op_modifier;
3893 int block_loopback = vhcr->in_modifier >> 31;
3894 u8 steer_type_mask = 2;
75c6062c 3895 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
c82e9aa0
EC		 3896
3897 qpn = vhcr->in_modifier & 0xffffff;
3898 err = get_res(dev, slave, qpn, RES_QP, &rqp);
3899 if (err)
3900 return err;
3901
3902 qp.qpn = qpn;
3903 if (attach) {
449fc488 3904 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
fab1e24a
HHZ		 3905 type, &reg_id);
3906 if (err) {
3907 pr_err("Fail to attach rule to qp 0x%x\n", qpn);
c82e9aa0 3908 goto ex_put;
fab1e24a
HHZ		 3909 }
3910 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
c82e9aa0 3911 if (err)
fab1e24a 3912 goto ex_detach;
c82e9aa0 3913 } else {
531d9014
JM		 3914 err = mlx4_adjust_port(dev, slave, gid, prot);
3915 if (err)
3916 goto ex_put;
3917
fab1e24a 3918 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
c82e9aa0
EC		 3919 if (err)
3920 goto ex_put;
c82e9aa0 3921
fab1e24a
HHZ		 3922 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
3923 if (err)
3924 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
3925 qpn, reg_id);
3926 }
c82e9aa0 3927 put_res(dev, slave, qpn, RES_QP);
fab1e24a 3928 return err;
c82e9aa0 3929
fab1e24a
HHZ		 3930ex_detach:
3931 qp_detach(dev, &qp, gid, prot, type, reg_id);
c82e9aa0
EC		 3932ex_put:
3933 put_res(dev, slave, qpn, RES_QP);
c82e9aa0
EC		 3934 return err;
3935}
3936
7fb40f87
HHZ		 3937/*
3938 * MAC validation for Flow Steering rules.
3939 * VF can attach rules only with a mac address which is assigned to it.
3940 */
3941static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
3942 struct list_head *rlist)
3943{
3944 struct mac_res *res, *tmp;
3945 __be64 be_mac;
3946
3947 /* make sure it isn't multicast or broadcast mac*/
3948 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
3949 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
3950 list_for_each_entry_safe(res, tmp, rlist, list) {
3951 be_mac = cpu_to_be64(res->mac << 16);
c0623e58 3952 if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
7fb40f87
HHZ		 3953 return 0;
3954 }
3955 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
3956 eth_header->eth.dst_mac, slave);
3957 return -EINVAL;
3958 }
3959 return 0;
3960}
3961
3962/*
3963 * In case of missing eth header, append eth header with a MAC address
3964 * assigned to the VF.
3965 */
3966static int add_eth_header(struct mlx4_dev *dev, int slave,
3967 struct mlx4_cmd_mailbox *inbox,
3968 struct list_head *rlist, int header_id)
3969{
3970 struct mac_res *res, *tmp;
3971 u8 port;
3972 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
3973 struct mlx4_net_trans_rule_hw_eth *eth_header;
3974 struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
3975 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
3976 __be64 be_mac = 0;
3977 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
3978
3979 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
015465f8 3980 port = ctrl->port;
7fb40f87
HHZ		 3981 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
3982
3983 /* Clear a space in the inbox for eth header */
3984 switch (header_id) {
3985 case MLX4_NET_TRANS_RULE_ID_IPV4:
3986 ip_header =
3987 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
3988 memmove(ip_header, eth_header,
3989 sizeof(*ip_header) + sizeof(*l4_header));
3990 break;
3991 case MLX4_NET_TRANS_RULE_ID_TCP:
3992 case MLX4_NET_TRANS_RULE_ID_UDP:
3993 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
3994 (eth_header + 1);
3995 memmove(l4_header, eth_header, sizeof(*l4_header));
3996 break;
3997 default:
3998 return -EINVAL;
3999 }
4000 list_for_each_entry_safe(res, tmp, rlist, list) {
4001 if (port == res->port) {
4002 be_mac = cpu_to_be64(res->mac << 16);
4003 break;
4004 }
4005 }
4006 if (!be_mac) {
1a91de28 4007 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
7fb40f87
HHZ		 4008 port);
4009 return -EINVAL;
4010 }
4011
4012 memset(eth_header, 0, sizeof(*eth_header));
4013 eth_header->size = sizeof(*eth_header) >> 2;
4014 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
4015 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
4016 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
4017
4018 return 0;
4019
4020}
4021
ce8d9e0d
MB		 4022#define MLX4_UPD_QP_PATH_MASK_SUPPORTED (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)
4023int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
4024 struct mlx4_vhcr *vhcr,
4025 struct mlx4_cmd_mailbox *inbox,
4026 struct mlx4_cmd_mailbox *outbox,
4027 struct mlx4_cmd_info *cmd_info)
4028{
4029 int err;
4030 u32 qpn = vhcr->in_modifier & 0xffffff;
4031 struct res_qp *rqp;
4032 u64 mac;
4033 unsigned port;
4034 u64 pri_addr_path_mask;
4035 struct mlx4_update_qp_context *cmd;
4036 int smac_index;
4037
4038 cmd = (struct mlx4_update_qp_context *)inbox->buf;
4039
4040 pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
4041 if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
4042 (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
4043 return -EPERM;
4044
4045 /* Just change the smac for the QP */
4046 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4047 if (err) {
4048 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
4049 return err;
4050 }
4051
4052 port = (rqp->sched_queue >> 6 & 1) + 1;
b7834758
MB		 4053
4054 if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
4055 smac_index = cmd->qp_context.pri_path.grh_mylmc;
4056 err = mac_find_smac_ix_in_slave(dev, slave, port,
4057 smac_index, &mac);
4058
4059 if (err) {
4060 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
4061 qpn, smac_index);
4062 goto err_mac;
4063 }
ce8d9e0d
MB		 4064 }
4065
4066 err = mlx4_cmd(dev, inbox->dma,
4067 vhcr->in_modifier, 0,
4068 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
4069 MLX4_CMD_NATIVE);
4070 if (err) {
4071 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
4072 goto err_mac;
4073 }
4074
4075err_mac:
4076 put_res(dev, slave, qpn, RES_QP);
4077 return err;
4078}
4079
8fcfb4db
HHZ		 4080int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4081 struct mlx4_vhcr *vhcr,
4082 struct mlx4_cmd_mailbox *inbox,
4083 struct mlx4_cmd_mailbox *outbox,
4084 struct mlx4_cmd_info *cmd)
4085{
7fb40f87
HHZ		 4086
4087 struct mlx4_priv *priv = mlx4_priv(dev);
4088 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4089 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
1b9c6b06 4090 int err;
a9c01e7a 4091 int qpn;
2c473ae7 4092 struct res_qp *rqp;
7fb40f87
HHZ		 4093 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4094 struct _rule_hw *rule_header;
4095 int header_id;
1b9c6b06 4096
0ff1fb65
HHZ		 4097 if (dev->caps.steering_mode !=
4098 MLX4_STEERING_MODE_DEVICE_MANAGED)
4099 return -EOPNOTSUPP;
1b9c6b06 4100
7fb40f87 4101 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
449fc488
MB		 4102 ctrl->port = mlx4_slave_convert_port(dev, slave, ctrl->port);
4103 if (ctrl->port <= 0)
4104 return -EINVAL;
a9c01e7a 4105 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
2c473ae7 4106 err = get_res(dev, slave, qpn, RES_QP, &rqp);
a9c01e7a 4107 if (err) {
1a91de28 4108 pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
a9c01e7a
HHZ		 4109 return err;
4110 }
7fb40f87
HHZ		 4111 rule_header = (struct _rule_hw *)(ctrl + 1);
4112 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
4113
4114 switch (header_id) {
4115 case MLX4_NET_TRANS_RULE_ID_ETH:
a9c01e7a
HHZ		 4116 if (validate_eth_header_mac(slave, rule_header, rlist)) {
4117 err = -EINVAL;
4118 goto err_put;
4119 }
7fb40f87 4120 break;
60396683
JM		 4121 case MLX4_NET_TRANS_RULE_ID_IB:
4122 break;
7fb40f87
HHZ		 4123 case MLX4_NET_TRANS_RULE_ID_IPV4:
4124 case MLX4_NET_TRANS_RULE_ID_TCP:
4125 case MLX4_NET_TRANS_RULE_ID_UDP:
1a91de28 4126 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
a9c01e7a
HHZ		 4127 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4128 err = -EINVAL;
4129 goto err_put;
4130 }
7fb40f87
HHZ		 4131 vhcr->in_modifier +=
4132 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4133 break;
4134 default:
1a91de28 4135 pr_err("Corrupted mailbox\n");
a9c01e7a
HHZ		 4136 err = -EINVAL;
4137 goto err_put;
7fb40f87
HHZ		 4138 }
4139
1b9c6b06
HHZ		 4140 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4141 vhcr->in_modifier, 0,
4142 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4143 MLX4_CMD_NATIVE);
4144 if (err)
a9c01e7a 4145 goto err_put;
1b9c6b06 4146
2c473ae7 4147 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
1b9c6b06 4148 if (err) {
1a91de28 4149 mlx4_err(dev, "Fail to add flow steering resources\n");
1b9c6b06
HHZ		 4150 /* detach rule*/
4151 mlx4_cmd(dev, vhcr->out_param, 0, 0,
2065b38b 4152 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1b9c6b06 4153 MLX4_CMD_NATIVE);
2c473ae7 4154 goto err_put;
1b9c6b06 4155 }
2c473ae7 4156 atomic_inc(&rqp->ref_count);
a9c01e7a
HHZ		 4157err_put:
4158 put_res(dev, slave, qpn, RES_QP);
1b9c6b06 4159 return err;
8fcfb4db
HHZ		 4160}
4161
4162int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4163 struct mlx4_vhcr *vhcr,
4164 struct mlx4_cmd_mailbox *inbox,
4165 struct mlx4_cmd_mailbox *outbox,
4166 struct mlx4_cmd_info *cmd)
4167{
1b9c6b06 4168 int err;
2c473ae7
HHZ		 4169 struct res_qp *rqp;
4170 struct res_fs_rule *rrule;
1b9c6b06 4171
0ff1fb65
HHZ		 4172 if (dev->caps.steering_mode !=
4173 MLX4_STEERING_MODE_DEVICE_MANAGED)
4174 return -EOPNOTSUPP;
1b9c6b06 4175
2c473ae7
HHZ		 4176 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4177 if (err)
4178 return err;
4179 /* Release the rule form busy state before removal */
4180 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4181 err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
4182 if (err)
4183 return err;
4184
1b9c6b06
HHZ		 4185 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4186 if (err) {
1a91de28 4187 mlx4_err(dev, "Fail to remove flow steering resources\n");
2c473ae7 4188 goto out;
1b9c6b06
HHZ		 4189 }
4190
4191 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4192 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4193 MLX4_CMD_NATIVE);
2c473ae7
HHZ		 4194 if (!err)
4195 atomic_dec(&rqp->ref_count);
4196out:
4197 put_res(dev, slave, rrule->qpn, RES_QP);
1b9c6b06 4198 return err;
8fcfb4db
HHZ		 4199}
4200
c82e9aa0
EC		 4201enum {
4202 BUSY_MAX_RETRIES = 10
4203};
4204
4205int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4206 struct mlx4_vhcr *vhcr,
4207 struct mlx4_cmd_mailbox *inbox,
4208 struct mlx4_cmd_mailbox *outbox,
4209 struct mlx4_cmd_info *cmd)
4210{
4211 int err;
4212 int index = vhcr->in_modifier & 0xffff;
4213
4214 err = get_res(dev, slave, index, RES_COUNTER, NULL);
4215 if (err)
4216 return err;
4217
4218 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4219 put_res(dev, slave, index, RES_COUNTER);
4220 return err;
4221}
4222
4223static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4224{
4225 struct res_gid *rgid;
4226 struct res_gid *tmp;
c82e9aa0
EC		 4227 struct mlx4_qp qp; /* dummy for calling attach/detach */
4228
4229 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
fab1e24a
HHZ		 4230 switch (dev->caps.steering_mode) {
4231 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4232 mlx4_flow_detach(dev, rgid->reg_id);
4233 break;
4234 case MLX4_STEERING_MODE_B0:
4235 qp.qpn = rqp->local_qpn;
4236 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4237 rgid->prot, rgid->steer);
4238 break;
4239 }
c82e9aa0
EC		 4240 list_del(&rgid->list);
4241 kfree(rgid);
4242 }
4243}
4244
4245static int _move_all_busy(struct mlx4_dev *dev, int slave,
4246 enum mlx4_resource type, int print)
4247{
4248 struct mlx4_priv *priv = mlx4_priv(dev);
4249 struct mlx4_resource_tracker *tracker =
4250 &priv->mfunc.master.res_tracker;
4251 struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4252 struct res_common *r;
4253 struct res_common *tmp;
4254 int busy;
4255
4256 busy = 0;
4257 spin_lock_irq(mlx4_tlock(dev));
4258 list_for_each_entry_safe(r, tmp, rlist, list) {
4259 if (r->owner == slave) {
4260 if (!r->removing) {
4261 if (r->state == RES_ANY_BUSY) {
4262 if (print)
4263 mlx4_dbg(dev,
aa1ec3dd 4264 "%s id 0x%llx is busy\n",
95646373 4265 resource_str(type),
c82e9aa0
EC		 4266 r->res_id);
4267 ++busy;
4268 } else {
4269 r->from_state = r->state;
4270 r->state = RES_ANY_BUSY;
4271 r->removing = 1;
4272 }
4273 }
4274 }
4275 }
4276 spin_unlock_irq(mlx4_tlock(dev));
4277
4278 return busy;
4279}
4280
4281static int move_all_busy(struct mlx4_dev *dev, int slave,
4282 enum mlx4_resource type)
4283{
4284 unsigned long begin;
4285 int busy;
4286
4287 begin = jiffies;
4288 do {
4289 busy = _move_all_busy(dev, slave, type, 0);
4290 if (time_after(jiffies, begin + 5 * HZ))
4291 break;
4292 if (busy)
4293 cond_resched();
4294 } while (busy);
4295
4296 if (busy)
4297 busy = _move_all_busy(dev, slave, type, 1);
4298
4299 return busy;
4300}
4301static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4302{
4303 struct mlx4_priv *priv = mlx4_priv(dev);
4304 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4305 struct list_head *qp_list =
4306 &tracker->slave_list[slave].res_list[RES_QP];
4307 struct res_qp *qp;
4308 struct res_qp *tmp;
4309 int state;
4310 u64 in_param;
4311 int qpn;
4312 int err;
4313
4314 err = move_all_busy(dev, slave, RES_QP);
4315 if (err)
1a91de28
JP		 4316 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
4317 slave);
c82e9aa0
EC		 4318
4319 spin_lock_irq(mlx4_tlock(dev));
4320 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4321 spin_unlock_irq(mlx4_tlock(dev));
4322 if (qp->com.owner == slave) {
4323 qpn = qp->com.res_id;
4324 detach_qp(dev, slave, qp);
4325 state = qp->com.from_state;
4326 while (state != 0) {
4327 switch (state) {
4328 case RES_QP_RESERVED:
4329 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4330 rb_erase(&qp->com.node,
4331 &tracker->res_tree[RES_QP]);
c82e9aa0
EC		 4332 list_del(&qp->com.list);
4333 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4334 if (!valid_reserved(dev, slave, qpn)) {
4335 __mlx4_qp_release_range(dev, qpn, 1);
4336 mlx4_release_resource(dev, slave,
4337 RES_QP, 1, 0);
4338 }
c82e9aa0
EC		 4339 kfree(qp);
4340 state = 0;
4341 break;
4342 case RES_QP_MAPPED:
4343 if (!valid_reserved(dev, slave, qpn))
4344 __mlx4_qp_free_icm(dev, qpn);
4345 state = RES_QP_RESERVED;
4346 break;
4347 case RES_QP_HW:
4348 in_param = slave;
4349 err = mlx4_cmd(dev, in_param,
4350 qp->local_qpn, 2,
4351 MLX4_CMD_2RST_QP,
4352 MLX4_CMD_TIME_CLASS_A,
4353 MLX4_CMD_NATIVE);
4354 if (err)
1a91de28
JP		 4355 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
4356 slave, qp->local_qpn);
c82e9aa0
EC		 4357 atomic_dec(&qp->rcq->ref_count);
4358 atomic_dec(&qp->scq->ref_count);
4359 atomic_dec(&qp->mtt->ref_count);
4360 if (qp->srq)
4361 atomic_dec(&qp->srq->ref_count);
4362 state = RES_QP_MAPPED;
4363 break;
4364 default:
4365 state = 0;
4366 }
4367 }
4368 }
4369 spin_lock_irq(mlx4_tlock(dev));
4370 }
4371 spin_unlock_irq(mlx4_tlock(dev));
4372}
4373
4374static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4375{
4376 struct mlx4_priv *priv = mlx4_priv(dev);
4377 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4378 struct list_head *srq_list =
4379 &tracker->slave_list[slave].res_list[RES_SRQ];
4380 struct res_srq *srq;
4381 struct res_srq *tmp;
4382 int state;
4383 u64 in_param;
4384 LIST_HEAD(tlist);
4385 int srqn;
4386 int err;
4387
4388 err = move_all_busy(dev, slave, RES_SRQ);
4389 if (err)
1a91de28
JP		 4390 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
4391 slave);
c82e9aa0
EC		 4392
4393 spin_lock_irq(mlx4_tlock(dev));
4394 list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4395 spin_unlock_irq(mlx4_tlock(dev));
4396 if (srq->com.owner == slave) {
4397 srqn = srq->com.res_id;
4398 state = srq->com.from_state;
4399 while (state != 0) {
4400 switch (state) {
4401 case RES_SRQ_ALLOCATED:
4402 __mlx4_srq_free_icm(dev, srqn);
4403 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4404 rb_erase(&srq->com.node,
4405 &tracker->res_tree[RES_SRQ]);
c82e9aa0
EC		 4406 list_del(&srq->com.list);
4407 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4408 mlx4_release_resource(dev, slave,
4409 RES_SRQ, 1, 0);
c82e9aa0
EC		 4410 kfree(srq);
4411 state = 0;
4412 break;
4413
4414 case RES_SRQ_HW:
4415 in_param = slave;
4416 err = mlx4_cmd(dev, in_param, srqn, 1,
4417 MLX4_CMD_HW2SW_SRQ,
4418 MLX4_CMD_TIME_CLASS_A,
4419 MLX4_CMD_NATIVE);
4420 if (err)
1a91de28 4421 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
c82e9aa0
EC		 4422 slave, srqn);
4423
4424 atomic_dec(&srq->mtt->ref_count);
4425 if (srq->cq)
4426 atomic_dec(&srq->cq->ref_count);
4427 state = RES_SRQ_ALLOCATED;
4428 break;
4429
4430 default:
4431 state = 0;
4432 }
4433 }
4434 }
4435 spin_lock_irq(mlx4_tlock(dev));
4436 }
4437 spin_unlock_irq(mlx4_tlock(dev));
4438}
4439
4440static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4441{
4442 struct mlx4_priv *priv = mlx4_priv(dev);
4443 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4444 struct list_head *cq_list =
4445 &tracker->slave_list[slave].res_list[RES_CQ];
4446 struct res_cq *cq;
4447 struct res_cq *tmp;
4448 int state;
4449 u64 in_param;
4450 LIST_HEAD(tlist);
4451 int cqn;
4452 int err;
4453
4454 err = move_all_busy(dev, slave, RES_CQ);
4455 if (err)
1a91de28
JP		 4456 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
4457 slave);
c82e9aa0
EC		 4458
4459 spin_lock_irq(mlx4_tlock(dev));
4460 list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4461 spin_unlock_irq(mlx4_tlock(dev));
4462 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4463 cqn = cq->com.res_id;
4464 state = cq->com.from_state;
4465 while (state != 0) {
4466 switch (state) {
4467 case RES_CQ_ALLOCATED:
4468 __mlx4_cq_free_icm(dev, cqn);
4469 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4470 rb_erase(&cq->com.node,
4471 &tracker->res_tree[RES_CQ]);
c82e9aa0
EC		 4472 list_del(&cq->com.list);
4473 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4474 mlx4_release_resource(dev, slave,
4475 RES_CQ, 1, 0);
c82e9aa0
EC		 4476 kfree(cq);
4477 state = 0;
4478 break;
4479
4480 case RES_CQ_HW:
4481 in_param = slave;
4482 err = mlx4_cmd(dev, in_param, cqn, 1,
4483 MLX4_CMD_HW2SW_CQ,
4484 MLX4_CMD_TIME_CLASS_A,
4485 MLX4_CMD_NATIVE);
4486 if (err)
1a91de28 4487 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
c82e9aa0
EC		 4488 slave, cqn);
4489 atomic_dec(&cq->mtt->ref_count);
4490 state = RES_CQ_ALLOCATED;
4491 break;
4492
4493 default:
4494 state = 0;
4495 }
4496 }
4497 }
4498 spin_lock_irq(mlx4_tlock(dev));
4499 }
4500 spin_unlock_irq(mlx4_tlock(dev));
4501}
4502
4503static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4504{
4505 struct mlx4_priv *priv = mlx4_priv(dev);
4506 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4507 struct list_head *mpt_list =
4508 &tracker->slave_list[slave].res_list[RES_MPT];
4509 struct res_mpt *mpt;
4510 struct res_mpt *tmp;
4511 int state;
4512 u64 in_param;
4513 LIST_HEAD(tlist);
4514 int mptn;
4515 int err;
4516
4517 err = move_all_busy(dev, slave, RES_MPT);
4518 if (err)
1a91de28
JP		 4519 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
4520 slave);
c82e9aa0
EC		 4521
4522 spin_lock_irq(mlx4_tlock(dev));
4523 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4524 spin_unlock_irq(mlx4_tlock(dev));
4525 if (mpt->com.owner == slave) {
4526 mptn = mpt->com.res_id;
4527 state = mpt->com.from_state;
4528 while (state != 0) {
4529 switch (state) {
4530 case RES_MPT_RESERVED:
b20e519a 4531 __mlx4_mpt_release(dev, mpt->key);
c82e9aa0 4532 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4533 rb_erase(&mpt->com.node,
4534 &tracker->res_tree[RES_MPT]);
c82e9aa0
EC		 4535 list_del(&mpt->com.list);
4536 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4537 mlx4_release_resource(dev, slave,
4538 RES_MPT, 1, 0);
c82e9aa0
EC		 4539 kfree(mpt);
4540 state = 0;
4541 break;
4542
4543 case RES_MPT_MAPPED:
b20e519a 4544 __mlx4_mpt_free_icm(dev, mpt->key);
c82e9aa0
EC		 4545 state = RES_MPT_RESERVED;
4546 break;
4547
4548 case RES_MPT_HW:
4549 in_param = slave;
4550 err = mlx4_cmd(dev, in_param, mptn, 0,
4551 MLX4_CMD_HW2SW_MPT,
4552 MLX4_CMD_TIME_CLASS_A,
4553 MLX4_CMD_NATIVE);
4554 if (err)
1a91de28 4555 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
c82e9aa0
EC		 4556 slave, mptn);
4557 if (mpt->mtt)
4558 atomic_dec(&mpt->mtt->ref_count);
4559 state = RES_MPT_MAPPED;
4560 break;
4561 default:
4562 state = 0;
4563 }
4564 }
4565 }
4566 spin_lock_irq(mlx4_tlock(dev));
4567 }
4568 spin_unlock_irq(mlx4_tlock(dev));
4569}
4570
4571static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4572{
4573 struct mlx4_priv *priv = mlx4_priv(dev);
4574 struct mlx4_resource_tracker *tracker =
4575 &priv->mfunc.master.res_tracker;
4576 struct list_head *mtt_list =
4577 &tracker->slave_list[slave].res_list[RES_MTT];
4578 struct res_mtt *mtt;
4579 struct res_mtt *tmp;
4580 int state;
4581 LIST_HEAD(tlist);
4582 int base;
4583 int err;
4584
4585 err = move_all_busy(dev, slave, RES_MTT);
4586 if (err)
1a91de28
JP		 4587 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n",
4588 slave);
c82e9aa0
EC		 4589
4590 spin_lock_irq(mlx4_tlock(dev));
4591 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4592 spin_unlock_irq(mlx4_tlock(dev));
4593 if (mtt->com.owner == slave) {
4594 base = mtt->com.res_id;
4595 state = mtt->com.from_state;
4596 while (state != 0) {
4597 switch (state) {
4598 case RES_MTT_ALLOCATED:
4599 __mlx4_free_mtt_range(dev, base,
4600 mtt->order);
4601 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4602 rb_erase(&mtt->com.node,
4603 &tracker->res_tree[RES_MTT]);
c82e9aa0
EC		 4604 list_del(&mtt->com.list);
4605 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4606 mlx4_release_resource(dev, slave, RES_MTT,
4607 1 << mtt->order, 0);
c82e9aa0
EC		 4608 kfree(mtt);
4609 state = 0;
4610 break;
4611
4612 default:
4613 state = 0;
4614 }
4615 }
4616 }
4617 spin_lock_irq(mlx4_tlock(dev));
4618 }
4619 spin_unlock_irq(mlx4_tlock(dev));
4620}
4621
1b9c6b06
HHZ		 4622static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
4623{
4624 struct mlx4_priv *priv = mlx4_priv(dev);
4625 struct mlx4_resource_tracker *tracker =
4626 &priv->mfunc.master.res_tracker;
4627 struct list_head *fs_rule_list =
4628 &tracker->slave_list[slave].res_list[RES_FS_RULE];
4629 struct res_fs_rule *fs_rule;
4630 struct res_fs_rule *tmp;
4631 int state;
4632 u64 base;
4633 int err;
4634
4635 err = move_all_busy(dev, slave, RES_FS_RULE);
4636 if (err)
4637 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
4638 slave);
4639
4640 spin_lock_irq(mlx4_tlock(dev));
4641 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
4642 spin_unlock_irq(mlx4_tlock(dev));
4643 if (fs_rule->com.owner == slave) {
4644 base = fs_rule->com.res_id;
4645 state = fs_rule->com.from_state;
4646 while (state != 0) {
4647 switch (state) {
4648 case RES_FS_RULE_ALLOCATED:
4649 /* detach rule */
4650 err = mlx4_cmd(dev, base, 0, 0,
4651 MLX4_QP_FLOW_STEERING_DETACH,
4652 MLX4_CMD_TIME_CLASS_A,
4653 MLX4_CMD_NATIVE);
4654
4655 spin_lock_irq(mlx4_tlock(dev));
4656 rb_erase(&fs_rule->com.node,
4657 &tracker->res_tree[RES_FS_RULE]);
4658 list_del(&fs_rule->com.list);
4659 spin_unlock_irq(mlx4_tlock(dev));
4660 kfree(fs_rule);
4661 state = 0;
4662 break;
4663
4664 default:
4665 state = 0;
4666 }
4667 }
4668 }
4669 spin_lock_irq(mlx4_tlock(dev));
4670 }
4671 spin_unlock_irq(mlx4_tlock(dev));
4672}
4673
c82e9aa0
EC		 4674static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
4675{
4676 struct mlx4_priv *priv = mlx4_priv(dev);
4677 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4678 struct list_head *eq_list =
4679 &tracker->slave_list[slave].res_list[RES_EQ];
4680 struct res_eq *eq;
4681 struct res_eq *tmp;
4682 int err;
4683 int state;
4684 LIST_HEAD(tlist);
4685 int eqn;
c82e9aa0
EC		 4686
4687 err = move_all_busy(dev, slave, RES_EQ);
4688 if (err)
1a91de28
JP		 4689 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
4690 slave);
c82e9aa0
EC		 4691
4692 spin_lock_irq(mlx4_tlock(dev));
4693 list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
4694 spin_unlock_irq(mlx4_tlock(dev));
4695 if (eq->com.owner == slave) {
4696 eqn = eq->com.res_id;
4697 state = eq->com.from_state;
4698 while (state != 0) {
4699 switch (state) {
4700 case RES_EQ_RESERVED:
4701 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4702 rb_erase(&eq->com.node,
4703 &tracker->res_tree[RES_EQ]);
c82e9aa0
EC		 4704 list_del(&eq->com.list);
4705 spin_unlock_irq(mlx4_tlock(dev));
4706 kfree(eq);
4707 state = 0;
4708 break;
4709
4710 case RES_EQ_HW:
30a5da5b
JM		 4711 err = mlx4_cmd(dev, slave, eqn & 0xff,
4712 1, MLX4_CMD_HW2SW_EQ,
4713 MLX4_CMD_TIME_CLASS_A,
4714 MLX4_CMD_NATIVE);
eb71d0d6 4715 if (err)
1a91de28
JP		 4716 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
4717 slave, eqn);
eb71d0d6
JM		 4718 atomic_dec(&eq->mtt->ref_count);
4719 state = RES_EQ_RESERVED;
c82e9aa0
EC		 4720 break;
4721
4722 default:
4723 state = 0;
4724 }
4725 }
4726 }
4727 spin_lock_irq(mlx4_tlock(dev));
4728 }
4729 spin_unlock_irq(mlx4_tlock(dev));
4730}
4731
ba062d52
JM		 4732static void rem_slave_counters(struct mlx4_dev *dev, int slave)
4733{
4734 struct mlx4_priv *priv = mlx4_priv(dev);
4735 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4736 struct list_head *counter_list =
4737 &tracker->slave_list[slave].res_list[RES_COUNTER];
4738 struct res_counter *counter;
4739 struct res_counter *tmp;
4740 int err;
4741 int index;
4742
4743 err = move_all_busy(dev, slave, RES_COUNTER);
4744 if (err)
1a91de28
JP		 4745 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
4746 slave);
ba062d52
JM		 4747
4748 spin_lock_irq(mlx4_tlock(dev));
4749 list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
4750 if (counter->com.owner == slave) {
4751 index = counter->com.res_id;
4af1c048
HHZ		 4752 rb_erase(&counter->com.node,
4753 &tracker->res_tree[RES_COUNTER]);
ba062d52
JM		 4754 list_del(&counter->com.list);
4755 kfree(counter);
4756 __mlx4_counter_free(dev, index);
146f3ef4 4757 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 4758 }
4759 }
4760 spin_unlock_irq(mlx4_tlock(dev));
4761}
4762
4763static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
4764{
4765 struct mlx4_priv *priv = mlx4_priv(dev);
4766 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4767 struct list_head *xrcdn_list =
4768 &tracker->slave_list[slave].res_list[RES_XRCD];
4769 struct res_xrcdn *xrcd;
4770 struct res_xrcdn *tmp;
4771 int err;
4772 int xrcdn;
4773
4774 err = move_all_busy(dev, slave, RES_XRCD);
4775 if (err)
1a91de28
JP		 4776 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
4777 slave);
ba062d52
JM		 4778
4779 spin_lock_irq(mlx4_tlock(dev));
4780 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
4781 if (xrcd->com.owner == slave) {
4782 xrcdn = xrcd->com.res_id;
4af1c048 4783 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
ba062d52
JM		 4784 list_del(&xrcd->com.list);
4785 kfree(xrcd);
4786 __mlx4_xrcd_free(dev, xrcdn);
4787 }
4788 }
4789 spin_unlock_irq(mlx4_tlock(dev));
4790}
4791
c82e9aa0
EC		 4792void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
4793{
4794 struct mlx4_priv *priv = mlx4_priv(dev);
111c6094 4795 mlx4_reset_roce_gids(dev, slave);
c82e9aa0 4796 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4874080d 4797 rem_slave_vlans(dev, slave);
c82e9aa0 4798 rem_slave_macs(dev, slave);
80cb0021 4799 rem_slave_fs_rule(dev, slave);
c82e9aa0
EC		 4800 rem_slave_qps(dev, slave);
4801 rem_slave_srqs(dev, slave);
4802 rem_slave_cqs(dev, slave);
4803 rem_slave_mrs(dev, slave);
4804 rem_slave_eqs(dev, slave);
4805 rem_slave_mtts(dev, slave);
ba062d52
JM		 4806 rem_slave_counters(dev, slave);
4807 rem_slave_xrcdns(dev, slave);
c82e9aa0
EC		 4808 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4809}
b01978ca
JM		 4810
4811void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
4812{
4813 struct mlx4_vf_immed_vlan_work *work =
4814 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
4815 struct mlx4_cmd_mailbox *mailbox;
4816 struct mlx4_update_qp_context *upd_context;
4817 struct mlx4_dev *dev = &work->priv->dev;
4818 struct mlx4_resource_tracker *tracker =
4819 &work->priv->mfunc.master.res_tracker;
4820 struct list_head *qp_list =
4821 &tracker->slave_list[work->slave].res_list[RES_QP];
4822 struct res_qp *qp;
4823 struct res_qp *tmp;
f0f829bf
RE		 4824 u64 qp_path_mask_vlan_ctrl =
4825 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
b01978ca
JM		 4826 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
4827 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
4828 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
4829 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
f0f829bf
RE		 4830 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
4831
4832 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
4833 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
4834 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
4835 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
4836 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
4837 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
b01978ca
JM		 4838 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
4839
4840 int err;
4841 int port, errors = 0;
4842 u8 vlan_control;
4843
4844 if (mlx4_is_slave(dev)) {
4845 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
4846 work->slave);
4847 goto out;
4848 }
4849
4850 mailbox = mlx4_alloc_cmd_mailbox(dev);
4851 if (IS_ERR(mailbox))
4852 goto out;
0a6eac24
RE		 4853 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
4854 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4855 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
4856 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
4857 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
4858 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
4859 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
4860 else if (!work->vlan_id)
b01978ca
JM		 4861 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4862 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
4863 else
4864 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4865 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
4866 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
4867
4868 upd_context = mailbox->buf;
311be98a 4869 upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
b01978ca
JM		 4870
4871 spin_lock_irq(mlx4_tlock(dev));
4872 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4873 spin_unlock_irq(mlx4_tlock(dev));
4874 if (qp->com.owner == work->slave) {
4875 if (qp->com.from_state != RES_QP_HW ||
4876 !qp->sched_queue || /* no INIT2RTR trans yet */
4877 mlx4_is_qp_reserved(dev, qp->local_qpn) ||
4878 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
4879 spin_lock_irq(mlx4_tlock(dev));
4880 continue;
4881 }
4882 port = (qp->sched_queue >> 6 & 1) + 1;
4883 if (port != work->port) {
4884 spin_lock_irq(mlx4_tlock(dev));
4885 continue;
4886 }
f0f829bf
RE		 4887 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
4888 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
4889 else
4890 upd_context->primary_addr_path_mask =
4891 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
4892 if (work->vlan_id == MLX4_VGT) {
4893 upd_context->qp_context.param3 = qp->param3;
4894 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
4895 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
4896 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
4897 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
4898 upd_context->qp_context.pri_path.feup = qp->feup;
4899 upd_context->qp_context.pri_path.sched_queue =
4900 qp->sched_queue;
4901 } else {
4902 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
4903 upd_context->qp_context.pri_path.vlan_control = vlan_control;
4904 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
4905 upd_context->qp_context.pri_path.fvl_rx =
4906 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
4907 upd_context->qp_context.pri_path.fl =
4908 qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
4909 upd_context->qp_context.pri_path.feup =
4910 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
4911 upd_context->qp_context.pri_path.sched_queue =
4912 qp->sched_queue & 0xC7;
4913 upd_context->qp_context.pri_path.sched_queue |=
4914 ((work->qos & 0x7) << 3);
4915 }
b01978ca
JM		 4916
4917 err = mlx4_cmd(dev, mailbox->dma,
4918 qp->local_qpn & 0xffffff,
4919 0, MLX4_CMD_UPDATE_QP,
4920 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
4921 if (err) {
1a91de28
JP		 4922 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
4923 work->slave, port, qp->local_qpn, err);
b01978ca
JM		 4924 errors++;
4925 }
4926 }
4927 spin_lock_irq(mlx4_tlock(dev));
4928 }
4929 spin_unlock_irq(mlx4_tlock(dev));
4930 mlx4_free_cmd_mailbox(dev, mailbox);
4931
4932 if (errors)
4933 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
4934 errors, work->slave, work->port);
4935
4936 /* unregister previous vlan_id if needed and we had no errors
4937 * while updating the QPs
4938 */
4939 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
4940 NO_INDX != work->orig_vlan_ix)
4941 __mlx4_unregister_vlan(&work->priv->dev, work->port,
2009d005 4942 work->orig_vlan_id);
b01978ca
JM		 4943out:
4944 kfree(work);
4945 return;
4946}
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