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net/mlx5e: Wake On LAN support
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97 34#include <linux/module.h>
e126ba97
EC		 35#include <linux/errno.h>
36#include <linux/pci.h>
37#include <linux/dma-mapping.h>
38#include <linux/slab.h>
39#include <linux/delay.h>
40#include <linux/random.h>
41#include <linux/io-mapping.h>
42#include <linux/mlx5/driver.h>
43#include <linux/debugfs.h>
44
45#include "mlx5_core.h"
46
47enum {
0a324f31 48 CMD_IF_REV = 5,
e126ba97
EC		 49};
50
51enum {
52 CMD_MODE_POLLING,
53 CMD_MODE_EVENTS
54};
55
56enum {
57 NUM_LONG_LISTS = 2,
58 NUM_MED_LISTS = 64,
59 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
60 MLX5_CMD_DATA_BLOCK_SIZE,
61 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
62};
63
64enum {
65 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
66 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
67 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
68 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
69 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
70 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
71 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
72 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
73 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
74 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
75 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
76};
77
e126ba97
EC		 78static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
79 struct mlx5_cmd_msg *in,
80 struct mlx5_cmd_msg *out,
746b5583 81 void *uout, int uout_size,
e126ba97
EC		 82 mlx5_cmd_cbk_t cbk,
83 void *context, int page_queue)
84{
85 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
86 struct mlx5_cmd_work_ent *ent;
87
88 ent = kzalloc(sizeof(*ent), alloc_flags);
89 if (!ent)
90 return ERR_PTR(-ENOMEM);
91
92 ent->in = in;
93 ent->out = out;
746b5583
EC		 94 ent->uout = uout;
95 ent->uout_size = uout_size;
e126ba97
EC		 96 ent->callback = cbk;
97 ent->context = context;
98 ent->cmd = cmd;
99 ent->page_queue = page_queue;
100
101 return ent;
102}
103
104static u8 alloc_token(struct mlx5_cmd *cmd)
105{
106 u8 token;
107
108 spin_lock(&cmd->token_lock);
4cbdd27c
AS		 109 cmd->token++;
110 if (cmd->token == 0)
111 cmd->token++;
112 token = cmd->token;
e126ba97
EC		 113 spin_unlock(&cmd->token_lock);
114
115 return token;
116}
117
118static int alloc_ent(struct mlx5_cmd *cmd)
119{
120 unsigned long flags;
121 int ret;
122
123 spin_lock_irqsave(&cmd->alloc_lock, flags);
124 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
125 if (ret < cmd->max_reg_cmds)
126 clear_bit(ret, &cmd->bitmask);
127 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
128
129 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
130}
131
132static void free_ent(struct mlx5_cmd *cmd, int idx)
133{
134 unsigned long flags;
135
136 spin_lock_irqsave(&cmd->alloc_lock, flags);
137 set_bit(idx, &cmd->bitmask);
138 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
139}
140
141static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
142{
143 return cmd->cmd_buf + (idx << cmd->log_stride);
144}
145
146static u8 xor8_buf(void *buf, int len)
147{
148 u8 *ptr = buf;
149 u8 sum = 0;
150 int i;
151
152 for (i = 0; i < len; i++)
153 sum ^= ptr[i];
154
155 return sum;
156}
157
158static int verify_block_sig(struct mlx5_cmd_prot_block *block)
159{
160 if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
161 return -EINVAL;
162
163 if (xor8_buf(block, sizeof(*block)) != 0xff)
164 return -EINVAL;
165
166 return 0;
167}
168
c1868b82
EC		 169static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
170 int csum)
e126ba97
EC		 171{
172 block->token = token;
c1868b82
EC		 173 if (csum) {
174 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
175 sizeof(block->data) - 2);
176 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
177 }
e126ba97
EC		 178}
179
c1868b82 180static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
e126ba97
EC		 181{
182 struct mlx5_cmd_mailbox *next = msg->next;
183
184 while (next) {
c1868b82 185 calc_block_sig(next->buf, token, csum);
e126ba97
EC		 186 next = next->next;
187 }
188}
189
c1868b82 190static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
e126ba97
EC		 191{
192 ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
c1868b82
EC		 193 calc_chain_sig(ent->in, ent->token, csum);
194 calc_chain_sig(ent->out, ent->token, csum);
e126ba97
EC		 195}
196
197static void poll_timeout(struct mlx5_cmd_work_ent *ent)
198{
199 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
200 u8 own;
201
202 do {
203 own = ent->lay->status_own;
204 if (!(own & CMD_OWNER_HW)) {
205 ent->ret = 0;
206 return;
207 }
208 usleep_range(5000, 10000);
209 } while (time_before(jiffies, poll_end));
210
211 ent->ret = -ETIMEDOUT;
212}
213
214static void free_cmd(struct mlx5_cmd_work_ent *ent)
215{
216 kfree(ent);
217}
218
219
220static int verify_signature(struct mlx5_cmd_work_ent *ent)
221{
222 struct mlx5_cmd_mailbox *next = ent->out->next;
223 int err;
224 u8 sig;
225
226 sig = xor8_buf(ent->lay, sizeof(*ent->lay));
227 if (sig != 0xff)
228 return -EINVAL;
229
230 while (next) {
231 err = verify_block_sig(next->buf);
232 if (err)
233 return err;
234
235 next = next->next;
236 }
237
238 return 0;
239}
240
241static void dump_buf(void *buf, int size, int data_only, int offset)
242{
243 __be32 *p = buf;
244 int i;
245
246 for (i = 0; i < size; i += 16) {
247 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
248 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
249 be32_to_cpu(p[3]));
250 p += 4;
251 offset += 16;
252 }
253 if (!data_only)
254 pr_debug("\n");
255}
256
020446e0
EC		 257enum {
258 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
89d44f0a 259 MLX5_DRIVER_SYND = 0xbadd00de,
020446e0
EC		 260};
261
89d44f0a
MD		 262static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
263 u32 *synd, u8 *status)
264{
265 *synd = 0;
266 *status = 0;
267
268 switch (op) {
269 case MLX5_CMD_OP_TEARDOWN_HCA:
270 case MLX5_CMD_OP_DISABLE_HCA:
271 case MLX5_CMD_OP_MANAGE_PAGES:
272 case MLX5_CMD_OP_DESTROY_MKEY:
273 case MLX5_CMD_OP_DESTROY_EQ:
274 case MLX5_CMD_OP_DESTROY_CQ:
275 case MLX5_CMD_OP_DESTROY_QP:
276 case MLX5_CMD_OP_DESTROY_PSV:
277 case MLX5_CMD_OP_DESTROY_SRQ:
278 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
279 case MLX5_CMD_OP_DESTROY_DCT:
280 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
281 case MLX5_CMD_OP_DEALLOC_PD:
282 case MLX5_CMD_OP_DEALLOC_UAR:
283 case MLX5_CMD_OP_DETTACH_FROM_MCG:
284 case MLX5_CMD_OP_DEALLOC_XRCD:
285 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
286 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
287 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
288 case MLX5_CMD_OP_DESTROY_TIR:
289 case MLX5_CMD_OP_DESTROY_SQ:
290 case MLX5_CMD_OP_DESTROY_RQ:
291 case MLX5_CMD_OP_DESTROY_RMP:
292 case MLX5_CMD_OP_DESTROY_TIS:
293 case MLX5_CMD_OP_DESTROY_RQT:
294 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
295 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
296 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
297 return MLX5_CMD_STAT_OK;
298
299 case MLX5_CMD_OP_QUERY_HCA_CAP:
300 case MLX5_CMD_OP_QUERY_ADAPTER:
301 case MLX5_CMD_OP_INIT_HCA:
302 case MLX5_CMD_OP_ENABLE_HCA:
303 case MLX5_CMD_OP_QUERY_PAGES:
304 case MLX5_CMD_OP_SET_HCA_CAP:
305 case MLX5_CMD_OP_QUERY_ISSI:
306 case MLX5_CMD_OP_SET_ISSI:
307 case MLX5_CMD_OP_CREATE_MKEY:
308 case MLX5_CMD_OP_QUERY_MKEY:
309 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
310 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
311 case MLX5_CMD_OP_CREATE_EQ:
312 case MLX5_CMD_OP_QUERY_EQ:
313 case MLX5_CMD_OP_GEN_EQE:
314 case MLX5_CMD_OP_CREATE_CQ:
315 case MLX5_CMD_OP_QUERY_CQ:
316 case MLX5_CMD_OP_MODIFY_CQ:
317 case MLX5_CMD_OP_CREATE_QP:
318 case MLX5_CMD_OP_RST2INIT_QP:
319 case MLX5_CMD_OP_INIT2RTR_QP:
320 case MLX5_CMD_OP_RTR2RTS_QP:
321 case MLX5_CMD_OP_RTS2RTS_QP:
322 case MLX5_CMD_OP_SQERR2RTS_QP:
323 case MLX5_CMD_OP_2ERR_QP:
324 case MLX5_CMD_OP_2RST_QP:
325 case MLX5_CMD_OP_QUERY_QP:
326 case MLX5_CMD_OP_SQD_RTS_QP:
327 case MLX5_CMD_OP_INIT2INIT_QP:
328 case MLX5_CMD_OP_CREATE_PSV:
329 case MLX5_CMD_OP_CREATE_SRQ:
330 case MLX5_CMD_OP_QUERY_SRQ:
331 case MLX5_CMD_OP_ARM_RQ:
332 case MLX5_CMD_OP_CREATE_XRC_SRQ:
333 case MLX5_CMD_OP_QUERY_XRC_SRQ:
334 case MLX5_CMD_OP_ARM_XRC_SRQ:
335 case MLX5_CMD_OP_CREATE_DCT:
336 case MLX5_CMD_OP_DRAIN_DCT:
337 case MLX5_CMD_OP_QUERY_DCT:
338 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
339 case MLX5_CMD_OP_QUERY_VPORT_STATE:
340 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
341 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
342 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
343 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
344 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
345 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
346 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
347 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
348 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
349 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
350 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
351 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
352 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
353 case MLX5_CMD_OP_QUERY_Q_COUNTER:
354 case MLX5_CMD_OP_ALLOC_PD:
355 case MLX5_CMD_OP_ALLOC_UAR:
356 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
357 case MLX5_CMD_OP_ACCESS_REG:
358 case MLX5_CMD_OP_ATTACH_TO_MCG:
359 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
360 case MLX5_CMD_OP_MAD_IFC:
361 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
362 case MLX5_CMD_OP_SET_MAD_DEMUX:
363 case MLX5_CMD_OP_NOP:
364 case MLX5_CMD_OP_ALLOC_XRCD:
365 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
366 case MLX5_CMD_OP_QUERY_CONG_STATUS:
367 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
368 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
369 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
370 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
371 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
372 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
373 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
374 case MLX5_CMD_OP_CREATE_TIR:
375 case MLX5_CMD_OP_MODIFY_TIR:
376 case MLX5_CMD_OP_QUERY_TIR:
377 case MLX5_CMD_OP_CREATE_SQ:
378 case MLX5_CMD_OP_MODIFY_SQ:
379 case MLX5_CMD_OP_QUERY_SQ:
380 case MLX5_CMD_OP_CREATE_RQ:
381 case MLX5_CMD_OP_MODIFY_RQ:
382 case MLX5_CMD_OP_QUERY_RQ:
383 case MLX5_CMD_OP_CREATE_RMP:
384 case MLX5_CMD_OP_MODIFY_RMP:
385 case MLX5_CMD_OP_QUERY_RMP:
386 case MLX5_CMD_OP_CREATE_TIS:
387 case MLX5_CMD_OP_MODIFY_TIS:
388 case MLX5_CMD_OP_QUERY_TIS:
389 case MLX5_CMD_OP_CREATE_RQT:
390 case MLX5_CMD_OP_MODIFY_RQT:
391 case MLX5_CMD_OP_QUERY_RQT:
392 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
393 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
394 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
395 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
396 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
397 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
398 *status = MLX5_DRIVER_STATUS_ABORTED;
399 *synd = MLX5_DRIVER_SYND;
400 return -EIO;
401 default:
402 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
403 return -EINVAL;
404 }
405}
406
e126ba97
EC		 407const char *mlx5_command_str(int command)
408{
409 switch (command) {
410 case MLX5_CMD_OP_QUERY_HCA_CAP:
411 return "QUERY_HCA_CAP";
412
413 case MLX5_CMD_OP_SET_HCA_CAP:
414 return "SET_HCA_CAP";
415
416 case MLX5_CMD_OP_QUERY_ADAPTER:
417 return "QUERY_ADAPTER";
418
419 case MLX5_CMD_OP_INIT_HCA:
420 return "INIT_HCA";
421
422 case MLX5_CMD_OP_TEARDOWN_HCA:
423 return "TEARDOWN_HCA";
424
cd23b14b
EC		 425 case MLX5_CMD_OP_ENABLE_HCA:
426 return "MLX5_CMD_OP_ENABLE_HCA";
427
428 case MLX5_CMD_OP_DISABLE_HCA:
429 return "MLX5_CMD_OP_DISABLE_HCA";
430
e126ba97
EC		 431 case MLX5_CMD_OP_QUERY_PAGES:
432 return "QUERY_PAGES";
433
434 case MLX5_CMD_OP_MANAGE_PAGES:
435 return "MANAGE_PAGES";
436
437 case MLX5_CMD_OP_CREATE_MKEY:
438 return "CREATE_MKEY";
439
440 case MLX5_CMD_OP_QUERY_MKEY:
441 return "QUERY_MKEY";
442
443 case MLX5_CMD_OP_DESTROY_MKEY:
444 return "DESTROY_MKEY";
445
446 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
447 return "QUERY_SPECIAL_CONTEXTS";
448
449 case MLX5_CMD_OP_CREATE_EQ:
450 return "CREATE_EQ";
451
452 case MLX5_CMD_OP_DESTROY_EQ:
453 return "DESTROY_EQ";
454
455 case MLX5_CMD_OP_QUERY_EQ:
456 return "QUERY_EQ";
457
458 case MLX5_CMD_OP_CREATE_CQ:
459 return "CREATE_CQ";
460
461 case MLX5_CMD_OP_DESTROY_CQ:
462 return "DESTROY_CQ";
463
464 case MLX5_CMD_OP_QUERY_CQ:
465 return "QUERY_CQ";
466
467 case MLX5_CMD_OP_MODIFY_CQ:
468 return "MODIFY_CQ";
469
470 case MLX5_CMD_OP_CREATE_QP:
471 return "CREATE_QP";
472
473 case MLX5_CMD_OP_DESTROY_QP:
474 return "DESTROY_QP";
475
476 case MLX5_CMD_OP_RST2INIT_QP:
477 return "RST2INIT_QP";
478
479 case MLX5_CMD_OP_INIT2RTR_QP:
480 return "INIT2RTR_QP";
481
482 case MLX5_CMD_OP_RTR2RTS_QP:
483 return "RTR2RTS_QP";
484
485 case MLX5_CMD_OP_RTS2RTS_QP:
486 return "RTS2RTS_QP";
487
488 case MLX5_CMD_OP_SQERR2RTS_QP:
489 return "SQERR2RTS_QP";
490
491 case MLX5_CMD_OP_2ERR_QP:
492 return "2ERR_QP";
493
e126ba97
EC		 494 case MLX5_CMD_OP_2RST_QP:
495 return "2RST_QP";
496
497 case MLX5_CMD_OP_QUERY_QP:
498 return "QUERY_QP";
499
e126ba97
EC		 500 case MLX5_CMD_OP_MAD_IFC:
501 return "MAD_IFC";
502
503 case MLX5_CMD_OP_INIT2INIT_QP:
504 return "INIT2INIT_QP";
505
e126ba97
EC		 506 case MLX5_CMD_OP_CREATE_PSV:
507 return "CREATE_PSV";
508
509 case MLX5_CMD_OP_DESTROY_PSV:
510 return "DESTROY_PSV";
511
e126ba97
EC		 512 case MLX5_CMD_OP_CREATE_SRQ:
513 return "CREATE_SRQ";
514
515 case MLX5_CMD_OP_DESTROY_SRQ:
516 return "DESTROY_SRQ";
517
518 case MLX5_CMD_OP_QUERY_SRQ:
519 return "QUERY_SRQ";
520
521 case MLX5_CMD_OP_ARM_RQ:
522 return "ARM_RQ";
523
e281682b
SM		 524 case MLX5_CMD_OP_CREATE_XRC_SRQ:
525 return "CREATE_XRC_SRQ";
526
527 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
528 return "DESTROY_XRC_SRQ";
529
530 case MLX5_CMD_OP_QUERY_XRC_SRQ:
531 return "QUERY_XRC_SRQ";
532
533 case MLX5_CMD_OP_ARM_XRC_SRQ:
534 return "ARM_XRC_SRQ";
e126ba97
EC		 535
536 case MLX5_CMD_OP_ALLOC_PD:
537 return "ALLOC_PD";
538
539 case MLX5_CMD_OP_DEALLOC_PD:
540 return "DEALLOC_PD";
541
542 case MLX5_CMD_OP_ALLOC_UAR:
543 return "ALLOC_UAR";
544
545 case MLX5_CMD_OP_DEALLOC_UAR:
546 return "DEALLOC_UAR";
547
548 case MLX5_CMD_OP_ATTACH_TO_MCG:
549 return "ATTACH_TO_MCG";
550
e281682b
SM		 551 case MLX5_CMD_OP_DETTACH_FROM_MCG:
552 return "DETTACH_FROM_MCG";
e126ba97
EC		 553
554 case MLX5_CMD_OP_ALLOC_XRCD:
555 return "ALLOC_XRCD";
556
557 case MLX5_CMD_OP_DEALLOC_XRCD:
558 return "DEALLOC_XRCD";
559
560 case MLX5_CMD_OP_ACCESS_REG:
561 return "MLX5_CMD_OP_ACCESS_REG";
562
928cfe87
TT		 563 case MLX5_CMD_OP_SET_WOL_ROL:
564 return "SET_WOL_ROL";
565
566 case MLX5_CMD_OP_QUERY_WOL_ROL:
567 return "QUERY_WOL_ROL";
568
e126ba97
EC		 569 default: return "unknown command opcode";
570 }
571}
572
573static void dump_command(struct mlx5_core_dev *dev,
574 struct mlx5_cmd_work_ent *ent, int input)
575{
576 u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
577 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
578 struct mlx5_cmd_mailbox *next = msg->next;
579 int data_only;
f241e749 580 u32 offset = 0;
e126ba97
EC		 581 int dump_len;
582
583 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
584
585 if (data_only)
586 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
587 "dump command data %s(0x%x) %s\n",
588 mlx5_command_str(op), op,
589 input ? "INPUT" : "OUTPUT");
590 else
591 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
592 mlx5_command_str(op), op,
593 input ? "INPUT" : "OUTPUT");
594
595 if (data_only) {
596 if (input) {
597 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
598 offset += sizeof(ent->lay->in);
599 } else {
600 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
601 offset += sizeof(ent->lay->out);
602 }
603 } else {
604 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
605 offset += sizeof(*ent->lay);
606 }
607
608 while (next && offset < msg->len) {
609 if (data_only) {
610 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
611 dump_buf(next->buf, dump_len, 1, offset);
612 offset += MLX5_CMD_DATA_BLOCK_SIZE;
613 } else {
614 mlx5_core_dbg(dev, "command block:\n");
615 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
616 offset += sizeof(struct mlx5_cmd_prot_block);
617 }
618 next = next->next;
619 }
620
621 if (data_only)
622 pr_debug("\n");
623}
624
625static void cmd_work_handler(struct work_struct *work)
626{
627 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
628 struct mlx5_cmd *cmd = ent->cmd;
629 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
630 struct mlx5_cmd_layout *lay;
631 struct semaphore *sem;
020446e0 632 unsigned long flags;
e126ba97
EC		 633
634 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
635 down(sem);
636 if (!ent->page_queue) {
637 ent->idx = alloc_ent(cmd);
638 if (ent->idx < 0) {
639 mlx5_core_err(dev, "failed to allocate command entry\n");
640 up(sem);
641 return;
642 }
643 } else {
644 ent->idx = cmd->max_reg_cmds;
020446e0
EC		 645 spin_lock_irqsave(&cmd->alloc_lock, flags);
646 clear_bit(ent->idx, &cmd->bitmask);
647 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
e126ba97
EC		 648 }
649
650 ent->token = alloc_token(cmd);
651 cmd->ent_arr[ent->idx] = ent;
652 lay = get_inst(cmd, ent->idx);
653 ent->lay = lay;
654 memset(lay, 0, sizeof(*lay));
655 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
746b5583 656 ent->op = be32_to_cpu(lay->in[0]) >> 16;
e126ba97
EC		 657 if (ent->in->next)
658 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
659 lay->inlen = cpu_to_be32(ent->in->len);
660 if (ent->out->next)
661 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
662 lay->outlen = cpu_to_be32(ent->out->len);
663 lay->type = MLX5_PCI_CMD_XPORT;
664 lay->token = ent->token;
665 lay->status_own = CMD_OWNER_HW;
c1868b82 666 set_signature(ent, !cmd->checksum_disabled);
e126ba97 667 dump_command(dev, ent, 1);
14a70046 668 ent->ts1 = ktime_get_ns();
e126ba97
EC		 669
670 /* ring doorbell after the descriptor is valid */
21db5074 671 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
e126ba97
EC		 672 wmb();
673 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
e126ba97 674 mmiowb();
21db5074 675 /* if not in polling don't use ent after this point */
e126ba97
EC		 676 if (cmd->mode == CMD_MODE_POLLING) {
677 poll_timeout(ent);
678 /* make sure we read the descriptor after ownership is SW */
679 rmb();
680 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
681 }
682}
683
684static const char *deliv_status_to_str(u8 status)
685{
686 switch (status) {
687 case MLX5_CMD_DELIVERY_STAT_OK:
688 return "no errors";
689 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
690 return "signature error";
691 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
692 return "token error";
693 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
694 return "bad block number";
695 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
696 return "output pointer not aligned to block size";
697 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
698 return "input pointer not aligned to block size";
699 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
700 return "firmware internal error";
701 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
702 return "command input length error";
703 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
704 return "command ouput length error";
705 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
706 return "reserved fields not cleared";
707 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
708 return "bad command descriptor type";
709 default:
710 return "unknown status code";
711 }
712}
713
714static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
715{
716 struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
717
718 return be16_to_cpu(hdr->opcode);
719}
720
721static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
722{
723 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
724 struct mlx5_cmd *cmd = &dev->cmd;
725 int err;
726
727 if (cmd->mode == CMD_MODE_POLLING) {
728 wait_for_completion(&ent->done);
729 err = ent->ret;
730 } else {
731 if (!wait_for_completion_timeout(&ent->done, timeout))
732 err = -ETIMEDOUT;
733 else
734 err = 0;
735 }
736 if (err == -ETIMEDOUT) {
737 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
738 mlx5_command_str(msg_to_opcode(ent->in)),
739 msg_to_opcode(ent->in));
740 }
1a91de28
JP		 741 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
742 err, deliv_status_to_str(ent->status), ent->status);
e126ba97
EC		 743
744 return err;
745}
746
89d44f0a
MD		 747static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
748{
749 return &out->syndrome;
750}
751
752static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
753{
754 return &out->status;
755}
756
e126ba97
EC		 757/* Notes:
758 * 1. Callback functions may not sleep
759 * 2. page queue commands do not support asynchrous completion
760 */
761static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
746b5583
EC		 762 struct mlx5_cmd_msg *out, void *uout, int uout_size,
763 mlx5_cmd_cbk_t callback,
e126ba97
EC		 764 void *context, int page_queue, u8 *status)
765{
766 struct mlx5_cmd *cmd = &dev->cmd;
767 struct mlx5_cmd_work_ent *ent;
e126ba97
EC		 768 struct mlx5_cmd_stats *stats;
769 int err = 0;
770 s64 ds;
771 u16 op;
772
773 if (callback && page_queue)
774 return -EINVAL;
775
746b5583
EC		 776 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
777 page_queue);
e126ba97
EC		 778 if (IS_ERR(ent))
779 return PTR_ERR(ent);
780
781 if (!callback)
782 init_completion(&ent->done);
783
784 INIT_WORK(&ent->work, cmd_work_handler);
785 if (page_queue) {
786 cmd_work_handler(&ent->work);
787 } else if (!queue_work(cmd->wq, &ent->work)) {
788 mlx5_core_warn(dev, "failed to queue work\n");
789 err = -ENOMEM;
790 goto out_free;
791 }
792
793 if (!callback) {
794 err = wait_func(dev, ent);
795 if (err == -ETIMEDOUT)
796 goto out;
797
14a70046 798 ds = ent->ts2 - ent->ts1;
e126ba97
EC		 799 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
800 if (op < ARRAY_SIZE(cmd->stats)) {
801 stats = &cmd->stats[op];
746b5583 802 spin_lock_irq(&stats->lock);
e126ba97
EC		 803 stats->sum += ds;
804 ++stats->n;
746b5583 805 spin_unlock_irq(&stats->lock);
e126ba97
EC		 806 }
807 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
808 "fw exec time for %s is %lld nsec\n",
809 mlx5_command_str(op), ds);
810 *status = ent->status;
811 free_cmd(ent);
812 }
813
814 return err;
815
816out_free:
817 free_cmd(ent);
818out:
819 return err;
820}
821
822static ssize_t dbg_write(struct file *filp, const char __user *buf,
823 size_t count, loff_t *pos)
824{
825 struct mlx5_core_dev *dev = filp->private_data;
826 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
827 char lbuf[3];
828 int err;
829
830 if (!dbg->in_msg || !dbg->out_msg)
831 return -ENOMEM;
832
833 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
5e631a03 834 return -EFAULT;
e126ba97
EC		 835
836 lbuf[sizeof(lbuf) - 1] = 0;
837
838 if (strcmp(lbuf, "go"))
839 return -EINVAL;
840
841 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
842
843 return err ? err : count;
844}
845
846
847static const struct file_operations fops = {
848 .owner = THIS_MODULE,
849 .open = simple_open,
850 .write = dbg_write,
851};
852
853static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
854{
855 struct mlx5_cmd_prot_block *block;
856 struct mlx5_cmd_mailbox *next;
857 int copy;
858
859 if (!to || !from)
860 return -ENOMEM;
861
862 copy = min_t(int, size, sizeof(to->first.data));
863 memcpy(to->first.data, from, copy);
864 size -= copy;
865 from += copy;
866
867 next = to->next;
868 while (size) {
869 if (!next) {
870 /* this is a BUG */
871 return -ENOMEM;
872 }
873
874 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
875 block = next->buf;
876 memcpy(block->data, from, copy);
877 from += copy;
878 size -= copy;
879 next = next->next;
880 }
881
882 return 0;
883}
884
885static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
886{
887 struct mlx5_cmd_prot_block *block;
888 struct mlx5_cmd_mailbox *next;
889 int copy;
890
891 if (!to || !from)
892 return -ENOMEM;
893
894 copy = min_t(int, size, sizeof(from->first.data));
895 memcpy(to, from->first.data, copy);
896 size -= copy;
897 to += copy;
898
899 next = from->next;
900 while (size) {
901 if (!next) {
902 /* this is a BUG */
903 return -ENOMEM;
904 }
905
906 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
907 block = next->buf;
e126ba97
EC		 908
909 memcpy(to, block->data, copy);
910 to += copy;
911 size -= copy;
912 next = next->next;
913 }
914
915 return 0;
916}
917
918static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
919 gfp_t flags)
920{
921 struct mlx5_cmd_mailbox *mailbox;
922
923 mailbox = kmalloc(sizeof(*mailbox), flags);
924 if (!mailbox)
925 return ERR_PTR(-ENOMEM);
926
927 mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
928 &mailbox->dma);
929 if (!mailbox->buf) {
930 mlx5_core_dbg(dev, "failed allocation\n");
931 kfree(mailbox);
932 return ERR_PTR(-ENOMEM);
933 }
934 memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
935 mailbox->next = NULL;
936
937 return mailbox;
938}
939
940static void free_cmd_box(struct mlx5_core_dev *dev,
941 struct mlx5_cmd_mailbox *mailbox)
942{
943 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
944 kfree(mailbox);
945}
946
947static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
948 gfp_t flags, int size)
949{
950 struct mlx5_cmd_mailbox *tmp, *head = NULL;
951 struct mlx5_cmd_prot_block *block;
952 struct mlx5_cmd_msg *msg;
953 int blen;
954 int err;
955 int n;
956 int i;
957
746b5583 958 msg = kzalloc(sizeof(*msg), flags);
e126ba97
EC		 959 if (!msg)
960 return ERR_PTR(-ENOMEM);
961
962 blen = size - min_t(int, sizeof(msg->first.data), size);
963 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
964
965 for (i = 0; i < n; i++) {
966 tmp = alloc_cmd_box(dev, flags);
967 if (IS_ERR(tmp)) {
968 mlx5_core_warn(dev, "failed allocating block\n");
969 err = PTR_ERR(tmp);
970 goto err_alloc;
971 }
972
973 block = tmp->buf;
974 tmp->next = head;
975 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
976 block->block_num = cpu_to_be32(n - i - 1);
977 head = tmp;
978 }
979 msg->next = head;
980 msg->len = size;
981 return msg;
982
983err_alloc:
984 while (head) {
985 tmp = head->next;
986 free_cmd_box(dev, head);
987 head = tmp;
988 }
989 kfree(msg);
990
991 return ERR_PTR(err);
992}
993
994static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
995 struct mlx5_cmd_msg *msg)
996{
997 struct mlx5_cmd_mailbox *head = msg->next;
998 struct mlx5_cmd_mailbox *next;
999
1000 while (head) {
1001 next = head->next;
1002 free_cmd_box(dev, head);
1003 head = next;
1004 }
1005 kfree(msg);
1006}
1007
1008static ssize_t data_write(struct file *filp, const char __user *buf,
1009 size_t count, loff_t *pos)
1010{
1011 struct mlx5_core_dev *dev = filp->private_data;
1012 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1013 void *ptr;
1014 int err;
1015
1016 if (*pos != 0)
1017 return -EINVAL;
1018
1019 kfree(dbg->in_msg);
1020 dbg->in_msg = NULL;
1021 dbg->inlen = 0;
1022
1023 ptr = kzalloc(count, GFP_KERNEL);
1024 if (!ptr)
1025 return -ENOMEM;
1026
1027 if (copy_from_user(ptr, buf, count)) {
5e631a03 1028 err = -EFAULT;
e126ba97
EC		 1029 goto out;
1030 }
1031 dbg->in_msg = ptr;
1032 dbg->inlen = count;
1033
1034 *pos = count;
1035
1036 return count;
1037
1038out:
1039 kfree(ptr);
1040 return err;
1041}
1042
1043static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1044 loff_t *pos)
1045{
1046 struct mlx5_core_dev *dev = filp->private_data;
1047 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1048 int copy;
1049
1050 if (*pos)
1051 return 0;
1052
1053 if (!dbg->out_msg)
1054 return -ENOMEM;
1055
1056 copy = min_t(int, count, dbg->outlen);
1057 if (copy_to_user(buf, dbg->out_msg, copy))
5e631a03 1058 return -EFAULT;
e126ba97
EC		 1059
1060 *pos += copy;
1061
1062 return copy;
1063}
1064
1065static const struct file_operations dfops = {
1066 .owner = THIS_MODULE,
1067 .open = simple_open,
1068 .write = data_write,
1069 .read = data_read,
1070};
1071
1072static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1073 loff_t *pos)
1074{
1075 struct mlx5_core_dev *dev = filp->private_data;
1076 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1077 char outlen[8];
1078 int err;
1079
1080 if (*pos)
1081 return 0;
1082
1083 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1084 if (err < 0)
1085 return err;
1086
1087 if (copy_to_user(buf, &outlen, err))
5e631a03 1088 return -EFAULT;
e126ba97
EC		 1089
1090 *pos += err;
1091
1092 return err;
1093}
1094
1095static ssize_t outlen_write(struct file *filp, const char __user *buf,
1096 size_t count, loff_t *pos)
1097{
1098 struct mlx5_core_dev *dev = filp->private_data;
1099 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1100 char outlen_str[8];
1101 int outlen;
1102 void *ptr;
1103 int err;
1104
1105 if (*pos != 0 || count > 6)
1106 return -EINVAL;
1107
1108 kfree(dbg->out_msg);
1109 dbg->out_msg = NULL;
1110 dbg->outlen = 0;
1111
1112 if (copy_from_user(outlen_str, buf, count))
5e631a03 1113 return -EFAULT;
e126ba97
EC		 1114
1115 outlen_str[7] = 0;
1116
1117 err = sscanf(outlen_str, "%d", &outlen);
1118 if (err < 0)
1119 return err;
1120
1121 ptr = kzalloc(outlen, GFP_KERNEL);
1122 if (!ptr)
1123 return -ENOMEM;
1124
1125 dbg->out_msg = ptr;
1126 dbg->outlen = outlen;
1127
1128 *pos = count;
1129
1130 return count;
1131}
1132
1133static const struct file_operations olfops = {
1134 .owner = THIS_MODULE,
1135 .open = simple_open,
1136 .write = outlen_write,
1137 .read = outlen_read,
1138};
1139
1140static void set_wqname(struct mlx5_core_dev *dev)
1141{
1142 struct mlx5_cmd *cmd = &dev->cmd;
1143
1144 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1145 dev_name(&dev->pdev->dev));
1146}
1147
1148static void clean_debug_files(struct mlx5_core_dev *dev)
1149{
1150 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1151
1152 if (!mlx5_debugfs_root)
1153 return;
1154
1155 mlx5_cmdif_debugfs_cleanup(dev);
1156 debugfs_remove_recursive(dbg->dbg_root);
1157}
1158
1159static int create_debugfs_files(struct mlx5_core_dev *dev)
1160{
1161 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1162 int err = -ENOMEM;
1163
1164 if (!mlx5_debugfs_root)
1165 return 0;
1166
1167 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1168 if (!dbg->dbg_root)
1169 return err;
1170
1171 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1172 dev, &dfops);
1173 if (!dbg->dbg_in)
1174 goto err_dbg;
1175
1176 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1177 dev, &dfops);
1178 if (!dbg->dbg_out)
1179 goto err_dbg;
1180
1181 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1182 dev, &olfops);
1183 if (!dbg->dbg_outlen)
1184 goto err_dbg;
1185
1186 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1187 &dbg->status);
1188 if (!dbg->dbg_status)
1189 goto err_dbg;
1190
1191 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1192 if (!dbg->dbg_run)
1193 goto err_dbg;
1194
1195 mlx5_cmdif_debugfs_init(dev);
1196
1197 return 0;
1198
1199err_dbg:
1200 clean_debug_files(dev);
1201 return err;
1202}
1203
1204void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1205{
1206 struct mlx5_cmd *cmd = &dev->cmd;
1207 int i;
1208
1209 for (i = 0; i < cmd->max_reg_cmds; i++)
1210 down(&cmd->sem);
1211
1212 down(&cmd->pages_sem);
1213
1214 flush_workqueue(cmd->wq);
1215
1216 cmd->mode = CMD_MODE_EVENTS;
1217
1218 up(&cmd->pages_sem);
1219 for (i = 0; i < cmd->max_reg_cmds; i++)
1220 up(&cmd->sem);
1221}
1222
1223void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1224{
1225 struct mlx5_cmd *cmd = &dev->cmd;
1226 int i;
1227
1228 for (i = 0; i < cmd->max_reg_cmds; i++)
1229 down(&cmd->sem);
1230
1231 down(&cmd->pages_sem);
1232
1233 flush_workqueue(cmd->wq);
1234 cmd->mode = CMD_MODE_POLLING;
1235
1236 up(&cmd->pages_sem);
1237 for (i = 0; i < cmd->max_reg_cmds; i++)
1238 up(&cmd->sem);
1239}
1240
746b5583
EC		 1241static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1242{
1243 unsigned long flags;
1244
1245 if (msg->cache) {
1246 spin_lock_irqsave(&msg->cache->lock, flags);
1247 list_add_tail(&msg->list, &msg->cache->head);
1248 spin_unlock_irqrestore(&msg->cache->lock, flags);
1249 } else {
1250 mlx5_free_cmd_msg(dev, msg);
1251 }
1252}
1253
020446e0 1254void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
e126ba97
EC		 1255{
1256 struct mlx5_cmd *cmd = &dev->cmd;
1257 struct mlx5_cmd_work_ent *ent;
1258 mlx5_cmd_cbk_t callback;
1259 void *context;
1260 int err;
1261 int i;
746b5583
EC		 1262 s64 ds;
1263 struct mlx5_cmd_stats *stats;
1264 unsigned long flags;
020446e0 1265 unsigned long vector;
e126ba97 1266
020446e0
EC		 1267 /* there can be at most 32 command queues */
1268 vector = vec & 0xffffffff;
e126ba97
EC		 1269 for (i = 0; i < (1 << cmd->log_sz); i++) {
1270 if (test_bit(i, &vector)) {
11940c87
DC		 1271 struct semaphore *sem;
1272
e126ba97 1273 ent = cmd->ent_arr[i];
11940c87
DC		 1274 if (ent->page_queue)
1275 sem = &cmd->pages_sem;
1276 else
1277 sem = &cmd->sem;
14a70046 1278 ent->ts2 = ktime_get_ns();
e126ba97
EC		 1279 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1280 dump_command(dev, ent, 0);
1281 if (!ent->ret) {
1282 if (!cmd->checksum_disabled)
1283 ent->ret = verify_signature(ent);
1284 else
1285 ent->ret = 0;
020446e0
EC		 1286 if (vec & MLX5_TRIGGERED_CMD_COMP)
1287 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1288 else
1289 ent->status = ent->lay->status_own >> 1;
1290
e126ba97
EC		 1291 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1292 ent->ret, deliv_status_to_str(ent->status), ent->status);
1293 }
1294 free_ent(cmd, ent->idx);
020446e0 1295
e126ba97 1296 if (ent->callback) {
14a70046 1297 ds = ent->ts2 - ent->ts1;
746b5583
EC		 1298 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1299 stats = &cmd->stats[ent->op];
1300 spin_lock_irqsave(&stats->lock, flags);
1301 stats->sum += ds;
1302 ++stats->n;
1303 spin_unlock_irqrestore(&stats->lock, flags);
1304 }
1305
e126ba97
EC		 1306 callback = ent->callback;
1307 context = ent->context;
1308 err = ent->ret;
746b5583
EC		 1309 if (!err)
1310 err = mlx5_copy_from_msg(ent->uout,
1311 ent->out,
1312 ent->uout_size);
1313
1314 mlx5_free_cmd_msg(dev, ent->out);
1315 free_msg(dev, ent->in);
1316
be87544d 1317 err = err ? err : ent->status;
e126ba97
EC		 1318 free_cmd(ent);
1319 callback(err, context);
1320 } else {
1321 complete(&ent->done);
1322 }
11940c87 1323 up(sem);
e126ba97
EC		 1324 }
1325 }
1326}
1327EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1328
1329static int status_to_err(u8 status)
1330{
1331 return status ? -1 : 0; /* TBD more meaningful codes */
1332}
1333
746b5583
EC		 1334static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1335 gfp_t gfp)
e126ba97
EC		 1336{
1337 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1338 struct mlx5_cmd *cmd = &dev->cmd;
1339 struct cache_ent *ent = NULL;
1340
1341 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1342 ent = &cmd->cache.large;
1343 else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1344 ent = &cmd->cache.med;
1345
1346 if (ent) {
746b5583 1347 spin_lock_irq(&ent->lock);
e126ba97
EC		 1348 if (!list_empty(&ent->head)) {
1349 msg = list_entry(ent->head.next, typeof(*msg), list);
1350 /* For cached lists, we must explicitly state what is
1351 * the real size
1352 */
1353 msg->len = in_size;
1354 list_del(&msg->list);
1355 }
746b5583 1356 spin_unlock_irq(&ent->lock);
e126ba97
EC		 1357 }
1358
1359 if (IS_ERR(msg))
746b5583 1360 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
e126ba97
EC		 1361
1362 return msg;
1363}
1364
89d44f0a
MD		 1365static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
1366{
1367 return be16_to_cpu(in->opcode);
1368}
1369
e126ba97
EC		 1370static int is_manage_pages(struct mlx5_inbox_hdr *in)
1371{
1372 return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1373}
1374
746b5583
EC		 1375static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1376 int out_size, mlx5_cmd_cbk_t callback, void *context)
e126ba97
EC		 1377{
1378 struct mlx5_cmd_msg *inb;
1379 struct mlx5_cmd_msg *outb;
1380 int pages_queue;
746b5583 1381 gfp_t gfp;
e126ba97
EC		 1382 int err;
1383 u8 status = 0;
89d44f0a
MD		 1384 u32 drv_synd;
1385
1386 if (pci_channel_offline(dev->pdev) ||
1387 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1388 err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
1389 *get_synd_ptr(out) = cpu_to_be32(drv_synd);
1390 *get_status_ptr(out) = status;
1391 return err;
1392 }
e126ba97
EC		 1393
1394 pages_queue = is_manage_pages(in);
746b5583 1395 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
e126ba97 1396
746b5583 1397 inb = alloc_msg(dev, in_size, gfp);
e126ba97
EC		 1398 if (IS_ERR(inb)) {
1399 err = PTR_ERR(inb);
1400 return err;
1401 }
1402
1403 err = mlx5_copy_to_msg(inb, in, in_size);
1404 if (err) {
1405 mlx5_core_warn(dev, "err %d\n", err);
1406 goto out_in;
1407 }
1408
746b5583 1409 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
e126ba97
EC		 1410 if (IS_ERR(outb)) {
1411 err = PTR_ERR(outb);
1412 goto out_in;
1413 }
1414
746b5583
EC		 1415 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1416 pages_queue, &status);
e126ba97
EC		 1417 if (err)
1418 goto out_out;
1419
1420 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1421 if (status) {
1422 err = status_to_err(status);
1423 goto out_out;
1424 }
1425
05e4ecd1
EC		 1426 if (!callback)
1427 err = mlx5_copy_from_msg(out, outb, out_size);
e126ba97
EC		 1428
1429out_out:
746b5583
EC		 1430 if (!callback)
1431 mlx5_free_cmd_msg(dev, outb);
e126ba97
EC		 1432
1433out_in:
746b5583
EC		 1434 if (!callback)
1435 free_msg(dev, inb);
e126ba97
EC		 1436 return err;
1437}
746b5583
EC		 1438
1439int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1440 int out_size)
1441{
1442 return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1443}
e126ba97
EC		 1444EXPORT_SYMBOL(mlx5_cmd_exec);
1445
746b5583
EC		 1446int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1447 void *out, int out_size, mlx5_cmd_cbk_t callback,
1448 void *context)
1449{
1450 return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1451}
1452EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1453
e126ba97
EC		 1454static void destroy_msg_cache(struct mlx5_core_dev *dev)
1455{
1456 struct mlx5_cmd *cmd = &dev->cmd;
1457 struct mlx5_cmd_msg *msg;
1458 struct mlx5_cmd_msg *n;
1459
1460 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1461 list_del(&msg->list);
1462 mlx5_free_cmd_msg(dev, msg);
1463 }
1464
1465 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1466 list_del(&msg->list);
1467 mlx5_free_cmd_msg(dev, msg);
1468 }
1469}
1470
1471static int create_msg_cache(struct mlx5_core_dev *dev)
1472{
1473 struct mlx5_cmd *cmd = &dev->cmd;
1474 struct mlx5_cmd_msg *msg;
1475 int err;
1476 int i;
1477
1478 spin_lock_init(&cmd->cache.large.lock);
1479 INIT_LIST_HEAD(&cmd->cache.large.head);
1480 spin_lock_init(&cmd->cache.med.lock);
1481 INIT_LIST_HEAD(&cmd->cache.med.head);
1482
1483 for (i = 0; i < NUM_LONG_LISTS; i++) {
1484 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1485 if (IS_ERR(msg)) {
1486 err = PTR_ERR(msg);
1487 goto ex_err;
1488 }
1489 msg->cache = &cmd->cache.large;
1490 list_add_tail(&msg->list, &cmd->cache.large.head);
1491 }
1492
1493 for (i = 0; i < NUM_MED_LISTS; i++) {
1494 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1495 if (IS_ERR(msg)) {
1496 err = PTR_ERR(msg);
1497 goto ex_err;
1498 }
1499 msg->cache = &cmd->cache.med;
1500 list_add_tail(&msg->list, &cmd->cache.med.head);
1501 }
1502
1503 return 0;
1504
1505ex_err:
1506 destroy_msg_cache(dev);
1507 return err;
1508}
1509
64599cca
EC		 1510static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1511{
1512 struct device *ddev = &dev->pdev->dev;
1513
1514 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1515 &cmd->alloc_dma, GFP_KERNEL);
1516 if (!cmd->cmd_alloc_buf)
1517 return -ENOMEM;
1518
1519 /* make sure it is aligned to 4K */
1520 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1521 cmd->cmd_buf = cmd->cmd_alloc_buf;
1522 cmd->dma = cmd->alloc_dma;
1523 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1524 return 0;
1525 }
1526
1527 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1528 cmd->alloc_dma);
1529 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1530 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1531 &cmd->alloc_dma, GFP_KERNEL);
1532 if (!cmd->cmd_alloc_buf)
1533 return -ENOMEM;
1534
1535 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1536 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1537 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1538 return 0;
1539}
1540
1541static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1542{
1543 struct device *ddev = &dev->pdev->dev;
1544
1545 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1546 cmd->alloc_dma);
1547}
1548
e126ba97
EC		 1549int mlx5_cmd_init(struct mlx5_core_dev *dev)
1550{
1551 int size = sizeof(struct mlx5_cmd_prot_block);
1552 int align = roundup_pow_of_two(size);
1553 struct mlx5_cmd *cmd = &dev->cmd;
1554 u32 cmd_h, cmd_l;
1555 u16 cmd_if_rev;
1556 int err;
1557 int i;
1558
a31208b1 1559 memset(cmd, 0, sizeof(*cmd));
e126ba97
EC		 1560 cmd_if_rev = cmdif_rev(dev);
1561 if (cmd_if_rev != CMD_IF_REV) {
1562 dev_err(&dev->pdev->dev,
1563 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1564 CMD_IF_REV, cmd_if_rev);
1565 return -EINVAL;
1566 }
1567
1568 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1569 if (!cmd->pool)
1570 return -ENOMEM;
1571
64599cca
EC		 1572 err = alloc_cmd_page(dev, cmd);
1573 if (err)
e126ba97 1574 goto err_free_pool;
e126ba97
EC		 1575
1576 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1577 cmd->log_sz = cmd_l >> 4 & 0xf;
1578 cmd->log_stride = cmd_l & 0xf;
1579 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1580 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1581 1 << cmd->log_sz);
1582 err = -EINVAL;
64599cca 1583 goto err_free_page;
e126ba97
EC		 1584 }
1585
2d446d18 1586 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
e126ba97
EC		 1587 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1588 err = -EINVAL;
64599cca 1589 goto err_free_page;
e126ba97
EC		 1590 }
1591
c1868b82 1592 cmd->checksum_disabled = 1;
e126ba97
EC		 1593 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1594 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1595
1596 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1597 if (cmd->cmdif_rev > CMD_IF_REV) {
1598 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1599 CMD_IF_REV, cmd->cmdif_rev);
1600 err = -ENOTSUPP;
64599cca 1601 goto err_free_page;
e126ba97
EC		 1602 }
1603
1604 spin_lock_init(&cmd->alloc_lock);
1605 spin_lock_init(&cmd->token_lock);
1606 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1607 spin_lock_init(&cmd->stats[i].lock);
1608
1609 sema_init(&cmd->sem, cmd->max_reg_cmds);
1610 sema_init(&cmd->pages_sem, 1);
1611
1612 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1613 cmd_l = (u32)(cmd->dma);
1614 if (cmd_l & 0xfff) {
1615 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1616 err = -ENOMEM;
64599cca 1617 goto err_free_page;
e126ba97
EC		 1618 }
1619
1620 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1621 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1622
1623 /* Make sure firmware sees the complete address before we proceed */
1624 wmb();
1625
1626 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1627
1628 cmd->mode = CMD_MODE_POLLING;
1629
1630 err = create_msg_cache(dev);
1631 if (err) {
1632 dev_err(&dev->pdev->dev, "failed to create command cache\n");
64599cca 1633 goto err_free_page;
e126ba97
EC		 1634 }
1635
1636 set_wqname(dev);
1637 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1638 if (!cmd->wq) {
1639 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1640 err = -ENOMEM;
1641 goto err_cache;
1642 }
1643
1644 err = create_debugfs_files(dev);
1645 if (err) {
1646 err = -ENOMEM;
1647 goto err_wq;
1648 }
1649
1650 return 0;
1651
1652err_wq:
1653 destroy_workqueue(cmd->wq);
1654
1655err_cache:
1656 destroy_msg_cache(dev);
1657
64599cca
EC		 1658err_free_page:
1659 free_cmd_page(dev, cmd);
e126ba97
EC		 1660
1661err_free_pool:
1662 pci_pool_destroy(cmd->pool);
1663
1664 return err;
1665}
1666EXPORT_SYMBOL(mlx5_cmd_init);
1667
1668void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1669{
1670 struct mlx5_cmd *cmd = &dev->cmd;
1671
1672 clean_debug_files(dev);
1673 destroy_workqueue(cmd->wq);
1674 destroy_msg_cache(dev);
64599cca 1675 free_cmd_page(dev, cmd);
e126ba97
EC		 1676 pci_pool_destroy(cmd->pool);
1677}
1678EXPORT_SYMBOL(mlx5_cmd_cleanup);
1679
1680static const char *cmd_status_str(u8 status)
1681{
1682 switch (status) {
1683 case MLX5_CMD_STAT_OK:
1684 return "OK";
1685 case MLX5_CMD_STAT_INT_ERR:
1686 return "internal error";
1687 case MLX5_CMD_STAT_BAD_OP_ERR:
1688 return "bad operation";
1689 case MLX5_CMD_STAT_BAD_PARAM_ERR:
1690 return "bad parameter";
1691 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1692 return "bad system state";
1693 case MLX5_CMD_STAT_BAD_RES_ERR:
1694 return "bad resource";
1695 case MLX5_CMD_STAT_RES_BUSY:
1696 return "resource busy";
1697 case MLX5_CMD_STAT_LIM_ERR:
1698 return "limits exceeded";
1699 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1700 return "bad resource state";
1701 case MLX5_CMD_STAT_IX_ERR:
1702 return "bad index";
1703 case MLX5_CMD_STAT_NO_RES_ERR:
1704 return "no resources";
1705 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1706 return "bad input length";
1707 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1708 return "bad output length";
1709 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1710 return "bad QP state";
1711 case MLX5_CMD_STAT_BAD_PKT_ERR:
1712 return "bad packet (discarded)";
1713 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1714 return "bad size too many outstanding CQEs";
1715 default:
1716 return "unknown status";
1717 }
1718}
1719
c7a08ac7 1720static int cmd_status_to_err(u8 status)
e126ba97 1721{
c7a08ac7 1722 switch (status) {
e126ba97
EC		 1723 case MLX5_CMD_STAT_OK: return 0;
1724 case MLX5_CMD_STAT_INT_ERR: return -EIO;
1725 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
1726 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
1727 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
1728 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
1729 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
9c865131 1730 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
e126ba97
EC		 1731 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
1732 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
1733 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
1734 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
1735 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
1736 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
1737 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
1738 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
1739 default: return -EIO;
1740 }
1741}
c7a08ac7
EC		 1742
1743/* this will be available till all the commands use set/get macros */
1744int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1745{
1746 if (!hdr->status)
1747 return 0;
1748
1749 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1750 cmd_status_str(hdr->status), hdr->status,
1751 be32_to_cpu(hdr->syndrome));
1752
1753 return cmd_status_to_err(hdr->status);
1754}
b775516b
EC		 1755
1756int mlx5_cmd_status_to_err_v2(void *ptr)
1757{
1758 u32 syndrome;
1759 u8 status;
1760
1761 status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1762 if (!status)
1763 return 0;
1764
1765 syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1766
1767 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1768 cmd_status_str(status), status, syndrome);
1769
1770 return cmd_status_to_err(status);
1771}
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