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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 47 | #include <linux/mlx5/fs.h> |
e8f887ac | 48 | #include <linux/rhashtable.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4c4dbb4a | 51 | #include <linux/net_dim.h> |
f62b8bb8 | 52 | #include "wq.h" |
f62b8bb8 | 53 | #include "mlx5_core.h" |
9218b44d | 54 | #include "en_stats.h" |
fe6d86b3 | 55 | #include "en/fs.h" |
f62b8bb8 | 56 | |
4d8fcf21 | 57 | extern const struct net_device_ops mlx5e_netdev_ops; |
60bbf7ee JDB |
58 | struct page_pool; |
59 | ||
bb909416 IL |
60 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
61 | #define MLX5E_METADATA_ETHER_LEN 8 | |
62 | ||
1cabe6b0 MG |
63 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
64 | ||
c139dbfd ES |
65 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
66 | ||
472a1e44 TT |
67 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
68 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 69 | |
0696d608 | 70 | #define MLX5E_MAX_PRIORITY 8 |
2a5e7a13 | 71 | #define MLX5E_MAX_DSCP 64 |
f62b8bb8 AV |
72 | #define MLX5E_MAX_NUM_TC 8 |
73 | ||
1bfecfca | 74 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
75 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
76 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 77 | |
f32f5bd2 DJ |
78 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
79 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
80 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
81 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
82 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
83 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
696a97cf EE |
84 | #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \ |
85 | (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \ | |
86 | MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)) | |
f32f5bd2 | 87 | |
7e426671 | 88 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
89 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
90 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
91 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
92 | |
93 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
73281b78 | 94 | #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) |
b8a98a4c | 95 | #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS)) |
73281b78 TT |
96 | #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) |
97 | #define MLX5E_MAX_RQ_NUM_MTTS \ | |
98 | ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ | |
99 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) | |
100 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ | |
101 | (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) | |
102 | #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ | |
103 | (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ | |
104 | (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) | |
105 | ||
069d1146 TT |
106 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
107 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
108 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
109 | ||
73281b78 TT |
110 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
111 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
112 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
113 | ||
069d1146 | 114 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 TT |
115 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
116 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ | |
117 | MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) | |
118 | ||
119 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 120 | |
75aa889f | 121 | #define MLX5E_RX_MAX_HEAD (256) |
461017cb | 122 | |
d9a40271 | 123 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
124 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
125 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
126 | ||
f62b8bb8 | 127 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 128 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
129 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
130 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 131 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
132 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
133 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 134 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 135 | |
936896e9 AS |
136 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
137 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 138 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 139 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 140 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 | 141 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
db75373c | 142 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 143 | |
ea3886ca TT |
144 | #define MLX5E_UMR_WQE_INLINE_SZ \ |
145 | (sizeof(struct mlx5e_umr_wqe) + \ | |
146 | ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ | |
147 | MLX5_UMR_MTT_ALIGNMENT)) | |
148 | #define MLX5E_UMR_WQEBBS \ | |
149 | (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) | |
2f48af12 | 150 | |
79c48764 GP |
151 | #define MLX5E_MSG_LEVEL NETIF_MSG_LINK |
152 | ||
153 | #define mlx5e_dbg(mlevel, priv, format, ...) \ | |
154 | do { \ | |
155 | if (NETIF_MSG_##mlevel & (priv)->msglevel) \ | |
156 | netdev_warn(priv->netdev, format, \ | |
157 | ##__VA_ARGS__); \ | |
158 | } while (0) | |
159 | ||
160 | ||
461017cb TT |
161 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
162 | { | |
163 | switch (wq_type) { | |
164 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
165 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
166 | wq_size / 2); | |
167 | default: | |
168 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
169 | wq_size / 2); | |
170 | } | |
171 | } | |
172 | ||
779d986d | 173 | /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ |
48935bbb SM |
174 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
175 | { | |
176 | return is_kdump_kernel() ? | |
177 | MLX5E_MIN_NUM_CHANNELS : | |
178 | min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
179 | MLX5E_MAX_NUM_CHANNELS); | |
180 | } | |
181 | ||
779d986d FD |
182 | /* Use this function to get max num channels after netdev was created */ |
183 | static inline int mlx5e_get_netdev_max_channels(struct net_device *netdev) | |
184 | { | |
185 | return min_t(unsigned int, netdev->num_rx_queues, | |
186 | netdev->num_tx_queues); | |
187 | } | |
188 | ||
2f48af12 TT |
189 | struct mlx5e_tx_wqe { |
190 | struct mlx5_wqe_ctrl_seg ctrl; | |
191 | struct mlx5_wqe_eth_seg eth; | |
043dc78e | 192 | struct mlx5_wqe_data_seg data[0]; |
2f48af12 TT |
193 | }; |
194 | ||
99cbfa93 | 195 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 196 | struct mlx5_wqe_srq_next_seg next; |
99cbfa93 TT |
197 | struct mlx5_wqe_data_seg data[0]; |
198 | }; | |
199 | ||
200 | struct mlx5e_rx_wqe_cyc { | |
201 | struct mlx5_wqe_data_seg data[0]; | |
2f48af12 | 202 | }; |
86d722ad | 203 | |
bc77b240 TT |
204 | struct mlx5e_umr_wqe { |
205 | struct mlx5_wqe_ctrl_seg ctrl; | |
206 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
207 | struct mlx5_mkey_seg mkc; | |
ea3886ca | 208 | struct mlx5_mtt inline_mtts[0]; |
bc77b240 TT |
209 | }; |
210 | ||
d605d668 KH |
211 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
212 | ||
4e59e288 | 213 | enum mlx5e_priv_flag { |
9908aa29 | 214 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
0088cbbc TG |
215 | MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1), |
216 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2), | |
2ccb0a79 | 217 | MLX5E_PFLAG_RX_STRIDING_RQ = (1 << 3), |
b856df28 | 218 | MLX5E_PFLAG_RX_NO_CSUM_COMPLETE = (1 << 4), |
4e59e288 GP |
219 | }; |
220 | ||
6a9764ef | 221 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
222 | do { \ |
223 | if (enable) \ | |
6a9764ef | 224 | (params)->pflags |= (pflag); \ |
59ece1c9 | 225 | else \ |
6a9764ef | 226 | (params)->pflags &= ~(pflag); \ |
4e59e288 GP |
227 | } while (0) |
228 | ||
6a9764ef | 229 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag))) |
59ece1c9 | 230 | |
08fb1dac SM |
231 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
232 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
233 | #endif |
234 | ||
f62b8bb8 AV |
235 | struct mlx5e_params { |
236 | u8 log_sq_size; | |
461017cb | 237 | u8 rq_wq_type; |
73281b78 | 238 | u8 log_rq_mtu_frames; |
f62b8bb8 | 239 | u16 num_channels; |
f62b8bb8 | 240 | u8 num_tc; |
9bcc8606 | 241 | bool rx_cqe_compress_def; |
9a317425 AG |
242 | struct net_dim_cq_moder rx_cq_moderation; |
243 | struct net_dim_cq_moder tx_cq_moderation; | |
f62b8bb8 AV |
244 | bool lro_en; |
245 | u32 lro_wqe_sz; | |
cff92d7c | 246 | u8 tx_min_inline_mode; |
2d75b2bc AS |
247 | u8 rss_hfunc; |
248 | u8 toeplitz_hash_key[40]; | |
249 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 250 | bool vlan_strip_disable; |
102722fc | 251 | bool scatter_fcs_en; |
9a317425 | 252 | bool rx_dim_enabled; |
cbce4f44 | 253 | bool tx_dim_enabled; |
2b029556 | 254 | u32 lro_timeout; |
59ece1c9 | 255 | u32 pflags; |
6a9764ef | 256 | struct bpf_prog *xdp_prog; |
472a1e44 TT |
257 | unsigned int sw_mtu; |
258 | int hard_mtu; | |
f62b8bb8 AV |
259 | }; |
260 | ||
3a6a931d HN |
261 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
262 | struct mlx5e_cee_config { | |
263 | /* bw pct for priority group */ | |
264 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
265 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
266 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
267 | bool pfc_enable; | |
268 | }; | |
269 | ||
270 | enum { | |
271 | MLX5_DCB_CHG_RESET, | |
272 | MLX5_DCB_NO_CHG, | |
273 | MLX5_DCB_CHG_NO_RESET, | |
274 | }; | |
275 | ||
276 | struct mlx5e_dcbx { | |
e207b7e9 | 277 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 278 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
2a5e7a13 | 279 | u8 dscp_app_cnt; |
820c2c5e HN |
280 | |
281 | /* The only setting that cannot be read from FW */ | |
282 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
9e10bf1d | 283 | u8 cap; |
0696d608 HN |
284 | |
285 | /* Buffer configuration */ | |
ecdf2dad | 286 | bool manual_buffer; |
0696d608 HN |
287 | u32 cable_len; |
288 | u32 xoff; | |
3a6a931d | 289 | }; |
2a5e7a13 HN |
290 | |
291 | struct mlx5e_dcbx_dp { | |
292 | u8 dscp2prio[MLX5E_MAX_DSCP]; | |
293 | u8 trust_state; | |
294 | }; | |
3a6a931d HN |
295 | #endif |
296 | ||
f62b8bb8 | 297 | enum { |
c0f1147d | 298 | MLX5E_RQ_STATE_ENABLED, |
cb3c7fd4 | 299 | MLX5E_RQ_STATE_AM, |
b856df28 | 300 | MLX5E_RQ_STATE_NO_CSUM_COMPLETE, |
f62b8bb8 AV |
301 | }; |
302 | ||
f62b8bb8 AV |
303 | struct mlx5e_cq { |
304 | /* data path - accessed per cqe */ | |
305 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
306 | |
307 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 308 | u16 event_ctr; |
f62b8bb8 AV |
309 | struct napi_struct *napi; |
310 | struct mlx5_core_cq mcq; | |
311 | struct mlx5e_channel *channel; | |
312 | ||
7219ab34 TT |
313 | /* cqe decompression */ |
314 | struct mlx5_cqe64 title; | |
315 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
316 | u8 mini_arr_idx; | |
317 | u16 decmprs_left; | |
318 | u16 decmprs_wqe_counter; | |
319 | ||
f62b8bb8 | 320 | /* control */ |
a43b25da | 321 | struct mlx5_core_dev *mdev; |
3a2f7033 | 322 | struct mlx5_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
323 | } ____cacheline_aligned_in_smp; |
324 | ||
eba2db2b | 325 | struct mlx5e_tx_wqe_info { |
77bdf895 | 326 | struct sk_buff *skb; |
eba2db2b SM |
327 | u32 num_bytes; |
328 | u8 num_wqebbs; | |
329 | u8 num_dma; | |
330 | }; | |
331 | ||
332 | enum mlx5e_dma_map_type { | |
333 | MLX5E_DMA_MAP_SINGLE, | |
334 | MLX5E_DMA_MAP_PAGE | |
335 | }; | |
336 | ||
337 | struct mlx5e_sq_dma { | |
338 | dma_addr_t addr; | |
339 | u32 size; | |
340 | enum mlx5e_dma_map_type type; | |
341 | }; | |
342 | ||
343 | enum { | |
344 | MLX5E_SQ_STATE_ENABLED, | |
db75373c | 345 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 346 | MLX5E_SQ_STATE_IPSEC, |
cbce4f44 | 347 | MLX5E_SQ_STATE_AM, |
bf239741 | 348 | MLX5E_SQ_STATE_TLS, |
58b99ee3 | 349 | MLX5E_SQ_STATE_REDIRECT, |
eba2db2b SM |
350 | }; |
351 | ||
352 | struct mlx5e_sq_wqe_info { | |
353 | u8 opcode; | |
eba2db2b | 354 | }; |
2f48af12 | 355 | |
31391048 | 356 | struct mlx5e_txqsq { |
eba2db2b SM |
357 | /* data path */ |
358 | ||
359 | /* dirtied @completion */ | |
360 | u16 cc; | |
361 | u32 dma_fifo_cc; | |
cbce4f44 | 362 | struct net_dim dim; /* Adaptive Moderation */ |
eba2db2b SM |
363 | |
364 | /* dirtied @xmit */ | |
365 | u16 pc ____cacheline_aligned_in_smp; | |
366 | u32 dma_fifo_pc; | |
eba2db2b SM |
367 | |
368 | struct mlx5e_cq cq; | |
369 | ||
eba2db2b SM |
370 | /* read only */ |
371 | struct mlx5_wq_cyc wq; | |
372 | u32 dma_fifo_mask; | |
05909bab | 373 | struct mlx5e_sq_stats *stats; |
9a3956da TT |
374 | struct { |
375 | struct mlx5e_sq_dma *dma_fifo; | |
376 | struct mlx5e_tx_wqe_info *wqe_info; | |
377 | } db; | |
eba2db2b SM |
378 | void __iomem *uar_map; |
379 | struct netdev_queue *txq; | |
380 | u32 sqn; | |
eba2db2b | 381 | u8 min_inline_mode; |
eba2db2b | 382 | struct device *pdev; |
eba2db2b SM |
383 | __be32 mkey_be; |
384 | unsigned long state; | |
7c39afb3 FD |
385 | struct hwtstamp_config *tstamp; |
386 | struct mlx5_clock *clock; | |
eba2db2b SM |
387 | |
388 | /* control path */ | |
389 | struct mlx5_wq_ctrl wq_ctrl; | |
390 | struct mlx5e_channel *channel; | |
acc6c595 | 391 | int txq_ix; |
eba2db2b | 392 | u32 rate_limit; |
db75373c EBE |
393 | struct mlx5e_txqsq_recover { |
394 | struct work_struct recover_work; | |
395 | u64 last_recover; | |
396 | } recover; | |
31391048 SM |
397 | } ____cacheline_aligned_in_smp; |
398 | ||
c94e4f11 TT |
399 | struct mlx5e_dma_info { |
400 | struct page *page; | |
401 | dma_addr_t addr; | |
402 | }; | |
403 | ||
404 | struct mlx5e_xdp_info { | |
405 | struct xdp_frame *xdpf; | |
406 | dma_addr_t dma_addr; | |
407 | struct mlx5e_dma_info di; | |
408 | }; | |
409 | ||
31391048 SM |
410 | struct mlx5e_xdpsq { |
411 | /* data path */ | |
412 | ||
dac0d15f | 413 | /* dirtied @completion */ |
31391048 | 414 | u16 cc; |
dac0d15f | 415 | bool redirect_flush; |
31391048 | 416 | |
dac0d15f TT |
417 | /* dirtied @xmit */ |
418 | u16 pc ____cacheline_aligned_in_smp; | |
419 | bool doorbell; | |
31391048 | 420 | |
dac0d15f | 421 | struct mlx5e_cq cq; |
31391048 SM |
422 | |
423 | /* read only */ | |
424 | struct mlx5_wq_cyc wq; | |
890388ad | 425 | struct mlx5e_xdpsq_stats *stats; |
dac0d15f TT |
426 | struct { |
427 | struct mlx5e_xdp_info *xdpi; | |
428 | } db; | |
31391048 SM |
429 | void __iomem *uar_map; |
430 | u32 sqn; | |
431 | struct device *pdev; | |
432 | __be32 mkey_be; | |
433 | u8 min_inline_mode; | |
434 | unsigned long state; | |
c94e4f11 | 435 | unsigned int hw_mtu; |
31391048 SM |
436 | |
437 | /* control path */ | |
438 | struct mlx5_wq_ctrl wq_ctrl; | |
439 | struct mlx5e_channel *channel; | |
440 | } ____cacheline_aligned_in_smp; | |
441 | ||
442 | struct mlx5e_icosq { | |
443 | /* data path */ | |
444 | ||
31391048 SM |
445 | /* dirtied @xmit */ |
446 | u16 pc ____cacheline_aligned_in_smp; | |
31391048 SM |
447 | |
448 | struct mlx5e_cq cq; | |
449 | ||
450 | /* write@xmit, read@completion */ | |
451 | struct { | |
452 | struct mlx5e_sq_wqe_info *ico_wqe; | |
453 | } db; | |
454 | ||
455 | /* read only */ | |
456 | struct mlx5_wq_cyc wq; | |
457 | void __iomem *uar_map; | |
458 | u32 sqn; | |
31391048 SM |
459 | unsigned long state; |
460 | ||
461 | /* control path */ | |
462 | struct mlx5_wq_ctrl wq_ctrl; | |
463 | struct mlx5e_channel *channel; | |
eba2db2b SM |
464 | } ____cacheline_aligned_in_smp; |
465 | ||
864b2d71 SM |
466 | static inline bool |
467 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 468 | { |
ddf385e3 | 469 | return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc); |
eba2db2b | 470 | } |
6cd392a0 | 471 | |
accd5883 | 472 | struct mlx5e_wqe_frag_info { |
069d1146 | 473 | struct mlx5e_dma_info *di; |
accd5883 | 474 | u32 offset; |
069d1146 | 475 | bool last_in_page; |
accd5883 TT |
476 | }; |
477 | ||
eba2db2b | 478 | struct mlx5e_umr_dma_info { |
eba2db2b | 479 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
eba2db2b SM |
480 | }; |
481 | ||
482 | struct mlx5e_mpw_info { | |
483 | struct mlx5e_umr_dma_info umr; | |
484 | u16 consumed_strides; | |
22f45398 | 485 | DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
eba2db2b SM |
486 | }; |
487 | ||
069d1146 TT |
488 | #define MLX5E_MAX_RX_FRAGS 4 |
489 | ||
4415a031 TT |
490 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
491 | * or a MPWQE (for striding rq). | |
492 | */ | |
493 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
494 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
29c2849e | 495 | #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) |
4415a031 TT |
496 | struct mlx5e_page_cache { |
497 | u32 head; | |
498 | u32 tail; | |
499 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
500 | }; | |
501 | ||
eba2db2b SM |
502 | struct mlx5e_rq; |
503 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
504 | typedef struct sk_buff * |
505 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
506 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
507 | typedef struct sk_buff * |
508 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
509 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
7cc6d77b | 510 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b SM |
511 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
512 | ||
121e8927 TT |
513 | enum mlx5e_rq_flag { |
514 | MLX5E_RQ_FLAG_XDP_XMIT = BIT(0), | |
515 | }; | |
516 | ||
069d1146 TT |
517 | struct mlx5e_rq_frag_info { |
518 | int frag_size; | |
519 | int frag_stride; | |
520 | }; | |
521 | ||
522 | struct mlx5e_rq_frags_info { | |
523 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
524 | u8 num_frags; | |
525 | u8 log_num_frags; | |
526 | u8 wqe_bulk; | |
527 | }; | |
528 | ||
f62b8bb8 AV |
529 | struct mlx5e_rq { |
530 | /* data path */ | |
21c59685 | 531 | union { |
accd5883 | 532 | struct { |
069d1146 TT |
533 | struct mlx5_wq_cyc wq; |
534 | struct mlx5e_wqe_frag_info *frags; | |
535 | struct mlx5e_dma_info *di; | |
536 | struct mlx5e_rq_frags_info info; | |
537 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 538 | } wqe; |
21c59685 | 539 | struct { |
422d4c40 | 540 | struct mlx5_wq_ll wq; |
b8a98a4c | 541 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 542 | struct mlx5e_mpw_info *info; |
619a8f2a | 543 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
b45d8b50 | 544 | u16 num_strides; |
89e89f7a | 545 | u8 log_stride_sz; |
a071cb9f | 546 | bool umr_in_progress; |
21c59685 SM |
547 | } mpwqe; |
548 | }; | |
1bfecfca | 549 | struct { |
b45d8b50 | 550 | u16 headroom; |
b5503b99 | 551 | u8 map_dir; /* dma map direction */ |
1bfecfca | 552 | } buff; |
f62b8bb8 | 553 | |
7cc6d77b | 554 | struct mlx5e_channel *channel; |
f62b8bb8 AV |
555 | struct device *pdev; |
556 | struct net_device *netdev; | |
05909bab | 557 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 558 | struct mlx5e_cq cq; |
4415a031 | 559 | struct mlx5e_page_cache page_cache; |
7c39afb3 FD |
560 | struct hwtstamp_config *tstamp; |
561 | struct mlx5_clock *clock; | |
4415a031 | 562 | |
2f48af12 | 563 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 564 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 565 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
566 | |
567 | unsigned long state; | |
568 | int ix; | |
0073c8f7 | 569 | unsigned int hw_mtu; |
f62b8bb8 | 570 | |
9a317425 | 571 | struct net_dim dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
572 | |
573 | /* XDP */ | |
86994156 | 574 | struct bpf_prog *xdp_prog; |
31391048 | 575 | struct mlx5e_xdpsq xdpsq; |
121e8927 | 576 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 577 | struct page_pool *page_pool; |
cb3c7fd4 | 578 | |
f62b8bb8 AV |
579 | /* control */ |
580 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 581 | __be32 mkey_be; |
461017cb | 582 | u8 wq_type; |
f62b8bb8 | 583 | u32 rqn; |
a43b25da | 584 | struct mlx5_core_dev *mdev; |
ec8b9981 | 585 | struct mlx5_core_mkey umr_mkey; |
0ddf5432 JDB |
586 | |
587 | /* XDP read-mostly */ | |
588 | struct xdp_rxq_info xdp_rxq; | |
f62b8bb8 AV |
589 | } ____cacheline_aligned_in_smp; |
590 | ||
f62b8bb8 AV |
591 | struct mlx5e_channel { |
592 | /* data path */ | |
593 | struct mlx5e_rq rq; | |
31391048 SM |
594 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
595 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 596 | bool xdp; |
f62b8bb8 AV |
597 | struct napi_struct napi; |
598 | struct device *pdev; | |
599 | struct net_device *netdev; | |
600 | __be32 mkey_be; | |
601 | u8 num_tc; | |
f62b8bb8 | 602 | |
58b99ee3 TT |
603 | /* XDP_REDIRECT */ |
604 | struct mlx5e_xdpsq xdpsq; | |
605 | ||
a8c2eb15 TT |
606 | /* data path - accessed per napi poll */ |
607 | struct irq_desc *irq_desc; | |
05909bab | 608 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
609 | |
610 | /* control */ | |
611 | struct mlx5e_priv *priv; | |
a43b25da | 612 | struct mlx5_core_dev *mdev; |
7c39afb3 | 613 | struct hwtstamp_config *tstamp; |
f62b8bb8 | 614 | int ix; |
231243c8 | 615 | int cpu; |
f62b8bb8 AV |
616 | }; |
617 | ||
ff9c852f SM |
618 | struct mlx5e_channels { |
619 | struct mlx5e_channel **c; | |
620 | unsigned int num; | |
6a9764ef | 621 | struct mlx5e_params params; |
ff9c852f SM |
622 | }; |
623 | ||
05909bab EBE |
624 | struct mlx5e_channel_stats { |
625 | struct mlx5e_ch_stats ch; | |
626 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
627 | struct mlx5e_rq_stats rq; | |
890388ad | 628 | struct mlx5e_xdpsq_stats rq_xdpsq; |
58b99ee3 | 629 | struct mlx5e_xdpsq_stats xdpsq; |
05909bab EBE |
630 | } ____cacheline_aligned_in_smp; |
631 | ||
acff797c | 632 | enum { |
e0f46eb9 | 633 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
634 | MLX5E_STATE_OPENED, |
635 | MLX5E_STATE_DESTROYING, | |
636 | }; | |
637 | ||
398f3351 | 638 | struct mlx5e_rqt { |
1da36696 | 639 | u32 rqtn; |
398f3351 HHZ |
640 | bool enabled; |
641 | }; | |
642 | ||
643 | struct mlx5e_tir { | |
644 | u32 tirn; | |
645 | struct mlx5e_rqt rqt; | |
646 | struct list_head list; | |
1da36696 TT |
647 | }; |
648 | ||
acff797c MG |
649 | enum { |
650 | MLX5E_TC_PRIO = 0, | |
651 | MLX5E_NIC_PRIO | |
652 | }; | |
653 | ||
f62b8bb8 AV |
654 | struct mlx5e_priv { |
655 | /* priv data path fields - start */ | |
acc6c595 SM |
656 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
657 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
2a5e7a13 HN |
658 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
659 | struct mlx5e_dcbx_dp dcbx_dp; | |
660 | #endif | |
f62b8bb8 AV |
661 | /* priv data path fields - end */ |
662 | ||
79c48764 | 663 | u32 msglevel; |
f62b8bb8 AV |
664 | unsigned long state; |
665 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 666 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 667 | |
ff9c852f | 668 | struct mlx5e_channels channels; |
f62b8bb8 | 669 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 670 | struct mlx5e_rqt indir_rqt; |
724b2aa1 | 671 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
7b3722fa | 672 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; |
724b2aa1 | 673 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; |
507f0c81 | 674 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 675 | |
acff797c | 676 | struct mlx5e_flow_steering fs; |
f62b8bb8 | 677 | |
7bb29755 | 678 | struct workqueue_struct *wq; |
f62b8bb8 AV |
679 | struct work_struct update_carrier_work; |
680 | struct work_struct set_rx_mode_work; | |
3947ca18 | 681 | struct work_struct tx_timeout_work; |
cdeef2b1 | 682 | struct work_struct update_stats_work; |
f62b8bb8 AV |
683 | |
684 | struct mlx5_core_dev *mdev; | |
685 | struct net_device *netdev; | |
686 | struct mlx5e_stats stats; | |
05909bab EBE |
687 | struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS]; |
688 | u8 max_opened_tc; | |
7c39afb3 | 689 | struct hwtstamp_config tstamp; |
7cbaf9a3 MS |
690 | u16 q_counter; |
691 | u16 drop_rq_q_counter; | |
3a6a931d HN |
692 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
693 | struct mlx5e_dcbx dcbx; | |
694 | #endif | |
695 | ||
6bfd390b | 696 | const struct mlx5e_profile *profile; |
127ea380 | 697 | void *ppriv; |
547eede0 IT |
698 | #ifdef CONFIG_MLX5_EN_IPSEC |
699 | struct mlx5e_ipsec *ipsec; | |
700 | #endif | |
43585a41 IL |
701 | #ifdef CONFIG_MLX5_EN_TLS |
702 | struct mlx5e_tls *tls; | |
703 | #endif | |
f62b8bb8 AV |
704 | }; |
705 | ||
a43b25da | 706 | struct mlx5e_profile { |
182570b2 | 707 | int (*init)(struct mlx5_core_dev *mdev, |
a43b25da SM |
708 | struct net_device *netdev, |
709 | const struct mlx5e_profile *profile, void *ppriv); | |
710 | void (*cleanup)(struct mlx5e_priv *priv); | |
711 | int (*init_rx)(struct mlx5e_priv *priv); | |
712 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
713 | int (*init_tx)(struct mlx5e_priv *priv); | |
714 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
715 | void (*enable)(struct mlx5e_priv *priv); | |
716 | void (*disable)(struct mlx5e_priv *priv); | |
717 | void (*update_stats)(struct mlx5e_priv *priv); | |
7ca42c80 | 718 | void (*update_carrier)(struct mlx5e_priv *priv); |
20fd0c19 SM |
719 | struct { |
720 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
721 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
722 | } rx_handlers; | |
a43b25da SM |
723 | int max_tc; |
724 | }; | |
725 | ||
665bc539 GP |
726 | void mlx5e_build_ptys2ethtool_map(void); |
727 | ||
f62b8bb8 | 728 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
4f49dec9 AD |
729 | struct net_device *sb_dev, |
730 | select_queue_fallback_t fallback); | |
f62b8bb8 | 731 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); |
bf239741 IL |
732 | netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
733 | struct mlx5e_tx_wqe *wqe, u16 pi); | |
f62b8bb8 AV |
734 | |
735 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
736 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
737 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 738 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 739 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
31391048 | 740 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
461017cb | 741 | |
2ccb0a79 TT |
742 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); |
743 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, | |
744 | struct mlx5e_params *params); | |
745 | ||
159d2131 | 746 | void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info); |
4415a031 TT |
747 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
748 | bool recycle); | |
2f48af12 | 749 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 750 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 751 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
7cc6d77b | 752 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); |
6cd392a0 DJ |
753 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
754 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
619a8f2a TT |
755 | struct sk_buff * |
756 | mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
757 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
758 | struct sk_buff * | |
759 | mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
760 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
761 | struct sk_buff * |
762 | mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
763 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
764 | struct sk_buff * | |
765 | mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
766 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
f62b8bb8 | 767 | |
19386177 | 768 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
f62b8bb8 | 769 | |
33cfaaa8 | 770 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
d605d668 KH |
771 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
772 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
773 | u64 *buf); | |
f62b8bb8 AV |
774 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
775 | ||
1170fbd8 FD |
776 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
777 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 778 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 779 | |
f62b8bb8 AV |
780 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
781 | u16 vid); | |
782 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
783 | u16 vid); | |
237f258c | 784 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 785 | |
a5f97fee SM |
786 | struct mlx5e_redirect_rqt_param { |
787 | bool is_rss; | |
788 | union { | |
789 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
790 | struct { | |
791 | u8 hfunc; | |
792 | struct mlx5e_channels *channels; | |
793 | } rss; /* RSS data */ | |
794 | }; | |
795 | }; | |
796 | ||
797 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
798 | struct mlx5e_redirect_rqt_param rrp); | |
6a9764ef SM |
799 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
800 | enum mlx5e_traffic_types tt, | |
7b3722fa | 801 | void *tirc, bool inner); |
080d1b17 | 802 | void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen); |
2d75b2bc | 803 | |
f62b8bb8 AV |
804 | int mlx5e_open_locked(struct net_device *netdev); |
805 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
806 | |
807 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
808 | struct mlx5e_channels *chs); | |
809 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
810 | |
811 | /* Function pointer to be used to modify WH settings while | |
812 | * switching channels | |
813 | */ | |
814 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
55c2503d | 815 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
816 | struct mlx5e_channels *new_chs, |
817 | mlx5e_fp_hw_modify hw_modify); | |
603f4a45 SM |
818 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
819 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 820 | |
d4b6c488 | 821 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba | 822 | int num_channels); |
0088cbbc TG |
823 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, |
824 | u8 cq_period_mode); | |
9908aa29 TT |
825 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
826 | u8 cq_period_mode); | |
2ccb0a79 | 827 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params); |
696a97cf | 828 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 829 | struct mlx5e_params *params); |
9908aa29 | 830 | |
7b3722fa GP |
831 | static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) |
832 | { | |
833 | return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) && | |
834 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version)); | |
835 | } | |
836 | ||
bf239741 IL |
837 | static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq, |
838 | struct mlx5e_tx_wqe **wqe, | |
839 | u16 *pi) | |
840 | { | |
ddf385e3 | 841 | struct mlx5_wq_cyc *wq = &sq->wq; |
bf239741 | 842 | |
ddf385e3 | 843 | *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
bf239741 IL |
844 | *wqe = mlx5_wq_cyc_get_wqe(wq, *pi); |
845 | memset(*wqe, 0, sizeof(**wqe)); | |
846 | } | |
847 | ||
864b2d71 SM |
848 | static inline |
849 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 850 | { |
ddf385e3 | 851 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc); |
864b2d71 SM |
852 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); |
853 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
854 | ||
855 | memset(cseg, 0, sizeof(*cseg)); | |
856 | ||
857 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
858 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
859 | ||
860 | (*pc)++; | |
861 | ||
862 | return wqe; | |
863 | } | |
864 | ||
865 | static inline | |
866 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
867 | void __iomem *uar_map, | |
868 | struct mlx5_wqe_ctrl_seg *ctrl) | |
869 | { | |
870 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
871 | /* ensure wqe is visible to device before updating doorbell record */ |
872 | dma_wmb(); | |
873 | ||
864b2d71 | 874 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
875 | |
876 | /* ensure doorbell record is visible to device before ringing the | |
877 | * doorbell | |
878 | */ | |
879 | wmb(); | |
f62b8bb8 | 880 | |
864b2d71 | 881 | mlx5_write64((__be32 *)ctrl, uar_map, NULL); |
f62b8bb8 AV |
882 | } |
883 | ||
884 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
885 | { | |
886 | struct mlx5_core_cq *mcq; | |
887 | ||
888 | mcq = &cq->mcq; | |
5fe9dec0 | 889 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
890 | } |
891 | ||
892 | extern const struct ethtool_ops mlx5e_ethtool_ops; | |
08fb1dac SM |
893 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
894 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
895 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 896 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
2a5e7a13 HN |
897 | void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv); |
898 | void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv); | |
08fb1dac SM |
899 | #endif |
900 | ||
724b2aa1 HHZ |
901 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
902 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
903 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
904 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
905 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
906 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 907 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 908 | |
bc81b9d3 | 909 | /* common netdev helpers */ |
1462e48d RD |
910 | void mlx5e_create_q_counters(struct mlx5e_priv *priv); |
911 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); | |
912 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, | |
913 | struct mlx5e_rq *drop_rq); | |
914 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); | |
915 | ||
8f493ffd SM |
916 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
917 | ||
46dc933c OG |
918 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); |
919 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); | |
8f493ffd | 920 | |
cb67b832 | 921 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); |
8f493ffd | 922 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); |
cb67b832 HHZ |
923 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); |
924 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
8f493ffd SM |
925 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
926 | ||
5426a0b2 SM |
927 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
928 | u32 underlay_qpn, u32 *tisn); | |
929 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); | |
930 | ||
cb67b832 HHZ |
931 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
932 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
933 | int mlx5e_close(struct net_device *netdev); | |
934 | int mlx5e_open(struct net_device *netdev); | |
cb67b832 | 935 | |
cdeef2b1 | 936 | void mlx5e_queue_update_stats(struct mlx5e_priv *priv); |
3f6d08d1 OG |
937 | int mlx5e_bits_invert(unsigned long a, int size); |
938 | ||
250a42b6 AN |
939 | typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv); |
940 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, | |
941 | change_hw_mtu_cb set_mtu_cb); | |
942 | ||
076b0936 ES |
943 | /* ethtool helpers */ |
944 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
945 | struct ethtool_drvinfo *drvinfo); | |
946 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
947 | uint32_t stringset, uint8_t *data); | |
948 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
949 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
950 | struct ethtool_stats *stats, u64 *data); | |
951 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
952 | struct ethtool_ringparam *param); | |
953 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
954 | struct ethtool_ringparam *param); | |
955 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
956 | struct ethtool_channels *ch); | |
957 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
958 | struct ethtool_channels *ch); | |
959 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
960 | struct ethtool_coalesce *coal); | |
961 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
962 | struct ethtool_coalesce *coal); | |
a5355de8 OG |
963 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); |
964 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); | |
3844b07e FD |
965 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
966 | struct ethtool_ts_info *info); | |
3ffaabec OG |
967 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
968 | struct ethtool_flash *flash); | |
076b0936 | 969 | |
2c3b5bee | 970 | /* mlx5e generic netdev management API */ |
519a0bf5 SM |
971 | int mlx5e_netdev_init(struct net_device *netdev, |
972 | struct mlx5e_priv *priv, | |
973 | struct mlx5_core_dev *mdev, | |
974 | const struct mlx5e_profile *profile, | |
975 | void *ppriv); | |
182570b2 | 976 | void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv); |
2c3b5bee SM |
977 | struct net_device* |
978 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
779d986d | 979 | int nch, void *ppriv); |
2c3b5bee SM |
980 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); |
981 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
982 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
8f493ffd SM |
983 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
984 | struct mlx5e_params *params, | |
472a1e44 | 985 | u16 max_channels, u16 mtu); |
749359f4 GT |
986 | void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, |
987 | struct mlx5e_params *params); | |
3edc0159 | 988 | void mlx5e_build_rss_params(struct mlx5e_params *params); |
fbcb127e | 989 | u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev); |
9a317425 | 990 | void mlx5e_rx_dim_work(struct work_struct *work); |
cbce4f44 | 991 | void mlx5e_tx_dim_work(struct work_struct *work); |
1afff42c | 992 | #endif /* __MLX5_EN_H__ */ |