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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
d8bec2b2 MKL |
54 | #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
55 | #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
56 | ||
f62b8bb8 AV |
57 | #define MLX5E_MAX_NUM_TC 8 |
58 | ||
e842b100 | 59 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
60 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
61 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
62 | ||
e842b100 | 63 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
64 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
65 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
66 | ||
461017cb | 67 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 68 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
69 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
70 | ||
1bfecfca SM |
71 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
72 | ||
461017cb | 73 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 | 74 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
7e426671 | 75 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
76 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
77 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
78 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
79 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
80 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
81 | |
82 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
ec8b9981 TT |
83 | #define MLX5E_REQUIRED_MTTS(wqes) \ |
84 | (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
85 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) | |
fe4c988b | 86 | |
bc77b240 | 87 | #define MLX5_UMR_ALIGN (2048) |
461017cb TT |
88 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
89 | ||
d9a40271 | 90 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
91 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
92 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
93 | ||
f62b8bb8 | 94 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 95 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
96 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
97 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
98 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
99 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 100 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 101 | |
936896e9 AS |
102 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
103 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
104 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
507f0c81 | 105 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
106 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
107 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 108 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 109 | |
f10b7cc7 SM |
110 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
111 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
112 | ||
b5503b99 SM |
113 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
114 | #define MLX5E_XDP_IHS_DS_COUNT \ | |
115 | DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS) | |
116 | #define MLX5E_XDP_TX_DS_COUNT \ | |
117 | (MLX5E_XDP_IHS_DS_COUNT + \ | |
118 | (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) | |
119 | #define MLX5E_XDP_TX_WQEBBS \ | |
120 | DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS) | |
121 | ||
86d722ad | 122 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 123 | |
461017cb TT |
124 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
125 | { | |
126 | switch (wq_type) { | |
127 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
128 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
129 | wq_size / 2); | |
130 | default: | |
131 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
132 | wq_size / 2); | |
133 | } | |
134 | } | |
135 | ||
136 | static inline int mlx5_min_log_rq_size(int wq_type) | |
137 | { | |
138 | switch (wq_type) { | |
139 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
140 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
141 | default: | |
142 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
143 | } | |
144 | } | |
145 | ||
146 | static inline int mlx5_max_log_rq_size(int wq_type) | |
147 | { | |
148 | switch (wq_type) { | |
149 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
150 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
151 | default: | |
152 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
153 | } | |
154 | } | |
155 | ||
2f48af12 TT |
156 | struct mlx5e_tx_wqe { |
157 | struct mlx5_wqe_ctrl_seg ctrl; | |
158 | struct mlx5_wqe_eth_seg eth; | |
159 | }; | |
160 | ||
161 | struct mlx5e_rx_wqe { | |
162 | struct mlx5_wqe_srq_next_seg next; | |
163 | struct mlx5_wqe_data_seg data; | |
164 | }; | |
86d722ad | 165 | |
bc77b240 TT |
166 | struct mlx5e_umr_wqe { |
167 | struct mlx5_wqe_ctrl_seg ctrl; | |
168 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
169 | struct mlx5_mkey_seg mkc; | |
170 | struct mlx5_wqe_data_seg data; | |
171 | }; | |
172 | ||
d605d668 KH |
173 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
174 | ||
4e59e288 | 175 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 176 | "rx_cqe_moder", |
9bcc8606 | 177 | "rx_cqe_compress", |
4e59e288 GP |
178 | }; |
179 | ||
180 | enum mlx5e_priv_flag { | |
9908aa29 | 181 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
9bcc8606 | 182 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1), |
4e59e288 GP |
183 | }; |
184 | ||
59ece1c9 SD |
185 | #define MLX5E_SET_PFLAG(priv, pflag, enable) \ |
186 | do { \ | |
187 | if (enable) \ | |
188 | (priv)->params.pflags |= (pflag); \ | |
189 | else \ | |
190 | (priv)->params.pflags &= ~(pflag); \ | |
4e59e288 GP |
191 | } while (0) |
192 | ||
59ece1c9 SD |
193 | #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag))) |
194 | ||
08fb1dac SM |
195 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
196 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
197 | #endif |
198 | ||
9908aa29 TT |
199 | struct mlx5e_cq_moder { |
200 | u16 usec; | |
201 | u16 pkts; | |
202 | }; | |
203 | ||
f62b8bb8 AV |
204 | struct mlx5e_params { |
205 | u8 log_sq_size; | |
461017cb | 206 | u8 rq_wq_type; |
d9d9f156 TT |
207 | u8 mpwqe_log_stride_sz; |
208 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
209 | u8 log_rq_size; |
210 | u16 num_channels; | |
f62b8bb8 | 211 | u8 num_tc; |
9908aa29 | 212 | u8 rx_cq_period_mode; |
9bcc8606 | 213 | bool rx_cqe_compress_def; |
9908aa29 TT |
214 | struct mlx5e_cq_moder rx_cq_moderation; |
215 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 216 | u16 min_rx_wqes; |
f62b8bb8 AV |
217 | bool lro_en; |
218 | u32 lro_wqe_sz; | |
58d52291 | 219 | u16 tx_max_inline; |
cff92d7c | 220 | u8 tx_min_inline_mode; |
2d75b2bc AS |
221 | u8 rss_hfunc; |
222 | u8 toeplitz_hash_key[40]; | |
223 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 224 | bool vlan_strip_disable; |
cb3c7fd4 | 225 | bool rx_am_enabled; |
2b029556 | 226 | u32 lro_timeout; |
59ece1c9 | 227 | u32 pflags; |
f62b8bb8 AV |
228 | }; |
229 | ||
3a6a931d HN |
230 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
231 | struct mlx5e_cee_config { | |
232 | /* bw pct for priority group */ | |
233 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
234 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
235 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
236 | bool pfc_enable; | |
237 | }; | |
238 | ||
239 | enum { | |
240 | MLX5_DCB_CHG_RESET, | |
241 | MLX5_DCB_NO_CHG, | |
242 | MLX5_DCB_CHG_NO_RESET, | |
243 | }; | |
244 | ||
245 | struct mlx5e_dcbx { | |
e207b7e9 | 246 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 247 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
820c2c5e HN |
248 | |
249 | /* The only setting that cannot be read from FW */ | |
250 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
3a6a931d HN |
251 | }; |
252 | #endif | |
253 | ||
ef9814de EBE |
254 | struct mlx5e_tstamp { |
255 | rwlock_t lock; | |
256 | struct cyclecounter cycles; | |
257 | struct timecounter clock; | |
258 | struct hwtstamp_config hwtstamp_config; | |
259 | u32 nominal_c_mult; | |
260 | unsigned long overflow_period; | |
261 | struct delayed_work overflow_work; | |
262 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
263 | struct ptp_clock *ptp; |
264 | struct ptp_clock_info ptp_info; | |
ee7f1220 | 265 | u8 *pps_pin_caps; |
ef9814de EBE |
266 | }; |
267 | ||
f62b8bb8 | 268 | enum { |
c0f1147d | 269 | MLX5E_RQ_STATE_ENABLED, |
bc77b240 | 270 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 271 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
272 | }; |
273 | ||
f62b8bb8 AV |
274 | struct mlx5e_cq { |
275 | /* data path - accessed per cqe */ | |
276 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
277 | |
278 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 279 | u16 event_ctr; |
f62b8bb8 AV |
280 | struct napi_struct *napi; |
281 | struct mlx5_core_cq mcq; | |
282 | struct mlx5e_channel *channel; | |
50cfa25a | 283 | struct mlx5e_priv *priv; |
f62b8bb8 | 284 | |
7219ab34 TT |
285 | /* cqe decompression */ |
286 | struct mlx5_cqe64 title; | |
287 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
288 | u8 mini_arr_idx; | |
289 | u16 decmprs_left; | |
290 | u16 decmprs_wqe_counter; | |
291 | ||
f62b8bb8 | 292 | /* control */ |
1c1b5228 | 293 | struct mlx5_frag_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
294 | } ____cacheline_aligned_in_smp; |
295 | ||
2f48af12 TT |
296 | struct mlx5e_rq; |
297 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
298 | struct mlx5_cqe64 *cqe); | |
299 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
300 | u16 ix); | |
301 | ||
6cd392a0 DJ |
302 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix); |
303 | ||
461017cb TT |
304 | struct mlx5e_dma_info { |
305 | struct page *page; | |
306 | dma_addr_t addr; | |
307 | }; | |
308 | ||
cb3c7fd4 GR |
309 | struct mlx5e_rx_am_stats { |
310 | int ppms; /* packets per msec */ | |
311 | int epms; /* events per msec */ | |
312 | }; | |
313 | ||
314 | struct mlx5e_rx_am_sample { | |
315 | ktime_t time; | |
316 | unsigned int pkt_ctr; | |
317 | u16 event_ctr; | |
318 | }; | |
319 | ||
320 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
321 | u8 state; | |
322 | struct mlx5e_rx_am_stats prev_stats; | |
323 | struct mlx5e_rx_am_sample start_sample; | |
324 | struct work_struct work; | |
325 | u8 profile_ix; | |
326 | u8 mode; | |
327 | u8 tune_state; | |
328 | u8 steps_right; | |
329 | u8 steps_left; | |
330 | u8 tired; | |
331 | }; | |
332 | ||
4415a031 TT |
333 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
334 | * or a MPWQE (for striding rq). | |
335 | */ | |
336 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
337 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
338 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
339 | struct mlx5e_page_cache { | |
340 | u32 head; | |
341 | u32 tail; | |
342 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
343 | }; | |
344 | ||
f62b8bb8 AV |
345 | struct mlx5e_rq { |
346 | /* data path */ | |
347 | struct mlx5_wq_ll wq; | |
1bfecfca | 348 | |
21c59685 SM |
349 | union { |
350 | struct mlx5e_dma_info *dma_info; | |
351 | struct { | |
352 | struct mlx5e_mpw_info *info; | |
353 | void *mtt_no_align; | |
21c59685 SM |
354 | } mpwqe; |
355 | }; | |
1bfecfca SM |
356 | struct { |
357 | u8 page_order; | |
358 | u32 wqe_sz; /* wqe data buffer size */ | |
b5503b99 | 359 | u8 map_dir; /* dma map direction */ |
1bfecfca | 360 | } buff; |
bc77b240 | 361 | __be32 mkey_be; |
f62b8bb8 AV |
362 | |
363 | struct device *pdev; | |
364 | struct net_device *netdev; | |
ef9814de | 365 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
366 | struct mlx5e_rq_stats stats; |
367 | struct mlx5e_cq cq; | |
4415a031 TT |
368 | struct mlx5e_page_cache page_cache; |
369 | ||
2f48af12 TT |
370 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
371 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 372 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
373 | |
374 | unsigned long state; | |
375 | int ix; | |
d8bec2b2 | 376 | u16 rx_headroom; |
f62b8bb8 | 377 | |
cb3c7fd4 | 378 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
86994156 | 379 | struct bpf_prog *xdp_prog; |
cb3c7fd4 | 380 | |
f62b8bb8 AV |
381 | /* control */ |
382 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 383 | u8 wq_type; |
d9d9f156 TT |
384 | u32 mpwqe_stride_sz; |
385 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
386 | u32 rqn; |
387 | struct mlx5e_channel *channel; | |
50cfa25a | 388 | struct mlx5e_priv *priv; |
ec8b9981 | 389 | struct mlx5_core_mkey umr_mkey; |
f62b8bb8 AV |
390 | } ____cacheline_aligned_in_smp; |
391 | ||
bc77b240 TT |
392 | struct mlx5e_umr_dma_info { |
393 | __be64 *mtt; | |
bc77b240 | 394 | dma_addr_t mtt_addr; |
7e426671 TT |
395 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
396 | struct mlx5e_umr_wqe wqe; | |
bc77b240 TT |
397 | }; |
398 | ||
399 | struct mlx5e_mpw_info { | |
7e426671 | 400 | struct mlx5e_umr_dma_info umr; |
bc77b240 TT |
401 | u16 consumed_strides; |
402 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
bc77b240 TT |
403 | }; |
404 | ||
34802a42 | 405 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
406 | u32 num_bytes; |
407 | u8 num_wqebbs; | |
408 | u8 num_dma; | |
409 | }; | |
410 | ||
d4e28cbd AS |
411 | enum mlx5e_dma_map_type { |
412 | MLX5E_DMA_MAP_SINGLE, | |
413 | MLX5E_DMA_MAP_PAGE | |
414 | }; | |
415 | ||
f62b8bb8 | 416 | struct mlx5e_sq_dma { |
d4e28cbd AS |
417 | dma_addr_t addr; |
418 | u32 size; | |
419 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
420 | }; |
421 | ||
422 | enum { | |
c0f1147d | 423 | MLX5E_SQ_STATE_ENABLED, |
0ba42241 | 424 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
425 | }; |
426 | ||
b5503b99 | 427 | struct mlx5e_sq_wqe_info { |
d3c9bc27 TT |
428 | u8 opcode; |
429 | u8 num_wqebbs; | |
430 | }; | |
431 | ||
f10b7cc7 SM |
432 | enum mlx5e_sq_type { |
433 | MLX5E_SQ_TXQ, | |
b5503b99 SM |
434 | MLX5E_SQ_ICO, |
435 | MLX5E_SQ_XDP | |
f10b7cc7 SM |
436 | }; |
437 | ||
f62b8bb8 AV |
438 | struct mlx5e_sq { |
439 | /* data path */ | |
440 | ||
441 | /* dirtied @completion */ | |
442 | u16 cc; | |
443 | u32 dma_fifo_cc; | |
444 | ||
445 | /* dirtied @xmit */ | |
446 | u16 pc ____cacheline_aligned_in_smp; | |
447 | u32 dma_fifo_pc; | |
88a85f99 AS |
448 | u16 bf_offset; |
449 | u16 prev_cc; | |
450 | u8 bf_budget; | |
f62b8bb8 AV |
451 | struct mlx5e_sq_stats stats; |
452 | ||
453 | struct mlx5e_cq cq; | |
454 | ||
f10b7cc7 SM |
455 | /* pointers to per tx element info: write@xmit, read@completion */ |
456 | union { | |
457 | struct { | |
458 | struct sk_buff **skb; | |
459 | struct mlx5e_sq_dma *dma_fifo; | |
460 | struct mlx5e_tx_wqe_info *wqe_info; | |
461 | } txq; | |
b5503b99 SM |
462 | struct mlx5e_sq_wqe_info *ico_wqe; |
463 | struct { | |
464 | struct mlx5e_sq_wqe_info *wqe_info; | |
465 | struct mlx5e_dma_info *di; | |
35b510e2 | 466 | bool doorbell; |
b5503b99 | 467 | } xdp; |
f10b7cc7 | 468 | } db; |
f62b8bb8 AV |
469 | |
470 | /* read only */ | |
471 | struct mlx5_wq_cyc wq; | |
472 | u32 dma_fifo_mask; | |
f62b8bb8 AV |
473 | struct netdev_queue *txq; |
474 | u32 sqn; | |
88a85f99 | 475 | u16 bf_buf_size; |
12be4b21 | 476 | u16 max_inline; |
ae76715d | 477 | u8 min_inline_mode; |
12be4b21 | 478 | u16 edge; |
f62b8bb8 | 479 | struct device *pdev; |
ef9814de | 480 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
481 | __be32 mkey_be; |
482 | unsigned long state; | |
483 | ||
484 | /* control path */ | |
485 | struct mlx5_wq_ctrl wq_ctrl; | |
30aa60b3 | 486 | struct mlx5_sq_bfreg bfreg; |
f62b8bb8 AV |
487 | struct mlx5e_channel *channel; |
488 | int tc; | |
507f0c81 | 489 | u32 rate_limit; |
f10b7cc7 | 490 | u8 type; |
f62b8bb8 AV |
491 | } ____cacheline_aligned_in_smp; |
492 | ||
493 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
494 | { | |
495 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
496 | (sq->cc == sq->pc)); | |
497 | } | |
498 | ||
499 | enum channel_flags { | |
500 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
501 | }; | |
502 | ||
503 | struct mlx5e_channel { | |
504 | /* data path */ | |
505 | struct mlx5e_rq rq; | |
b5503b99 | 506 | struct mlx5e_sq xdp_sq; |
f62b8bb8 | 507 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; |
d3c9bc27 | 508 | struct mlx5e_sq icosq; /* internal control operations */ |
b5503b99 | 509 | bool xdp; |
f62b8bb8 AV |
510 | struct napi_struct napi; |
511 | struct device *pdev; | |
512 | struct net_device *netdev; | |
513 | __be32 mkey_be; | |
514 | u8 num_tc; | |
515 | unsigned long flags; | |
516 | ||
517 | /* control */ | |
518 | struct mlx5e_priv *priv; | |
519 | int ix; | |
520 | int cpu; | |
521 | }; | |
522 | ||
523 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
524 | MLX5E_TT_IPV4_TCP, |
525 | MLX5E_TT_IPV6_TCP, | |
526 | MLX5E_TT_IPV4_UDP, | |
527 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
528 | MLX5E_TT_IPV4_IPSEC_AH, |
529 | MLX5E_TT_IPV6_IPSEC_AH, | |
530 | MLX5E_TT_IPV4_IPSEC_ESP, | |
531 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
532 | MLX5E_TT_IPV4, |
533 | MLX5E_TT_IPV6, | |
534 | MLX5E_TT_ANY, | |
535 | MLX5E_NUM_TT, | |
1da36696 | 536 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
537 | }; |
538 | ||
acff797c | 539 | enum { |
e0f46eb9 | 540 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
541 | MLX5E_STATE_OPENED, |
542 | MLX5E_STATE_DESTROYING, | |
543 | }; | |
544 | ||
545 | struct mlx5e_vxlan_db { | |
546 | spinlock_t lock; /* protect vxlan table */ | |
547 | struct radix_tree_root tree; | |
548 | }; | |
549 | ||
33cfaaa8 | 550 | struct mlx5e_l2_rule { |
f62b8bb8 | 551 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 552 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
553 | }; |
554 | ||
acff797c MG |
555 | struct mlx5e_flow_table { |
556 | int num_groups; | |
557 | struct mlx5_flow_table *t; | |
558 | struct mlx5_flow_group **g; | |
559 | }; | |
560 | ||
33cfaaa8 | 561 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 562 | |
acff797c MG |
563 | struct mlx5e_tc_table { |
564 | struct mlx5_flow_table *t; | |
565 | ||
566 | struct rhashtable_params ht_params; | |
567 | struct rhashtable ht; | |
f62b8bb8 AV |
568 | }; |
569 | ||
acff797c MG |
570 | struct mlx5e_vlan_table { |
571 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 572 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
74491de9 MB |
573 | struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID]; |
574 | struct mlx5_flow_handle *untagged_rule; | |
575 | struct mlx5_flow_handle *any_vlan_rule; | |
576 | bool filter_disabled; | |
f62b8bb8 AV |
577 | }; |
578 | ||
33cfaaa8 MG |
579 | struct mlx5e_l2_table { |
580 | struct mlx5e_flow_table ft; | |
581 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
582 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
583 | struct mlx5e_l2_rule broadcast; | |
584 | struct mlx5e_l2_rule allmulti; | |
585 | struct mlx5e_l2_rule promisc; | |
586 | bool broadcast_enabled; | |
587 | bool allmulti_enabled; | |
588 | bool promisc_enabled; | |
589 | }; | |
590 | ||
591 | /* L3/L4 traffic type classifier */ | |
592 | struct mlx5e_ttc_table { | |
593 | struct mlx5e_flow_table ft; | |
74491de9 | 594 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
33cfaaa8 MG |
595 | }; |
596 | ||
18c908e4 MG |
597 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
598 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
599 | struct arfs_table { |
600 | struct mlx5e_flow_table ft; | |
74491de9 | 601 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 602 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
603 | }; |
604 | ||
605 | enum arfs_type { | |
606 | ARFS_IPV4_TCP, | |
607 | ARFS_IPV6_TCP, | |
608 | ARFS_IPV4_UDP, | |
609 | ARFS_IPV6_UDP, | |
610 | ARFS_NUM_TYPES, | |
611 | }; | |
612 | ||
613 | struct mlx5e_arfs_tables { | |
614 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
615 | /* Protect aRFS rules list */ |
616 | spinlock_t arfs_lock; | |
617 | struct list_head rules; | |
618 | int last_filter_id; | |
619 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
620 | }; |
621 | ||
622 | /* NIC prio FTS */ | |
623 | enum { | |
624 | MLX5E_VLAN_FT_LEVEL = 0, | |
625 | MLX5E_L2_FT_LEVEL, | |
626 | MLX5E_TTC_FT_LEVEL, | |
627 | MLX5E_ARFS_FT_LEVEL | |
628 | }; | |
629 | ||
6dc6071c MG |
630 | struct mlx5e_ethtool_table { |
631 | struct mlx5_flow_table *ft; | |
632 | int num_rules; | |
633 | }; | |
634 | ||
1174fce8 | 635 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
636 | #define ETHTOOL_NUM_L2_FTS 4 |
637 | ||
638 | struct mlx5e_ethtool_steering { | |
1174fce8 | 639 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
640 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
641 | struct list_head rules; | |
642 | int tot_num_rules; | |
643 | }; | |
644 | ||
acff797c MG |
645 | struct mlx5e_flow_steering { |
646 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 647 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
648 | struct mlx5e_tc_table tc; |
649 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
650 | struct mlx5e_l2_table l2; |
651 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 652 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
653 | }; |
654 | ||
398f3351 | 655 | struct mlx5e_rqt { |
1da36696 | 656 | u32 rqtn; |
398f3351 HHZ |
657 | bool enabled; |
658 | }; | |
659 | ||
660 | struct mlx5e_tir { | |
661 | u32 tirn; | |
662 | struct mlx5e_rqt rqt; | |
663 | struct list_head list; | |
1da36696 TT |
664 | }; |
665 | ||
acff797c MG |
666 | enum { |
667 | MLX5E_TC_PRIO = 0, | |
668 | MLX5E_NIC_PRIO | |
669 | }; | |
670 | ||
6bfd390b HHZ |
671 | struct mlx5e_profile { |
672 | void (*init)(struct mlx5_core_dev *mdev, | |
673 | struct net_device *netdev, | |
127ea380 | 674 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
675 | void (*cleanup)(struct mlx5e_priv *priv); |
676 | int (*init_rx)(struct mlx5e_priv *priv); | |
677 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
678 | int (*init_tx)(struct mlx5e_priv *priv); | |
679 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
680 | void (*enable)(struct mlx5e_priv *priv); | |
681 | void (*disable)(struct mlx5e_priv *priv); | |
682 | void (*update_stats)(struct mlx5e_priv *priv); | |
683 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
684 | int max_tc; | |
685 | }; | |
686 | ||
f62b8bb8 AV |
687 | struct mlx5e_priv { |
688 | /* priv data path fields - start */ | |
03289b88 | 689 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 690 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
86994156 | 691 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
692 | /* priv data path fields - end */ |
693 | ||
694 | unsigned long state; | |
695 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 696 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
697 | |
698 | struct mlx5e_channel **channel; | |
699 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
398f3351 | 700 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
701 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
702 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 703 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 704 | |
acff797c | 705 | struct mlx5e_flow_steering fs; |
b3f63c3d | 706 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
707 | |
708 | struct mlx5e_params params; | |
7bb29755 | 709 | struct workqueue_struct *wq; |
f62b8bb8 AV |
710 | struct work_struct update_carrier_work; |
711 | struct work_struct set_rx_mode_work; | |
3947ca18 | 712 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
713 | struct delayed_work update_stats_work; |
714 | ||
715 | struct mlx5_core_dev *mdev; | |
716 | struct net_device *netdev; | |
717 | struct mlx5e_stats stats; | |
ef9814de | 718 | struct mlx5e_tstamp tstamp; |
593cf338 | 719 | u16 q_counter; |
3a6a931d HN |
720 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
721 | struct mlx5e_dcbx dcbx; | |
722 | #endif | |
723 | ||
6bfd390b | 724 | const struct mlx5e_profile *profile; |
127ea380 | 725 | void *ppriv; |
f62b8bb8 AV |
726 | }; |
727 | ||
665bc539 GP |
728 | void mlx5e_build_ptys2ethtool_map(void); |
729 | ||
12be4b21 | 730 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
731 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
732 | void *accel_priv, select_queue_fallback_t fallback); | |
733 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
734 | |
735 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
736 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
737 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 738 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 739 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
b5503b99 | 740 | void mlx5e_free_sq_descs(struct mlx5e_sq *sq); |
461017cb | 741 | |
4415a031 TT |
742 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
743 | bool recycle); | |
2f48af12 | 744 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 745 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 746 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 747 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 748 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
749 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
750 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
751 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
752 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
753 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
754 | ||
cb3c7fd4 GR |
755 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
756 | void mlx5e_rx_am_work(struct work_struct *work); | |
757 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
758 | ||
f62b8bb8 AV |
759 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
760 | ||
acff797c MG |
761 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
762 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 763 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 764 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
765 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
766 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
767 | u64 *buf); | |
f913a72a MG |
768 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
769 | int location); | |
770 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
771 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
772 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
773 | struct ethtool_rx_flow_spec *fs); | |
774 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
775 | int location); | |
776 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
777 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
778 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
779 | ||
ef9814de EBE |
780 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
781 | struct skb_shared_hwtstamps *hwts); | |
782 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
783 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
ee7f1220 EE |
784 | void mlx5e_pps_event_handler(struct mlx5e_priv *priv, |
785 | struct ptp_clock_event *event); | |
ef9814de EBE |
786 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); |
787 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 788 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 789 | |
f62b8bb8 AV |
790 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
791 | u16 vid); | |
792 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
793 | u16 vid); | |
794 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
795 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 796 | |
36350114 GP |
797 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
798 | ||
1da36696 | 799 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 800 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 801 | |
f62b8bb8 AV |
802 | int mlx5e_open_locked(struct net_device *netdev); |
803 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
804 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
805 | u32 *indirection_rqt, int len, | |
85082dba | 806 | int num_channels); |
b797a684 | 807 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 808 | |
9908aa29 TT |
809 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
810 | u8 cq_period_mode); | |
811 | ||
f62b8bb8 | 812 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
bc77b240 | 813 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 814 | { |
30aa60b3 | 815 | u16 ofst = sq->bf_offset; |
88a85f99 | 816 | |
f62b8bb8 AV |
817 | /* ensure wqe is visible to device before updating doorbell record */ |
818 | dma_wmb(); | |
819 | ||
820 | *sq->wq.db = cpu_to_be32(sq->pc); | |
821 | ||
822 | /* ensure doorbell record is visible to device before ringing the | |
823 | * doorbell | |
824 | */ | |
825 | wmb(); | |
0ba42241 | 826 | if (bf_sz) |
30aa60b3 | 827 | __iowrite64_copy(sq->bfreg.map + ofst, ctrl, bf_sz); |
0ba42241 | 828 | else |
30aa60b3 | 829 | mlx5_write64((__be32 *)ctrl, sq->bfreg.map + ofst, NULL); |
0ba42241 ML |
830 | /* flush the write-combining mapped buffer */ |
831 | wmb(); | |
f62b8bb8 AV |
832 | |
833 | sq->bf_offset ^= sq->bf_buf_size; | |
834 | } | |
835 | ||
836 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
837 | { | |
838 | struct mlx5_core_cq *mcq; | |
839 | ||
840 | mcq = &cq->mcq; | |
5fe9dec0 | 841 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
842 | } |
843 | ||
7e426671 TT |
844 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
845 | { | |
ec8b9981 | 846 | return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
7e426671 TT |
847 | } |
848 | ||
3435ab59 AS |
849 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
850 | { | |
851 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
852 | MLX5E_MAX_NUM_CHANNELS); | |
853 | } | |
854 | ||
f62b8bb8 | 855 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
856 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
857 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
858 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 859 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
08fb1dac SM |
860 | #endif |
861 | ||
1cabe6b0 MG |
862 | #ifndef CONFIG_RFS_ACCEL |
863 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
864 | { | |
865 | return 0; | |
866 | } | |
867 | ||
868 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
869 | |
870 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
871 | { | |
872 | return -ENOTSUPP; | |
873 | } | |
874 | ||
875 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
876 | { | |
877 | return -ENOTSUPP; | |
878 | } | |
1cabe6b0 MG |
879 | #else |
880 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
881 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
882 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
883 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
884 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
885 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
886 | #endif |
887 | ||
58d52291 | 888 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
889 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
890 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
891 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
892 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
893 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
894 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
0952da79 SM |
895 | int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev, |
896 | bool enable_uc_lb); | |
1afff42c | 897 | |
cb67b832 HHZ |
898 | struct mlx5_eswitch_rep; |
899 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
900 | struct mlx5_eswitch_rep *rep); | |
901 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
902 | struct mlx5_eswitch_rep *rep); | |
903 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
904 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
905 | struct mlx5_eswitch_rep *rep); | |
906 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
907 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
908 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
f5f82476 | 909 | void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
370bad0f | 910 | void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv); |
cb67b832 HHZ |
911 | |
912 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
913 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
914 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
915 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
916 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
917 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
918 | int mlx5e_close(struct net_device *netdev); | |
919 | int mlx5e_open(struct net_device *netdev); | |
920 | void mlx5e_update_stats_work(struct work_struct *work); | |
26e59d80 MHY |
921 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
922 | const struct mlx5e_profile *profile, | |
923 | void *ppriv); | |
cb67b832 | 924 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); |
26e59d80 MHY |
925 | int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); |
926 | void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); | |
2b029556 | 927 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); |
4a25730e HHZ |
928 | void mlx5e_add_vxlan_port(struct net_device *netdev, |
929 | struct udp_tunnel_info *ti); | |
930 | void mlx5e_del_vxlan_port(struct net_device *netdev, | |
931 | struct udp_tunnel_info *ti); | |
cb67b832 | 932 | |
370bad0f OG |
933 | int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, |
934 | void *sp); | |
935 | bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id); | |
936 | ||
937 | bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv); | |
938 | bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv); | |
1afff42c | 939 | #endif /* __MLX5_EN_H__ */ |