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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
f62b8bb8 AV |
54 | #define MLX5E_MAX_NUM_TC 8 |
55 | ||
e842b100 | 56 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
57 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
58 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
59 | ||
e842b100 | 60 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
61 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
62 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
63 | ||
461017cb TT |
64 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
65 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4 | |
66 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 | |
67 | ||
461017cb | 68 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 TT |
69 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
70 | #define MLX5_MPWRQ_LOG_WQE_SZ 17 | |
461017cb TT |
71 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
72 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
73 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
74 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
75 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
bc77b240 TT |
76 | #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \ |
77 | BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW)) | |
78 | #define MLX5_UMR_ALIGN (2048) | |
461017cb TT |
79 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
80 | ||
d9a40271 | 81 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 | 82 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 83 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
84 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
85 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
86 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
87 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 88 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 89 | |
936896e9 AS |
90 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
91 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
92 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
507f0c81 | 93 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
94 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
95 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 96 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 97 | |
86d722ad | 98 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 99 | |
461017cb TT |
100 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
101 | { | |
102 | switch (wq_type) { | |
103 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
104 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
105 | wq_size / 2); | |
106 | default: | |
107 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
108 | wq_size / 2); | |
109 | } | |
110 | } | |
111 | ||
112 | static inline int mlx5_min_log_rq_size(int wq_type) | |
113 | { | |
114 | switch (wq_type) { | |
115 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
116 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
117 | default: | |
118 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
119 | } | |
120 | } | |
121 | ||
122 | static inline int mlx5_max_log_rq_size(int wq_type) | |
123 | { | |
124 | switch (wq_type) { | |
125 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
126 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
127 | default: | |
128 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
129 | } | |
130 | } | |
131 | ||
2f48af12 TT |
132 | struct mlx5e_tx_wqe { |
133 | struct mlx5_wqe_ctrl_seg ctrl; | |
134 | struct mlx5_wqe_eth_seg eth; | |
135 | }; | |
136 | ||
137 | struct mlx5e_rx_wqe { | |
138 | struct mlx5_wqe_srq_next_seg next; | |
139 | struct mlx5_wqe_data_seg data; | |
140 | }; | |
86d722ad | 141 | |
bc77b240 TT |
142 | struct mlx5e_umr_wqe { |
143 | struct mlx5_wqe_ctrl_seg ctrl; | |
144 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
145 | struct mlx5_mkey_seg mkc; | |
146 | struct mlx5_wqe_data_seg data; | |
147 | }; | |
148 | ||
4e59e288 | 149 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 150 | "rx_cqe_moder", |
4e59e288 GP |
151 | }; |
152 | ||
153 | enum mlx5e_priv_flag { | |
9908aa29 | 154 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
4e59e288 GP |
155 | }; |
156 | ||
157 | #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \ | |
158 | do { \ | |
159 | if (enable) \ | |
160 | priv->pflags |= pflag; \ | |
161 | else \ | |
162 | priv->pflags &= ~pflag; \ | |
163 | } while (0) | |
164 | ||
08fb1dac SM |
165 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
166 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
167 | #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */ | |
168 | #endif | |
169 | ||
9908aa29 TT |
170 | struct mlx5e_cq_moder { |
171 | u16 usec; | |
172 | u16 pkts; | |
173 | }; | |
174 | ||
f62b8bb8 AV |
175 | struct mlx5e_params { |
176 | u8 log_sq_size; | |
461017cb | 177 | u8 rq_wq_type; |
d9d9f156 TT |
178 | u8 mpwqe_log_stride_sz; |
179 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
180 | u8 log_rq_size; |
181 | u16 num_channels; | |
f62b8bb8 | 182 | u8 num_tc; |
9908aa29 | 183 | u8 rx_cq_period_mode; |
7219ab34 TT |
184 | bool rx_cqe_compress_admin; |
185 | bool rx_cqe_compress; | |
9908aa29 TT |
186 | struct mlx5e_cq_moder rx_cq_moderation; |
187 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 188 | u16 min_rx_wqes; |
f62b8bb8 AV |
189 | bool lro_en; |
190 | u32 lro_wqe_sz; | |
58d52291 | 191 | u16 tx_max_inline; |
2d75b2bc AS |
192 | u8 rss_hfunc; |
193 | u8 toeplitz_hash_key[40]; | |
194 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 195 | bool vlan_strip_disable; |
08fb1dac SM |
196 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
197 | struct ieee_ets ets; | |
198 | #endif | |
cb3c7fd4 | 199 | bool rx_am_enabled; |
f62b8bb8 AV |
200 | }; |
201 | ||
ef9814de EBE |
202 | struct mlx5e_tstamp { |
203 | rwlock_t lock; | |
204 | struct cyclecounter cycles; | |
205 | struct timecounter clock; | |
206 | struct hwtstamp_config hwtstamp_config; | |
207 | u32 nominal_c_mult; | |
208 | unsigned long overflow_period; | |
209 | struct delayed_work overflow_work; | |
210 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
211 | struct ptp_clock *ptp; |
212 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
213 | }; |
214 | ||
f62b8bb8 AV |
215 | enum { |
216 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
bc77b240 | 217 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 218 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
219 | }; |
220 | ||
f62b8bb8 AV |
221 | struct mlx5e_cq { |
222 | /* data path - accessed per cqe */ | |
223 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
224 | |
225 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 226 | u16 event_ctr; |
f62b8bb8 AV |
227 | struct napi_struct *napi; |
228 | struct mlx5_core_cq mcq; | |
229 | struct mlx5e_channel *channel; | |
50cfa25a | 230 | struct mlx5e_priv *priv; |
f62b8bb8 | 231 | |
7219ab34 TT |
232 | /* cqe decompression */ |
233 | struct mlx5_cqe64 title; | |
234 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
235 | u8 mini_arr_idx; | |
236 | u16 decmprs_left; | |
237 | u16 decmprs_wqe_counter; | |
238 | ||
f62b8bb8 AV |
239 | /* control */ |
240 | struct mlx5_wq_ctrl wq_ctrl; | |
241 | } ____cacheline_aligned_in_smp; | |
242 | ||
2f48af12 TT |
243 | struct mlx5e_rq; |
244 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
245 | struct mlx5_cqe64 *cqe); | |
246 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
247 | u16 ix); | |
248 | ||
461017cb TT |
249 | struct mlx5e_dma_info { |
250 | struct page *page; | |
251 | dma_addr_t addr; | |
252 | }; | |
253 | ||
cb3c7fd4 GR |
254 | struct mlx5e_rx_am_stats { |
255 | int ppms; /* packets per msec */ | |
256 | int epms; /* events per msec */ | |
257 | }; | |
258 | ||
259 | struct mlx5e_rx_am_sample { | |
260 | ktime_t time; | |
261 | unsigned int pkt_ctr; | |
262 | u16 event_ctr; | |
263 | }; | |
264 | ||
265 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
266 | u8 state; | |
267 | struct mlx5e_rx_am_stats prev_stats; | |
268 | struct mlx5e_rx_am_sample start_sample; | |
269 | struct work_struct work; | |
270 | u8 profile_ix; | |
271 | u8 mode; | |
272 | u8 tune_state; | |
273 | u8 steps_right; | |
274 | u8 steps_left; | |
275 | u8 tired; | |
276 | }; | |
277 | ||
f62b8bb8 AV |
278 | struct mlx5e_rq { |
279 | /* data path */ | |
280 | struct mlx5_wq_ll wq; | |
281 | u32 wqe_sz; | |
282 | struct sk_buff **skb; | |
461017cb | 283 | struct mlx5e_mpw_info *wqe_info; |
bc77b240 TT |
284 | __be32 mkey_be; |
285 | __be32 umr_mkey_be; | |
f62b8bb8 AV |
286 | |
287 | struct device *pdev; | |
288 | struct net_device *netdev; | |
ef9814de | 289 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
290 | struct mlx5e_rq_stats stats; |
291 | struct mlx5e_cq cq; | |
2f48af12 TT |
292 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
293 | mlx5e_fp_alloc_wqe alloc_wqe; | |
f62b8bb8 AV |
294 | |
295 | unsigned long state; | |
296 | int ix; | |
297 | ||
cb3c7fd4 GR |
298 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
299 | ||
f62b8bb8 AV |
300 | /* control */ |
301 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 302 | u8 wq_type; |
d9d9f156 TT |
303 | u32 mpwqe_stride_sz; |
304 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
305 | u32 rqn; |
306 | struct mlx5e_channel *channel; | |
50cfa25a | 307 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
308 | } ____cacheline_aligned_in_smp; |
309 | ||
bc77b240 TT |
310 | struct mlx5e_umr_dma_info { |
311 | __be64 *mtt; | |
312 | __be64 *mtt_no_align; | |
313 | dma_addr_t mtt_addr; | |
314 | struct mlx5e_dma_info *dma_info; | |
315 | }; | |
316 | ||
317 | struct mlx5e_mpw_info { | |
318 | union { | |
319 | struct mlx5e_dma_info dma_info; | |
320 | struct mlx5e_umr_dma_info umr; | |
321 | }; | |
322 | u16 consumed_strides; | |
323 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
324 | ||
325 | void (*dma_pre_sync)(struct device *pdev, | |
326 | struct mlx5e_mpw_info *wi, | |
327 | u32 wqe_offset, u32 len); | |
d9d9f156 | 328 | void (*add_skb_frag)(struct mlx5e_rq *rq, |
bc77b240 TT |
329 | struct sk_buff *skb, |
330 | struct mlx5e_mpw_info *wi, | |
331 | u32 page_idx, u32 frag_offset, u32 len); | |
332 | void (*copy_skb_header)(struct device *pdev, | |
333 | struct sk_buff *skb, | |
334 | struct mlx5e_mpw_info *wi, | |
335 | u32 page_idx, u32 offset, | |
336 | u32 headlen); | |
337 | void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
338 | }; | |
339 | ||
34802a42 | 340 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
341 | u32 num_bytes; |
342 | u8 num_wqebbs; | |
343 | u8 num_dma; | |
344 | }; | |
345 | ||
d4e28cbd AS |
346 | enum mlx5e_dma_map_type { |
347 | MLX5E_DMA_MAP_SINGLE, | |
348 | MLX5E_DMA_MAP_PAGE | |
349 | }; | |
350 | ||
f62b8bb8 | 351 | struct mlx5e_sq_dma { |
d4e28cbd AS |
352 | dma_addr_t addr; |
353 | u32 size; | |
354 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
355 | }; |
356 | ||
357 | enum { | |
358 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
0ba42241 | 359 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
360 | }; |
361 | ||
d3c9bc27 TT |
362 | struct mlx5e_ico_wqe_info { |
363 | u8 opcode; | |
364 | u8 num_wqebbs; | |
365 | }; | |
366 | ||
f62b8bb8 AV |
367 | struct mlx5e_sq { |
368 | /* data path */ | |
369 | ||
370 | /* dirtied @completion */ | |
371 | u16 cc; | |
372 | u32 dma_fifo_cc; | |
373 | ||
374 | /* dirtied @xmit */ | |
375 | u16 pc ____cacheline_aligned_in_smp; | |
376 | u32 dma_fifo_pc; | |
88a85f99 AS |
377 | u16 bf_offset; |
378 | u16 prev_cc; | |
379 | u8 bf_budget; | |
f62b8bb8 AV |
380 | struct mlx5e_sq_stats stats; |
381 | ||
382 | struct mlx5e_cq cq; | |
383 | ||
384 | /* pointers to per packet info: write@xmit, read@completion */ | |
385 | struct sk_buff **skb; | |
386 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 387 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
388 | |
389 | /* read only */ | |
390 | struct mlx5_wq_cyc wq; | |
391 | u32 dma_fifo_mask; | |
392 | void __iomem *uar_map; | |
393 | struct netdev_queue *txq; | |
394 | u32 sqn; | |
88a85f99 | 395 | u16 bf_buf_size; |
12be4b21 SM |
396 | u16 max_inline; |
397 | u16 edge; | |
f62b8bb8 | 398 | struct device *pdev; |
ef9814de | 399 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
400 | __be32 mkey_be; |
401 | unsigned long state; | |
402 | ||
403 | /* control path */ | |
404 | struct mlx5_wq_ctrl wq_ctrl; | |
405 | struct mlx5_uar uar; | |
406 | struct mlx5e_channel *channel; | |
407 | int tc; | |
d3c9bc27 | 408 | struct mlx5e_ico_wqe_info *ico_wqe_info; |
507f0c81 | 409 | u32 rate_limit; |
f62b8bb8 AV |
410 | } ____cacheline_aligned_in_smp; |
411 | ||
412 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
413 | { | |
414 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
415 | (sq->cc == sq->pc)); | |
416 | } | |
417 | ||
418 | enum channel_flags { | |
419 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
420 | }; | |
421 | ||
422 | struct mlx5e_channel { | |
423 | /* data path */ | |
424 | struct mlx5e_rq rq; | |
425 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
d3c9bc27 | 426 | struct mlx5e_sq icosq; /* internal control operations */ |
f62b8bb8 AV |
427 | struct napi_struct napi; |
428 | struct device *pdev; | |
429 | struct net_device *netdev; | |
430 | __be32 mkey_be; | |
431 | u8 num_tc; | |
432 | unsigned long flags; | |
433 | ||
434 | /* control */ | |
435 | struct mlx5e_priv *priv; | |
436 | int ix; | |
437 | int cpu; | |
438 | }; | |
439 | ||
440 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
441 | MLX5E_TT_IPV4_TCP, |
442 | MLX5E_TT_IPV6_TCP, | |
443 | MLX5E_TT_IPV4_UDP, | |
444 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
445 | MLX5E_TT_IPV4_IPSEC_AH, |
446 | MLX5E_TT_IPV6_IPSEC_AH, | |
447 | MLX5E_TT_IPV4_IPSEC_ESP, | |
448 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
449 | MLX5E_TT_IPV4, |
450 | MLX5E_TT_IPV6, | |
451 | MLX5E_TT_ANY, | |
452 | MLX5E_NUM_TT, | |
1da36696 | 453 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
454 | }; |
455 | ||
acff797c | 456 | enum { |
e0f46eb9 | 457 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
458 | MLX5E_STATE_OPENED, |
459 | MLX5E_STATE_DESTROYING, | |
460 | }; | |
461 | ||
462 | struct mlx5e_vxlan_db { | |
463 | spinlock_t lock; /* protect vxlan table */ | |
464 | struct radix_tree_root tree; | |
465 | }; | |
466 | ||
33cfaaa8 | 467 | struct mlx5e_l2_rule { |
f62b8bb8 | 468 | u8 addr[ETH_ALEN + 2]; |
33cfaaa8 | 469 | struct mlx5_flow_rule *rule; |
f62b8bb8 AV |
470 | }; |
471 | ||
acff797c MG |
472 | struct mlx5e_flow_table { |
473 | int num_groups; | |
474 | struct mlx5_flow_table *t; | |
475 | struct mlx5_flow_group **g; | |
476 | }; | |
477 | ||
33cfaaa8 | 478 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 479 | |
acff797c MG |
480 | struct mlx5e_tc_table { |
481 | struct mlx5_flow_table *t; | |
482 | ||
483 | struct rhashtable_params ht_params; | |
484 | struct rhashtable ht; | |
f62b8bb8 AV |
485 | }; |
486 | ||
acff797c MG |
487 | struct mlx5e_vlan_table { |
488 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 489 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
490 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
491 | struct mlx5_flow_rule *untagged_rule; | |
492 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
493 | bool filter_disabled; |
494 | }; | |
495 | ||
33cfaaa8 MG |
496 | struct mlx5e_l2_table { |
497 | struct mlx5e_flow_table ft; | |
498 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
499 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
500 | struct mlx5e_l2_rule broadcast; | |
501 | struct mlx5e_l2_rule allmulti; | |
502 | struct mlx5e_l2_rule promisc; | |
503 | bool broadcast_enabled; | |
504 | bool allmulti_enabled; | |
505 | bool promisc_enabled; | |
506 | }; | |
507 | ||
508 | /* L3/L4 traffic type classifier */ | |
509 | struct mlx5e_ttc_table { | |
510 | struct mlx5e_flow_table ft; | |
511 | struct mlx5_flow_rule *rules[MLX5E_NUM_TT]; | |
512 | }; | |
513 | ||
18c908e4 MG |
514 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
515 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
516 | struct arfs_table { |
517 | struct mlx5e_flow_table ft; | |
518 | struct mlx5_flow_rule *default_rule; | |
18c908e4 | 519 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
520 | }; |
521 | ||
522 | enum arfs_type { | |
523 | ARFS_IPV4_TCP, | |
524 | ARFS_IPV6_TCP, | |
525 | ARFS_IPV4_UDP, | |
526 | ARFS_IPV6_UDP, | |
527 | ARFS_NUM_TYPES, | |
528 | }; | |
529 | ||
530 | struct mlx5e_arfs_tables { | |
531 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
532 | /* Protect aRFS rules list */ |
533 | spinlock_t arfs_lock; | |
534 | struct list_head rules; | |
535 | int last_filter_id; | |
536 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
537 | }; |
538 | ||
539 | /* NIC prio FTS */ | |
540 | enum { | |
541 | MLX5E_VLAN_FT_LEVEL = 0, | |
542 | MLX5E_L2_FT_LEVEL, | |
543 | MLX5E_TTC_FT_LEVEL, | |
544 | MLX5E_ARFS_FT_LEVEL | |
545 | }; | |
546 | ||
6dc6071c MG |
547 | struct mlx5e_ethtool_table { |
548 | struct mlx5_flow_table *ft; | |
549 | int num_rules; | |
550 | }; | |
551 | ||
1174fce8 | 552 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
553 | #define ETHTOOL_NUM_L2_FTS 4 |
554 | ||
555 | struct mlx5e_ethtool_steering { | |
1174fce8 | 556 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
557 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
558 | struct list_head rules; | |
559 | int tot_num_rules; | |
560 | }; | |
561 | ||
acff797c MG |
562 | struct mlx5e_flow_steering { |
563 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 564 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
565 | struct mlx5e_tc_table tc; |
566 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
567 | struct mlx5e_l2_table l2; |
568 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 569 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
570 | }; |
571 | ||
398f3351 | 572 | struct mlx5e_rqt { |
1da36696 | 573 | u32 rqtn; |
398f3351 HHZ |
574 | bool enabled; |
575 | }; | |
576 | ||
577 | struct mlx5e_tir { | |
578 | u32 tirn; | |
579 | struct mlx5e_rqt rqt; | |
580 | struct list_head list; | |
1da36696 TT |
581 | }; |
582 | ||
acff797c MG |
583 | enum { |
584 | MLX5E_TC_PRIO = 0, | |
585 | MLX5E_NIC_PRIO | |
586 | }; | |
587 | ||
6bfd390b HHZ |
588 | struct mlx5e_profile { |
589 | void (*init)(struct mlx5_core_dev *mdev, | |
590 | struct net_device *netdev, | |
127ea380 | 591 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
592 | void (*cleanup)(struct mlx5e_priv *priv); |
593 | int (*init_rx)(struct mlx5e_priv *priv); | |
594 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
595 | int (*init_tx)(struct mlx5e_priv *priv); | |
596 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
597 | void (*enable)(struct mlx5e_priv *priv); | |
598 | void (*disable)(struct mlx5e_priv *priv); | |
599 | void (*update_stats)(struct mlx5e_priv *priv); | |
600 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
601 | int max_tc; | |
602 | }; | |
603 | ||
f62b8bb8 AV |
604 | struct mlx5e_priv { |
605 | /* priv data path fields - start */ | |
03289b88 | 606 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 607 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
608 | /* priv data path fields - end */ |
609 | ||
610 | unsigned long state; | |
611 | struct mutex state_lock; /* Protects Interface state */ | |
bc77b240 | 612 | struct mlx5_core_mkey umr_mkey; |
50cfa25a | 613 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
614 | |
615 | struct mlx5e_channel **channel; | |
616 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
398f3351 | 617 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
618 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
619 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 620 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 621 | |
acff797c | 622 | struct mlx5e_flow_steering fs; |
b3f63c3d | 623 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
624 | |
625 | struct mlx5e_params params; | |
7bb29755 | 626 | struct workqueue_struct *wq; |
f62b8bb8 AV |
627 | struct work_struct update_carrier_work; |
628 | struct work_struct set_rx_mode_work; | |
629 | struct delayed_work update_stats_work; | |
630 | ||
4e59e288 | 631 | u32 pflags; |
f62b8bb8 AV |
632 | struct mlx5_core_dev *mdev; |
633 | struct net_device *netdev; | |
634 | struct mlx5e_stats stats; | |
ef9814de | 635 | struct mlx5e_tstamp tstamp; |
593cf338 | 636 | u16 q_counter; |
6bfd390b | 637 | const struct mlx5e_profile *profile; |
127ea380 | 638 | void *ppriv; |
f62b8bb8 AV |
639 | }; |
640 | ||
f62b8bb8 AV |
641 | enum mlx5e_link_mode { |
642 | MLX5E_1000BASE_CX_SGMII = 0, | |
643 | MLX5E_1000BASE_KX = 1, | |
644 | MLX5E_10GBASE_CX4 = 2, | |
645 | MLX5E_10GBASE_KX4 = 3, | |
646 | MLX5E_10GBASE_KR = 4, | |
647 | MLX5E_20GBASE_KR2 = 5, | |
648 | MLX5E_40GBASE_CR4 = 6, | |
649 | MLX5E_40GBASE_KR4 = 7, | |
650 | MLX5E_56GBASE_R4 = 8, | |
651 | MLX5E_10GBASE_CR = 12, | |
652 | MLX5E_10GBASE_SR = 13, | |
653 | MLX5E_10GBASE_ER = 14, | |
654 | MLX5E_40GBASE_SR4 = 15, | |
655 | MLX5E_40GBASE_LR4 = 16, | |
4a50e35b | 656 | MLX5E_50GBASE_SR2 = 18, |
f62b8bb8 AV |
657 | MLX5E_100GBASE_CR4 = 20, |
658 | MLX5E_100GBASE_SR4 = 21, | |
659 | MLX5E_100GBASE_KR4 = 22, | |
660 | MLX5E_100GBASE_LR4 = 23, | |
661 | MLX5E_100BASE_TX = 24, | |
6e4c2189 | 662 | MLX5E_1000BASE_T = 25, |
f62b8bb8 AV |
663 | MLX5E_10GBASE_T = 26, |
664 | MLX5E_25GBASE_CR = 27, | |
665 | MLX5E_25GBASE_KR = 28, | |
666 | MLX5E_25GBASE_SR = 29, | |
667 | MLX5E_50GBASE_CR2 = 30, | |
668 | MLX5E_50GBASE_KR2 = 31, | |
669 | MLX5E_LINK_MODES_NUMBER, | |
670 | }; | |
671 | ||
672 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
673 | ||
665bc539 GP |
674 | |
675 | void mlx5e_build_ptys2ethtool_map(void); | |
676 | ||
12be4b21 | 677 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
678 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
679 | void *accel_priv, select_queue_fallback_t fallback); | |
680 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
681 | |
682 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
683 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
684 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 685 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 686 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
461017cb | 687 | |
2f48af12 | 688 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 689 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 690 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 691 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
461017cb | 692 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
bc77b240 TT |
693 | void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq); |
694 | void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
695 | struct mlx5_cqe64 *cqe, | |
696 | u16 byte_cnt, | |
697 | struct mlx5e_mpw_info *wi, | |
698 | struct sk_buff *skb); | |
699 | void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
700 | struct mlx5_cqe64 *cqe, | |
701 | u16 byte_cnt, | |
702 | struct mlx5e_mpw_info *wi, | |
703 | struct sk_buff *skb); | |
704 | void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
705 | struct mlx5e_mpw_info *wi); | |
706 | void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
707 | struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
708 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
709 | ||
cb3c7fd4 GR |
710 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
711 | void mlx5e_rx_am_work(struct work_struct *work); | |
712 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
713 | ||
f62b8bb8 AV |
714 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
715 | ||
acff797c MG |
716 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
717 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 718 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 719 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
6dc6071c MG |
720 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
721 | struct ethtool_rx_flow_spec *fs); | |
722 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
723 | int location); | |
724 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
725 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
726 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
727 | ||
ef9814de EBE |
728 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
729 | struct skb_shared_hwtstamps *hwts); | |
730 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
731 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
732 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
733 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 734 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 735 | |
f62b8bb8 AV |
736 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
737 | u16 vid); | |
738 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
739 | u16 vid); | |
740 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
741 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 742 | |
36350114 GP |
743 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
744 | ||
1da36696 | 745 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 746 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 747 | |
f62b8bb8 AV |
748 | int mlx5e_open_locked(struct net_device *netdev); |
749 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
750 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
751 | u32 *indirection_rqt, int len, | |
85082dba | 752 | int num_channels); |
b797a684 | 753 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 754 | |
9908aa29 TT |
755 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
756 | u8 cq_period_mode); | |
757 | ||
f62b8bb8 | 758 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
bc77b240 | 759 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 760 | { |
88a85f99 AS |
761 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
762 | ||
f62b8bb8 AV |
763 | /* ensure wqe is visible to device before updating doorbell record */ |
764 | dma_wmb(); | |
765 | ||
766 | *sq->wq.db = cpu_to_be32(sq->pc); | |
767 | ||
768 | /* ensure doorbell record is visible to device before ringing the | |
769 | * doorbell | |
770 | */ | |
771 | wmb(); | |
0ba42241 | 772 | if (bf_sz) |
bc77b240 | 773 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 774 | else |
bc77b240 | 775 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
776 | /* flush the write-combining mapped buffer */ |
777 | wmb(); | |
f62b8bb8 AV |
778 | |
779 | sq->bf_offset ^= sq->bf_buf_size; | |
780 | } | |
781 | ||
782 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
783 | { | |
784 | struct mlx5_core_cq *mcq; | |
785 | ||
786 | mcq = &cq->mcq; | |
787 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
788 | } | |
789 | ||
3435ab59 AS |
790 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
791 | { | |
792 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
793 | MLX5E_MAX_NUM_CHANNELS); | |
794 | } | |
795 | ||
bc77b240 TT |
796 | static inline int mlx5e_get_mtt_octw(int npages) |
797 | { | |
798 | return ALIGN(npages, 8) / 2; | |
799 | } | |
800 | ||
f62b8bb8 | 801 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
802 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
803 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
804 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
805 | #endif | |
806 | ||
1cabe6b0 MG |
807 | #ifndef CONFIG_RFS_ACCEL |
808 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
809 | { | |
810 | return 0; | |
811 | } | |
812 | ||
813 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
814 | |
815 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
816 | { | |
817 | return -ENOTSUPP; | |
818 | } | |
819 | ||
820 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
821 | { | |
822 | return -ENOTSUPP; | |
823 | } | |
1cabe6b0 MG |
824 | #else |
825 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
826 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
827 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
828 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
829 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
830 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
831 | #endif |
832 | ||
58d52291 | 833 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
834 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
835 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
836 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
837 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
838 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
839 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
724b2aa1 | 840 | int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev); |
1afff42c | 841 | |
cb67b832 HHZ |
842 | struct mlx5_eswitch_rep; |
843 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
844 | struct mlx5_eswitch_rep *rep); | |
845 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
846 | struct mlx5_eswitch_rep *rep); | |
847 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
848 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
849 | struct mlx5_eswitch_rep *rep); | |
850 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
851 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
852 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
853 | ||
854 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
855 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
856 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
857 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
858 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
859 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
860 | int mlx5e_close(struct net_device *netdev); | |
861 | int mlx5e_open(struct net_device *netdev); | |
862 | void mlx5e_update_stats_work(struct work_struct *work); | |
863 | void *mlx5e_create_netdev(struct mlx5_core_dev *mdev, | |
864 | const struct mlx5e_profile *profile, void *ppriv); | |
865 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); | |
866 | struct rtnl_link_stats64 * | |
867 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); | |
868 | ||
1afff42c | 869 | #endif /* __MLX5_EN_H__ */ |