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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
f62b8bb8 | 47 | #include "wq.h" |
f62b8bb8 | 48 | #include "mlx5_core.h" |
9218b44d | 49 | #include "en_stats.h" |
f62b8bb8 | 50 | |
1cabe6b0 MG |
51 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
52 | ||
f62b8bb8 AV |
53 | #define MLX5E_MAX_NUM_TC 8 |
54 | ||
e842b100 | 55 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
56 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
57 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
58 | ||
e842b100 | 59 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
60 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
61 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
62 | ||
461017cb TT |
63 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
64 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4 | |
65 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 | |
66 | ||
461017cb | 67 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 TT |
68 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
69 | #define MLX5_MPWRQ_LOG_WQE_SZ 17 | |
461017cb TT |
70 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
71 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
72 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
73 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
74 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
bc77b240 TT |
75 | #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \ |
76 | BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW)) | |
77 | #define MLX5_UMR_ALIGN (2048) | |
461017cb TT |
78 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
79 | ||
d9a40271 | 80 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 | 81 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 82 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
83 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
84 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
85 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
86 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 87 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 88 | |
936896e9 AS |
89 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
90 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
91 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
507f0c81 | 92 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
93 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
94 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 95 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 96 | |
86d722ad | 97 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 98 | |
461017cb TT |
99 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
100 | { | |
101 | switch (wq_type) { | |
102 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
103 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
104 | wq_size / 2); | |
105 | default: | |
106 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
107 | wq_size / 2); | |
108 | } | |
109 | } | |
110 | ||
111 | static inline int mlx5_min_log_rq_size(int wq_type) | |
112 | { | |
113 | switch (wq_type) { | |
114 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
115 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
116 | default: | |
117 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
118 | } | |
119 | } | |
120 | ||
121 | static inline int mlx5_max_log_rq_size(int wq_type) | |
122 | { | |
123 | switch (wq_type) { | |
124 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
125 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
126 | default: | |
127 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
128 | } | |
129 | } | |
130 | ||
2f48af12 TT |
131 | struct mlx5e_tx_wqe { |
132 | struct mlx5_wqe_ctrl_seg ctrl; | |
133 | struct mlx5_wqe_eth_seg eth; | |
134 | }; | |
135 | ||
136 | struct mlx5e_rx_wqe { | |
137 | struct mlx5_wqe_srq_next_seg next; | |
138 | struct mlx5_wqe_data_seg data; | |
139 | }; | |
86d722ad | 140 | |
bc77b240 TT |
141 | struct mlx5e_umr_wqe { |
142 | struct mlx5_wqe_ctrl_seg ctrl; | |
143 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
144 | struct mlx5_mkey_seg mkc; | |
145 | struct mlx5_wqe_data_seg data; | |
146 | }; | |
147 | ||
4e59e288 | 148 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 149 | "rx_cqe_moder", |
4e59e288 GP |
150 | }; |
151 | ||
152 | enum mlx5e_priv_flag { | |
9908aa29 | 153 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
4e59e288 GP |
154 | }; |
155 | ||
156 | #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \ | |
157 | do { \ | |
158 | if (enable) \ | |
159 | priv->pflags |= pflag; \ | |
160 | else \ | |
161 | priv->pflags &= ~pflag; \ | |
162 | } while (0) | |
163 | ||
08fb1dac SM |
164 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
165 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
166 | #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */ | |
167 | #endif | |
168 | ||
9908aa29 TT |
169 | struct mlx5e_cq_moder { |
170 | u16 usec; | |
171 | u16 pkts; | |
172 | }; | |
173 | ||
f62b8bb8 AV |
174 | struct mlx5e_params { |
175 | u8 log_sq_size; | |
461017cb | 176 | u8 rq_wq_type; |
d9d9f156 TT |
177 | u8 mpwqe_log_stride_sz; |
178 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
179 | u8 log_rq_size; |
180 | u16 num_channels; | |
f62b8bb8 | 181 | u8 num_tc; |
9908aa29 | 182 | u8 rx_cq_period_mode; |
7219ab34 TT |
183 | bool rx_cqe_compress_admin; |
184 | bool rx_cqe_compress; | |
9908aa29 TT |
185 | struct mlx5e_cq_moder rx_cq_moderation; |
186 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 187 | u16 min_rx_wqes; |
f62b8bb8 AV |
188 | bool lro_en; |
189 | u32 lro_wqe_sz; | |
58d52291 | 190 | u16 tx_max_inline; |
2d75b2bc AS |
191 | u8 rss_hfunc; |
192 | u8 toeplitz_hash_key[40]; | |
193 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 194 | bool vlan_strip_disable; |
08fb1dac SM |
195 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
196 | struct ieee_ets ets; | |
197 | #endif | |
cb3c7fd4 | 198 | bool rx_am_enabled; |
f62b8bb8 AV |
199 | }; |
200 | ||
ef9814de EBE |
201 | struct mlx5e_tstamp { |
202 | rwlock_t lock; | |
203 | struct cyclecounter cycles; | |
204 | struct timecounter clock; | |
205 | struct hwtstamp_config hwtstamp_config; | |
206 | u32 nominal_c_mult; | |
207 | unsigned long overflow_period; | |
208 | struct delayed_work overflow_work; | |
209 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
210 | struct ptp_clock *ptp; |
211 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
212 | }; |
213 | ||
f62b8bb8 AV |
214 | enum { |
215 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
bc77b240 | 216 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 217 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
218 | }; |
219 | ||
f62b8bb8 AV |
220 | struct mlx5e_cq { |
221 | /* data path - accessed per cqe */ | |
222 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
223 | |
224 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 225 | u16 event_ctr; |
f62b8bb8 AV |
226 | struct napi_struct *napi; |
227 | struct mlx5_core_cq mcq; | |
228 | struct mlx5e_channel *channel; | |
50cfa25a | 229 | struct mlx5e_priv *priv; |
f62b8bb8 | 230 | |
7219ab34 TT |
231 | /* cqe decompression */ |
232 | struct mlx5_cqe64 title; | |
233 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
234 | u8 mini_arr_idx; | |
235 | u16 decmprs_left; | |
236 | u16 decmprs_wqe_counter; | |
237 | ||
f62b8bb8 AV |
238 | /* control */ |
239 | struct mlx5_wq_ctrl wq_ctrl; | |
240 | } ____cacheline_aligned_in_smp; | |
241 | ||
2f48af12 TT |
242 | struct mlx5e_rq; |
243 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
244 | struct mlx5_cqe64 *cqe); | |
245 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
246 | u16 ix); | |
247 | ||
461017cb TT |
248 | struct mlx5e_dma_info { |
249 | struct page *page; | |
250 | dma_addr_t addr; | |
251 | }; | |
252 | ||
cb3c7fd4 GR |
253 | struct mlx5e_rx_am_stats { |
254 | int ppms; /* packets per msec */ | |
255 | int epms; /* events per msec */ | |
256 | }; | |
257 | ||
258 | struct mlx5e_rx_am_sample { | |
259 | ktime_t time; | |
260 | unsigned int pkt_ctr; | |
261 | u16 event_ctr; | |
262 | }; | |
263 | ||
264 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
265 | u8 state; | |
266 | struct mlx5e_rx_am_stats prev_stats; | |
267 | struct mlx5e_rx_am_sample start_sample; | |
268 | struct work_struct work; | |
269 | u8 profile_ix; | |
270 | u8 mode; | |
271 | u8 tune_state; | |
272 | u8 steps_right; | |
273 | u8 steps_left; | |
274 | u8 tired; | |
275 | }; | |
276 | ||
f62b8bb8 AV |
277 | struct mlx5e_rq { |
278 | /* data path */ | |
279 | struct mlx5_wq_ll wq; | |
280 | u32 wqe_sz; | |
281 | struct sk_buff **skb; | |
461017cb | 282 | struct mlx5e_mpw_info *wqe_info; |
bc77b240 TT |
283 | __be32 mkey_be; |
284 | __be32 umr_mkey_be; | |
f62b8bb8 AV |
285 | |
286 | struct device *pdev; | |
287 | struct net_device *netdev; | |
ef9814de | 288 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
289 | struct mlx5e_rq_stats stats; |
290 | struct mlx5e_cq cq; | |
2f48af12 TT |
291 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
292 | mlx5e_fp_alloc_wqe alloc_wqe; | |
f62b8bb8 AV |
293 | |
294 | unsigned long state; | |
295 | int ix; | |
296 | ||
cb3c7fd4 GR |
297 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
298 | ||
f62b8bb8 AV |
299 | /* control */ |
300 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 301 | u8 wq_type; |
d9d9f156 TT |
302 | u32 mpwqe_stride_sz; |
303 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
304 | u32 rqn; |
305 | struct mlx5e_channel *channel; | |
50cfa25a | 306 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
307 | } ____cacheline_aligned_in_smp; |
308 | ||
bc77b240 TT |
309 | struct mlx5e_umr_dma_info { |
310 | __be64 *mtt; | |
311 | __be64 *mtt_no_align; | |
312 | dma_addr_t mtt_addr; | |
313 | struct mlx5e_dma_info *dma_info; | |
314 | }; | |
315 | ||
316 | struct mlx5e_mpw_info { | |
317 | union { | |
318 | struct mlx5e_dma_info dma_info; | |
319 | struct mlx5e_umr_dma_info umr; | |
320 | }; | |
321 | u16 consumed_strides; | |
322 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
323 | ||
324 | void (*dma_pre_sync)(struct device *pdev, | |
325 | struct mlx5e_mpw_info *wi, | |
326 | u32 wqe_offset, u32 len); | |
d9d9f156 | 327 | void (*add_skb_frag)(struct mlx5e_rq *rq, |
bc77b240 TT |
328 | struct sk_buff *skb, |
329 | struct mlx5e_mpw_info *wi, | |
330 | u32 page_idx, u32 frag_offset, u32 len); | |
331 | void (*copy_skb_header)(struct device *pdev, | |
332 | struct sk_buff *skb, | |
333 | struct mlx5e_mpw_info *wi, | |
334 | u32 page_idx, u32 offset, | |
335 | u32 headlen); | |
336 | void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
337 | }; | |
338 | ||
34802a42 | 339 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
340 | u32 num_bytes; |
341 | u8 num_wqebbs; | |
342 | u8 num_dma; | |
343 | }; | |
344 | ||
d4e28cbd AS |
345 | enum mlx5e_dma_map_type { |
346 | MLX5E_DMA_MAP_SINGLE, | |
347 | MLX5E_DMA_MAP_PAGE | |
348 | }; | |
349 | ||
f62b8bb8 | 350 | struct mlx5e_sq_dma { |
d4e28cbd AS |
351 | dma_addr_t addr; |
352 | u32 size; | |
353 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
354 | }; |
355 | ||
356 | enum { | |
357 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
0ba42241 | 358 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
359 | }; |
360 | ||
d3c9bc27 TT |
361 | struct mlx5e_ico_wqe_info { |
362 | u8 opcode; | |
363 | u8 num_wqebbs; | |
364 | }; | |
365 | ||
f62b8bb8 AV |
366 | struct mlx5e_sq { |
367 | /* data path */ | |
368 | ||
369 | /* dirtied @completion */ | |
370 | u16 cc; | |
371 | u32 dma_fifo_cc; | |
372 | ||
373 | /* dirtied @xmit */ | |
374 | u16 pc ____cacheline_aligned_in_smp; | |
375 | u32 dma_fifo_pc; | |
88a85f99 AS |
376 | u16 bf_offset; |
377 | u16 prev_cc; | |
378 | u8 bf_budget; | |
f62b8bb8 AV |
379 | struct mlx5e_sq_stats stats; |
380 | ||
381 | struct mlx5e_cq cq; | |
382 | ||
383 | /* pointers to per packet info: write@xmit, read@completion */ | |
384 | struct sk_buff **skb; | |
385 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 386 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
387 | |
388 | /* read only */ | |
389 | struct mlx5_wq_cyc wq; | |
390 | u32 dma_fifo_mask; | |
391 | void __iomem *uar_map; | |
392 | struct netdev_queue *txq; | |
393 | u32 sqn; | |
88a85f99 | 394 | u16 bf_buf_size; |
12be4b21 SM |
395 | u16 max_inline; |
396 | u16 edge; | |
f62b8bb8 | 397 | struct device *pdev; |
ef9814de | 398 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
399 | __be32 mkey_be; |
400 | unsigned long state; | |
401 | ||
402 | /* control path */ | |
403 | struct mlx5_wq_ctrl wq_ctrl; | |
404 | struct mlx5_uar uar; | |
405 | struct mlx5e_channel *channel; | |
406 | int tc; | |
d3c9bc27 | 407 | struct mlx5e_ico_wqe_info *ico_wqe_info; |
507f0c81 | 408 | u32 rate_limit; |
f62b8bb8 AV |
409 | } ____cacheline_aligned_in_smp; |
410 | ||
411 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
412 | { | |
413 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
414 | (sq->cc == sq->pc)); | |
415 | } | |
416 | ||
417 | enum channel_flags { | |
418 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
419 | }; | |
420 | ||
421 | struct mlx5e_channel { | |
422 | /* data path */ | |
423 | struct mlx5e_rq rq; | |
424 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
d3c9bc27 | 425 | struct mlx5e_sq icosq; /* internal control operations */ |
f62b8bb8 AV |
426 | struct napi_struct napi; |
427 | struct device *pdev; | |
428 | struct net_device *netdev; | |
429 | __be32 mkey_be; | |
430 | u8 num_tc; | |
431 | unsigned long flags; | |
432 | ||
433 | /* control */ | |
434 | struct mlx5e_priv *priv; | |
435 | int ix; | |
436 | int cpu; | |
437 | }; | |
438 | ||
439 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
440 | MLX5E_TT_IPV4_TCP, |
441 | MLX5E_TT_IPV6_TCP, | |
442 | MLX5E_TT_IPV4_UDP, | |
443 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
444 | MLX5E_TT_IPV4_IPSEC_AH, |
445 | MLX5E_TT_IPV6_IPSEC_AH, | |
446 | MLX5E_TT_IPV4_IPSEC_ESP, | |
447 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
448 | MLX5E_TT_IPV4, |
449 | MLX5E_TT_IPV6, | |
450 | MLX5E_TT_ANY, | |
451 | MLX5E_NUM_TT, | |
1da36696 | 452 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
453 | }; |
454 | ||
acff797c | 455 | enum { |
e0f46eb9 | 456 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
457 | MLX5E_STATE_OPENED, |
458 | MLX5E_STATE_DESTROYING, | |
459 | }; | |
460 | ||
461 | struct mlx5e_vxlan_db { | |
462 | spinlock_t lock; /* protect vxlan table */ | |
463 | struct radix_tree_root tree; | |
464 | }; | |
465 | ||
33cfaaa8 | 466 | struct mlx5e_l2_rule { |
f62b8bb8 | 467 | u8 addr[ETH_ALEN + 2]; |
33cfaaa8 | 468 | struct mlx5_flow_rule *rule; |
f62b8bb8 AV |
469 | }; |
470 | ||
acff797c MG |
471 | struct mlx5e_flow_table { |
472 | int num_groups; | |
473 | struct mlx5_flow_table *t; | |
474 | struct mlx5_flow_group **g; | |
475 | }; | |
476 | ||
33cfaaa8 | 477 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 478 | |
acff797c MG |
479 | struct mlx5e_tc_table { |
480 | struct mlx5_flow_table *t; | |
481 | ||
482 | struct rhashtable_params ht_params; | |
483 | struct rhashtable ht; | |
f62b8bb8 AV |
484 | }; |
485 | ||
acff797c MG |
486 | struct mlx5e_vlan_table { |
487 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 488 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
489 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
490 | struct mlx5_flow_rule *untagged_rule; | |
491 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
492 | bool filter_disabled; |
493 | }; | |
494 | ||
33cfaaa8 MG |
495 | struct mlx5e_l2_table { |
496 | struct mlx5e_flow_table ft; | |
497 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
498 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
499 | struct mlx5e_l2_rule broadcast; | |
500 | struct mlx5e_l2_rule allmulti; | |
501 | struct mlx5e_l2_rule promisc; | |
502 | bool broadcast_enabled; | |
503 | bool allmulti_enabled; | |
504 | bool promisc_enabled; | |
505 | }; | |
506 | ||
507 | /* L3/L4 traffic type classifier */ | |
508 | struct mlx5e_ttc_table { | |
509 | struct mlx5e_flow_table ft; | |
510 | struct mlx5_flow_rule *rules[MLX5E_NUM_TT]; | |
511 | }; | |
512 | ||
18c908e4 MG |
513 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
514 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
515 | struct arfs_table { |
516 | struct mlx5e_flow_table ft; | |
517 | struct mlx5_flow_rule *default_rule; | |
18c908e4 | 518 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
519 | }; |
520 | ||
521 | enum arfs_type { | |
522 | ARFS_IPV4_TCP, | |
523 | ARFS_IPV6_TCP, | |
524 | ARFS_IPV4_UDP, | |
525 | ARFS_IPV6_UDP, | |
526 | ARFS_NUM_TYPES, | |
527 | }; | |
528 | ||
529 | struct mlx5e_arfs_tables { | |
530 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
531 | /* Protect aRFS rules list */ |
532 | spinlock_t arfs_lock; | |
533 | struct list_head rules; | |
534 | int last_filter_id; | |
535 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
536 | }; |
537 | ||
538 | /* NIC prio FTS */ | |
539 | enum { | |
540 | MLX5E_VLAN_FT_LEVEL = 0, | |
541 | MLX5E_L2_FT_LEVEL, | |
542 | MLX5E_TTC_FT_LEVEL, | |
543 | MLX5E_ARFS_FT_LEVEL | |
544 | }; | |
545 | ||
acff797c MG |
546 | struct mlx5e_flow_steering { |
547 | struct mlx5_flow_namespace *ns; | |
548 | struct mlx5e_tc_table tc; | |
549 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
550 | struct mlx5e_l2_table l2; |
551 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 552 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
553 | }; |
554 | ||
398f3351 | 555 | struct mlx5e_rqt { |
1da36696 | 556 | u32 rqtn; |
398f3351 HHZ |
557 | bool enabled; |
558 | }; | |
559 | ||
560 | struct mlx5e_tir { | |
561 | u32 tirn; | |
562 | struct mlx5e_rqt rqt; | |
563 | struct list_head list; | |
1da36696 TT |
564 | }; |
565 | ||
acff797c MG |
566 | enum { |
567 | MLX5E_TC_PRIO = 0, | |
568 | MLX5E_NIC_PRIO | |
569 | }; | |
570 | ||
6bfd390b HHZ |
571 | struct mlx5e_profile { |
572 | void (*init)(struct mlx5_core_dev *mdev, | |
573 | struct net_device *netdev, | |
127ea380 | 574 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
575 | void (*cleanup)(struct mlx5e_priv *priv); |
576 | int (*init_rx)(struct mlx5e_priv *priv); | |
577 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
578 | int (*init_tx)(struct mlx5e_priv *priv); | |
579 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
580 | void (*enable)(struct mlx5e_priv *priv); | |
581 | void (*disable)(struct mlx5e_priv *priv); | |
582 | void (*update_stats)(struct mlx5e_priv *priv); | |
583 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
584 | int max_tc; | |
585 | }; | |
586 | ||
f62b8bb8 AV |
587 | struct mlx5e_priv { |
588 | /* priv data path fields - start */ | |
03289b88 | 589 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 590 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
591 | /* priv data path fields - end */ |
592 | ||
593 | unsigned long state; | |
594 | struct mutex state_lock; /* Protects Interface state */ | |
bc77b240 | 595 | struct mlx5_core_mkey umr_mkey; |
50cfa25a | 596 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
597 | |
598 | struct mlx5e_channel **channel; | |
599 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
398f3351 | 600 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
601 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
602 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 603 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 604 | |
acff797c | 605 | struct mlx5e_flow_steering fs; |
b3f63c3d | 606 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
607 | |
608 | struct mlx5e_params params; | |
7bb29755 | 609 | struct workqueue_struct *wq; |
f62b8bb8 AV |
610 | struct work_struct update_carrier_work; |
611 | struct work_struct set_rx_mode_work; | |
612 | struct delayed_work update_stats_work; | |
613 | ||
4e59e288 | 614 | u32 pflags; |
f62b8bb8 AV |
615 | struct mlx5_core_dev *mdev; |
616 | struct net_device *netdev; | |
617 | struct mlx5e_stats stats; | |
ef9814de | 618 | struct mlx5e_tstamp tstamp; |
593cf338 | 619 | u16 q_counter; |
6bfd390b | 620 | const struct mlx5e_profile *profile; |
127ea380 | 621 | void *ppriv; |
f62b8bb8 AV |
622 | }; |
623 | ||
f62b8bb8 AV |
624 | enum mlx5e_link_mode { |
625 | MLX5E_1000BASE_CX_SGMII = 0, | |
626 | MLX5E_1000BASE_KX = 1, | |
627 | MLX5E_10GBASE_CX4 = 2, | |
628 | MLX5E_10GBASE_KX4 = 3, | |
629 | MLX5E_10GBASE_KR = 4, | |
630 | MLX5E_20GBASE_KR2 = 5, | |
631 | MLX5E_40GBASE_CR4 = 6, | |
632 | MLX5E_40GBASE_KR4 = 7, | |
633 | MLX5E_56GBASE_R4 = 8, | |
634 | MLX5E_10GBASE_CR = 12, | |
635 | MLX5E_10GBASE_SR = 13, | |
636 | MLX5E_10GBASE_ER = 14, | |
637 | MLX5E_40GBASE_SR4 = 15, | |
638 | MLX5E_40GBASE_LR4 = 16, | |
4a50e35b | 639 | MLX5E_50GBASE_SR2 = 18, |
f62b8bb8 AV |
640 | MLX5E_100GBASE_CR4 = 20, |
641 | MLX5E_100GBASE_SR4 = 21, | |
642 | MLX5E_100GBASE_KR4 = 22, | |
643 | MLX5E_100GBASE_LR4 = 23, | |
644 | MLX5E_100BASE_TX = 24, | |
6e4c2189 | 645 | MLX5E_1000BASE_T = 25, |
f62b8bb8 AV |
646 | MLX5E_10GBASE_T = 26, |
647 | MLX5E_25GBASE_CR = 27, | |
648 | MLX5E_25GBASE_KR = 28, | |
649 | MLX5E_25GBASE_SR = 29, | |
650 | MLX5E_50GBASE_CR2 = 30, | |
651 | MLX5E_50GBASE_KR2 = 31, | |
652 | MLX5E_LINK_MODES_NUMBER, | |
653 | }; | |
654 | ||
655 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
656 | ||
665bc539 GP |
657 | |
658 | void mlx5e_build_ptys2ethtool_map(void); | |
659 | ||
12be4b21 | 660 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
661 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
662 | void *accel_priv, select_queue_fallback_t fallback); | |
663 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
664 | |
665 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
666 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
667 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 668 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 669 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
461017cb | 670 | |
2f48af12 | 671 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 672 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 673 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 674 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
461017cb | 675 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
bc77b240 TT |
676 | void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq); |
677 | void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
678 | struct mlx5_cqe64 *cqe, | |
679 | u16 byte_cnt, | |
680 | struct mlx5e_mpw_info *wi, | |
681 | struct sk_buff *skb); | |
682 | void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
683 | struct mlx5_cqe64 *cqe, | |
684 | u16 byte_cnt, | |
685 | struct mlx5e_mpw_info *wi, | |
686 | struct sk_buff *skb); | |
687 | void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
688 | struct mlx5e_mpw_info *wi); | |
689 | void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
690 | struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
691 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
692 | ||
cb3c7fd4 GR |
693 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
694 | void mlx5e_rx_am_work(struct work_struct *work); | |
695 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
696 | ||
f62b8bb8 AV |
697 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
698 | ||
acff797c MG |
699 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
700 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 701 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 702 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
f62b8bb8 AV |
703 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
704 | ||
ef9814de EBE |
705 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
706 | struct skb_shared_hwtstamps *hwts); | |
707 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
708 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
709 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
710 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 711 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 712 | |
f62b8bb8 AV |
713 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
714 | u16 vid); | |
715 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
716 | u16 vid); | |
717 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
718 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 719 | |
36350114 GP |
720 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
721 | ||
1da36696 | 722 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 723 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 724 | |
f62b8bb8 AV |
725 | int mlx5e_open_locked(struct net_device *netdev); |
726 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
727 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
728 | u32 *indirection_rqt, int len, | |
85082dba | 729 | int num_channels); |
b797a684 | 730 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 731 | |
9908aa29 TT |
732 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
733 | u8 cq_period_mode); | |
734 | ||
f62b8bb8 | 735 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
bc77b240 | 736 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 737 | { |
88a85f99 AS |
738 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
739 | ||
f62b8bb8 AV |
740 | /* ensure wqe is visible to device before updating doorbell record */ |
741 | dma_wmb(); | |
742 | ||
743 | *sq->wq.db = cpu_to_be32(sq->pc); | |
744 | ||
745 | /* ensure doorbell record is visible to device before ringing the | |
746 | * doorbell | |
747 | */ | |
748 | wmb(); | |
0ba42241 | 749 | if (bf_sz) |
bc77b240 | 750 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 751 | else |
bc77b240 | 752 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
753 | /* flush the write-combining mapped buffer */ |
754 | wmb(); | |
f62b8bb8 AV |
755 | |
756 | sq->bf_offset ^= sq->bf_buf_size; | |
757 | } | |
758 | ||
759 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
760 | { | |
761 | struct mlx5_core_cq *mcq; | |
762 | ||
763 | mcq = &cq->mcq; | |
764 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
765 | } | |
766 | ||
3435ab59 AS |
767 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
768 | { | |
769 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
770 | MLX5E_MAX_NUM_CHANNELS); | |
771 | } | |
772 | ||
bc77b240 TT |
773 | static inline int mlx5e_get_mtt_octw(int npages) |
774 | { | |
775 | return ALIGN(npages, 8) / 2; | |
776 | } | |
777 | ||
f62b8bb8 | 778 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
779 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
780 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
781 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
782 | #endif | |
783 | ||
1cabe6b0 MG |
784 | #ifndef CONFIG_RFS_ACCEL |
785 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
786 | { | |
787 | return 0; | |
788 | } | |
789 | ||
790 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
791 | |
792 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
793 | { | |
794 | return -ENOTSUPP; | |
795 | } | |
796 | ||
797 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
798 | { | |
799 | return -ENOTSUPP; | |
800 | } | |
1cabe6b0 MG |
801 | #else |
802 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
803 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
804 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
805 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
806 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
807 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
808 | #endif |
809 | ||
58d52291 | 810 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
811 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
812 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
813 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
814 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
815 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
816 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
724b2aa1 | 817 | int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev); |
1afff42c MF |
818 | |
819 | #endif /* __MLX5_EN_H__ */ |