]>
Commit | Line | Data |
---|---|---|
f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
f62b8bb8 AV |
54 | #define MLX5E_MAX_NUM_TC 8 |
55 | ||
e842b100 | 56 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
57 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
58 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
59 | ||
e842b100 | 60 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
61 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
62 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
63 | ||
461017cb | 64 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 65 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
66 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
67 | ||
1bfecfca SM |
68 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
69 | ||
461017cb | 70 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 | 71 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
7e426671 | 72 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
73 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
74 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
75 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
76 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
77 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
78 | |
79 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
ec8b9981 TT |
80 | #define MLX5E_REQUIRED_MTTS(wqes) \ |
81 | (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
82 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) | |
fe4c988b | 83 | |
bc77b240 | 84 | #define MLX5_UMR_ALIGN (2048) |
461017cb TT |
85 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
86 | ||
d9a40271 | 87 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
88 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
89 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
90 | ||
f62b8bb8 | 91 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 92 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
93 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
94 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
95 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
96 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 97 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 98 | |
936896e9 AS |
99 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
100 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
101 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
507f0c81 | 102 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
103 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
104 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 105 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 106 | |
f10b7cc7 SM |
107 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
108 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
109 | ||
b5503b99 SM |
110 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
111 | #define MLX5E_XDP_IHS_DS_COUNT \ | |
112 | DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS) | |
113 | #define MLX5E_XDP_TX_DS_COUNT \ | |
114 | (MLX5E_XDP_IHS_DS_COUNT + \ | |
115 | (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) | |
116 | #define MLX5E_XDP_TX_WQEBBS \ | |
117 | DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS) | |
118 | ||
86d722ad | 119 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 120 | |
461017cb TT |
121 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
122 | { | |
123 | switch (wq_type) { | |
124 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
125 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
126 | wq_size / 2); | |
127 | default: | |
128 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
129 | wq_size / 2); | |
130 | } | |
131 | } | |
132 | ||
133 | static inline int mlx5_min_log_rq_size(int wq_type) | |
134 | { | |
135 | switch (wq_type) { | |
136 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
137 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
138 | default: | |
139 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
140 | } | |
141 | } | |
142 | ||
143 | static inline int mlx5_max_log_rq_size(int wq_type) | |
144 | { | |
145 | switch (wq_type) { | |
146 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
147 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
148 | default: | |
149 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
150 | } | |
151 | } | |
152 | ||
2f48af12 TT |
153 | struct mlx5e_tx_wqe { |
154 | struct mlx5_wqe_ctrl_seg ctrl; | |
155 | struct mlx5_wqe_eth_seg eth; | |
156 | }; | |
157 | ||
158 | struct mlx5e_rx_wqe { | |
159 | struct mlx5_wqe_srq_next_seg next; | |
160 | struct mlx5_wqe_data_seg data; | |
161 | }; | |
86d722ad | 162 | |
bc77b240 TT |
163 | struct mlx5e_umr_wqe { |
164 | struct mlx5_wqe_ctrl_seg ctrl; | |
165 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
166 | struct mlx5_mkey_seg mkc; | |
167 | struct mlx5_wqe_data_seg data; | |
168 | }; | |
169 | ||
d605d668 KH |
170 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
171 | ||
4e59e288 | 172 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 173 | "rx_cqe_moder", |
9bcc8606 | 174 | "rx_cqe_compress", |
4e59e288 GP |
175 | }; |
176 | ||
177 | enum mlx5e_priv_flag { | |
9908aa29 | 178 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
9bcc8606 | 179 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1), |
4e59e288 GP |
180 | }; |
181 | ||
59ece1c9 SD |
182 | #define MLX5E_SET_PFLAG(priv, pflag, enable) \ |
183 | do { \ | |
184 | if (enable) \ | |
185 | (priv)->params.pflags |= (pflag); \ | |
186 | else \ | |
187 | (priv)->params.pflags &= ~(pflag); \ | |
4e59e288 GP |
188 | } while (0) |
189 | ||
59ece1c9 SD |
190 | #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag))) |
191 | ||
08fb1dac SM |
192 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
193 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
194 | #endif |
195 | ||
9908aa29 TT |
196 | struct mlx5e_cq_moder { |
197 | u16 usec; | |
198 | u16 pkts; | |
199 | }; | |
200 | ||
f62b8bb8 AV |
201 | struct mlx5e_params { |
202 | u8 log_sq_size; | |
461017cb | 203 | u8 rq_wq_type; |
d9d9f156 TT |
204 | u8 mpwqe_log_stride_sz; |
205 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
206 | u8 log_rq_size; |
207 | u16 num_channels; | |
f62b8bb8 | 208 | u8 num_tc; |
9908aa29 | 209 | u8 rx_cq_period_mode; |
9bcc8606 | 210 | bool rx_cqe_compress_def; |
9908aa29 TT |
211 | struct mlx5e_cq_moder rx_cq_moderation; |
212 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 213 | u16 min_rx_wqes; |
f62b8bb8 AV |
214 | bool lro_en; |
215 | u32 lro_wqe_sz; | |
58d52291 | 216 | u16 tx_max_inline; |
cff92d7c | 217 | u8 tx_min_inline_mode; |
2d75b2bc AS |
218 | u8 rss_hfunc; |
219 | u8 toeplitz_hash_key[40]; | |
220 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 221 | bool vlan_strip_disable; |
cb3c7fd4 | 222 | bool rx_am_enabled; |
2b029556 | 223 | u32 lro_timeout; |
59ece1c9 | 224 | u32 pflags; |
f62b8bb8 AV |
225 | }; |
226 | ||
3a6a931d HN |
227 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
228 | struct mlx5e_cee_config { | |
229 | /* bw pct for priority group */ | |
230 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
231 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
232 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
233 | bool pfc_enable; | |
234 | }; | |
235 | ||
236 | enum { | |
237 | MLX5_DCB_CHG_RESET, | |
238 | MLX5_DCB_NO_CHG, | |
239 | MLX5_DCB_CHG_NO_RESET, | |
240 | }; | |
241 | ||
242 | struct mlx5e_dcbx { | |
e207b7e9 | 243 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 244 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
820c2c5e HN |
245 | |
246 | /* The only setting that cannot be read from FW */ | |
247 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
3a6a931d HN |
248 | }; |
249 | #endif | |
250 | ||
ef9814de EBE |
251 | struct mlx5e_tstamp { |
252 | rwlock_t lock; | |
253 | struct cyclecounter cycles; | |
254 | struct timecounter clock; | |
255 | struct hwtstamp_config hwtstamp_config; | |
256 | u32 nominal_c_mult; | |
257 | unsigned long overflow_period; | |
258 | struct delayed_work overflow_work; | |
259 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
260 | struct ptp_clock *ptp; |
261 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
262 | }; |
263 | ||
f62b8bb8 | 264 | enum { |
c0f1147d | 265 | MLX5E_RQ_STATE_ENABLED, |
bc77b240 | 266 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 267 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
268 | }; |
269 | ||
f62b8bb8 AV |
270 | struct mlx5e_cq { |
271 | /* data path - accessed per cqe */ | |
272 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
273 | |
274 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 275 | u16 event_ctr; |
f62b8bb8 AV |
276 | struct napi_struct *napi; |
277 | struct mlx5_core_cq mcq; | |
278 | struct mlx5e_channel *channel; | |
50cfa25a | 279 | struct mlx5e_priv *priv; |
f62b8bb8 | 280 | |
7219ab34 TT |
281 | /* cqe decompression */ |
282 | struct mlx5_cqe64 title; | |
283 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
284 | u8 mini_arr_idx; | |
285 | u16 decmprs_left; | |
286 | u16 decmprs_wqe_counter; | |
287 | ||
f62b8bb8 | 288 | /* control */ |
1c1b5228 | 289 | struct mlx5_frag_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
290 | } ____cacheline_aligned_in_smp; |
291 | ||
2f48af12 TT |
292 | struct mlx5e_rq; |
293 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
294 | struct mlx5_cqe64 *cqe); | |
295 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
296 | u16 ix); | |
297 | ||
6cd392a0 DJ |
298 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix); |
299 | ||
461017cb TT |
300 | struct mlx5e_dma_info { |
301 | struct page *page; | |
302 | dma_addr_t addr; | |
303 | }; | |
304 | ||
cb3c7fd4 GR |
305 | struct mlx5e_rx_am_stats { |
306 | int ppms; /* packets per msec */ | |
307 | int epms; /* events per msec */ | |
308 | }; | |
309 | ||
310 | struct mlx5e_rx_am_sample { | |
311 | ktime_t time; | |
312 | unsigned int pkt_ctr; | |
313 | u16 event_ctr; | |
314 | }; | |
315 | ||
316 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
317 | u8 state; | |
318 | struct mlx5e_rx_am_stats prev_stats; | |
319 | struct mlx5e_rx_am_sample start_sample; | |
320 | struct work_struct work; | |
321 | u8 profile_ix; | |
322 | u8 mode; | |
323 | u8 tune_state; | |
324 | u8 steps_right; | |
325 | u8 steps_left; | |
326 | u8 tired; | |
327 | }; | |
328 | ||
4415a031 TT |
329 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
330 | * or a MPWQE (for striding rq). | |
331 | */ | |
332 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
333 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
334 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
335 | struct mlx5e_page_cache { | |
336 | u32 head; | |
337 | u32 tail; | |
338 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
339 | }; | |
340 | ||
f62b8bb8 AV |
341 | struct mlx5e_rq { |
342 | /* data path */ | |
343 | struct mlx5_wq_ll wq; | |
1bfecfca | 344 | |
21c59685 SM |
345 | union { |
346 | struct mlx5e_dma_info *dma_info; | |
347 | struct { | |
348 | struct mlx5e_mpw_info *info; | |
349 | void *mtt_no_align; | |
21c59685 SM |
350 | } mpwqe; |
351 | }; | |
1bfecfca SM |
352 | struct { |
353 | u8 page_order; | |
354 | u32 wqe_sz; /* wqe data buffer size */ | |
b5503b99 | 355 | u8 map_dir; /* dma map direction */ |
1bfecfca | 356 | } buff; |
bc77b240 | 357 | __be32 mkey_be; |
f62b8bb8 AV |
358 | |
359 | struct device *pdev; | |
360 | struct net_device *netdev; | |
ef9814de | 361 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
362 | struct mlx5e_rq_stats stats; |
363 | struct mlx5e_cq cq; | |
4415a031 TT |
364 | struct mlx5e_page_cache page_cache; |
365 | ||
2f48af12 TT |
366 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
367 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 368 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
369 | |
370 | unsigned long state; | |
371 | int ix; | |
372 | ||
cb3c7fd4 | 373 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
86994156 | 374 | struct bpf_prog *xdp_prog; |
cb3c7fd4 | 375 | |
f62b8bb8 AV |
376 | /* control */ |
377 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 378 | u8 wq_type; |
d9d9f156 TT |
379 | u32 mpwqe_stride_sz; |
380 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
381 | u32 rqn; |
382 | struct mlx5e_channel *channel; | |
50cfa25a | 383 | struct mlx5e_priv *priv; |
ec8b9981 | 384 | struct mlx5_core_mkey umr_mkey; |
f62b8bb8 AV |
385 | } ____cacheline_aligned_in_smp; |
386 | ||
bc77b240 TT |
387 | struct mlx5e_umr_dma_info { |
388 | __be64 *mtt; | |
bc77b240 | 389 | dma_addr_t mtt_addr; |
7e426671 TT |
390 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
391 | struct mlx5e_umr_wqe wqe; | |
bc77b240 TT |
392 | }; |
393 | ||
394 | struct mlx5e_mpw_info { | |
7e426671 | 395 | struct mlx5e_umr_dma_info umr; |
bc77b240 TT |
396 | u16 consumed_strides; |
397 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
bc77b240 TT |
398 | }; |
399 | ||
34802a42 | 400 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
401 | u32 num_bytes; |
402 | u8 num_wqebbs; | |
403 | u8 num_dma; | |
404 | }; | |
405 | ||
d4e28cbd AS |
406 | enum mlx5e_dma_map_type { |
407 | MLX5E_DMA_MAP_SINGLE, | |
408 | MLX5E_DMA_MAP_PAGE | |
409 | }; | |
410 | ||
f62b8bb8 | 411 | struct mlx5e_sq_dma { |
d4e28cbd AS |
412 | dma_addr_t addr; |
413 | u32 size; | |
414 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
415 | }; |
416 | ||
417 | enum { | |
c0f1147d | 418 | MLX5E_SQ_STATE_ENABLED, |
0ba42241 | 419 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
420 | }; |
421 | ||
b5503b99 | 422 | struct mlx5e_sq_wqe_info { |
d3c9bc27 TT |
423 | u8 opcode; |
424 | u8 num_wqebbs; | |
425 | }; | |
426 | ||
f10b7cc7 SM |
427 | enum mlx5e_sq_type { |
428 | MLX5E_SQ_TXQ, | |
b5503b99 SM |
429 | MLX5E_SQ_ICO, |
430 | MLX5E_SQ_XDP | |
f10b7cc7 SM |
431 | }; |
432 | ||
f62b8bb8 AV |
433 | struct mlx5e_sq { |
434 | /* data path */ | |
435 | ||
436 | /* dirtied @completion */ | |
437 | u16 cc; | |
438 | u32 dma_fifo_cc; | |
439 | ||
440 | /* dirtied @xmit */ | |
441 | u16 pc ____cacheline_aligned_in_smp; | |
442 | u32 dma_fifo_pc; | |
88a85f99 AS |
443 | u16 bf_offset; |
444 | u16 prev_cc; | |
445 | u8 bf_budget; | |
f62b8bb8 AV |
446 | struct mlx5e_sq_stats stats; |
447 | ||
448 | struct mlx5e_cq cq; | |
449 | ||
f10b7cc7 SM |
450 | /* pointers to per tx element info: write@xmit, read@completion */ |
451 | union { | |
452 | struct { | |
453 | struct sk_buff **skb; | |
454 | struct mlx5e_sq_dma *dma_fifo; | |
455 | struct mlx5e_tx_wqe_info *wqe_info; | |
456 | } txq; | |
b5503b99 SM |
457 | struct mlx5e_sq_wqe_info *ico_wqe; |
458 | struct { | |
459 | struct mlx5e_sq_wqe_info *wqe_info; | |
460 | struct mlx5e_dma_info *di; | |
35b510e2 | 461 | bool doorbell; |
b5503b99 | 462 | } xdp; |
f10b7cc7 | 463 | } db; |
f62b8bb8 AV |
464 | |
465 | /* read only */ | |
466 | struct mlx5_wq_cyc wq; | |
467 | u32 dma_fifo_mask; | |
468 | void __iomem *uar_map; | |
469 | struct netdev_queue *txq; | |
470 | u32 sqn; | |
88a85f99 | 471 | u16 bf_buf_size; |
12be4b21 | 472 | u16 max_inline; |
ae76715d | 473 | u8 min_inline_mode; |
12be4b21 | 474 | u16 edge; |
f62b8bb8 | 475 | struct device *pdev; |
ef9814de | 476 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
477 | __be32 mkey_be; |
478 | unsigned long state; | |
479 | ||
480 | /* control path */ | |
481 | struct mlx5_wq_ctrl wq_ctrl; | |
482 | struct mlx5_uar uar; | |
483 | struct mlx5e_channel *channel; | |
484 | int tc; | |
507f0c81 | 485 | u32 rate_limit; |
f10b7cc7 | 486 | u8 type; |
f62b8bb8 AV |
487 | } ____cacheline_aligned_in_smp; |
488 | ||
489 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
490 | { | |
491 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
492 | (sq->cc == sq->pc)); | |
493 | } | |
494 | ||
495 | enum channel_flags { | |
496 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
497 | }; | |
498 | ||
499 | struct mlx5e_channel { | |
500 | /* data path */ | |
501 | struct mlx5e_rq rq; | |
b5503b99 | 502 | struct mlx5e_sq xdp_sq; |
f62b8bb8 | 503 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; |
d3c9bc27 | 504 | struct mlx5e_sq icosq; /* internal control operations */ |
b5503b99 | 505 | bool xdp; |
f62b8bb8 AV |
506 | struct napi_struct napi; |
507 | struct device *pdev; | |
508 | struct net_device *netdev; | |
509 | __be32 mkey_be; | |
510 | u8 num_tc; | |
511 | unsigned long flags; | |
512 | ||
513 | /* control */ | |
514 | struct mlx5e_priv *priv; | |
515 | int ix; | |
516 | int cpu; | |
517 | }; | |
518 | ||
519 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
520 | MLX5E_TT_IPV4_TCP, |
521 | MLX5E_TT_IPV6_TCP, | |
522 | MLX5E_TT_IPV4_UDP, | |
523 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
524 | MLX5E_TT_IPV4_IPSEC_AH, |
525 | MLX5E_TT_IPV6_IPSEC_AH, | |
526 | MLX5E_TT_IPV4_IPSEC_ESP, | |
527 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
528 | MLX5E_TT_IPV4, |
529 | MLX5E_TT_IPV6, | |
530 | MLX5E_TT_ANY, | |
531 | MLX5E_NUM_TT, | |
1da36696 | 532 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
533 | }; |
534 | ||
acff797c | 535 | enum { |
e0f46eb9 | 536 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
537 | MLX5E_STATE_OPENED, |
538 | MLX5E_STATE_DESTROYING, | |
539 | }; | |
540 | ||
541 | struct mlx5e_vxlan_db { | |
542 | spinlock_t lock; /* protect vxlan table */ | |
543 | struct radix_tree_root tree; | |
544 | }; | |
545 | ||
33cfaaa8 | 546 | struct mlx5e_l2_rule { |
f62b8bb8 | 547 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 548 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
549 | }; |
550 | ||
acff797c MG |
551 | struct mlx5e_flow_table { |
552 | int num_groups; | |
553 | struct mlx5_flow_table *t; | |
554 | struct mlx5_flow_group **g; | |
555 | }; | |
556 | ||
33cfaaa8 | 557 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 558 | |
acff797c MG |
559 | struct mlx5e_tc_table { |
560 | struct mlx5_flow_table *t; | |
561 | ||
562 | struct rhashtable_params ht_params; | |
563 | struct rhashtable ht; | |
f62b8bb8 AV |
564 | }; |
565 | ||
acff797c MG |
566 | struct mlx5e_vlan_table { |
567 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 568 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
74491de9 MB |
569 | struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID]; |
570 | struct mlx5_flow_handle *untagged_rule; | |
571 | struct mlx5_flow_handle *any_vlan_rule; | |
572 | bool filter_disabled; | |
f62b8bb8 AV |
573 | }; |
574 | ||
33cfaaa8 MG |
575 | struct mlx5e_l2_table { |
576 | struct mlx5e_flow_table ft; | |
577 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
578 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
579 | struct mlx5e_l2_rule broadcast; | |
580 | struct mlx5e_l2_rule allmulti; | |
581 | struct mlx5e_l2_rule promisc; | |
582 | bool broadcast_enabled; | |
583 | bool allmulti_enabled; | |
584 | bool promisc_enabled; | |
585 | }; | |
586 | ||
587 | /* L3/L4 traffic type classifier */ | |
588 | struct mlx5e_ttc_table { | |
589 | struct mlx5e_flow_table ft; | |
74491de9 | 590 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
33cfaaa8 MG |
591 | }; |
592 | ||
18c908e4 MG |
593 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
594 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
595 | struct arfs_table { |
596 | struct mlx5e_flow_table ft; | |
74491de9 | 597 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 598 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
599 | }; |
600 | ||
601 | enum arfs_type { | |
602 | ARFS_IPV4_TCP, | |
603 | ARFS_IPV6_TCP, | |
604 | ARFS_IPV4_UDP, | |
605 | ARFS_IPV6_UDP, | |
606 | ARFS_NUM_TYPES, | |
607 | }; | |
608 | ||
609 | struct mlx5e_arfs_tables { | |
610 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
611 | /* Protect aRFS rules list */ |
612 | spinlock_t arfs_lock; | |
613 | struct list_head rules; | |
614 | int last_filter_id; | |
615 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
616 | }; |
617 | ||
618 | /* NIC prio FTS */ | |
619 | enum { | |
620 | MLX5E_VLAN_FT_LEVEL = 0, | |
621 | MLX5E_L2_FT_LEVEL, | |
622 | MLX5E_TTC_FT_LEVEL, | |
623 | MLX5E_ARFS_FT_LEVEL | |
624 | }; | |
625 | ||
6dc6071c MG |
626 | struct mlx5e_ethtool_table { |
627 | struct mlx5_flow_table *ft; | |
628 | int num_rules; | |
629 | }; | |
630 | ||
1174fce8 | 631 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
632 | #define ETHTOOL_NUM_L2_FTS 4 |
633 | ||
634 | struct mlx5e_ethtool_steering { | |
1174fce8 | 635 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
636 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
637 | struct list_head rules; | |
638 | int tot_num_rules; | |
639 | }; | |
640 | ||
acff797c MG |
641 | struct mlx5e_flow_steering { |
642 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 643 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
644 | struct mlx5e_tc_table tc; |
645 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
646 | struct mlx5e_l2_table l2; |
647 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 648 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
649 | }; |
650 | ||
398f3351 | 651 | struct mlx5e_rqt { |
1da36696 | 652 | u32 rqtn; |
398f3351 HHZ |
653 | bool enabled; |
654 | }; | |
655 | ||
656 | struct mlx5e_tir { | |
657 | u32 tirn; | |
658 | struct mlx5e_rqt rqt; | |
659 | struct list_head list; | |
1da36696 TT |
660 | }; |
661 | ||
acff797c MG |
662 | enum { |
663 | MLX5E_TC_PRIO = 0, | |
664 | MLX5E_NIC_PRIO | |
665 | }; | |
666 | ||
6bfd390b HHZ |
667 | struct mlx5e_profile { |
668 | void (*init)(struct mlx5_core_dev *mdev, | |
669 | struct net_device *netdev, | |
127ea380 | 670 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
671 | void (*cleanup)(struct mlx5e_priv *priv); |
672 | int (*init_rx)(struct mlx5e_priv *priv); | |
673 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
674 | int (*init_tx)(struct mlx5e_priv *priv); | |
675 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
676 | void (*enable)(struct mlx5e_priv *priv); | |
677 | void (*disable)(struct mlx5e_priv *priv); | |
678 | void (*update_stats)(struct mlx5e_priv *priv); | |
679 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
680 | int max_tc; | |
681 | }; | |
682 | ||
f62b8bb8 AV |
683 | struct mlx5e_priv { |
684 | /* priv data path fields - start */ | |
03289b88 | 685 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 686 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
86994156 | 687 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
688 | /* priv data path fields - end */ |
689 | ||
690 | unsigned long state; | |
691 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 692 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
693 | |
694 | struct mlx5e_channel **channel; | |
695 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
398f3351 | 696 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
697 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
698 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 699 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 700 | |
acff797c | 701 | struct mlx5e_flow_steering fs; |
b3f63c3d | 702 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
703 | |
704 | struct mlx5e_params params; | |
7bb29755 | 705 | struct workqueue_struct *wq; |
f62b8bb8 AV |
706 | struct work_struct update_carrier_work; |
707 | struct work_struct set_rx_mode_work; | |
3947ca18 | 708 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
709 | struct delayed_work update_stats_work; |
710 | ||
711 | struct mlx5_core_dev *mdev; | |
712 | struct net_device *netdev; | |
713 | struct mlx5e_stats stats; | |
ef9814de | 714 | struct mlx5e_tstamp tstamp; |
593cf338 | 715 | u16 q_counter; |
3a6a931d HN |
716 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
717 | struct mlx5e_dcbx dcbx; | |
718 | #endif | |
719 | ||
6bfd390b | 720 | const struct mlx5e_profile *profile; |
127ea380 | 721 | void *ppriv; |
f62b8bb8 AV |
722 | }; |
723 | ||
665bc539 GP |
724 | void mlx5e_build_ptys2ethtool_map(void); |
725 | ||
12be4b21 | 726 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
727 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
728 | void *accel_priv, select_queue_fallback_t fallback); | |
729 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
730 | |
731 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
732 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
733 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 734 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 735 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
b5503b99 | 736 | void mlx5e_free_sq_descs(struct mlx5e_sq *sq); |
461017cb | 737 | |
4415a031 TT |
738 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
739 | bool recycle); | |
2f48af12 | 740 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 741 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 742 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 743 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 744 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
745 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
746 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
747 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
748 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
749 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
750 | ||
cb3c7fd4 GR |
751 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
752 | void mlx5e_rx_am_work(struct work_struct *work); | |
753 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
754 | ||
f62b8bb8 AV |
755 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
756 | ||
acff797c MG |
757 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
758 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 759 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 760 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
761 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
762 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
763 | u64 *buf); | |
f913a72a MG |
764 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
765 | int location); | |
766 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
767 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
768 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
769 | struct ethtool_rx_flow_spec *fs); | |
770 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
771 | int location); | |
772 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
773 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
774 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
775 | ||
ef9814de EBE |
776 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
777 | struct skb_shared_hwtstamps *hwts); | |
778 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
779 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
780 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
781 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 782 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 783 | |
f62b8bb8 AV |
784 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
785 | u16 vid); | |
786 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
787 | u16 vid); | |
788 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
789 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 790 | |
36350114 GP |
791 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
792 | ||
1da36696 | 793 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 794 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 795 | |
f62b8bb8 AV |
796 | int mlx5e_open_locked(struct net_device *netdev); |
797 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
798 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
799 | u32 *indirection_rqt, int len, | |
85082dba | 800 | int num_channels); |
b797a684 | 801 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 802 | |
9908aa29 TT |
803 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
804 | u8 cq_period_mode); | |
805 | ||
f62b8bb8 | 806 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
bc77b240 | 807 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 808 | { |
88a85f99 AS |
809 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
810 | ||
f62b8bb8 AV |
811 | /* ensure wqe is visible to device before updating doorbell record */ |
812 | dma_wmb(); | |
813 | ||
814 | *sq->wq.db = cpu_to_be32(sq->pc); | |
815 | ||
816 | /* ensure doorbell record is visible to device before ringing the | |
817 | * doorbell | |
818 | */ | |
819 | wmb(); | |
0ba42241 | 820 | if (bf_sz) |
bc77b240 | 821 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 822 | else |
bc77b240 | 823 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
824 | /* flush the write-combining mapped buffer */ |
825 | wmb(); | |
f62b8bb8 AV |
826 | |
827 | sq->bf_offset ^= sq->bf_buf_size; | |
828 | } | |
829 | ||
830 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
831 | { | |
832 | struct mlx5_core_cq *mcq; | |
833 | ||
834 | mcq = &cq->mcq; | |
835 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
836 | } | |
837 | ||
7e426671 TT |
838 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
839 | { | |
ec8b9981 | 840 | return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
7e426671 TT |
841 | } |
842 | ||
3435ab59 AS |
843 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
844 | { | |
845 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
846 | MLX5E_MAX_NUM_CHANNELS); | |
847 | } | |
848 | ||
f62b8bb8 | 849 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
850 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
851 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
852 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 853 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
08fb1dac SM |
854 | #endif |
855 | ||
1cabe6b0 MG |
856 | #ifndef CONFIG_RFS_ACCEL |
857 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
858 | { | |
859 | return 0; | |
860 | } | |
861 | ||
862 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
863 | |
864 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
865 | { | |
9eb78923 | 866 | return -EOPNOTSUPP; |
45bf454a MG |
867 | } |
868 | ||
869 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
870 | { | |
9eb78923 | 871 | return -EOPNOTSUPP; |
45bf454a | 872 | } |
1cabe6b0 MG |
873 | #else |
874 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
875 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
876 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
877 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
878 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
879 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
880 | #endif |
881 | ||
58d52291 | 882 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
883 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
884 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
885 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
886 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
887 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
888 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
0952da79 SM |
889 | int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev, |
890 | bool enable_uc_lb); | |
1afff42c | 891 | |
cb67b832 HHZ |
892 | struct mlx5_eswitch_rep; |
893 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
894 | struct mlx5_eswitch_rep *rep); | |
895 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
896 | struct mlx5_eswitch_rep *rep); | |
897 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
898 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
899 | struct mlx5_eswitch_rep *rep); | |
900 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
901 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
902 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
f5f82476 | 903 | void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
370bad0f | 904 | void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv); |
cb67b832 HHZ |
905 | |
906 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
907 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
908 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
909 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
910 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
911 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
912 | int mlx5e_close(struct net_device *netdev); | |
913 | int mlx5e_open(struct net_device *netdev); | |
914 | void mlx5e_update_stats_work(struct work_struct *work); | |
26e59d80 MHY |
915 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
916 | const struct mlx5e_profile *profile, | |
917 | void *ppriv); | |
cb67b832 | 918 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); |
26e59d80 MHY |
919 | int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); |
920 | void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); | |
2b029556 | 921 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); |
4a25730e HHZ |
922 | void mlx5e_add_vxlan_port(struct net_device *netdev, |
923 | struct udp_tunnel_info *ti); | |
924 | void mlx5e_del_vxlan_port(struct net_device *netdev, | |
925 | struct udp_tunnel_info *ti); | |
cb67b832 | 926 | |
370bad0f OG |
927 | int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, |
928 | void *sp); | |
929 | bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id); | |
930 | ||
931 | bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv); | |
932 | bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv); | |
1afff42c | 933 | #endif /* __MLX5_EN_H__ */ |