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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
f62b8bb8 AV |
54 | #define MLX5E_MAX_NUM_TC 8 |
55 | ||
e842b100 | 56 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
57 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
58 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
59 | ||
e842b100 | 60 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
61 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
62 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
63 | ||
461017cb | 64 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 65 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
66 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
67 | ||
1bfecfca SM |
68 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
69 | ||
461017cb | 70 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 | 71 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
7e426671 | 72 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
73 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
74 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
75 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
76 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
77 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
78 | |
79 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
80 | #define MLX5E_REQUIRED_MTTS(rqs, wqes)\ | |
81 | (rqs * wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
82 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) <= U16_MAX) | |
83 | ||
bc77b240 | 84 | #define MLX5_UMR_ALIGN (2048) |
461017cb TT |
85 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
86 | ||
d9a40271 | 87 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 | 88 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 89 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
90 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
91 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
92 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
93 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 94 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 95 | |
936896e9 AS |
96 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
97 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
98 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
507f0c81 | 99 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
100 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
101 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 102 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 103 | |
86d722ad | 104 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 105 | |
461017cb TT |
106 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
107 | { | |
108 | switch (wq_type) { | |
109 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
110 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
111 | wq_size / 2); | |
112 | default: | |
113 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
114 | wq_size / 2); | |
115 | } | |
116 | } | |
117 | ||
118 | static inline int mlx5_min_log_rq_size(int wq_type) | |
119 | { | |
120 | switch (wq_type) { | |
121 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
122 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
123 | default: | |
124 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
125 | } | |
126 | } | |
127 | ||
128 | static inline int mlx5_max_log_rq_size(int wq_type) | |
129 | { | |
130 | switch (wq_type) { | |
131 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
132 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
133 | default: | |
134 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
135 | } | |
136 | } | |
137 | ||
cff92d7c HHZ |
138 | enum { |
139 | MLX5E_INLINE_MODE_L2, | |
140 | MLX5E_INLINE_MODE_VPORT_CONTEXT, | |
141 | MLX5_INLINE_MODE_NOT_REQUIRED, | |
142 | }; | |
143 | ||
2f48af12 TT |
144 | struct mlx5e_tx_wqe { |
145 | struct mlx5_wqe_ctrl_seg ctrl; | |
146 | struct mlx5_wqe_eth_seg eth; | |
147 | }; | |
148 | ||
149 | struct mlx5e_rx_wqe { | |
150 | struct mlx5_wqe_srq_next_seg next; | |
151 | struct mlx5_wqe_data_seg data; | |
152 | }; | |
86d722ad | 153 | |
bc77b240 TT |
154 | struct mlx5e_umr_wqe { |
155 | struct mlx5_wqe_ctrl_seg ctrl; | |
156 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
157 | struct mlx5_mkey_seg mkc; | |
158 | struct mlx5_wqe_data_seg data; | |
159 | }; | |
160 | ||
4e59e288 | 161 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 162 | "rx_cqe_moder", |
4e59e288 GP |
163 | }; |
164 | ||
165 | enum mlx5e_priv_flag { | |
9908aa29 | 166 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
4e59e288 GP |
167 | }; |
168 | ||
169 | #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \ | |
170 | do { \ | |
171 | if (enable) \ | |
172 | priv->pflags |= pflag; \ | |
173 | else \ | |
174 | priv->pflags &= ~pflag; \ | |
175 | } while (0) | |
176 | ||
08fb1dac SM |
177 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
178 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
179 | #endif |
180 | ||
9908aa29 TT |
181 | struct mlx5e_cq_moder { |
182 | u16 usec; | |
183 | u16 pkts; | |
184 | }; | |
185 | ||
f62b8bb8 AV |
186 | struct mlx5e_params { |
187 | u8 log_sq_size; | |
461017cb | 188 | u8 rq_wq_type; |
d9d9f156 TT |
189 | u8 mpwqe_log_stride_sz; |
190 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
191 | u8 log_rq_size; |
192 | u16 num_channels; | |
f62b8bb8 | 193 | u8 num_tc; |
9908aa29 | 194 | u8 rx_cq_period_mode; |
7219ab34 TT |
195 | bool rx_cqe_compress_admin; |
196 | bool rx_cqe_compress; | |
9908aa29 TT |
197 | struct mlx5e_cq_moder rx_cq_moderation; |
198 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 199 | u16 min_rx_wqes; |
f62b8bb8 AV |
200 | bool lro_en; |
201 | u32 lro_wqe_sz; | |
58d52291 | 202 | u16 tx_max_inline; |
cff92d7c | 203 | u8 tx_min_inline_mode; |
2d75b2bc AS |
204 | u8 rss_hfunc; |
205 | u8 toeplitz_hash_key[40]; | |
206 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 207 | bool vlan_strip_disable; |
08fb1dac SM |
208 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
209 | struct ieee_ets ets; | |
210 | #endif | |
cb3c7fd4 | 211 | bool rx_am_enabled; |
f62b8bb8 AV |
212 | }; |
213 | ||
ef9814de EBE |
214 | struct mlx5e_tstamp { |
215 | rwlock_t lock; | |
216 | struct cyclecounter cycles; | |
217 | struct timecounter clock; | |
218 | struct hwtstamp_config hwtstamp_config; | |
219 | u32 nominal_c_mult; | |
220 | unsigned long overflow_period; | |
221 | struct delayed_work overflow_work; | |
222 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
223 | struct ptp_clock *ptp; |
224 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
225 | }; |
226 | ||
f62b8bb8 | 227 | enum { |
f2fde18c | 228 | MLX5E_RQ_STATE_FLUSH, |
bc77b240 | 229 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 230 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
231 | }; |
232 | ||
f62b8bb8 AV |
233 | struct mlx5e_cq { |
234 | /* data path - accessed per cqe */ | |
235 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
236 | |
237 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 238 | u16 event_ctr; |
f62b8bb8 AV |
239 | struct napi_struct *napi; |
240 | struct mlx5_core_cq mcq; | |
241 | struct mlx5e_channel *channel; | |
50cfa25a | 242 | struct mlx5e_priv *priv; |
f62b8bb8 | 243 | |
7219ab34 TT |
244 | /* cqe decompression */ |
245 | struct mlx5_cqe64 title; | |
246 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
247 | u8 mini_arr_idx; | |
248 | u16 decmprs_left; | |
249 | u16 decmprs_wqe_counter; | |
250 | ||
f62b8bb8 AV |
251 | /* control */ |
252 | struct mlx5_wq_ctrl wq_ctrl; | |
253 | } ____cacheline_aligned_in_smp; | |
254 | ||
2f48af12 TT |
255 | struct mlx5e_rq; |
256 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
257 | struct mlx5_cqe64 *cqe); | |
258 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
259 | u16 ix); | |
260 | ||
6cd392a0 DJ |
261 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix); |
262 | ||
461017cb TT |
263 | struct mlx5e_dma_info { |
264 | struct page *page; | |
265 | dma_addr_t addr; | |
266 | }; | |
267 | ||
cb3c7fd4 GR |
268 | struct mlx5e_rx_am_stats { |
269 | int ppms; /* packets per msec */ | |
270 | int epms; /* events per msec */ | |
271 | }; | |
272 | ||
273 | struct mlx5e_rx_am_sample { | |
274 | ktime_t time; | |
275 | unsigned int pkt_ctr; | |
276 | u16 event_ctr; | |
277 | }; | |
278 | ||
279 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
280 | u8 state; | |
281 | struct mlx5e_rx_am_stats prev_stats; | |
282 | struct mlx5e_rx_am_sample start_sample; | |
283 | struct work_struct work; | |
284 | u8 profile_ix; | |
285 | u8 mode; | |
286 | u8 tune_state; | |
287 | u8 steps_right; | |
288 | u8 steps_left; | |
289 | u8 tired; | |
290 | }; | |
291 | ||
4415a031 TT |
292 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
293 | * or a MPWQE (for striding rq). | |
294 | */ | |
295 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
296 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
297 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
298 | struct mlx5e_page_cache { | |
299 | u32 head; | |
300 | u32 tail; | |
301 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
302 | }; | |
303 | ||
f62b8bb8 AV |
304 | struct mlx5e_rq { |
305 | /* data path */ | |
306 | struct mlx5_wq_ll wq; | |
1bfecfca | 307 | |
21c59685 SM |
308 | union { |
309 | struct mlx5e_dma_info *dma_info; | |
310 | struct { | |
311 | struct mlx5e_mpw_info *info; | |
312 | void *mtt_no_align; | |
313 | u32 mtt_offset; | |
314 | } mpwqe; | |
315 | }; | |
1bfecfca SM |
316 | struct { |
317 | u8 page_order; | |
318 | u32 wqe_sz; /* wqe data buffer size */ | |
319 | } buff; | |
bc77b240 | 320 | __be32 mkey_be; |
f62b8bb8 AV |
321 | |
322 | struct device *pdev; | |
323 | struct net_device *netdev; | |
ef9814de | 324 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
325 | struct mlx5e_rq_stats stats; |
326 | struct mlx5e_cq cq; | |
4415a031 TT |
327 | struct mlx5e_page_cache page_cache; |
328 | ||
2f48af12 TT |
329 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
330 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 331 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
332 | |
333 | unsigned long state; | |
334 | int ix; | |
335 | ||
cb3c7fd4 GR |
336 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
337 | ||
f62b8bb8 AV |
338 | /* control */ |
339 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 340 | u8 wq_type; |
d9d9f156 TT |
341 | u32 mpwqe_stride_sz; |
342 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
343 | u32 rqn; |
344 | struct mlx5e_channel *channel; | |
50cfa25a | 345 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
346 | } ____cacheline_aligned_in_smp; |
347 | ||
bc77b240 TT |
348 | struct mlx5e_umr_dma_info { |
349 | __be64 *mtt; | |
bc77b240 | 350 | dma_addr_t mtt_addr; |
7e426671 TT |
351 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
352 | struct mlx5e_umr_wqe wqe; | |
bc77b240 TT |
353 | }; |
354 | ||
355 | struct mlx5e_mpw_info { | |
7e426671 | 356 | struct mlx5e_umr_dma_info umr; |
bc77b240 TT |
357 | u16 consumed_strides; |
358 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
bc77b240 TT |
359 | }; |
360 | ||
34802a42 | 361 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
362 | u32 num_bytes; |
363 | u8 num_wqebbs; | |
364 | u8 num_dma; | |
365 | }; | |
366 | ||
d4e28cbd AS |
367 | enum mlx5e_dma_map_type { |
368 | MLX5E_DMA_MAP_SINGLE, | |
369 | MLX5E_DMA_MAP_PAGE | |
370 | }; | |
371 | ||
f62b8bb8 | 372 | struct mlx5e_sq_dma { |
d4e28cbd AS |
373 | dma_addr_t addr; |
374 | u32 size; | |
375 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
376 | }; |
377 | ||
378 | enum { | |
6e8dd6d6 | 379 | MLX5E_SQ_STATE_FLUSH, |
0ba42241 | 380 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
381 | }; |
382 | ||
d3c9bc27 TT |
383 | struct mlx5e_ico_wqe_info { |
384 | u8 opcode; | |
385 | u8 num_wqebbs; | |
386 | }; | |
387 | ||
f62b8bb8 AV |
388 | struct mlx5e_sq { |
389 | /* data path */ | |
390 | ||
391 | /* dirtied @completion */ | |
392 | u16 cc; | |
393 | u32 dma_fifo_cc; | |
394 | ||
395 | /* dirtied @xmit */ | |
396 | u16 pc ____cacheline_aligned_in_smp; | |
397 | u32 dma_fifo_pc; | |
88a85f99 AS |
398 | u16 bf_offset; |
399 | u16 prev_cc; | |
400 | u8 bf_budget; | |
f62b8bb8 AV |
401 | struct mlx5e_sq_stats stats; |
402 | ||
403 | struct mlx5e_cq cq; | |
404 | ||
405 | /* pointers to per packet info: write@xmit, read@completion */ | |
406 | struct sk_buff **skb; | |
407 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 408 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
409 | |
410 | /* read only */ | |
411 | struct mlx5_wq_cyc wq; | |
412 | u32 dma_fifo_mask; | |
413 | void __iomem *uar_map; | |
414 | struct netdev_queue *txq; | |
415 | u32 sqn; | |
88a85f99 | 416 | u16 bf_buf_size; |
12be4b21 | 417 | u16 max_inline; |
ae76715d | 418 | u8 min_inline_mode; |
12be4b21 | 419 | u16 edge; |
f62b8bb8 | 420 | struct device *pdev; |
ef9814de | 421 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
422 | __be32 mkey_be; |
423 | unsigned long state; | |
424 | ||
425 | /* control path */ | |
426 | struct mlx5_wq_ctrl wq_ctrl; | |
427 | struct mlx5_uar uar; | |
428 | struct mlx5e_channel *channel; | |
429 | int tc; | |
d3c9bc27 | 430 | struct mlx5e_ico_wqe_info *ico_wqe_info; |
507f0c81 | 431 | u32 rate_limit; |
f62b8bb8 AV |
432 | } ____cacheline_aligned_in_smp; |
433 | ||
434 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
435 | { | |
436 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
437 | (sq->cc == sq->pc)); | |
438 | } | |
439 | ||
440 | enum channel_flags { | |
441 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
442 | }; | |
443 | ||
444 | struct mlx5e_channel { | |
445 | /* data path */ | |
446 | struct mlx5e_rq rq; | |
447 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
d3c9bc27 | 448 | struct mlx5e_sq icosq; /* internal control operations */ |
f62b8bb8 AV |
449 | struct napi_struct napi; |
450 | struct device *pdev; | |
451 | struct net_device *netdev; | |
452 | __be32 mkey_be; | |
453 | u8 num_tc; | |
454 | unsigned long flags; | |
455 | ||
456 | /* control */ | |
457 | struct mlx5e_priv *priv; | |
458 | int ix; | |
459 | int cpu; | |
460 | }; | |
461 | ||
462 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
463 | MLX5E_TT_IPV4_TCP, |
464 | MLX5E_TT_IPV6_TCP, | |
465 | MLX5E_TT_IPV4_UDP, | |
466 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
467 | MLX5E_TT_IPV4_IPSEC_AH, |
468 | MLX5E_TT_IPV6_IPSEC_AH, | |
469 | MLX5E_TT_IPV4_IPSEC_ESP, | |
470 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
471 | MLX5E_TT_IPV4, |
472 | MLX5E_TT_IPV6, | |
473 | MLX5E_TT_ANY, | |
474 | MLX5E_NUM_TT, | |
1da36696 | 475 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
476 | }; |
477 | ||
acff797c | 478 | enum { |
e0f46eb9 | 479 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
480 | MLX5E_STATE_OPENED, |
481 | MLX5E_STATE_DESTROYING, | |
482 | }; | |
483 | ||
484 | struct mlx5e_vxlan_db { | |
485 | spinlock_t lock; /* protect vxlan table */ | |
486 | struct radix_tree_root tree; | |
487 | }; | |
488 | ||
33cfaaa8 | 489 | struct mlx5e_l2_rule { |
f62b8bb8 | 490 | u8 addr[ETH_ALEN + 2]; |
33cfaaa8 | 491 | struct mlx5_flow_rule *rule; |
f62b8bb8 AV |
492 | }; |
493 | ||
acff797c MG |
494 | struct mlx5e_flow_table { |
495 | int num_groups; | |
496 | struct mlx5_flow_table *t; | |
497 | struct mlx5_flow_group **g; | |
498 | }; | |
499 | ||
33cfaaa8 | 500 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 501 | |
acff797c MG |
502 | struct mlx5e_tc_table { |
503 | struct mlx5_flow_table *t; | |
504 | ||
505 | struct rhashtable_params ht_params; | |
506 | struct rhashtable ht; | |
f62b8bb8 AV |
507 | }; |
508 | ||
acff797c MG |
509 | struct mlx5e_vlan_table { |
510 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 511 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
512 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
513 | struct mlx5_flow_rule *untagged_rule; | |
514 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
515 | bool filter_disabled; |
516 | }; | |
517 | ||
33cfaaa8 MG |
518 | struct mlx5e_l2_table { |
519 | struct mlx5e_flow_table ft; | |
520 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
521 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
522 | struct mlx5e_l2_rule broadcast; | |
523 | struct mlx5e_l2_rule allmulti; | |
524 | struct mlx5e_l2_rule promisc; | |
525 | bool broadcast_enabled; | |
526 | bool allmulti_enabled; | |
527 | bool promisc_enabled; | |
528 | }; | |
529 | ||
530 | /* L3/L4 traffic type classifier */ | |
531 | struct mlx5e_ttc_table { | |
532 | struct mlx5e_flow_table ft; | |
533 | struct mlx5_flow_rule *rules[MLX5E_NUM_TT]; | |
534 | }; | |
535 | ||
18c908e4 MG |
536 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
537 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
538 | struct arfs_table { |
539 | struct mlx5e_flow_table ft; | |
540 | struct mlx5_flow_rule *default_rule; | |
18c908e4 | 541 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
542 | }; |
543 | ||
544 | enum arfs_type { | |
545 | ARFS_IPV4_TCP, | |
546 | ARFS_IPV6_TCP, | |
547 | ARFS_IPV4_UDP, | |
548 | ARFS_IPV6_UDP, | |
549 | ARFS_NUM_TYPES, | |
550 | }; | |
551 | ||
552 | struct mlx5e_arfs_tables { | |
553 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
554 | /* Protect aRFS rules list */ |
555 | spinlock_t arfs_lock; | |
556 | struct list_head rules; | |
557 | int last_filter_id; | |
558 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
559 | }; |
560 | ||
561 | /* NIC prio FTS */ | |
562 | enum { | |
563 | MLX5E_VLAN_FT_LEVEL = 0, | |
564 | MLX5E_L2_FT_LEVEL, | |
565 | MLX5E_TTC_FT_LEVEL, | |
566 | MLX5E_ARFS_FT_LEVEL | |
567 | }; | |
568 | ||
6dc6071c MG |
569 | struct mlx5e_ethtool_table { |
570 | struct mlx5_flow_table *ft; | |
571 | int num_rules; | |
572 | }; | |
573 | ||
1174fce8 | 574 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
575 | #define ETHTOOL_NUM_L2_FTS 4 |
576 | ||
577 | struct mlx5e_ethtool_steering { | |
1174fce8 | 578 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
579 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
580 | struct list_head rules; | |
581 | int tot_num_rules; | |
582 | }; | |
583 | ||
acff797c MG |
584 | struct mlx5e_flow_steering { |
585 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 586 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
587 | struct mlx5e_tc_table tc; |
588 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
589 | struct mlx5e_l2_table l2; |
590 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 591 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
592 | }; |
593 | ||
398f3351 | 594 | struct mlx5e_rqt { |
1da36696 | 595 | u32 rqtn; |
398f3351 HHZ |
596 | bool enabled; |
597 | }; | |
598 | ||
599 | struct mlx5e_tir { | |
600 | u32 tirn; | |
601 | struct mlx5e_rqt rqt; | |
602 | struct list_head list; | |
1da36696 TT |
603 | }; |
604 | ||
acff797c MG |
605 | enum { |
606 | MLX5E_TC_PRIO = 0, | |
607 | MLX5E_NIC_PRIO | |
608 | }; | |
609 | ||
6bfd390b HHZ |
610 | struct mlx5e_profile { |
611 | void (*init)(struct mlx5_core_dev *mdev, | |
612 | struct net_device *netdev, | |
127ea380 | 613 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
614 | void (*cleanup)(struct mlx5e_priv *priv); |
615 | int (*init_rx)(struct mlx5e_priv *priv); | |
616 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
617 | int (*init_tx)(struct mlx5e_priv *priv); | |
618 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
619 | void (*enable)(struct mlx5e_priv *priv); | |
620 | void (*disable)(struct mlx5e_priv *priv); | |
621 | void (*update_stats)(struct mlx5e_priv *priv); | |
622 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
623 | int max_tc; | |
624 | }; | |
625 | ||
f62b8bb8 AV |
626 | struct mlx5e_priv { |
627 | /* priv data path fields - start */ | |
03289b88 | 628 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 629 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
630 | /* priv data path fields - end */ |
631 | ||
632 | unsigned long state; | |
633 | struct mutex state_lock; /* Protects Interface state */ | |
bc77b240 | 634 | struct mlx5_core_mkey umr_mkey; |
50cfa25a | 635 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
636 | |
637 | struct mlx5e_channel **channel; | |
638 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
398f3351 | 639 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
640 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
641 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 642 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 643 | |
acff797c | 644 | struct mlx5e_flow_steering fs; |
b3f63c3d | 645 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
646 | |
647 | struct mlx5e_params params; | |
7bb29755 | 648 | struct workqueue_struct *wq; |
f62b8bb8 AV |
649 | struct work_struct update_carrier_work; |
650 | struct work_struct set_rx_mode_work; | |
3947ca18 | 651 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
652 | struct delayed_work update_stats_work; |
653 | ||
4e59e288 | 654 | u32 pflags; |
f62b8bb8 AV |
655 | struct mlx5_core_dev *mdev; |
656 | struct net_device *netdev; | |
657 | struct mlx5e_stats stats; | |
ef9814de | 658 | struct mlx5e_tstamp tstamp; |
593cf338 | 659 | u16 q_counter; |
6bfd390b | 660 | const struct mlx5e_profile *profile; |
127ea380 | 661 | void *ppriv; |
f62b8bb8 AV |
662 | }; |
663 | ||
665bc539 GP |
664 | void mlx5e_build_ptys2ethtool_map(void); |
665 | ||
12be4b21 | 666 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
667 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
668 | void *accel_priv, select_queue_fallback_t fallback); | |
669 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
670 | |
671 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
672 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
673 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 674 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 675 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
29429f33 | 676 | void mlx5e_free_tx_descs(struct mlx5e_sq *sq); |
461017cb | 677 | |
4415a031 TT |
678 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
679 | bool recycle); | |
2f48af12 | 680 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 681 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 682 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 683 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 684 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
685 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
686 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
687 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
688 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
689 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
690 | ||
cb3c7fd4 GR |
691 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
692 | void mlx5e_rx_am_work(struct work_struct *work); | |
693 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
694 | ||
f62b8bb8 AV |
695 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
696 | ||
acff797c MG |
697 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
698 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 699 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 700 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
f913a72a MG |
701 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
702 | int location); | |
703 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
704 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
705 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
706 | struct ethtool_rx_flow_spec *fs); | |
707 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
708 | int location); | |
709 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
710 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
711 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
712 | ||
ef9814de EBE |
713 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
714 | struct skb_shared_hwtstamps *hwts); | |
715 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
716 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
717 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
718 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 719 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 720 | |
f62b8bb8 AV |
721 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
722 | u16 vid); | |
723 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
724 | u16 vid); | |
725 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
726 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 727 | |
36350114 GP |
728 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
729 | ||
1da36696 | 730 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 731 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 732 | |
f62b8bb8 AV |
733 | int mlx5e_open_locked(struct net_device *netdev); |
734 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
735 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
736 | u32 *indirection_rqt, int len, | |
85082dba | 737 | int num_channels); |
b797a684 | 738 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 739 | |
9908aa29 TT |
740 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
741 | u8 cq_period_mode); | |
742 | ||
f62b8bb8 | 743 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
bc77b240 | 744 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 745 | { |
88a85f99 AS |
746 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
747 | ||
f62b8bb8 AV |
748 | /* ensure wqe is visible to device before updating doorbell record */ |
749 | dma_wmb(); | |
750 | ||
751 | *sq->wq.db = cpu_to_be32(sq->pc); | |
752 | ||
753 | /* ensure doorbell record is visible to device before ringing the | |
754 | * doorbell | |
755 | */ | |
756 | wmb(); | |
0ba42241 | 757 | if (bf_sz) |
bc77b240 | 758 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 759 | else |
bc77b240 | 760 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
761 | /* flush the write-combining mapped buffer */ |
762 | wmb(); | |
f62b8bb8 AV |
763 | |
764 | sq->bf_offset ^= sq->bf_buf_size; | |
765 | } | |
766 | ||
767 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
768 | { | |
769 | struct mlx5_core_cq *mcq; | |
770 | ||
771 | mcq = &cq->mcq; | |
772 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
773 | } | |
774 | ||
7e426671 TT |
775 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
776 | { | |
21c59685 | 777 | return rq->mpwqe.mtt_offset + |
7e426671 TT |
778 | wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
779 | } | |
780 | ||
3435ab59 AS |
781 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
782 | { | |
783 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
784 | MLX5E_MAX_NUM_CHANNELS); | |
785 | } | |
786 | ||
f62b8bb8 | 787 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
788 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
789 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
790 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
791 | #endif | |
792 | ||
1cabe6b0 MG |
793 | #ifndef CONFIG_RFS_ACCEL |
794 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
795 | { | |
796 | return 0; | |
797 | } | |
798 | ||
799 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
800 | |
801 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
802 | { | |
803 | return -ENOTSUPP; | |
804 | } | |
805 | ||
806 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
807 | { | |
808 | return -ENOTSUPP; | |
809 | } | |
1cabe6b0 MG |
810 | #else |
811 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
812 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
813 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
814 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
815 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
816 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
817 | #endif |
818 | ||
58d52291 | 819 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
820 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
821 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
822 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
823 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
824 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
825 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
724b2aa1 | 826 | int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev); |
1afff42c | 827 | |
cb67b832 HHZ |
828 | struct mlx5_eswitch_rep; |
829 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
830 | struct mlx5_eswitch_rep *rep); | |
831 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
832 | struct mlx5_eswitch_rep *rep); | |
833 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
834 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
835 | struct mlx5_eswitch_rep *rep); | |
836 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
837 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
838 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
839 | ||
840 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
841 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
842 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
843 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
844 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
845 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
846 | int mlx5e_close(struct net_device *netdev); | |
847 | int mlx5e_open(struct net_device *netdev); | |
848 | void mlx5e_update_stats_work(struct work_struct *work); | |
26e59d80 MHY |
849 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
850 | const struct mlx5e_profile *profile, | |
851 | void *ppriv); | |
cb67b832 | 852 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); |
26e59d80 MHY |
853 | int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); |
854 | void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); | |
cb67b832 HHZ |
855 | struct rtnl_link_stats64 * |
856 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); | |
857 | ||
1afff42c | 858 | #endif /* __MLX5_EN_H__ */ |