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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 47 | #include <linux/mlx5/fs.h> |
e8f887ac | 48 | #include <linux/rhashtable.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4f75da36 | 51 | #include <linux/dim.h> |
8ff57c18 | 52 | #include <linux/bits.h> |
f62b8bb8 | 53 | #include "wq.h" |
f62b8bb8 | 54 | #include "mlx5_core.h" |
9218b44d | 55 | #include "en_stats.h" |
fe6d86b3 | 56 | #include "en/fs.h" |
f62b8bb8 | 57 | |
4d8fcf21 | 58 | extern const struct net_device_ops mlx5e_netdev_ops; |
60bbf7ee JDB |
59 | struct page_pool; |
60 | ||
bb909416 IL |
61 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
62 | #define MLX5E_METADATA_ETHER_LEN 8 | |
63 | ||
1cabe6b0 MG |
64 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
65 | ||
c139dbfd ES |
66 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
67 | ||
472a1e44 TT |
68 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
69 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 70 | |
0696d608 | 71 | #define MLX5E_MAX_PRIORITY 8 |
2a5e7a13 | 72 | #define MLX5E_MAX_DSCP 64 |
f62b8bb8 AV |
73 | #define MLX5E_MAX_NUM_TC 8 |
74 | ||
1bfecfca | 75 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
76 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
77 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 78 | |
94816278 TT |
79 | #define MLX5E_RX_MAX_HEAD (256) |
80 | ||
f32f5bd2 DJ |
81 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
82 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
83 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
84 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
94816278 TT |
85 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ |
86 | MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) | |
f32f5bd2 | 87 | |
7e426671 | 88 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
89 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
90 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
91 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
92 | |
93 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
73281b78 | 94 | #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) |
b8a98a4c | 95 | #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS)) |
73281b78 TT |
96 | #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) |
97 | #define MLX5E_MAX_RQ_NUM_MTTS \ | |
98 | ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ | |
99 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) | |
100 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ | |
101 | (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) | |
102 | #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ | |
103 | (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ | |
104 | (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) | |
105 | ||
069d1146 TT |
106 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
107 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
108 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
109 | ||
73281b78 TT |
110 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
111 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
112 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
113 | ||
069d1146 | 114 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 TT |
115 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
116 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ | |
117 | MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) | |
118 | ||
119 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 120 | |
d9a40271 | 121 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
122 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
123 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
124 | ||
f62b8bb8 | 125 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 126 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
127 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
128 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 129 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
130 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
131 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 132 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 133 | |
936896e9 AS |
134 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
135 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 136 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 137 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 138 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 | 139 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
db05815b | 140 | #define MLX5E_TX_XSK_POLL_BUDGET 64 |
db75373c | 141 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 142 | |
ea3886ca TT |
143 | #define MLX5E_UMR_WQE_INLINE_SZ \ |
144 | (sizeof(struct mlx5e_umr_wqe) + \ | |
145 | ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ | |
146 | MLX5_UMR_MTT_ALIGNMENT)) | |
147 | #define MLX5E_UMR_WQEBBS \ | |
148 | (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) | |
2f48af12 | 149 | |
79c48764 GP |
150 | #define MLX5E_MSG_LEVEL NETIF_MSG_LINK |
151 | ||
152 | #define mlx5e_dbg(mlevel, priv, format, ...) \ | |
153 | do { \ | |
154 | if (NETIF_MSG_##mlevel & (priv)->msglevel) \ | |
155 | netdev_warn(priv->netdev, format, \ | |
156 | ##__VA_ARGS__); \ | |
157 | } while (0) | |
158 | ||
db05815b MM |
159 | enum mlx5e_rq_group { |
160 | MLX5E_RQ_GROUP_REGULAR, | |
161 | MLX5E_RQ_GROUP_XSK, | |
694826e3 | 162 | #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g) |
db05815b | 163 | }; |
79c48764 | 164 | |
461017cb TT |
165 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
166 | { | |
167 | switch (wq_type) { | |
168 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
169 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
170 | wq_size / 2); | |
171 | default: | |
172 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
173 | wq_size / 2); | |
174 | } | |
175 | } | |
176 | ||
779d986d | 177 | /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ |
48935bbb SM |
178 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
179 | { | |
180 | return is_kdump_kernel() ? | |
181 | MLX5E_MIN_NUM_CHANNELS : | |
f2f3df55 | 182 | min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS); |
48935bbb SM |
183 | } |
184 | ||
2f48af12 TT |
185 | struct mlx5e_tx_wqe { |
186 | struct mlx5_wqe_ctrl_seg ctrl; | |
a9bc3390 TT |
187 | union { |
188 | struct { | |
189 | struct mlx5_wqe_eth_seg eth; | |
190 | struct mlx5_wqe_data_seg data[0]; | |
191 | }; | |
192 | u8 tls_progress_params_ctx[0]; | |
193 | }; | |
2f48af12 TT |
194 | }; |
195 | ||
99cbfa93 | 196 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 197 | struct mlx5_wqe_srq_next_seg next; |
99cbfa93 TT |
198 | struct mlx5_wqe_data_seg data[0]; |
199 | }; | |
200 | ||
201 | struct mlx5e_rx_wqe_cyc { | |
202 | struct mlx5_wqe_data_seg data[0]; | |
2f48af12 | 203 | }; |
86d722ad | 204 | |
bc77b240 TT |
205 | struct mlx5e_umr_wqe { |
206 | struct mlx5_wqe_ctrl_seg ctrl; | |
207 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
208 | struct mlx5_mkey_seg mkc; | |
d2ead1f3 TT |
209 | union { |
210 | struct mlx5_mtt inline_mtts[0]; | |
211 | u8 tls_static_params_ctx[0]; | |
212 | }; | |
bc77b240 TT |
213 | }; |
214 | ||
d605d668 KH |
215 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
216 | ||
4e59e288 | 217 | enum mlx5e_priv_flag { |
8ff57c18 TT |
218 | MLX5E_PFLAG_RX_CQE_BASED_MODER, |
219 | MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
220 | MLX5E_PFLAG_RX_CQE_COMPRESS, | |
221 | MLX5E_PFLAG_RX_STRIDING_RQ, | |
222 | MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, | |
6277053a | 223 | MLX5E_PFLAG_XDP_TX_MPWQE, |
8ff57c18 | 224 | MLX5E_NUM_PFLAGS, /* Keep last */ |
4e59e288 GP |
225 | }; |
226 | ||
6a9764ef | 227 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
228 | do { \ |
229 | if (enable) \ | |
8ff57c18 | 230 | (params)->pflags |= BIT(pflag); \ |
59ece1c9 | 231 | else \ |
8ff57c18 | 232 | (params)->pflags &= ~(BIT(pflag)); \ |
4e59e288 GP |
233 | } while (0) |
234 | ||
8ff57c18 | 235 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) |
59ece1c9 | 236 | |
08fb1dac SM |
237 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
238 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
239 | #endif |
240 | ||
f62b8bb8 AV |
241 | struct mlx5e_params { |
242 | u8 log_sq_size; | |
461017cb | 243 | u8 rq_wq_type; |
73281b78 | 244 | u8 log_rq_mtu_frames; |
f62b8bb8 | 245 | u16 num_channels; |
f62b8bb8 | 246 | u8 num_tc; |
9bcc8606 | 247 | bool rx_cqe_compress_def; |
69dad68d | 248 | bool tunneled_offload_en; |
8960b389 TG |
249 | struct dim_cq_moder rx_cq_moderation; |
250 | struct dim_cq_moder tx_cq_moderation; | |
f62b8bb8 | 251 | bool lro_en; |
cff92d7c | 252 | u8 tx_min_inline_mode; |
36350114 | 253 | bool vlan_strip_disable; |
102722fc | 254 | bool scatter_fcs_en; |
9a317425 | 255 | bool rx_dim_enabled; |
cbce4f44 | 256 | bool tx_dim_enabled; |
2b029556 | 257 | u32 lro_timeout; |
59ece1c9 | 258 | u32 pflags; |
6a9764ef | 259 | struct bpf_prog *xdp_prog; |
db05815b | 260 | struct mlx5e_xsk *xsk; |
472a1e44 TT |
261 | unsigned int sw_mtu; |
262 | int hard_mtu; | |
f62b8bb8 AV |
263 | }; |
264 | ||
3a6a931d HN |
265 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
266 | struct mlx5e_cee_config { | |
267 | /* bw pct for priority group */ | |
268 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
269 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
270 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
271 | bool pfc_enable; | |
272 | }; | |
273 | ||
274 | enum { | |
275 | MLX5_DCB_CHG_RESET, | |
276 | MLX5_DCB_NO_CHG, | |
277 | MLX5_DCB_CHG_NO_RESET, | |
278 | }; | |
279 | ||
280 | struct mlx5e_dcbx { | |
e207b7e9 | 281 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 282 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
2a5e7a13 | 283 | u8 dscp_app_cnt; |
820c2c5e HN |
284 | |
285 | /* The only setting that cannot be read from FW */ | |
286 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
9e10bf1d | 287 | u8 cap; |
0696d608 HN |
288 | |
289 | /* Buffer configuration */ | |
ecdf2dad | 290 | bool manual_buffer; |
0696d608 HN |
291 | u32 cable_len; |
292 | u32 xoff; | |
3a6a931d | 293 | }; |
2a5e7a13 HN |
294 | |
295 | struct mlx5e_dcbx_dp { | |
296 | u8 dscp2prio[MLX5E_MAX_DSCP]; | |
297 | u8 trust_state; | |
298 | }; | |
3a6a931d HN |
299 | #endif |
300 | ||
f62b8bb8 | 301 | enum { |
c0f1147d | 302 | MLX5E_RQ_STATE_ENABLED, |
8276ea13 | 303 | MLX5E_RQ_STATE_RECOVERING, |
cb3c7fd4 | 304 | MLX5E_RQ_STATE_AM, |
b856df28 | 305 | MLX5E_RQ_STATE_NO_CSUM_COMPLETE, |
db849faa | 306 | MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ |
f62b8bb8 AV |
307 | }; |
308 | ||
f62b8bb8 AV |
309 | struct mlx5e_cq { |
310 | /* data path - accessed per cqe */ | |
311 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
312 | |
313 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 314 | u16 event_ctr; |
f62b8bb8 AV |
315 | struct napi_struct *napi; |
316 | struct mlx5_core_cq mcq; | |
317 | struct mlx5e_channel *channel; | |
318 | ||
79d356ef TT |
319 | /* control */ |
320 | struct mlx5_core_dev *mdev; | |
321 | struct mlx5_wq_ctrl wq_ctrl; | |
322 | } ____cacheline_aligned_in_smp; | |
323 | ||
324 | struct mlx5e_cq_decomp { | |
7219ab34 TT |
325 | /* cqe decompression */ |
326 | struct mlx5_cqe64 title; | |
327 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
328 | u8 mini_arr_idx; | |
79d356ef TT |
329 | u16 left; |
330 | u16 wqe_counter; | |
f62b8bb8 AV |
331 | } ____cacheline_aligned_in_smp; |
332 | ||
eba2db2b | 333 | struct mlx5e_tx_wqe_info { |
77bdf895 | 334 | struct sk_buff *skb; |
eba2db2b SM |
335 | u32 num_bytes; |
336 | u8 num_wqebbs; | |
337 | u8 num_dma; | |
d2ead1f3 TT |
338 | #ifdef CONFIG_MLX5_EN_TLS |
339 | skb_frag_t *resync_dump_frag; | |
340 | #endif | |
eba2db2b SM |
341 | }; |
342 | ||
343 | enum mlx5e_dma_map_type { | |
344 | MLX5E_DMA_MAP_SINGLE, | |
345 | MLX5E_DMA_MAP_PAGE | |
346 | }; | |
347 | ||
348 | struct mlx5e_sq_dma { | |
349 | dma_addr_t addr; | |
350 | u32 size; | |
351 | enum mlx5e_dma_map_type type; | |
352 | }; | |
353 | ||
354 | enum { | |
355 | MLX5E_SQ_STATE_ENABLED, | |
db75373c | 356 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 357 | MLX5E_SQ_STATE_IPSEC, |
cbce4f44 | 358 | MLX5E_SQ_STATE_AM, |
bf239741 | 359 | MLX5E_SQ_STATE_TLS, |
b431302e | 360 | MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, |
eba2db2b SM |
361 | }; |
362 | ||
363 | struct mlx5e_sq_wqe_info { | |
364 | u8 opcode; | |
ed084fb6 MM |
365 | |
366 | /* Auxiliary data for different opcodes. */ | |
367 | union { | |
368 | struct { | |
369 | struct mlx5e_rq *rq; | |
370 | } umr; | |
371 | }; | |
eba2db2b | 372 | }; |
2f48af12 | 373 | |
31391048 | 374 | struct mlx5e_txqsq { |
eba2db2b SM |
375 | /* data path */ |
376 | ||
377 | /* dirtied @completion */ | |
378 | u16 cc; | |
379 | u32 dma_fifo_cc; | |
8960b389 | 380 | struct dim dim; /* Adaptive Moderation */ |
eba2db2b SM |
381 | |
382 | /* dirtied @xmit */ | |
383 | u16 pc ____cacheline_aligned_in_smp; | |
384 | u32 dma_fifo_pc; | |
eba2db2b SM |
385 | |
386 | struct mlx5e_cq cq; | |
387 | ||
eba2db2b SM |
388 | /* read only */ |
389 | struct mlx5_wq_cyc wq; | |
390 | u32 dma_fifo_mask; | |
05909bab | 391 | struct mlx5e_sq_stats *stats; |
9a3956da TT |
392 | struct { |
393 | struct mlx5e_sq_dma *dma_fifo; | |
394 | struct mlx5e_tx_wqe_info *wqe_info; | |
395 | } db; | |
eba2db2b SM |
396 | void __iomem *uar_map; |
397 | struct netdev_queue *txq; | |
398 | u32 sqn; | |
01614d4f | 399 | u16 stop_room; |
eba2db2b | 400 | u8 min_inline_mode; |
eba2db2b | 401 | struct device *pdev; |
eba2db2b SM |
402 | __be32 mkey_be; |
403 | unsigned long state; | |
7c39afb3 FD |
404 | struct hwtstamp_config *tstamp; |
405 | struct mlx5_clock *clock; | |
eba2db2b SM |
406 | |
407 | /* control path */ | |
408 | struct mlx5_wq_ctrl wq_ctrl; | |
409 | struct mlx5e_channel *channel; | |
57c70d87 | 410 | int ch_ix; |
acc6c595 | 411 | int txq_ix; |
eba2db2b | 412 | u32 rate_limit; |
de8650a8 | 413 | struct work_struct recover_work; |
31391048 SM |
414 | } ____cacheline_aligned_in_smp; |
415 | ||
c94e4f11 | 416 | struct mlx5e_dma_info { |
db05815b MM |
417 | dma_addr_t addr; |
418 | union { | |
419 | struct page *page; | |
420 | struct { | |
421 | u64 handle; | |
422 | void *data; | |
423 | } xsk; | |
424 | }; | |
c94e4f11 TT |
425 | }; |
426 | ||
d963fa15 MM |
427 | /* XDP packets can be transmitted in different ways. On completion, we need to |
428 | * distinguish between them to clean up things in a proper way. | |
429 | */ | |
430 | enum mlx5e_xdp_xmit_mode { | |
431 | /* An xdp_frame was transmitted due to either XDP_REDIRECT from another | |
432 | * device or XDP_TX from an XSK RQ. The frame has to be unmapped and | |
433 | * returned. | |
434 | */ | |
435 | MLX5E_XDP_XMIT_MODE_FRAME, | |
436 | ||
437 | /* The xdp_frame was created in place as a result of XDP_TX from a | |
438 | * regular RQ. No DMA remapping happened, and the page belongs to us. | |
439 | */ | |
440 | MLX5E_XDP_XMIT_MODE_PAGE, | |
441 | ||
442 | /* No xdp_frame was created at all, the transmit happened from a UMEM | |
443 | * page. The UMEM Completion Ring producer pointer has to be increased. | |
444 | */ | |
445 | MLX5E_XDP_XMIT_MODE_XSK, | |
c94e4f11 TT |
446 | }; |
447 | ||
448 | struct mlx5e_xdp_info { | |
d963fa15 MM |
449 | enum mlx5e_xdp_xmit_mode mode; |
450 | union { | |
451 | struct { | |
452 | struct xdp_frame *xdpf; | |
453 | dma_addr_t dma_addr; | |
454 | } frame; | |
455 | struct { | |
b9673cf5 | 456 | struct mlx5e_rq *rq; |
d963fa15 MM |
457 | struct mlx5e_dma_info di; |
458 | } page; | |
459 | }; | |
460 | }; | |
461 | ||
462 | struct mlx5e_xdp_xmit_data { | |
463 | dma_addr_t dma_addr; | |
464 | void *data; | |
465 | u32 len; | |
c94e4f11 TT |
466 | }; |
467 | ||
fea28dd6 TT |
468 | struct mlx5e_xdp_info_fifo { |
469 | struct mlx5e_xdp_info *xi; | |
470 | u32 *cc; | |
471 | u32 *pc; | |
472 | u32 mask; | |
473 | }; | |
474 | ||
1feeab80 TT |
475 | struct mlx5e_xdp_wqe_info { |
476 | u8 num_wqebbs; | |
c2273219 | 477 | u8 num_pkts; |
1feeab80 TT |
478 | }; |
479 | ||
5e0d2eef TT |
480 | struct mlx5e_xdp_mpwqe { |
481 | /* Current MPWQE session */ | |
482 | struct mlx5e_tx_wqe *wqe; | |
483 | u8 ds_count; | |
c2273219 | 484 | u8 pkt_count; |
c2273219 | 485 | u8 inline_on; |
5e0d2eef TT |
486 | }; |
487 | ||
488 | struct mlx5e_xdpsq; | |
db05815b | 489 | typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); |
d963fa15 MM |
490 | typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, |
491 | struct mlx5e_xdp_xmit_data *, | |
db05815b MM |
492 | struct mlx5e_xdp_info *, |
493 | int); | |
d963fa15 | 494 | |
31391048 SM |
495 | struct mlx5e_xdpsq { |
496 | /* data path */ | |
497 | ||
dac0d15f | 498 | /* dirtied @completion */ |
fea28dd6 | 499 | u32 xdpi_fifo_cc; |
31391048 | 500 | u16 cc; |
31391048 | 501 | |
dac0d15f | 502 | /* dirtied @xmit */ |
fea28dd6 TT |
503 | u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; |
504 | u16 pc; | |
b8180392 | 505 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
5e0d2eef | 506 | struct mlx5e_xdp_mpwqe mpwqe; |
31391048 | 507 | |
dac0d15f | 508 | struct mlx5e_cq cq; |
31391048 SM |
509 | |
510 | /* read only */ | |
db05815b | 511 | struct xdp_umem *umem; |
31391048 | 512 | struct mlx5_wq_cyc wq; |
890388ad | 513 | struct mlx5e_xdpsq_stats *stats; |
db05815b | 514 | mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; |
5e0d2eef | 515 | mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; |
dac0d15f | 516 | struct { |
1feeab80 | 517 | struct mlx5e_xdp_wqe_info *wqe_info; |
fea28dd6 | 518 | struct mlx5e_xdp_info_fifo xdpi_fifo; |
dac0d15f | 519 | } db; |
31391048 SM |
520 | void __iomem *uar_map; |
521 | u32 sqn; | |
522 | struct device *pdev; | |
523 | __be32 mkey_be; | |
524 | u8 min_inline_mode; | |
525 | unsigned long state; | |
c94e4f11 | 526 | unsigned int hw_mtu; |
31391048 SM |
527 | |
528 | /* control path */ | |
529 | struct mlx5_wq_ctrl wq_ctrl; | |
530 | struct mlx5e_channel *channel; | |
531 | } ____cacheline_aligned_in_smp; | |
532 | ||
533 | struct mlx5e_icosq { | |
534 | /* data path */ | |
fd9b4be8 TT |
535 | u16 cc; |
536 | u16 pc; | |
31391048 | 537 | |
fd9b4be8 | 538 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
31391048 SM |
539 | struct mlx5e_cq cq; |
540 | ||
541 | /* write@xmit, read@completion */ | |
542 | struct { | |
543 | struct mlx5e_sq_wqe_info *ico_wqe; | |
544 | } db; | |
545 | ||
546 | /* read only */ | |
547 | struct mlx5_wq_cyc wq; | |
548 | void __iomem *uar_map; | |
549 | u32 sqn; | |
31391048 SM |
550 | unsigned long state; |
551 | ||
552 | /* control path */ | |
553 | struct mlx5_wq_ctrl wq_ctrl; | |
554 | struct mlx5e_channel *channel; | |
be5323c8 AL |
555 | |
556 | struct work_struct recover_work; | |
eba2db2b SM |
557 | } ____cacheline_aligned_in_smp; |
558 | ||
accd5883 | 559 | struct mlx5e_wqe_frag_info { |
069d1146 | 560 | struct mlx5e_dma_info *di; |
accd5883 | 561 | u32 offset; |
069d1146 | 562 | bool last_in_page; |
accd5883 TT |
563 | }; |
564 | ||
eba2db2b | 565 | struct mlx5e_umr_dma_info { |
eba2db2b | 566 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
eba2db2b SM |
567 | }; |
568 | ||
569 | struct mlx5e_mpw_info { | |
570 | struct mlx5e_umr_dma_info umr; | |
571 | u16 consumed_strides; | |
22f45398 | 572 | DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
eba2db2b SM |
573 | }; |
574 | ||
069d1146 TT |
575 | #define MLX5E_MAX_RX_FRAGS 4 |
576 | ||
4415a031 TT |
577 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
578 | * or a MPWQE (for striding rq). | |
579 | */ | |
580 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
581 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
29c2849e | 582 | #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) |
4415a031 TT |
583 | struct mlx5e_page_cache { |
584 | u32 head; | |
585 | u32 tail; | |
586 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
587 | }; | |
588 | ||
eba2db2b SM |
589 | struct mlx5e_rq; |
590 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
591 | typedef struct sk_buff * |
592 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
593 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
594 | typedef struct sk_buff * |
595 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
596 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
7cc6d77b | 597 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b SM |
598 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
599 | ||
121e8927 | 600 | enum mlx5e_rq_flag { |
f03590f7 | 601 | MLX5E_RQ_FLAG_XDP_XMIT, |
15143bf5 | 602 | MLX5E_RQ_FLAG_XDP_REDIRECT, |
121e8927 TT |
603 | }; |
604 | ||
069d1146 TT |
605 | struct mlx5e_rq_frag_info { |
606 | int frag_size; | |
607 | int frag_stride; | |
608 | }; | |
609 | ||
610 | struct mlx5e_rq_frags_info { | |
611 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
612 | u8 num_frags; | |
613 | u8 log_num_frags; | |
614 | u8 wqe_bulk; | |
615 | }; | |
616 | ||
f62b8bb8 AV |
617 | struct mlx5e_rq { |
618 | /* data path */ | |
21c59685 | 619 | union { |
accd5883 | 620 | struct { |
069d1146 TT |
621 | struct mlx5_wq_cyc wq; |
622 | struct mlx5e_wqe_frag_info *frags; | |
623 | struct mlx5e_dma_info *di; | |
624 | struct mlx5e_rq_frags_info info; | |
625 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 626 | } wqe; |
21c59685 | 627 | struct { |
422d4c40 | 628 | struct mlx5_wq_ll wq; |
b8a98a4c | 629 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 630 | struct mlx5e_mpw_info *info; |
619a8f2a | 631 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
b45d8b50 | 632 | u16 num_strides; |
fd9b4be8 | 633 | u16 actual_wq_head; |
89e89f7a | 634 | u8 log_stride_sz; |
fd9b4be8 TT |
635 | u8 umr_in_progress; |
636 | u8 umr_last_bulk; | |
ed084fb6 | 637 | u8 umr_completed; |
21c59685 SM |
638 | } mpwqe; |
639 | }; | |
1bfecfca | 640 | struct { |
db05815b | 641 | u16 umem_headroom; |
b45d8b50 | 642 | u16 headroom; |
b5503b99 | 643 | u8 map_dir; /* dma map direction */ |
1bfecfca | 644 | } buff; |
f62b8bb8 | 645 | |
7cc6d77b | 646 | struct mlx5e_channel *channel; |
f62b8bb8 AV |
647 | struct device *pdev; |
648 | struct net_device *netdev; | |
05909bab | 649 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 650 | struct mlx5e_cq cq; |
79d356ef | 651 | struct mlx5e_cq_decomp cqd; |
4415a031 | 652 | struct mlx5e_page_cache page_cache; |
7c39afb3 FD |
653 | struct hwtstamp_config *tstamp; |
654 | struct mlx5_clock *clock; | |
4415a031 | 655 | |
2f48af12 | 656 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 657 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 658 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
659 | |
660 | unsigned long state; | |
661 | int ix; | |
0073c8f7 | 662 | unsigned int hw_mtu; |
f62b8bb8 | 663 | |
8960b389 | 664 | struct dim dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
665 | |
666 | /* XDP */ | |
86994156 | 667 | struct bpf_prog *xdp_prog; |
b9673cf5 | 668 | struct mlx5e_xdpsq *xdpsq; |
121e8927 | 669 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 670 | struct page_pool *page_pool; |
cb3c7fd4 | 671 | |
db05815b MM |
672 | /* AF_XDP zero-copy */ |
673 | struct zero_copy_allocator zca; | |
674 | struct xdp_umem *umem; | |
675 | ||
8276ea13 AL |
676 | struct work_struct recover_work; |
677 | ||
f62b8bb8 AV |
678 | /* control */ |
679 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 680 | __be32 mkey_be; |
461017cb | 681 | u8 wq_type; |
f62b8bb8 | 682 | u32 rqn; |
a43b25da | 683 | struct mlx5_core_dev *mdev; |
ec8b9981 | 684 | struct mlx5_core_mkey umr_mkey; |
0ddf5432 JDB |
685 | |
686 | /* XDP read-mostly */ | |
687 | struct xdp_rxq_info xdp_rxq; | |
f62b8bb8 AV |
688 | } ____cacheline_aligned_in_smp; |
689 | ||
db05815b MM |
690 | enum mlx5e_channel_state { |
691 | MLX5E_CHANNEL_STATE_XSK, | |
692 | MLX5E_CHANNEL_NUM_STATES | |
693 | }; | |
694 | ||
f62b8bb8 AV |
695 | struct mlx5e_channel { |
696 | /* data path */ | |
697 | struct mlx5e_rq rq; | |
b9673cf5 | 698 | struct mlx5e_xdpsq rq_xdpsq; |
31391048 SM |
699 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
700 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 701 | bool xdp; |
f62b8bb8 AV |
702 | struct napi_struct napi; |
703 | struct device *pdev; | |
704 | struct net_device *netdev; | |
705 | __be32 mkey_be; | |
706 | u8 num_tc; | |
f62b8bb8 | 707 | |
58b99ee3 TT |
708 | /* XDP_REDIRECT */ |
709 | struct mlx5e_xdpsq xdpsq; | |
710 | ||
db05815b MM |
711 | /* AF_XDP zero-copy */ |
712 | struct mlx5e_rq xskrq; | |
713 | struct mlx5e_xdpsq xsksq; | |
714 | struct mlx5e_icosq xskicosq; | |
715 | /* xskicosq can be accessed from any CPU - the spinlock protects it. */ | |
716 | spinlock_t xskicosq_lock; | |
717 | ||
a8c2eb15 TT |
718 | /* data path - accessed per napi poll */ |
719 | struct irq_desc *irq_desc; | |
05909bab | 720 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
721 | |
722 | /* control */ | |
723 | struct mlx5e_priv *priv; | |
a43b25da | 724 | struct mlx5_core_dev *mdev; |
7c39afb3 | 725 | struct hwtstamp_config *tstamp; |
db05815b | 726 | DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); |
f62b8bb8 | 727 | int ix; |
231243c8 | 728 | int cpu; |
149e566f | 729 | cpumask_var_t xps_cpumask; |
f62b8bb8 AV |
730 | }; |
731 | ||
ff9c852f SM |
732 | struct mlx5e_channels { |
733 | struct mlx5e_channel **c; | |
734 | unsigned int num; | |
6a9764ef | 735 | struct mlx5e_params params; |
ff9c852f SM |
736 | }; |
737 | ||
05909bab EBE |
738 | struct mlx5e_channel_stats { |
739 | struct mlx5e_ch_stats ch; | |
740 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
741 | struct mlx5e_rq_stats rq; | |
db05815b | 742 | struct mlx5e_rq_stats xskrq; |
890388ad | 743 | struct mlx5e_xdpsq_stats rq_xdpsq; |
58b99ee3 | 744 | struct mlx5e_xdpsq_stats xdpsq; |
db05815b | 745 | struct mlx5e_xdpsq_stats xsksq; |
05909bab EBE |
746 | } ____cacheline_aligned_in_smp; |
747 | ||
acff797c | 748 | enum { |
acff797c MG |
749 | MLX5E_STATE_OPENED, |
750 | MLX5E_STATE_DESTROYING, | |
407e17b1 | 751 | MLX5E_STATE_XDP_TX_ENABLED, |
db05815b | 752 | MLX5E_STATE_XDP_OPEN, |
acff797c MG |
753 | }; |
754 | ||
398f3351 | 755 | struct mlx5e_rqt { |
1da36696 | 756 | u32 rqtn; |
398f3351 HHZ |
757 | bool enabled; |
758 | }; | |
759 | ||
760 | struct mlx5e_tir { | |
761 | u32 tirn; | |
762 | struct mlx5e_rqt rqt; | |
763 | struct list_head list; | |
1da36696 TT |
764 | }; |
765 | ||
acff797c MG |
766 | enum { |
767 | MLX5E_TC_PRIO = 0, | |
768 | MLX5E_NIC_PRIO | |
769 | }; | |
770 | ||
bbeb53b8 AL |
771 | struct mlx5e_rss_params { |
772 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
756c4160 | 773 | u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS]; |
bbeb53b8 AL |
774 | u8 toeplitz_hash_key[40]; |
775 | u8 hfunc; | |
776 | }; | |
777 | ||
de8650a8 EBE |
778 | struct mlx5e_modify_sq_param { |
779 | int curr_state; | |
780 | int next_state; | |
781 | int rl_update; | |
782 | int rl_index; | |
783 | }; | |
784 | ||
db05815b MM |
785 | struct mlx5e_xsk { |
786 | /* UMEMs are stored separately from channels, because we don't want to | |
787 | * lose them when channels are recreated. The kernel also stores UMEMs, | |
788 | * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs, | |
789 | * so rely on our mechanism. | |
790 | */ | |
791 | struct xdp_umem **umems; | |
792 | u16 refcnt; | |
793 | bool ever_used; | |
794 | }; | |
795 | ||
f62b8bb8 AV |
796 | struct mlx5e_priv { |
797 | /* priv data path fields - start */ | |
acc6c595 SM |
798 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
799 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
2a5e7a13 HN |
800 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
801 | struct mlx5e_dcbx_dp dcbx_dp; | |
802 | #endif | |
f62b8bb8 AV |
803 | /* priv data path fields - end */ |
804 | ||
79c48764 | 805 | u32 msglevel; |
f62b8bb8 AV |
806 | unsigned long state; |
807 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 808 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 809 | |
ff9c852f | 810 | struct mlx5e_channels channels; |
f62b8bb8 | 811 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 812 | struct mlx5e_rqt indir_rqt; |
724b2aa1 | 813 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
7b3722fa | 814 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; |
724b2aa1 | 815 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; |
db05815b | 816 | struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS]; |
bbeb53b8 | 817 | struct mlx5e_rss_params rss_params; |
507f0c81 | 818 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 819 | |
acff797c | 820 | struct mlx5e_flow_steering fs; |
f62b8bb8 | 821 | |
7bb29755 | 822 | struct workqueue_struct *wq; |
f62b8bb8 AV |
823 | struct work_struct update_carrier_work; |
824 | struct work_struct set_rx_mode_work; | |
3947ca18 | 825 | struct work_struct tx_timeout_work; |
cdeef2b1 | 826 | struct work_struct update_stats_work; |
5c7e8bbb ED |
827 | struct work_struct monitor_counters_work; |
828 | struct mlx5_nb monitor_counters_nb; | |
f62b8bb8 AV |
829 | |
830 | struct mlx5_core_dev *mdev; | |
831 | struct net_device *netdev; | |
832 | struct mlx5e_stats stats; | |
05909bab | 833 | struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS]; |
694826e3 | 834 | u16 max_nch; |
05909bab | 835 | u8 max_opened_tc; |
7c39afb3 | 836 | struct hwtstamp_config tstamp; |
7cbaf9a3 MS |
837 | u16 q_counter; |
838 | u16 drop_rq_q_counter; | |
7cffaddd SM |
839 | struct notifier_block events_nb; |
840 | ||
3a6a931d HN |
841 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
842 | struct mlx5e_dcbx dcbx; | |
843 | #endif | |
844 | ||
6bfd390b | 845 | const struct mlx5e_profile *profile; |
127ea380 | 846 | void *ppriv; |
547eede0 IT |
847 | #ifdef CONFIG_MLX5_EN_IPSEC |
848 | struct mlx5e_ipsec *ipsec; | |
849 | #endif | |
43585a41 IL |
850 | #ifdef CONFIG_MLX5_EN_TLS |
851 | struct mlx5e_tls *tls; | |
852 | #endif | |
de8650a8 | 853 | struct devlink_health_reporter *tx_reporter; |
9032e719 | 854 | struct devlink_health_reporter *rx_reporter; |
db05815b | 855 | struct mlx5e_xsk xsk; |
f62b8bb8 AV |
856 | }; |
857 | ||
a43b25da | 858 | struct mlx5e_profile { |
182570b2 | 859 | int (*init)(struct mlx5_core_dev *mdev, |
a43b25da SM |
860 | struct net_device *netdev, |
861 | const struct mlx5e_profile *profile, void *ppriv); | |
862 | void (*cleanup)(struct mlx5e_priv *priv); | |
863 | int (*init_rx)(struct mlx5e_priv *priv); | |
864 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
865 | int (*init_tx)(struct mlx5e_priv *priv); | |
866 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
867 | void (*enable)(struct mlx5e_priv *priv); | |
868 | void (*disable)(struct mlx5e_priv *priv); | |
a90f88fe | 869 | int (*update_rx)(struct mlx5e_priv *priv); |
a43b25da | 870 | void (*update_stats)(struct mlx5e_priv *priv); |
7ca42c80 | 871 | void (*update_carrier)(struct mlx5e_priv *priv); |
20fd0c19 SM |
872 | struct { |
873 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
874 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
875 | } rx_handlers; | |
a43b25da | 876 | int max_tc; |
694826e3 | 877 | u8 rq_groups; |
a43b25da SM |
878 | }; |
879 | ||
665bc539 GP |
880 | void mlx5e_build_ptys2ethtool_map(void); |
881 | ||
f62b8bb8 | 882 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
a350ecce | 883 | struct net_device *sb_dev); |
f62b8bb8 | 884 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); |
bf239741 | 885 | netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
3c31ff22 | 886 | struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more); |
f62b8bb8 | 887 | |
63d26b49 | 888 | void mlx5e_trigger_irq(struct mlx5e_icosq *sq); |
4e0e2ea1 | 889 | void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe); |
f62b8bb8 AV |
890 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); |
891 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 892 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 893 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
31391048 | 894 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
461017cb | 895 | |
9032e719 AL |
896 | static inline u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq) |
897 | { | |
898 | switch (rq->wq_type) { | |
899 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
900 | return mlx5_wq_ll_get_size(&rq->mpwqe.wq); | |
901 | default: | |
902 | return mlx5_wq_cyc_get_size(&rq->wqe.wq); | |
903 | } | |
904 | } | |
905 | ||
906 | static inline u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq) | |
907 | { | |
908 | switch (rq->wq_type) { | |
909 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
910 | return rq->mpwqe.wq.cur_sz; | |
911 | default: | |
912 | return rq->wqe.wq.cur_sz; | |
913 | } | |
914 | } | |
915 | ||
2ccb0a79 TT |
916 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); |
917 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, | |
918 | struct mlx5e_params *params); | |
919 | ||
159d2131 | 920 | void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info); |
db05815b MM |
921 | void mlx5e_page_release_dynamic(struct mlx5e_rq *rq, |
922 | struct mlx5e_dma_info *dma_info, | |
923 | bool recycle); | |
2f48af12 | 924 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 925 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 926 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
ed084fb6 | 927 | void mlx5e_poll_ico_cq(struct mlx5e_cq *cq); |
7cc6d77b | 928 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); |
6cd392a0 DJ |
929 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
930 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
619a8f2a TT |
931 | struct sk_buff * |
932 | mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
933 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
934 | struct sk_buff * | |
935 | mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
936 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
937 | struct sk_buff * |
938 | mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
939 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
940 | struct sk_buff * | |
941 | mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
942 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
f62b8bb8 | 943 | |
19386177 | 944 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
d9ee0491 | 945 | void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); |
b832d4fd | 946 | void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); |
f62b8bb8 | 947 | |
33cfaaa8 | 948 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
d605d668 KH |
949 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
950 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
951 | u64 *buf); | |
f62b8bb8 AV |
952 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
953 | ||
1170fbd8 FD |
954 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
955 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 956 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 957 | |
f62b8bb8 AV |
958 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
959 | u16 vid); | |
960 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
961 | u16 vid); | |
237f258c | 962 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 963 | |
a5f97fee SM |
964 | struct mlx5e_redirect_rqt_param { |
965 | bool is_rss; | |
966 | union { | |
967 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
968 | struct { | |
969 | u8 hfunc; | |
970 | struct mlx5e_channels *channels; | |
971 | } rss; /* RSS data */ | |
972 | }; | |
973 | }; | |
974 | ||
975 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
976 | struct mlx5e_redirect_rqt_param rrp); | |
bbeb53b8 | 977 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params, |
d930ac79 | 978 | const struct mlx5e_tirc_config *ttconfig, |
7b3722fa | 979 | void *tirc, bool inner); |
080d1b17 | 980 | void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen); |
d930ac79 | 981 | struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt); |
2d75b2bc | 982 | |
db05815b MM |
983 | struct mlx5e_xsk_param; |
984 | ||
985 | struct mlx5e_rq_param; | |
986 | int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params, | |
987 | struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk, | |
988 | struct xdp_umem *umem, struct mlx5e_rq *rq); | |
989 | int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); | |
990 | void mlx5e_deactivate_rq(struct mlx5e_rq *rq); | |
991 | void mlx5e_close_rq(struct mlx5e_rq *rq); | |
992 | ||
993 | struct mlx5e_sq_param; | |
994 | int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, | |
995 | struct mlx5e_sq_param *param, struct mlx5e_icosq *sq); | |
996 | void mlx5e_close_icosq(struct mlx5e_icosq *sq); | |
997 | int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, | |
998 | struct mlx5e_sq_param *param, struct xdp_umem *umem, | |
999 | struct mlx5e_xdpsq *sq, bool is_redirect); | |
1000 | void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); | |
1001 | ||
1002 | struct mlx5e_cq_param; | |
c4cde580 | 1003 | int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder, |
db05815b MM |
1004 | struct mlx5e_cq_param *param, struct mlx5e_cq *cq); |
1005 | void mlx5e_close_cq(struct mlx5e_cq *cq); | |
1006 | ||
f62b8bb8 AV |
1007 | int mlx5e_open_locked(struct net_device *netdev); |
1008 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
1009 | |
1010 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
1011 | struct mlx5e_channels *chs); | |
1012 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
1013 | |
1014 | /* Function pointer to be used to modify WH settings while | |
1015 | * switching channels | |
1016 | */ | |
1017 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
484c1ada | 1018 | int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); |
877662e2 TT |
1019 | int mlx5e_safe_switch_channels(struct mlx5e_priv *priv, |
1020 | struct mlx5e_channels *new_chs, | |
1021 | mlx5e_fp_hw_modify hw_modify); | |
603f4a45 SM |
1022 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
1023 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 1024 | |
d4b6c488 | 1025 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba | 1026 | int num_channels); |
0088cbbc TG |
1027 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, |
1028 | u8 cq_period_mode); | |
9908aa29 TT |
1029 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
1030 | u8 cq_period_mode); | |
2ccb0a79 | 1031 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params); |
696a97cf | 1032 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 1033 | struct mlx5e_params *params); |
be5323c8 AL |
1034 | int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state); |
1035 | void mlx5e_activate_rq(struct mlx5e_rq *rq); | |
1036 | void mlx5e_deactivate_rq(struct mlx5e_rq *rq); | |
1037 | void mlx5e_free_rx_descs(struct mlx5e_rq *rq); | |
1038 | void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); | |
1039 | void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); | |
9908aa29 | 1040 | |
de8650a8 EBE |
1041 | int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
1042 | struct mlx5e_modify_sq_param *p); | |
1043 | void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); | |
1044 | void mlx5e_tx_disable_queue(struct netdev_queue *txq); | |
1045 | ||
7b3722fa GP |
1046 | static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) |
1047 | { | |
1048 | return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) && | |
1049 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version)); | |
1050 | } | |
1051 | ||
e3cfc7e6 MS |
1052 | static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) |
1053 | { | |
1054 | return MLX5_CAP_ETH(mdev, swp) && | |
1055 | MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); | |
1056 | } | |
1057 | ||
f62b8bb8 | 1058 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
1059 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
1060 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
1061 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 1062 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
2a5e7a13 HN |
1063 | void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv); |
1064 | void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv); | |
08fb1dac SM |
1065 | #endif |
1066 | ||
724b2aa1 HHZ |
1067 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
1068 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
1069 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
1070 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
1071 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1072 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 1073 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 1074 | |
bc81b9d3 | 1075 | /* common netdev helpers */ |
1462e48d RD |
1076 | void mlx5e_create_q_counters(struct mlx5e_priv *priv); |
1077 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); | |
1078 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, | |
1079 | struct mlx5e_rq *drop_rq); | |
1080 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); | |
1081 | ||
8f493ffd SM |
1082 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1083 | ||
46dc933c OG |
1084 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); |
1085 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); | |
8f493ffd | 1086 | |
db05815b MM |
1087 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs); |
1088 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs); | |
1089 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs); | |
1090 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs); | |
8f493ffd SM |
1091 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
1092 | ||
2b257a6e | 1093 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); |
5426a0b2 SM |
1094 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); |
1095 | ||
cb67b832 | 1096 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
a90f88fe | 1097 | int mlx5e_update_nic_rx(struct mlx5e_priv *priv); |
b36cdb42 | 1098 | void mlx5e_update_carrier(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1099 | int mlx5e_close(struct net_device *netdev); |
1100 | int mlx5e_open(struct net_device *netdev); | |
5c7e8bbb | 1101 | void mlx5e_update_ndo_stats(struct mlx5e_priv *priv); |
cb67b832 | 1102 | |
cdeef2b1 | 1103 | void mlx5e_queue_update_stats(struct mlx5e_priv *priv); |
3f6d08d1 OG |
1104 | int mlx5e_bits_invert(unsigned long a, int size); |
1105 | ||
250a42b6 | 1106 | typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv); |
d9ee0491 | 1107 | int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); |
250a42b6 AN |
1108 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
1109 | change_hw_mtu_cb set_mtu_cb); | |
1110 | ||
076b0936 ES |
1111 | /* ethtool helpers */ |
1112 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1113 | struct ethtool_drvinfo *drvinfo); | |
1114 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1115 | uint32_t stringset, uint8_t *data); | |
1116 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1117 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1118 | struct ethtool_stats *stats, u64 *data); | |
1119 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1120 | struct ethtool_ringparam *param); | |
1121 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1122 | struct ethtool_ringparam *param); | |
1123 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1124 | struct ethtool_channels *ch); | |
1125 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1126 | struct ethtool_channels *ch); | |
1127 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1128 | struct ethtool_coalesce *coal); | |
1129 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1130 | struct ethtool_coalesce *coal); | |
371289b6 OG |
1131 | int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, |
1132 | struct ethtool_link_ksettings *link_ksettings); | |
1133 | int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, | |
1134 | const struct ethtool_link_ksettings *link_ksettings); | |
a5355de8 OG |
1135 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); |
1136 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); | |
3844b07e FD |
1137 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1138 | struct ethtool_ts_info *info); | |
f43d48d1 EBE |
1139 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1140 | struct ethtool_flash *flash); | |
371289b6 OG |
1141 | void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, |
1142 | struct ethtool_pauseparam *pauseparam); | |
1143 | int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, | |
1144 | struct ethtool_pauseparam *pauseparam); | |
076b0936 | 1145 | |
2c3b5bee | 1146 | /* mlx5e generic netdev management API */ |
519a0bf5 SM |
1147 | int mlx5e_netdev_init(struct net_device *netdev, |
1148 | struct mlx5e_priv *priv, | |
1149 | struct mlx5_core_dev *mdev, | |
1150 | const struct mlx5e_profile *profile, | |
1151 | void *ppriv); | |
182570b2 | 1152 | void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv); |
2c3b5bee SM |
1153 | struct net_device* |
1154 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
779d986d | 1155 | int nch, void *ppriv); |
2c3b5bee SM |
1156 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); |
1157 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1158 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
6d7ee2ed | 1159 | void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); |
8f493ffd | 1160 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
db05815b | 1161 | struct mlx5e_xsk *xsk, |
bbeb53b8 | 1162 | struct mlx5e_rss_params *rss_params, |
8f493ffd | 1163 | struct mlx5e_params *params, |
472a1e44 | 1164 | u16 max_channels, u16 mtu); |
749359f4 GT |
1165 | void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, |
1166 | struct mlx5e_params *params); | |
bbeb53b8 AL |
1167 | void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params, |
1168 | u16 num_channels); | |
9a317425 | 1169 | void mlx5e_rx_dim_work(struct work_struct *work); |
cbce4f44 | 1170 | void mlx5e_tx_dim_work(struct work_struct *work); |
073caf50 OG |
1171 | |
1172 | void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti); | |
1173 | void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti); | |
1174 | netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
1175 | struct net_device *netdev, | |
1176 | netdev_features_t features); | |
d3cbd425 | 1177 | int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); |
073caf50 OG |
1178 | #ifdef CONFIG_MLX5_ESWITCH |
1179 | int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); | |
1180 | int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); | |
1181 | int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); | |
1182 | int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); | |
1183 | #endif | |
1afff42c | 1184 | #endif /* __MLX5_EN_H__ */ |