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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
f62b8bb8 | 47 | #include "wq.h" |
f62b8bb8 | 48 | #include "mlx5_core.h" |
9218b44d | 49 | #include "en_stats.h" |
f62b8bb8 | 50 | |
1cabe6b0 MG |
51 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
52 | ||
f62b8bb8 AV |
53 | #define MLX5E_MAX_NUM_TC 8 |
54 | ||
e842b100 | 55 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
56 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
57 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
58 | ||
e842b100 | 59 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
60 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
61 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
62 | ||
461017cb TT |
63 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
64 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4 | |
65 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 | |
66 | ||
461017cb | 67 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 TT |
68 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
69 | #define MLX5_MPWRQ_LOG_WQE_SZ 17 | |
461017cb TT |
70 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
71 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
72 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
73 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
74 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
bc77b240 TT |
75 | #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \ |
76 | BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW)) | |
77 | #define MLX5_UMR_ALIGN (2048) | |
461017cb TT |
78 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
79 | ||
d9a40271 | 80 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 AV |
81 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
82 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
83 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
84 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
85 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 86 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 87 | |
936896e9 AS |
88 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
89 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
90 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
f62b8bb8 AV |
91 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
92 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 93 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 94 | |
86d722ad | 95 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 96 | |
461017cb TT |
97 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
98 | { | |
99 | switch (wq_type) { | |
100 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
101 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
102 | wq_size / 2); | |
103 | default: | |
104 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
105 | wq_size / 2); | |
106 | } | |
107 | } | |
108 | ||
109 | static inline int mlx5_min_log_rq_size(int wq_type) | |
110 | { | |
111 | switch (wq_type) { | |
112 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
113 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
114 | default: | |
115 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
116 | } | |
117 | } | |
118 | ||
119 | static inline int mlx5_max_log_rq_size(int wq_type) | |
120 | { | |
121 | switch (wq_type) { | |
122 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
123 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
124 | default: | |
125 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
126 | } | |
127 | } | |
128 | ||
2f48af12 TT |
129 | struct mlx5e_tx_wqe { |
130 | struct mlx5_wqe_ctrl_seg ctrl; | |
131 | struct mlx5_wqe_eth_seg eth; | |
132 | }; | |
133 | ||
134 | struct mlx5e_rx_wqe { | |
135 | struct mlx5_wqe_srq_next_seg next; | |
136 | struct mlx5_wqe_data_seg data; | |
137 | }; | |
86d722ad | 138 | |
bc77b240 TT |
139 | struct mlx5e_umr_wqe { |
140 | struct mlx5_wqe_ctrl_seg ctrl; | |
141 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
142 | struct mlx5_mkey_seg mkc; | |
143 | struct mlx5_wqe_data_seg data; | |
144 | }; | |
145 | ||
08fb1dac SM |
146 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
147 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
148 | #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */ | |
149 | #endif | |
150 | ||
f62b8bb8 AV |
151 | struct mlx5e_params { |
152 | u8 log_sq_size; | |
461017cb | 153 | u8 rq_wq_type; |
d9d9f156 TT |
154 | u8 mpwqe_log_stride_sz; |
155 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
156 | u8 log_rq_size; |
157 | u16 num_channels; | |
f62b8bb8 | 158 | u8 num_tc; |
7219ab34 TT |
159 | bool rx_cqe_compress_admin; |
160 | bool rx_cqe_compress; | |
f62b8bb8 AV |
161 | u16 rx_cq_moderation_usec; |
162 | u16 rx_cq_moderation_pkts; | |
163 | u16 tx_cq_moderation_usec; | |
164 | u16 tx_cq_moderation_pkts; | |
165 | u16 min_rx_wqes; | |
f62b8bb8 AV |
166 | bool lro_en; |
167 | u32 lro_wqe_sz; | |
58d52291 | 168 | u16 tx_max_inline; |
2d75b2bc AS |
169 | u8 rss_hfunc; |
170 | u8 toeplitz_hash_key[40]; | |
171 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 172 | bool vlan_strip_disable; |
08fb1dac SM |
173 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
174 | struct ieee_ets ets; | |
175 | #endif | |
f62b8bb8 AV |
176 | }; |
177 | ||
ef9814de EBE |
178 | struct mlx5e_tstamp { |
179 | rwlock_t lock; | |
180 | struct cyclecounter cycles; | |
181 | struct timecounter clock; | |
182 | struct hwtstamp_config hwtstamp_config; | |
183 | u32 nominal_c_mult; | |
184 | unsigned long overflow_period; | |
185 | struct delayed_work overflow_work; | |
186 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
187 | struct ptp_clock *ptp; |
188 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
189 | }; |
190 | ||
f62b8bb8 AV |
191 | enum { |
192 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
bc77b240 | 193 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
f62b8bb8 AV |
194 | }; |
195 | ||
f62b8bb8 AV |
196 | struct mlx5e_cq { |
197 | /* data path - accessed per cqe */ | |
198 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
199 | |
200 | /* data path - accessed per napi poll */ | |
201 | struct napi_struct *napi; | |
202 | struct mlx5_core_cq mcq; | |
203 | struct mlx5e_channel *channel; | |
50cfa25a | 204 | struct mlx5e_priv *priv; |
f62b8bb8 | 205 | |
7219ab34 TT |
206 | /* cqe decompression */ |
207 | struct mlx5_cqe64 title; | |
208 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
209 | u8 mini_arr_idx; | |
210 | u16 decmprs_left; | |
211 | u16 decmprs_wqe_counter; | |
212 | ||
f62b8bb8 AV |
213 | /* control */ |
214 | struct mlx5_wq_ctrl wq_ctrl; | |
215 | } ____cacheline_aligned_in_smp; | |
216 | ||
2f48af12 TT |
217 | struct mlx5e_rq; |
218 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
219 | struct mlx5_cqe64 *cqe); | |
220 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
221 | u16 ix); | |
222 | ||
461017cb TT |
223 | struct mlx5e_dma_info { |
224 | struct page *page; | |
225 | dma_addr_t addr; | |
226 | }; | |
227 | ||
f62b8bb8 AV |
228 | struct mlx5e_rq { |
229 | /* data path */ | |
230 | struct mlx5_wq_ll wq; | |
231 | u32 wqe_sz; | |
232 | struct sk_buff **skb; | |
461017cb | 233 | struct mlx5e_mpw_info *wqe_info; |
bc77b240 TT |
234 | __be32 mkey_be; |
235 | __be32 umr_mkey_be; | |
f62b8bb8 AV |
236 | |
237 | struct device *pdev; | |
238 | struct net_device *netdev; | |
ef9814de | 239 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
240 | struct mlx5e_rq_stats stats; |
241 | struct mlx5e_cq cq; | |
2f48af12 TT |
242 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
243 | mlx5e_fp_alloc_wqe alloc_wqe; | |
f62b8bb8 AV |
244 | |
245 | unsigned long state; | |
246 | int ix; | |
247 | ||
248 | /* control */ | |
249 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 250 | u8 wq_type; |
d9d9f156 TT |
251 | u32 mpwqe_stride_sz; |
252 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
253 | u32 rqn; |
254 | struct mlx5e_channel *channel; | |
50cfa25a | 255 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
256 | } ____cacheline_aligned_in_smp; |
257 | ||
bc77b240 TT |
258 | struct mlx5e_umr_dma_info { |
259 | __be64 *mtt; | |
260 | __be64 *mtt_no_align; | |
261 | dma_addr_t mtt_addr; | |
262 | struct mlx5e_dma_info *dma_info; | |
263 | }; | |
264 | ||
265 | struct mlx5e_mpw_info { | |
266 | union { | |
267 | struct mlx5e_dma_info dma_info; | |
268 | struct mlx5e_umr_dma_info umr; | |
269 | }; | |
270 | u16 consumed_strides; | |
271 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
272 | ||
273 | void (*dma_pre_sync)(struct device *pdev, | |
274 | struct mlx5e_mpw_info *wi, | |
275 | u32 wqe_offset, u32 len); | |
d9d9f156 | 276 | void (*add_skb_frag)(struct mlx5e_rq *rq, |
bc77b240 TT |
277 | struct sk_buff *skb, |
278 | struct mlx5e_mpw_info *wi, | |
279 | u32 page_idx, u32 frag_offset, u32 len); | |
280 | void (*copy_skb_header)(struct device *pdev, | |
281 | struct sk_buff *skb, | |
282 | struct mlx5e_mpw_info *wi, | |
283 | u32 page_idx, u32 offset, | |
284 | u32 headlen); | |
285 | void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
286 | }; | |
287 | ||
34802a42 | 288 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
289 | u32 num_bytes; |
290 | u8 num_wqebbs; | |
291 | u8 num_dma; | |
292 | }; | |
293 | ||
d4e28cbd AS |
294 | enum mlx5e_dma_map_type { |
295 | MLX5E_DMA_MAP_SINGLE, | |
296 | MLX5E_DMA_MAP_PAGE | |
297 | }; | |
298 | ||
f62b8bb8 | 299 | struct mlx5e_sq_dma { |
d4e28cbd AS |
300 | dma_addr_t addr; |
301 | u32 size; | |
302 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
303 | }; |
304 | ||
305 | enum { | |
306 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
0ba42241 | 307 | MLX5E_SQ_STATE_BF_ENABLE, |
29429f33 | 308 | MLX5E_SQ_STATE_TX_TIMEOUT, |
f62b8bb8 AV |
309 | }; |
310 | ||
d3c9bc27 TT |
311 | struct mlx5e_ico_wqe_info { |
312 | u8 opcode; | |
313 | u8 num_wqebbs; | |
314 | }; | |
315 | ||
f62b8bb8 AV |
316 | struct mlx5e_sq { |
317 | /* data path */ | |
318 | ||
319 | /* dirtied @completion */ | |
320 | u16 cc; | |
321 | u32 dma_fifo_cc; | |
322 | ||
323 | /* dirtied @xmit */ | |
324 | u16 pc ____cacheline_aligned_in_smp; | |
325 | u32 dma_fifo_pc; | |
88a85f99 AS |
326 | u16 bf_offset; |
327 | u16 prev_cc; | |
328 | u8 bf_budget; | |
f62b8bb8 AV |
329 | struct mlx5e_sq_stats stats; |
330 | ||
331 | struct mlx5e_cq cq; | |
332 | ||
333 | /* pointers to per packet info: write@xmit, read@completion */ | |
334 | struct sk_buff **skb; | |
335 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 336 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
337 | |
338 | /* read only */ | |
339 | struct mlx5_wq_cyc wq; | |
340 | u32 dma_fifo_mask; | |
341 | void __iomem *uar_map; | |
342 | struct netdev_queue *txq; | |
343 | u32 sqn; | |
88a85f99 | 344 | u16 bf_buf_size; |
12be4b21 SM |
345 | u16 max_inline; |
346 | u16 edge; | |
f62b8bb8 | 347 | struct device *pdev; |
ef9814de | 348 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
349 | __be32 mkey_be; |
350 | unsigned long state; | |
351 | ||
352 | /* control path */ | |
353 | struct mlx5_wq_ctrl wq_ctrl; | |
354 | struct mlx5_uar uar; | |
355 | struct mlx5e_channel *channel; | |
356 | int tc; | |
d3c9bc27 | 357 | struct mlx5e_ico_wqe_info *ico_wqe_info; |
f62b8bb8 AV |
358 | } ____cacheline_aligned_in_smp; |
359 | ||
360 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
361 | { | |
362 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
363 | (sq->cc == sq->pc)); | |
364 | } | |
365 | ||
366 | enum channel_flags { | |
367 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
368 | }; | |
369 | ||
370 | struct mlx5e_channel { | |
371 | /* data path */ | |
372 | struct mlx5e_rq rq; | |
373 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
d3c9bc27 | 374 | struct mlx5e_sq icosq; /* internal control operations */ |
f62b8bb8 AV |
375 | struct napi_struct napi; |
376 | struct device *pdev; | |
377 | struct net_device *netdev; | |
378 | __be32 mkey_be; | |
379 | u8 num_tc; | |
380 | unsigned long flags; | |
381 | ||
382 | /* control */ | |
383 | struct mlx5e_priv *priv; | |
384 | int ix; | |
385 | int cpu; | |
386 | }; | |
387 | ||
388 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
389 | MLX5E_TT_IPV4_TCP, |
390 | MLX5E_TT_IPV6_TCP, | |
391 | MLX5E_TT_IPV4_UDP, | |
392 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
393 | MLX5E_TT_IPV4_IPSEC_AH, |
394 | MLX5E_TT_IPV6_IPSEC_AH, | |
395 | MLX5E_TT_IPV4_IPSEC_ESP, | |
396 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
397 | MLX5E_TT_IPV4, |
398 | MLX5E_TT_IPV6, | |
399 | MLX5E_TT_ANY, | |
400 | MLX5E_NUM_TT, | |
1da36696 | 401 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
402 | }; |
403 | ||
acff797c | 404 | enum { |
e0f46eb9 | 405 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
406 | MLX5E_STATE_OPENED, |
407 | MLX5E_STATE_DESTROYING, | |
408 | }; | |
409 | ||
410 | struct mlx5e_vxlan_db { | |
411 | spinlock_t lock; /* protect vxlan table */ | |
412 | struct radix_tree_root tree; | |
413 | }; | |
414 | ||
33cfaaa8 | 415 | struct mlx5e_l2_rule { |
f62b8bb8 | 416 | u8 addr[ETH_ALEN + 2]; |
33cfaaa8 | 417 | struct mlx5_flow_rule *rule; |
f62b8bb8 AV |
418 | }; |
419 | ||
acff797c MG |
420 | struct mlx5e_flow_table { |
421 | int num_groups; | |
422 | struct mlx5_flow_table *t; | |
423 | struct mlx5_flow_group **g; | |
424 | }; | |
425 | ||
33cfaaa8 | 426 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 427 | |
acff797c MG |
428 | struct mlx5e_tc_table { |
429 | struct mlx5_flow_table *t; | |
430 | ||
431 | struct rhashtable_params ht_params; | |
432 | struct rhashtable ht; | |
f62b8bb8 AV |
433 | }; |
434 | ||
acff797c MG |
435 | struct mlx5e_vlan_table { |
436 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 437 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
438 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
439 | struct mlx5_flow_rule *untagged_rule; | |
440 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
441 | bool filter_disabled; |
442 | }; | |
443 | ||
33cfaaa8 MG |
444 | struct mlx5e_l2_table { |
445 | struct mlx5e_flow_table ft; | |
446 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
447 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
448 | struct mlx5e_l2_rule broadcast; | |
449 | struct mlx5e_l2_rule allmulti; | |
450 | struct mlx5e_l2_rule promisc; | |
451 | bool broadcast_enabled; | |
452 | bool allmulti_enabled; | |
453 | bool promisc_enabled; | |
454 | }; | |
455 | ||
456 | /* L3/L4 traffic type classifier */ | |
457 | struct mlx5e_ttc_table { | |
458 | struct mlx5e_flow_table ft; | |
459 | struct mlx5_flow_rule *rules[MLX5E_NUM_TT]; | |
460 | }; | |
461 | ||
18c908e4 MG |
462 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
463 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
464 | struct arfs_table { |
465 | struct mlx5e_flow_table ft; | |
466 | struct mlx5_flow_rule *default_rule; | |
18c908e4 | 467 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
468 | }; |
469 | ||
470 | enum arfs_type { | |
471 | ARFS_IPV4_TCP, | |
472 | ARFS_IPV6_TCP, | |
473 | ARFS_IPV4_UDP, | |
474 | ARFS_IPV6_UDP, | |
475 | ARFS_NUM_TYPES, | |
476 | }; | |
477 | ||
478 | struct mlx5e_arfs_tables { | |
479 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
480 | /* Protect aRFS rules list */ |
481 | spinlock_t arfs_lock; | |
482 | struct list_head rules; | |
483 | int last_filter_id; | |
484 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
485 | }; |
486 | ||
487 | /* NIC prio FTS */ | |
488 | enum { | |
489 | MLX5E_VLAN_FT_LEVEL = 0, | |
490 | MLX5E_L2_FT_LEVEL, | |
491 | MLX5E_TTC_FT_LEVEL, | |
492 | MLX5E_ARFS_FT_LEVEL | |
493 | }; | |
494 | ||
acff797c MG |
495 | struct mlx5e_flow_steering { |
496 | struct mlx5_flow_namespace *ns; | |
497 | struct mlx5e_tc_table tc; | |
498 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
499 | struct mlx5e_l2_table l2; |
500 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 501 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
502 | }; |
503 | ||
1da36696 TT |
504 | struct mlx5e_direct_tir { |
505 | u32 tirn; | |
506 | u32 rqtn; | |
507 | }; | |
508 | ||
acff797c MG |
509 | enum { |
510 | MLX5E_TC_PRIO = 0, | |
511 | MLX5E_NIC_PRIO | |
512 | }; | |
513 | ||
f62b8bb8 AV |
514 | struct mlx5e_priv { |
515 | /* priv data path fields - start */ | |
03289b88 | 516 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 517 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
518 | /* priv data path fields - end */ |
519 | ||
520 | unsigned long state; | |
521 | struct mutex state_lock; /* Protects Interface state */ | |
522 | struct mlx5_uar cq_uar; | |
523 | u32 pdn; | |
3191e05f | 524 | u32 tdn; |
a606b0f6 | 525 | struct mlx5_core_mkey mkey; |
bc77b240 | 526 | struct mlx5_core_mkey umr_mkey; |
50cfa25a | 527 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
528 | |
529 | struct mlx5e_channel **channel; | |
530 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
1da36696 TT |
531 | u32 indir_rqtn; |
532 | u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; | |
533 | struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
f62b8bb8 | 534 | |
acff797c | 535 | struct mlx5e_flow_steering fs; |
b3f63c3d | 536 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
537 | |
538 | struct mlx5e_params params; | |
7bb29755 | 539 | struct workqueue_struct *wq; |
f62b8bb8 AV |
540 | struct work_struct update_carrier_work; |
541 | struct work_struct set_rx_mode_work; | |
3947ca18 | 542 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
543 | struct delayed_work update_stats_work; |
544 | ||
545 | struct mlx5_core_dev *mdev; | |
546 | struct net_device *netdev; | |
547 | struct mlx5e_stats stats; | |
ef9814de | 548 | struct mlx5e_tstamp tstamp; |
593cf338 | 549 | u16 q_counter; |
f62b8bb8 AV |
550 | }; |
551 | ||
f62b8bb8 AV |
552 | enum mlx5e_link_mode { |
553 | MLX5E_1000BASE_CX_SGMII = 0, | |
554 | MLX5E_1000BASE_KX = 1, | |
555 | MLX5E_10GBASE_CX4 = 2, | |
556 | MLX5E_10GBASE_KX4 = 3, | |
557 | MLX5E_10GBASE_KR = 4, | |
558 | MLX5E_20GBASE_KR2 = 5, | |
559 | MLX5E_40GBASE_CR4 = 6, | |
560 | MLX5E_40GBASE_KR4 = 7, | |
561 | MLX5E_56GBASE_R4 = 8, | |
562 | MLX5E_10GBASE_CR = 12, | |
563 | MLX5E_10GBASE_SR = 13, | |
564 | MLX5E_10GBASE_ER = 14, | |
565 | MLX5E_40GBASE_SR4 = 15, | |
566 | MLX5E_40GBASE_LR4 = 16, | |
567 | MLX5E_100GBASE_CR4 = 20, | |
568 | MLX5E_100GBASE_SR4 = 21, | |
569 | MLX5E_100GBASE_KR4 = 22, | |
570 | MLX5E_100GBASE_LR4 = 23, | |
571 | MLX5E_100BASE_TX = 24, | |
6e4c2189 | 572 | MLX5E_1000BASE_T = 25, |
f62b8bb8 AV |
573 | MLX5E_10GBASE_T = 26, |
574 | MLX5E_25GBASE_CR = 27, | |
575 | MLX5E_25GBASE_KR = 28, | |
576 | MLX5E_25GBASE_SR = 29, | |
577 | MLX5E_50GBASE_CR2 = 30, | |
578 | MLX5E_50GBASE_KR2 = 31, | |
579 | MLX5E_LINK_MODES_NUMBER, | |
580 | }; | |
581 | ||
582 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
583 | ||
12be4b21 | 584 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
585 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
586 | void *accel_priv, select_queue_fallback_t fallback); | |
587 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
588 | |
589 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
590 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
591 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 592 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 593 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
29429f33 | 594 | void mlx5e_free_tx_descs(struct mlx5e_sq *sq); |
461017cb | 595 | |
2f48af12 | 596 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 597 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 598 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 599 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
461017cb | 600 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
bc77b240 TT |
601 | void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq); |
602 | void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
603 | struct mlx5_cqe64 *cqe, | |
604 | u16 byte_cnt, | |
605 | struct mlx5e_mpw_info *wi, | |
606 | struct sk_buff *skb); | |
607 | void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
608 | struct mlx5_cqe64 *cqe, | |
609 | u16 byte_cnt, | |
610 | struct mlx5e_mpw_info *wi, | |
611 | struct sk_buff *skb); | |
612 | void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
613 | struct mlx5e_mpw_info *wi); | |
614 | void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
615 | struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
616 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
617 | ||
618 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
619 | ||
acff797c MG |
620 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
621 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 622 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 623 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
f62b8bb8 AV |
624 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
625 | ||
ef9814de EBE |
626 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
627 | struct skb_shared_hwtstamps *hwts); | |
628 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
629 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
630 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
631 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 632 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 633 | |
f62b8bb8 AV |
634 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
635 | u16 vid); | |
636 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
637 | u16 vid); | |
638 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
639 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 640 | |
36350114 GP |
641 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
642 | ||
1da36696 | 643 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 644 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 645 | |
f62b8bb8 AV |
646 | int mlx5e_open_locked(struct net_device *netdev); |
647 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
648 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
649 | u32 *indirection_rqt, int len, | |
85082dba | 650 | int num_channels); |
b797a684 | 651 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 AV |
652 | |
653 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
bc77b240 | 654 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 655 | { |
88a85f99 AS |
656 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
657 | ||
f62b8bb8 AV |
658 | /* ensure wqe is visible to device before updating doorbell record */ |
659 | dma_wmb(); | |
660 | ||
661 | *sq->wq.db = cpu_to_be32(sq->pc); | |
662 | ||
663 | /* ensure doorbell record is visible to device before ringing the | |
664 | * doorbell | |
665 | */ | |
666 | wmb(); | |
0ba42241 | 667 | if (bf_sz) |
bc77b240 | 668 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 669 | else |
bc77b240 | 670 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
671 | /* flush the write-combining mapped buffer */ |
672 | wmb(); | |
f62b8bb8 AV |
673 | |
674 | sq->bf_offset ^= sq->bf_buf_size; | |
675 | } | |
676 | ||
677 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
678 | { | |
679 | struct mlx5_core_cq *mcq; | |
680 | ||
681 | mcq = &cq->mcq; | |
682 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
683 | } | |
684 | ||
3435ab59 AS |
685 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
686 | { | |
687 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
688 | MLX5E_MAX_NUM_CHANNELS); | |
689 | } | |
690 | ||
bc77b240 TT |
691 | static inline int mlx5e_get_mtt_octw(int npages) |
692 | { | |
693 | return ALIGN(npages, 8) / 2; | |
694 | } | |
695 | ||
f62b8bb8 | 696 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
697 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
698 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
699 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
700 | #endif | |
701 | ||
1cabe6b0 MG |
702 | #ifndef CONFIG_RFS_ACCEL |
703 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
704 | { | |
705 | return 0; | |
706 | } | |
707 | ||
708 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
709 | |
710 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
711 | { | |
712 | return -ENOTSUPP; | |
713 | } | |
714 | ||
715 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
716 | { | |
717 | return -ENOTSUPP; | |
718 | } | |
1cabe6b0 MG |
719 | #else |
720 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
721 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
722 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
723 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
724 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
725 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
726 | #endif |
727 | ||
58d52291 | 728 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
1afff42c MF |
729 | |
730 | #endif /* __MLX5_EN_H__ */ |