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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
e8f887ac | 47 | #include <linux/rhashtable.h> |
cb67b832 | 48 | #include <net/switchdev.h> |
f62b8bb8 | 49 | #include "wq.h" |
f62b8bb8 | 50 | #include "mlx5_core.h" |
9218b44d | 51 | #include "en_stats.h" |
f62b8bb8 | 52 | |
1cabe6b0 MG |
53 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
54 | ||
c139dbfd ES |
55 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
56 | ||
57 | #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu)) | |
58 | #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu)) | |
d8bec2b2 | 59 | |
f62b8bb8 AV |
60 | #define MLX5E_MAX_NUM_TC 8 |
61 | ||
e842b100 | 62 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
63 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
64 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
65 | ||
e842b100 | 66 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
67 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
68 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
69 | ||
461017cb | 70 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 71 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
72 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
73 | ||
1bfecfca | 74 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
75 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
76 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 77 | |
f32f5bd2 DJ |
78 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
79 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
80 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
81 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
82 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
83 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
84 | ||
7e426671 | 85 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
86 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
87 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
88 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
89 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
90 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
91 | |
92 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
ec8b9981 TT |
93 | #define MLX5E_REQUIRED_MTTS(wqes) \ |
94 | (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
95 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) | |
fe4c988b | 96 | |
bc77b240 | 97 | #define MLX5_UMR_ALIGN (2048) |
cbad8cdd | 98 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256) |
461017cb | 99 | |
d9a40271 | 100 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
101 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
102 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
103 | ||
f62b8bb8 | 104 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 105 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
106 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
107 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
108 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
109 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 110 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 111 | |
936896e9 AS |
112 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
113 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 114 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 115 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 116 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
117 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
118 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
119 | ||
f10b7cc7 SM |
120 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
121 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
122 | ||
b5503b99 | 123 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
b5503b99 | 124 | #define MLX5E_XDP_TX_DS_COUNT \ |
b70149dd | 125 | ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) |
b5503b99 | 126 | |
86d722ad | 127 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 128 | |
461017cb TT |
129 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
130 | { | |
131 | switch (wq_type) { | |
132 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
133 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
134 | wq_size / 2); | |
135 | default: | |
136 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
137 | wq_size / 2); | |
138 | } | |
139 | } | |
140 | ||
141 | static inline int mlx5_min_log_rq_size(int wq_type) | |
142 | { | |
143 | switch (wq_type) { | |
144 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
145 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
146 | default: | |
147 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
148 | } | |
149 | } | |
150 | ||
151 | static inline int mlx5_max_log_rq_size(int wq_type) | |
152 | { | |
153 | switch (wq_type) { | |
154 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
155 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
156 | default: | |
157 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
158 | } | |
159 | } | |
160 | ||
48935bbb SM |
161 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
162 | { | |
163 | return is_kdump_kernel() ? | |
164 | MLX5E_MIN_NUM_CHANNELS : | |
165 | min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
166 | MLX5E_MAX_NUM_CHANNELS); | |
167 | } | |
168 | ||
2f48af12 TT |
169 | struct mlx5e_tx_wqe { |
170 | struct mlx5_wqe_ctrl_seg ctrl; | |
171 | struct mlx5_wqe_eth_seg eth; | |
172 | }; | |
173 | ||
174 | struct mlx5e_rx_wqe { | |
175 | struct mlx5_wqe_srq_next_seg next; | |
176 | struct mlx5_wqe_data_seg data; | |
177 | }; | |
86d722ad | 178 | |
bc77b240 TT |
179 | struct mlx5e_umr_wqe { |
180 | struct mlx5_wqe_ctrl_seg ctrl; | |
181 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
182 | struct mlx5_mkey_seg mkc; | |
183 | struct mlx5_wqe_data_seg data; | |
184 | }; | |
185 | ||
d605d668 KH |
186 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
187 | ||
4e59e288 | 188 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 189 | "rx_cqe_moder", |
9bcc8606 | 190 | "rx_cqe_compress", |
4e59e288 GP |
191 | }; |
192 | ||
193 | enum mlx5e_priv_flag { | |
9908aa29 | 194 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
9bcc8606 | 195 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1), |
4e59e288 GP |
196 | }; |
197 | ||
6a9764ef | 198 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
199 | do { \ |
200 | if (enable) \ | |
6a9764ef | 201 | (params)->pflags |= (pflag); \ |
59ece1c9 | 202 | else \ |
6a9764ef | 203 | (params)->pflags &= ~(pflag); \ |
4e59e288 GP |
204 | } while (0) |
205 | ||
6a9764ef | 206 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag))) |
59ece1c9 | 207 | |
08fb1dac SM |
208 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
209 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
210 | #endif |
211 | ||
9908aa29 TT |
212 | struct mlx5e_cq_moder { |
213 | u16 usec; | |
214 | u16 pkts; | |
215 | }; | |
216 | ||
f62b8bb8 AV |
217 | struct mlx5e_params { |
218 | u8 log_sq_size; | |
461017cb | 219 | u8 rq_wq_type; |
bce2b2bf | 220 | u16 rq_headroom; |
d9d9f156 TT |
221 | u8 mpwqe_log_stride_sz; |
222 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
223 | u8 log_rq_size; |
224 | u16 num_channels; | |
f62b8bb8 | 225 | u8 num_tc; |
9908aa29 | 226 | u8 rx_cq_period_mode; |
9bcc8606 | 227 | bool rx_cqe_compress_def; |
9908aa29 TT |
228 | struct mlx5e_cq_moder rx_cq_moderation; |
229 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 AV |
230 | bool lro_en; |
231 | u32 lro_wqe_sz; | |
58d52291 | 232 | u16 tx_max_inline; |
cff92d7c | 233 | u8 tx_min_inline_mode; |
2d75b2bc AS |
234 | u8 rss_hfunc; |
235 | u8 toeplitz_hash_key[40]; | |
236 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 237 | bool vlan_strip_disable; |
102722fc | 238 | bool scatter_fcs_en; |
cb3c7fd4 | 239 | bool rx_am_enabled; |
2b029556 | 240 | u32 lro_timeout; |
59ece1c9 | 241 | u32 pflags; |
6a9764ef | 242 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
243 | }; |
244 | ||
3a6a931d HN |
245 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
246 | struct mlx5e_cee_config { | |
247 | /* bw pct for priority group */ | |
248 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
249 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
250 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
251 | bool pfc_enable; | |
252 | }; | |
253 | ||
254 | enum { | |
255 | MLX5_DCB_CHG_RESET, | |
256 | MLX5_DCB_NO_CHG, | |
257 | MLX5_DCB_CHG_NO_RESET, | |
258 | }; | |
259 | ||
260 | struct mlx5e_dcbx { | |
e207b7e9 | 261 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 262 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
820c2c5e HN |
263 | |
264 | /* The only setting that cannot be read from FW */ | |
265 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
3a6a931d HN |
266 | }; |
267 | #endif | |
268 | ||
ef9814de EBE |
269 | struct mlx5e_tstamp { |
270 | rwlock_t lock; | |
271 | struct cyclecounter cycles; | |
272 | struct timecounter clock; | |
273 | struct hwtstamp_config hwtstamp_config; | |
274 | u32 nominal_c_mult; | |
275 | unsigned long overflow_period; | |
276 | struct delayed_work overflow_work; | |
277 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
278 | struct ptp_clock *ptp; |
279 | struct ptp_clock_info ptp_info; | |
ee7f1220 | 280 | u8 *pps_pin_caps; |
ef9814de EBE |
281 | }; |
282 | ||
f62b8bb8 | 283 | enum { |
c0f1147d | 284 | MLX5E_RQ_STATE_ENABLED, |
bc77b240 | 285 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 286 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
287 | }; |
288 | ||
f62b8bb8 AV |
289 | struct mlx5e_cq { |
290 | /* data path - accessed per cqe */ | |
291 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
292 | |
293 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 294 | u16 event_ctr; |
f62b8bb8 AV |
295 | struct napi_struct *napi; |
296 | struct mlx5_core_cq mcq; | |
297 | struct mlx5e_channel *channel; | |
298 | ||
7219ab34 TT |
299 | /* cqe decompression */ |
300 | struct mlx5_cqe64 title; | |
301 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
302 | u8 mini_arr_idx; | |
303 | u16 decmprs_left; | |
304 | u16 decmprs_wqe_counter; | |
305 | ||
f62b8bb8 | 306 | /* control */ |
a43b25da | 307 | struct mlx5_core_dev *mdev; |
1c1b5228 | 308 | struct mlx5_frag_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
309 | } ____cacheline_aligned_in_smp; |
310 | ||
eba2db2b | 311 | struct mlx5e_tx_wqe_info { |
77bdf895 | 312 | struct sk_buff *skb; |
eba2db2b SM |
313 | u32 num_bytes; |
314 | u8 num_wqebbs; | |
315 | u8 num_dma; | |
316 | }; | |
317 | ||
318 | enum mlx5e_dma_map_type { | |
319 | MLX5E_DMA_MAP_SINGLE, | |
320 | MLX5E_DMA_MAP_PAGE | |
321 | }; | |
322 | ||
323 | struct mlx5e_sq_dma { | |
324 | dma_addr_t addr; | |
325 | u32 size; | |
326 | enum mlx5e_dma_map_type type; | |
327 | }; | |
328 | ||
329 | enum { | |
330 | MLX5E_SQ_STATE_ENABLED, | |
331 | }; | |
332 | ||
333 | struct mlx5e_sq_wqe_info { | |
334 | u8 opcode; | |
335 | u8 num_wqebbs; | |
336 | }; | |
2f48af12 | 337 | |
31391048 | 338 | struct mlx5e_txqsq { |
eba2db2b SM |
339 | /* data path */ |
340 | ||
341 | /* dirtied @completion */ | |
342 | u16 cc; | |
343 | u32 dma_fifo_cc; | |
344 | ||
345 | /* dirtied @xmit */ | |
346 | u16 pc ____cacheline_aligned_in_smp; | |
347 | u32 dma_fifo_pc; | |
348 | struct mlx5e_sq_stats stats; | |
349 | ||
350 | struct mlx5e_cq cq; | |
351 | ||
31391048 SM |
352 | /* write@xmit, read@completion */ |
353 | struct { | |
31391048 SM |
354 | struct mlx5e_sq_dma *dma_fifo; |
355 | struct mlx5e_tx_wqe_info *wqe_info; | |
eba2db2b SM |
356 | } db; |
357 | ||
358 | /* read only */ | |
359 | struct mlx5_wq_cyc wq; | |
360 | u32 dma_fifo_mask; | |
361 | void __iomem *uar_map; | |
362 | struct netdev_queue *txq; | |
363 | u32 sqn; | |
364 | u16 max_inline; | |
365 | u8 min_inline_mode; | |
366 | u16 edge; | |
367 | struct device *pdev; | |
368 | struct mlx5e_tstamp *tstamp; | |
369 | __be32 mkey_be; | |
370 | unsigned long state; | |
371 | ||
372 | /* control path */ | |
373 | struct mlx5_wq_ctrl wq_ctrl; | |
374 | struct mlx5e_channel *channel; | |
acc6c595 | 375 | int txq_ix; |
eba2db2b | 376 | u32 rate_limit; |
31391048 SM |
377 | } ____cacheline_aligned_in_smp; |
378 | ||
379 | struct mlx5e_xdpsq { | |
380 | /* data path */ | |
381 | ||
382 | /* dirtied @rx completion */ | |
383 | u16 cc; | |
384 | u16 pc; | |
385 | ||
386 | struct mlx5e_cq cq; | |
387 | ||
388 | /* write@xmit, read@completion */ | |
389 | struct { | |
390 | struct mlx5e_dma_info *di; | |
391 | bool doorbell; | |
392 | } db; | |
393 | ||
394 | /* read only */ | |
395 | struct mlx5_wq_cyc wq; | |
396 | void __iomem *uar_map; | |
397 | u32 sqn; | |
398 | struct device *pdev; | |
399 | __be32 mkey_be; | |
400 | u8 min_inline_mode; | |
401 | unsigned long state; | |
402 | ||
403 | /* control path */ | |
404 | struct mlx5_wq_ctrl wq_ctrl; | |
405 | struct mlx5e_channel *channel; | |
406 | } ____cacheline_aligned_in_smp; | |
407 | ||
408 | struct mlx5e_icosq { | |
409 | /* data path */ | |
410 | ||
411 | /* dirtied @completion */ | |
412 | u16 cc; | |
413 | ||
414 | /* dirtied @xmit */ | |
415 | u16 pc ____cacheline_aligned_in_smp; | |
416 | u32 dma_fifo_pc; | |
417 | u16 prev_cc; | |
418 | ||
419 | struct mlx5e_cq cq; | |
420 | ||
421 | /* write@xmit, read@completion */ | |
422 | struct { | |
423 | struct mlx5e_sq_wqe_info *ico_wqe; | |
424 | } db; | |
425 | ||
426 | /* read only */ | |
427 | struct mlx5_wq_cyc wq; | |
428 | void __iomem *uar_map; | |
429 | u32 sqn; | |
430 | u16 edge; | |
431 | struct device *pdev; | |
432 | __be32 mkey_be; | |
433 | unsigned long state; | |
434 | ||
435 | /* control path */ | |
436 | struct mlx5_wq_ctrl wq_ctrl; | |
437 | struct mlx5e_channel *channel; | |
eba2db2b SM |
438 | } ____cacheline_aligned_in_smp; |
439 | ||
864b2d71 SM |
440 | static inline bool |
441 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 442 | { |
864b2d71 | 443 | return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc)); |
eba2db2b | 444 | } |
6cd392a0 | 445 | |
461017cb TT |
446 | struct mlx5e_dma_info { |
447 | struct page *page; | |
448 | dma_addr_t addr; | |
449 | }; | |
450 | ||
accd5883 TT |
451 | struct mlx5e_wqe_frag_info { |
452 | struct mlx5e_dma_info di; | |
453 | u32 offset; | |
454 | }; | |
455 | ||
eba2db2b SM |
456 | struct mlx5e_umr_dma_info { |
457 | __be64 *mtt; | |
458 | dma_addr_t mtt_addr; | |
459 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; | |
460 | struct mlx5e_umr_wqe wqe; | |
461 | }; | |
462 | ||
463 | struct mlx5e_mpw_info { | |
464 | struct mlx5e_umr_dma_info umr; | |
465 | u16 consumed_strides; | |
466 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
467 | }; | |
468 | ||
cb3c7fd4 GR |
469 | struct mlx5e_rx_am_stats { |
470 | int ppms; /* packets per msec */ | |
c3164d2f | 471 | int bpms; /* bytes per msec */ |
cb3c7fd4 GR |
472 | int epms; /* events per msec */ |
473 | }; | |
474 | ||
475 | struct mlx5e_rx_am_sample { | |
53acd76c TG |
476 | ktime_t time; |
477 | u32 pkt_ctr; | |
478 | u32 byte_ctr; | |
479 | u16 event_ctr; | |
cb3c7fd4 GR |
480 | }; |
481 | ||
482 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
483 | u8 state; | |
484 | struct mlx5e_rx_am_stats prev_stats; | |
485 | struct mlx5e_rx_am_sample start_sample; | |
486 | struct work_struct work; | |
487 | u8 profile_ix; | |
488 | u8 mode; | |
489 | u8 tune_state; | |
490 | u8 steps_right; | |
491 | u8 steps_left; | |
492 | u8 tired; | |
493 | }; | |
494 | ||
4415a031 TT |
495 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
496 | * or a MPWQE (for striding rq). | |
497 | */ | |
498 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
499 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
500 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
501 | struct mlx5e_page_cache { | |
502 | u32 head; | |
503 | u32 tail; | |
504 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
505 | }; | |
506 | ||
eba2db2b SM |
507 | struct mlx5e_rq; |
508 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
509 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16); | |
510 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); | |
511 | ||
f62b8bb8 AV |
512 | struct mlx5e_rq { |
513 | /* data path */ | |
514 | struct mlx5_wq_ll wq; | |
1bfecfca | 515 | |
21c59685 | 516 | union { |
accd5883 TT |
517 | struct { |
518 | struct mlx5e_wqe_frag_info *frag_info; | |
519 | u32 frag_sz; /* max possible skb frag_sz */ | |
520 | bool page_reuse; | |
521 | bool xdp_xmit; | |
522 | } wqe; | |
21c59685 SM |
523 | struct { |
524 | struct mlx5e_mpw_info *info; | |
525 | void *mtt_no_align; | |
21c59685 SM |
526 | } mpwqe; |
527 | }; | |
1bfecfca SM |
528 | struct { |
529 | u8 page_order; | |
530 | u32 wqe_sz; /* wqe data buffer size */ | |
b5503b99 | 531 | u8 map_dir; /* dma map direction */ |
1bfecfca | 532 | } buff; |
bc77b240 | 533 | __be32 mkey_be; |
f62b8bb8 AV |
534 | |
535 | struct device *pdev; | |
536 | struct net_device *netdev; | |
ef9814de | 537 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
538 | struct mlx5e_rq_stats stats; |
539 | struct mlx5e_cq cq; | |
4415a031 TT |
540 | struct mlx5e_page_cache page_cache; |
541 | ||
2f48af12 TT |
542 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
543 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 544 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
545 | |
546 | unsigned long state; | |
547 | int ix; | |
d8bec2b2 | 548 | u16 rx_headroom; |
f62b8bb8 | 549 | |
cb3c7fd4 | 550 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
31871f87 SM |
551 | |
552 | /* XDP */ | |
86994156 | 553 | struct bpf_prog *xdp_prog; |
31391048 | 554 | struct mlx5e_xdpsq xdpsq; |
cb3c7fd4 | 555 | |
f62b8bb8 AV |
556 | /* control */ |
557 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 558 | u8 wq_type; |
d9d9f156 TT |
559 | u32 mpwqe_stride_sz; |
560 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
561 | u32 rqn; |
562 | struct mlx5e_channel *channel; | |
a43b25da | 563 | struct mlx5_core_dev *mdev; |
ec8b9981 | 564 | struct mlx5_core_mkey umr_mkey; |
f62b8bb8 AV |
565 | } ____cacheline_aligned_in_smp; |
566 | ||
f62b8bb8 AV |
567 | enum channel_flags { |
568 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
569 | }; | |
570 | ||
571 | struct mlx5e_channel { | |
572 | /* data path */ | |
573 | struct mlx5e_rq rq; | |
31391048 SM |
574 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
575 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 576 | bool xdp; |
f62b8bb8 AV |
577 | struct napi_struct napi; |
578 | struct device *pdev; | |
579 | struct net_device *netdev; | |
580 | __be32 mkey_be; | |
581 | u8 num_tc; | |
582 | unsigned long flags; | |
583 | ||
584 | /* control */ | |
585 | struct mlx5e_priv *priv; | |
a43b25da SM |
586 | struct mlx5_core_dev *mdev; |
587 | struct mlx5e_tstamp *tstamp; | |
f62b8bb8 AV |
588 | int ix; |
589 | int cpu; | |
590 | }; | |
591 | ||
ff9c852f SM |
592 | struct mlx5e_channels { |
593 | struct mlx5e_channel **c; | |
594 | unsigned int num; | |
6a9764ef | 595 | struct mlx5e_params params; |
ff9c852f SM |
596 | }; |
597 | ||
f62b8bb8 | 598 | enum mlx5e_traffic_types { |
5a6f8aef AS |
599 | MLX5E_TT_IPV4_TCP, |
600 | MLX5E_TT_IPV6_TCP, | |
601 | MLX5E_TT_IPV4_UDP, | |
602 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
603 | MLX5E_TT_IPV4_IPSEC_AH, |
604 | MLX5E_TT_IPV6_IPSEC_AH, | |
605 | MLX5E_TT_IPV4_IPSEC_ESP, | |
606 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
607 | MLX5E_TT_IPV4, |
608 | MLX5E_TT_IPV6, | |
609 | MLX5E_TT_ANY, | |
610 | MLX5E_NUM_TT, | |
1da36696 | 611 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
612 | }; |
613 | ||
acff797c | 614 | enum { |
e0f46eb9 | 615 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
616 | MLX5E_STATE_OPENED, |
617 | MLX5E_STATE_DESTROYING, | |
618 | }; | |
619 | ||
620 | struct mlx5e_vxlan_db { | |
621 | spinlock_t lock; /* protect vxlan table */ | |
622 | struct radix_tree_root tree; | |
623 | }; | |
624 | ||
33cfaaa8 | 625 | struct mlx5e_l2_rule { |
f62b8bb8 | 626 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 627 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
628 | }; |
629 | ||
acff797c MG |
630 | struct mlx5e_flow_table { |
631 | int num_groups; | |
632 | struct mlx5_flow_table *t; | |
633 | struct mlx5_flow_group **g; | |
634 | }; | |
635 | ||
33cfaaa8 | 636 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 637 | |
acff797c MG |
638 | struct mlx5e_tc_table { |
639 | struct mlx5_flow_table *t; | |
640 | ||
641 | struct rhashtable_params ht_params; | |
642 | struct rhashtable ht; | |
11c9c548 OG |
643 | |
644 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); | |
f62b8bb8 AV |
645 | }; |
646 | ||
acff797c MG |
647 | struct mlx5e_vlan_table { |
648 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 649 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
74491de9 MB |
650 | struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID]; |
651 | struct mlx5_flow_handle *untagged_rule; | |
8a271746 MHY |
652 | struct mlx5_flow_handle *any_cvlan_rule; |
653 | struct mlx5_flow_handle *any_svlan_rule; | |
654 | bool filter_disabled; | |
f62b8bb8 AV |
655 | }; |
656 | ||
33cfaaa8 MG |
657 | struct mlx5e_l2_table { |
658 | struct mlx5e_flow_table ft; | |
659 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
660 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
661 | struct mlx5e_l2_rule broadcast; | |
662 | struct mlx5e_l2_rule allmulti; | |
663 | struct mlx5e_l2_rule promisc; | |
664 | bool broadcast_enabled; | |
665 | bool allmulti_enabled; | |
666 | bool promisc_enabled; | |
667 | }; | |
668 | ||
669 | /* L3/L4 traffic type classifier */ | |
670 | struct mlx5e_ttc_table { | |
671 | struct mlx5e_flow_table ft; | |
74491de9 | 672 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
33cfaaa8 MG |
673 | }; |
674 | ||
18c908e4 MG |
675 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
676 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
677 | struct arfs_table { |
678 | struct mlx5e_flow_table ft; | |
74491de9 | 679 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 680 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
681 | }; |
682 | ||
683 | enum arfs_type { | |
684 | ARFS_IPV4_TCP, | |
685 | ARFS_IPV6_TCP, | |
686 | ARFS_IPV4_UDP, | |
687 | ARFS_IPV6_UDP, | |
688 | ARFS_NUM_TYPES, | |
689 | }; | |
690 | ||
691 | struct mlx5e_arfs_tables { | |
692 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
693 | /* Protect aRFS rules list */ |
694 | spinlock_t arfs_lock; | |
695 | struct list_head rules; | |
696 | int last_filter_id; | |
697 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
698 | }; |
699 | ||
700 | /* NIC prio FTS */ | |
701 | enum { | |
702 | MLX5E_VLAN_FT_LEVEL = 0, | |
703 | MLX5E_L2_FT_LEVEL, | |
704 | MLX5E_TTC_FT_LEVEL, | |
705 | MLX5E_ARFS_FT_LEVEL | |
706 | }; | |
707 | ||
6dc6071c MG |
708 | struct mlx5e_ethtool_table { |
709 | struct mlx5_flow_table *ft; | |
710 | int num_rules; | |
711 | }; | |
712 | ||
1174fce8 | 713 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
714 | #define ETHTOOL_NUM_L2_FTS 4 |
715 | ||
716 | struct mlx5e_ethtool_steering { | |
1174fce8 | 717 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
718 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
719 | struct list_head rules; | |
720 | int tot_num_rules; | |
721 | }; | |
722 | ||
acff797c MG |
723 | struct mlx5e_flow_steering { |
724 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 725 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
726 | struct mlx5e_tc_table tc; |
727 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
728 | struct mlx5e_l2_table l2; |
729 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 730 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
731 | }; |
732 | ||
398f3351 | 733 | struct mlx5e_rqt { |
1da36696 | 734 | u32 rqtn; |
398f3351 HHZ |
735 | bool enabled; |
736 | }; | |
737 | ||
738 | struct mlx5e_tir { | |
739 | u32 tirn; | |
740 | struct mlx5e_rqt rqt; | |
741 | struct list_head list; | |
1da36696 TT |
742 | }; |
743 | ||
acff797c MG |
744 | enum { |
745 | MLX5E_TC_PRIO = 0, | |
746 | MLX5E_NIC_PRIO | |
747 | }; | |
748 | ||
f62b8bb8 AV |
749 | struct mlx5e_priv { |
750 | /* priv data path fields - start */ | |
acc6c595 SM |
751 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
752 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
f62b8bb8 AV |
753 | /* priv data path fields - end */ |
754 | ||
755 | unsigned long state; | |
756 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 757 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 758 | |
ff9c852f | 759 | struct mlx5e_channels channels; |
f62b8bb8 | 760 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 761 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
762 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
763 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 764 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
c139dbfd | 765 | int hard_mtu; |
f62b8bb8 | 766 | |
acff797c | 767 | struct mlx5e_flow_steering fs; |
b3f63c3d | 768 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 | 769 | |
7bb29755 | 770 | struct workqueue_struct *wq; |
f62b8bb8 AV |
771 | struct work_struct update_carrier_work; |
772 | struct work_struct set_rx_mode_work; | |
3947ca18 | 773 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
774 | struct delayed_work update_stats_work; |
775 | ||
776 | struct mlx5_core_dev *mdev; | |
777 | struct net_device *netdev; | |
778 | struct mlx5e_stats stats; | |
ef9814de | 779 | struct mlx5e_tstamp tstamp; |
593cf338 | 780 | u16 q_counter; |
3a6a931d HN |
781 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
782 | struct mlx5e_dcbx dcbx; | |
783 | #endif | |
784 | ||
6bfd390b | 785 | const struct mlx5e_profile *profile; |
127ea380 | 786 | void *ppriv; |
f62b8bb8 AV |
787 | }; |
788 | ||
a43b25da SM |
789 | struct mlx5e_profile { |
790 | void (*init)(struct mlx5_core_dev *mdev, | |
791 | struct net_device *netdev, | |
792 | const struct mlx5e_profile *profile, void *ppriv); | |
793 | void (*cleanup)(struct mlx5e_priv *priv); | |
794 | int (*init_rx)(struct mlx5e_priv *priv); | |
795 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
796 | int (*init_tx)(struct mlx5e_priv *priv); | |
797 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
798 | void (*enable)(struct mlx5e_priv *priv); | |
799 | void (*disable)(struct mlx5e_priv *priv); | |
800 | void (*update_stats)(struct mlx5e_priv *priv); | |
7ca42c80 | 801 | void (*update_carrier)(struct mlx5e_priv *priv); |
a43b25da | 802 | int (*max_nch)(struct mlx5_core_dev *mdev); |
20fd0c19 SM |
803 | struct { |
804 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
805 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
806 | } rx_handlers; | |
a43b25da SM |
807 | int max_tc; |
808 | }; | |
809 | ||
665bc539 GP |
810 | void mlx5e_build_ptys2ethtool_map(void); |
811 | ||
f62b8bb8 AV |
812 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
813 | void *accel_priv, select_queue_fallback_t fallback); | |
814 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
815 | |
816 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
817 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
818 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 819 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 820 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
1c4bf940 | 821 | bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq); |
31391048 SM |
822 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
823 | void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq); | |
461017cb | 824 | |
4415a031 TT |
825 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
826 | bool recycle); | |
2f48af12 | 827 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 828 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 829 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 830 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 831 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
832 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
833 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
834 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
835 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
836 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
837 | ||
cb3c7fd4 GR |
838 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
839 | void mlx5e_rx_am_work(struct work_struct *work); | |
840 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
841 | ||
3834a5e6 | 842 | void mlx5e_update_stats(struct mlx5e_priv *priv, bool full); |
f62b8bb8 | 843 | |
acff797c MG |
844 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
845 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 846 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 847 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
848 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
849 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
850 | u64 *buf); | |
f913a72a MG |
851 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
852 | int location); | |
853 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
854 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
855 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
856 | struct ethtool_rx_flow_spec *fs); | |
857 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
858 | int location); | |
859 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
860 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
861 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
862 | ||
ef9814de EBE |
863 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
864 | struct skb_shared_hwtstamps *hwts); | |
865 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
866 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
ee7f1220 EE |
867 | void mlx5e_pps_event_handler(struct mlx5e_priv *priv, |
868 | struct ptp_clock_event *event); | |
1170fbd8 FD |
869 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
870 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 871 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 872 | |
f62b8bb8 AV |
873 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
874 | u16 vid); | |
875 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
876 | u16 vid); | |
877 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
878 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 879 | |
a5f97fee SM |
880 | struct mlx5e_redirect_rqt_param { |
881 | bool is_rss; | |
882 | union { | |
883 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
884 | struct { | |
885 | u8 hfunc; | |
886 | struct mlx5e_channels *channels; | |
887 | } rss; /* RSS data */ | |
888 | }; | |
889 | }; | |
890 | ||
891 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
892 | struct mlx5e_redirect_rqt_param rrp); | |
6a9764ef SM |
893 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
894 | enum mlx5e_traffic_types tt, | |
895 | void *tirc); | |
2d75b2bc | 896 | |
f62b8bb8 AV |
897 | int mlx5e_open_locked(struct net_device *netdev); |
898 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
899 | |
900 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
901 | struct mlx5e_channels *chs); | |
902 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
903 | |
904 | /* Function pointer to be used to modify WH settings while | |
905 | * switching channels | |
906 | */ | |
907 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
55c2503d | 908 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
909 | struct mlx5e_channels *new_chs, |
910 | mlx5e_fp_hw_modify hw_modify); | |
603f4a45 SM |
911 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
912 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 913 | |
d8c9660d TT |
914 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
915 | u32 *indirection_rqt, int len, | |
85082dba | 916 | int num_channels); |
b797a684 | 917 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 918 | |
9908aa29 TT |
919 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
920 | u8 cq_period_mode); | |
6a9764ef SM |
921 | void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, |
922 | struct mlx5e_params *params, u8 rq_type); | |
9908aa29 | 923 | |
864b2d71 SM |
924 | static inline |
925 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 926 | { |
864b2d71 SM |
927 | u16 pi = *pc & wq->sz_m1; |
928 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
929 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
930 | ||
931 | memset(cseg, 0, sizeof(*cseg)); | |
932 | ||
933 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
934 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
935 | ||
936 | (*pc)++; | |
937 | ||
938 | return wqe; | |
939 | } | |
940 | ||
941 | static inline | |
942 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
943 | void __iomem *uar_map, | |
944 | struct mlx5_wqe_ctrl_seg *ctrl) | |
945 | { | |
946 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
947 | /* ensure wqe is visible to device before updating doorbell record */ |
948 | dma_wmb(); | |
949 | ||
864b2d71 | 950 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
951 | |
952 | /* ensure doorbell record is visible to device before ringing the | |
953 | * doorbell | |
954 | */ | |
955 | wmb(); | |
f62b8bb8 | 956 | |
864b2d71 | 957 | mlx5_write64((__be32 *)ctrl, uar_map, NULL); |
f62b8bb8 AV |
958 | } |
959 | ||
960 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
961 | { | |
962 | struct mlx5_core_cq *mcq; | |
963 | ||
964 | mcq = &cq->mcq; | |
5fe9dec0 | 965 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
966 | } |
967 | ||
7e426671 TT |
968 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
969 | { | |
ec8b9981 | 970 | return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
7e426671 TT |
971 | } |
972 | ||
f62b8bb8 | 973 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
974 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
975 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
976 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 977 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
08fb1dac SM |
978 | #endif |
979 | ||
1cabe6b0 MG |
980 | #ifndef CONFIG_RFS_ACCEL |
981 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
982 | { | |
983 | return 0; | |
984 | } | |
985 | ||
986 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
987 | |
988 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
989 | { | |
9eb78923 | 990 | return -EOPNOTSUPP; |
45bf454a MG |
991 | } |
992 | ||
993 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
994 | { | |
9eb78923 | 995 | return -EOPNOTSUPP; |
45bf454a | 996 | } |
1cabe6b0 MG |
997 | #else |
998 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
999 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
1000 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
1001 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
1002 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
1003 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
1004 | #endif |
1005 | ||
58d52291 | 1006 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
1007 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
1008 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
1009 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
1010 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
1011 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1012 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 1013 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 1014 | |
bc81b9d3 | 1015 | /* common netdev helpers */ |
8f493ffd SM |
1016 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1017 | ||
1018 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv); | |
1019 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv); | |
1020 | ||
cb67b832 | 1021 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); |
8f493ffd | 1022 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1023 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); |
1024 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
8f493ffd SM |
1025 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
1026 | ||
50854114 | 1027 | int mlx5e_create_ttc_table(struct mlx5e_priv *priv); |
bc81b9d3 SM |
1028 | void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv); |
1029 | ||
5426a0b2 SM |
1030 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
1031 | u32 underlay_qpn, u32 *tisn); | |
1032 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); | |
1033 | ||
cb67b832 HHZ |
1034 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
1035 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
1036 | int mlx5e_close(struct net_device *netdev); | |
1037 | int mlx5e_open(struct net_device *netdev); | |
1038 | void mlx5e_update_stats_work(struct work_struct *work); | |
2b029556 | 1039 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); |
cb67b832 | 1040 | |
076b0936 ES |
1041 | /* ethtool helpers */ |
1042 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1043 | struct ethtool_drvinfo *drvinfo); | |
1044 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1045 | uint32_t stringset, uint8_t *data); | |
1046 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1047 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1048 | struct ethtool_stats *stats, u64 *data); | |
1049 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1050 | struct ethtool_ringparam *param); | |
1051 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1052 | struct ethtool_ringparam *param); | |
1053 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1054 | struct ethtool_channels *ch); | |
1055 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1056 | struct ethtool_channels *ch); | |
1057 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1058 | struct ethtool_coalesce *coal); | |
1059 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1060 | struct ethtool_coalesce *coal); | |
3844b07e FD |
1061 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1062 | struct ethtool_ts_info *info); | |
3ffaabec OG |
1063 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1064 | struct ethtool_flash *flash); | |
076b0936 | 1065 | |
2c3b5bee SM |
1066 | /* mlx5e generic netdev management API */ |
1067 | struct net_device* | |
1068 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
1069 | void *ppriv); | |
1070 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); | |
1071 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1072 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
8f493ffd SM |
1073 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
1074 | struct mlx5e_params *params, | |
1075 | u16 max_channels); | |
2c3b5bee | 1076 | |
1afff42c | 1077 | #endif /* __MLX5_EN_H__ */ |