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f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/if_vlan.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/mlx5/driver.h> | |
36 | #include <linux/mlx5/qp.h> | |
37 | #include <linux/mlx5/cq.h> | |
d18a9470 | 38 | #include <linux/mlx5/vport.h> |
f62b8bb8 AV |
39 | #include "wq.h" |
40 | #include "transobj.h" | |
41 | #include "mlx5_core.h" | |
42 | ||
43 | #define MLX5E_MAX_NUM_TC 8 | |
44 | ||
45 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 | |
46 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
47 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
48 | ||
49 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 | |
50 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa | |
51 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
52 | ||
53 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (16 * 1024) | |
54 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 | |
55 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
56 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
57 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
58 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
59 | #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 | |
f62b8bb8 AV |
60 | |
61 | #define MLX5E_TX_CQ_POLL_BUDGET 128 | |
62 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 63 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 AV |
64 | |
65 | static const char vport_strings[][ETH_GSTRING_LEN] = { | |
66 | /* vport statistics */ | |
67 | "rx_packets", | |
68 | "rx_bytes", | |
69 | "tx_packets", | |
70 | "tx_bytes", | |
71 | "rx_error_packets", | |
72 | "rx_error_bytes", | |
73 | "tx_error_packets", | |
74 | "tx_error_bytes", | |
75 | "rx_unicast_packets", | |
76 | "rx_unicast_bytes", | |
77 | "tx_unicast_packets", | |
78 | "tx_unicast_bytes", | |
79 | "rx_multicast_packets", | |
80 | "rx_multicast_bytes", | |
81 | "tx_multicast_packets", | |
82 | "tx_multicast_bytes", | |
83 | "rx_broadcast_packets", | |
84 | "rx_broadcast_bytes", | |
85 | "tx_broadcast_packets", | |
86 | "tx_broadcast_bytes", | |
87 | ||
88 | /* SW counters */ | |
89 | "tso_packets", | |
90 | "tso_bytes", | |
91 | "lro_packets", | |
92 | "lro_bytes", | |
93 | "rx_csum_good", | |
94 | "rx_csum_none", | |
95 | "tx_csum_offload", | |
96 | "tx_queue_stopped", | |
97 | "tx_queue_wake", | |
98 | "tx_queue_dropped", | |
99 | "rx_wqe_err", | |
100 | }; | |
101 | ||
102 | struct mlx5e_vport_stats { | |
103 | /* HW counters */ | |
104 | u64 rx_packets; | |
105 | u64 rx_bytes; | |
106 | u64 tx_packets; | |
107 | u64 tx_bytes; | |
108 | u64 rx_error_packets; | |
109 | u64 rx_error_bytes; | |
110 | u64 tx_error_packets; | |
111 | u64 tx_error_bytes; | |
112 | u64 rx_unicast_packets; | |
113 | u64 rx_unicast_bytes; | |
114 | u64 tx_unicast_packets; | |
115 | u64 tx_unicast_bytes; | |
116 | u64 rx_multicast_packets; | |
117 | u64 rx_multicast_bytes; | |
118 | u64 tx_multicast_packets; | |
119 | u64 tx_multicast_bytes; | |
120 | u64 rx_broadcast_packets; | |
121 | u64 rx_broadcast_bytes; | |
122 | u64 tx_broadcast_packets; | |
123 | u64 tx_broadcast_bytes; | |
124 | ||
125 | /* SW counters */ | |
126 | u64 tso_packets; | |
127 | u64 tso_bytes; | |
128 | u64 lro_packets; | |
129 | u64 lro_bytes; | |
130 | u64 rx_csum_good; | |
131 | u64 rx_csum_none; | |
132 | u64 tx_csum_offload; | |
133 | u64 tx_queue_stopped; | |
134 | u64 tx_queue_wake; | |
135 | u64 tx_queue_dropped; | |
136 | u64 rx_wqe_err; | |
137 | ||
138 | #define NUM_VPORT_COUNTERS 31 | |
139 | }; | |
140 | ||
141 | static const char rq_stats_strings[][ETH_GSTRING_LEN] = { | |
142 | "packets", | |
143 | "csum_none", | |
144 | "lro_packets", | |
145 | "lro_bytes", | |
146 | "wqe_err" | |
147 | }; | |
148 | ||
149 | struct mlx5e_rq_stats { | |
150 | u64 packets; | |
151 | u64 csum_none; | |
152 | u64 lro_packets; | |
153 | u64 lro_bytes; | |
154 | u64 wqe_err; | |
155 | #define NUM_RQ_STATS 5 | |
156 | }; | |
157 | ||
158 | static const char sq_stats_strings[][ETH_GSTRING_LEN] = { | |
159 | "packets", | |
160 | "tso_packets", | |
161 | "tso_bytes", | |
162 | "csum_offload_none", | |
163 | "stopped", | |
164 | "wake", | |
165 | "dropped", | |
166 | "nop" | |
167 | }; | |
168 | ||
169 | struct mlx5e_sq_stats { | |
170 | u64 packets; | |
171 | u64 tso_packets; | |
172 | u64 tso_bytes; | |
173 | u64 csum_offload_none; | |
174 | u64 stopped; | |
175 | u64 wake; | |
176 | u64 dropped; | |
177 | u64 nop; | |
178 | #define NUM_SQ_STATS 8 | |
179 | }; | |
180 | ||
181 | struct mlx5e_stats { | |
182 | struct mlx5e_vport_stats vport; | |
183 | }; | |
184 | ||
185 | struct mlx5e_params { | |
186 | u8 log_sq_size; | |
187 | u8 log_rq_size; | |
188 | u16 num_channels; | |
189 | u8 default_vlan_prio; | |
190 | u8 num_tc; | |
191 | u16 rx_cq_moderation_usec; | |
192 | u16 rx_cq_moderation_pkts; | |
193 | u16 tx_cq_moderation_usec; | |
194 | u16 tx_cq_moderation_pkts; | |
195 | u16 min_rx_wqes; | |
196 | u16 rx_hash_log_tbl_sz; | |
197 | bool lro_en; | |
198 | u32 lro_wqe_sz; | |
2be6967c | 199 | u8 rss_hfunc; |
58d52291 | 200 | u16 tx_max_inline; |
f62b8bb8 AV |
201 | }; |
202 | ||
203 | enum { | |
204 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
205 | }; | |
206 | ||
207 | enum cq_flags { | |
208 | MLX5E_CQ_HAS_CQES = 1, | |
209 | }; | |
210 | ||
211 | struct mlx5e_cq { | |
212 | /* data path - accessed per cqe */ | |
213 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
214 | unsigned long flags; |
215 | ||
216 | /* data path - accessed per napi poll */ | |
217 | struct napi_struct *napi; | |
218 | struct mlx5_core_cq mcq; | |
219 | struct mlx5e_channel *channel; | |
220 | ||
221 | /* control */ | |
222 | struct mlx5_wq_ctrl wq_ctrl; | |
223 | } ____cacheline_aligned_in_smp; | |
224 | ||
225 | struct mlx5e_rq { | |
226 | /* data path */ | |
227 | struct mlx5_wq_ll wq; | |
228 | u32 wqe_sz; | |
229 | struct sk_buff **skb; | |
230 | ||
231 | struct device *pdev; | |
232 | struct net_device *netdev; | |
233 | struct mlx5e_rq_stats stats; | |
234 | struct mlx5e_cq cq; | |
235 | ||
236 | unsigned long state; | |
237 | int ix; | |
238 | ||
239 | /* control */ | |
240 | struct mlx5_wq_ctrl wq_ctrl; | |
241 | u32 rqn; | |
242 | struct mlx5e_channel *channel; | |
243 | } ____cacheline_aligned_in_smp; | |
244 | ||
245 | struct mlx5e_tx_skb_cb { | |
246 | u32 num_bytes; | |
247 | u8 num_wqebbs; | |
248 | u8 num_dma; | |
249 | }; | |
250 | ||
251 | #define MLX5E_TX_SKB_CB(__skb) ((struct mlx5e_tx_skb_cb *)__skb->cb) | |
252 | ||
253 | struct mlx5e_sq_dma { | |
254 | dma_addr_t addr; | |
255 | u32 size; | |
256 | }; | |
257 | ||
258 | enum { | |
259 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
260 | }; | |
261 | ||
262 | struct mlx5e_sq { | |
263 | /* data path */ | |
264 | ||
265 | /* dirtied @completion */ | |
266 | u16 cc; | |
267 | u32 dma_fifo_cc; | |
268 | ||
269 | /* dirtied @xmit */ | |
270 | u16 pc ____cacheline_aligned_in_smp; | |
271 | u32 dma_fifo_pc; | |
88a85f99 AS |
272 | u16 bf_offset; |
273 | u16 prev_cc; | |
274 | u8 bf_budget; | |
f62b8bb8 AV |
275 | struct mlx5e_sq_stats stats; |
276 | ||
277 | struct mlx5e_cq cq; | |
278 | ||
279 | /* pointers to per packet info: write@xmit, read@completion */ | |
280 | struct sk_buff **skb; | |
281 | struct mlx5e_sq_dma *dma_fifo; | |
282 | ||
283 | /* read only */ | |
284 | struct mlx5_wq_cyc wq; | |
285 | u32 dma_fifo_mask; | |
286 | void __iomem *uar_map; | |
88a85f99 | 287 | void __iomem *uar_bf_map; |
f62b8bb8 AV |
288 | struct netdev_queue *txq; |
289 | u32 sqn; | |
88a85f99 | 290 | u16 bf_buf_size; |
12be4b21 SM |
291 | u16 max_inline; |
292 | u16 edge; | |
f62b8bb8 AV |
293 | struct device *pdev; |
294 | __be32 mkey_be; | |
295 | unsigned long state; | |
296 | ||
297 | /* control path */ | |
298 | struct mlx5_wq_ctrl wq_ctrl; | |
299 | struct mlx5_uar uar; | |
300 | struct mlx5e_channel *channel; | |
301 | int tc; | |
302 | } ____cacheline_aligned_in_smp; | |
303 | ||
304 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
305 | { | |
306 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
307 | (sq->cc == sq->pc)); | |
308 | } | |
309 | ||
310 | enum channel_flags { | |
311 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
312 | }; | |
313 | ||
314 | struct mlx5e_channel { | |
315 | /* data path */ | |
316 | struct mlx5e_rq rq; | |
317 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
318 | struct napi_struct napi; | |
319 | struct device *pdev; | |
320 | struct net_device *netdev; | |
321 | __be32 mkey_be; | |
322 | u8 num_tc; | |
323 | unsigned long flags; | |
03289b88 | 324 | int tc_to_txq_map[MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
325 | |
326 | /* control */ | |
327 | struct mlx5e_priv *priv; | |
328 | int ix; | |
329 | int cpu; | |
330 | }; | |
331 | ||
332 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
333 | MLX5E_TT_IPV4_TCP, |
334 | MLX5E_TT_IPV6_TCP, | |
335 | MLX5E_TT_IPV4_UDP, | |
336 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
337 | MLX5E_TT_IPV4_IPSEC_AH, |
338 | MLX5E_TT_IPV6_IPSEC_AH, | |
339 | MLX5E_TT_IPV4_IPSEC_ESP, | |
340 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
341 | MLX5E_TT_IPV4, |
342 | MLX5E_TT_IPV6, | |
343 | MLX5E_TT_ANY, | |
344 | MLX5E_NUM_TT, | |
f62b8bb8 AV |
345 | }; |
346 | ||
4cbeaff5 AS |
347 | enum mlx5e_rqt_ix { |
348 | MLX5E_INDIRECTION_RQT, | |
349 | MLX5E_SINGLE_RQ_RQT, | |
350 | MLX5E_NUM_RQT, | |
f62b8bb8 AV |
351 | }; |
352 | ||
353 | struct mlx5e_eth_addr_info { | |
354 | u8 addr[ETH_ALEN + 2]; | |
355 | u32 tt_vec; | |
356 | u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */ | |
357 | }; | |
358 | ||
359 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) | |
360 | ||
361 | struct mlx5e_eth_addr_db { | |
362 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
363 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
364 | struct mlx5e_eth_addr_info broadcast; | |
365 | struct mlx5e_eth_addr_info allmulti; | |
366 | struct mlx5e_eth_addr_info promisc; | |
367 | bool broadcast_enabled; | |
368 | bool allmulti_enabled; | |
369 | bool promisc_enabled; | |
370 | }; | |
371 | ||
372 | enum { | |
373 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, | |
374 | MLX5E_STATE_OPENED, | |
375 | }; | |
376 | ||
377 | struct mlx5e_vlan_db { | |
378 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
379 | u32 active_vlans_ft_ix[VLAN_N_VID]; | |
380 | u32 untagged_rule_ft_ix; | |
381 | u32 any_vlan_rule_ft_ix; | |
382 | bool filter_disabled; | |
383 | }; | |
384 | ||
385 | struct mlx5e_flow_table { | |
386 | void *vlan; | |
387 | void *main; | |
388 | }; | |
389 | ||
390 | struct mlx5e_priv { | |
391 | /* priv data path fields - start */ | |
f62b8bb8 | 392 | int default_vlan_prio; |
03289b88 | 393 | struct mlx5e_sq **txq_to_sq_map; |
f62b8bb8 AV |
394 | /* priv data path fields - end */ |
395 | ||
396 | unsigned long state; | |
397 | struct mutex state_lock; /* Protects Interface state */ | |
398 | struct mlx5_uar cq_uar; | |
399 | u32 pdn; | |
3191e05f | 400 | u32 tdn; |
f62b8bb8 AV |
401 | struct mlx5_core_mr mr; |
402 | ||
403 | struct mlx5e_channel **channel; | |
404 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
4cbeaff5 | 405 | u32 rqtn[MLX5E_NUM_RQT]; |
f62b8bb8 AV |
406 | u32 tirn[MLX5E_NUM_TT]; |
407 | ||
408 | struct mlx5e_flow_table ft; | |
409 | struct mlx5e_eth_addr_db eth_addr; | |
410 | struct mlx5e_vlan_db vlan; | |
411 | ||
412 | struct mlx5e_params params; | |
413 | spinlock_t async_events_spinlock; /* sync hw events */ | |
414 | struct work_struct update_carrier_work; | |
415 | struct work_struct set_rx_mode_work; | |
416 | struct delayed_work update_stats_work; | |
417 | ||
418 | struct mlx5_core_dev *mdev; | |
419 | struct net_device *netdev; | |
420 | struct mlx5e_stats stats; | |
421 | }; | |
422 | ||
423 | #define MLX5E_NET_IP_ALIGN 2 | |
424 | ||
425 | struct mlx5e_tx_wqe { | |
426 | struct mlx5_wqe_ctrl_seg ctrl; | |
427 | struct mlx5_wqe_eth_seg eth; | |
428 | }; | |
429 | ||
430 | struct mlx5e_rx_wqe { | |
431 | struct mlx5_wqe_srq_next_seg next; | |
432 | struct mlx5_wqe_data_seg data; | |
433 | }; | |
434 | ||
435 | enum mlx5e_link_mode { | |
436 | MLX5E_1000BASE_CX_SGMII = 0, | |
437 | MLX5E_1000BASE_KX = 1, | |
438 | MLX5E_10GBASE_CX4 = 2, | |
439 | MLX5E_10GBASE_KX4 = 3, | |
440 | MLX5E_10GBASE_KR = 4, | |
441 | MLX5E_20GBASE_KR2 = 5, | |
442 | MLX5E_40GBASE_CR4 = 6, | |
443 | MLX5E_40GBASE_KR4 = 7, | |
444 | MLX5E_56GBASE_R4 = 8, | |
445 | MLX5E_10GBASE_CR = 12, | |
446 | MLX5E_10GBASE_SR = 13, | |
447 | MLX5E_10GBASE_ER = 14, | |
448 | MLX5E_40GBASE_SR4 = 15, | |
449 | MLX5E_40GBASE_LR4 = 16, | |
450 | MLX5E_100GBASE_CR4 = 20, | |
451 | MLX5E_100GBASE_SR4 = 21, | |
452 | MLX5E_100GBASE_KR4 = 22, | |
453 | MLX5E_100GBASE_LR4 = 23, | |
454 | MLX5E_100BASE_TX = 24, | |
455 | MLX5E_100BASE_T = 25, | |
456 | MLX5E_10GBASE_T = 26, | |
457 | MLX5E_25GBASE_CR = 27, | |
458 | MLX5E_25GBASE_KR = 28, | |
459 | MLX5E_25GBASE_SR = 29, | |
460 | MLX5E_50GBASE_CR2 = 30, | |
461 | MLX5E_50GBASE_KR2 = 31, | |
462 | MLX5E_LINK_MODES_NUMBER, | |
463 | }; | |
464 | ||
465 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
466 | ||
12be4b21 | 467 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
468 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
469 | void *accel_priv, select_queue_fallback_t fallback); | |
470 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
471 | |
472 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
473 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
474 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
475 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq); | |
476 | bool mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); | |
477 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); | |
478 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); | |
479 | ||
480 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
481 | ||
482 | int mlx5e_open_flow_table(struct mlx5e_priv *priv); | |
483 | void mlx5e_close_flow_table(struct mlx5e_priv *priv); | |
484 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); | |
485 | void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); | |
486 | void mlx5e_set_rx_mode_work(struct work_struct *work); | |
487 | ||
488 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, | |
489 | u16 vid); | |
490 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
491 | u16 vid); | |
492 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
493 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
494 | int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); | |
495 | void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); | |
496 | ||
497 | int mlx5e_open_locked(struct net_device *netdev); | |
498 | int mlx5e_close_locked(struct net_device *netdev); | |
f62b8bb8 AV |
499 | |
500 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
88a85f99 | 501 | struct mlx5e_tx_wqe *wqe, int bf_sz) |
f62b8bb8 | 502 | { |
88a85f99 AS |
503 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
504 | ||
f62b8bb8 AV |
505 | /* ensure wqe is visible to device before updating doorbell record */ |
506 | dma_wmb(); | |
507 | ||
508 | *sq->wq.db = cpu_to_be32(sq->pc); | |
509 | ||
510 | /* ensure doorbell record is visible to device before ringing the | |
511 | * doorbell | |
512 | */ | |
513 | wmb(); | |
514 | ||
88a85f99 AS |
515 | if (bf_sz) { |
516 | __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz); | |
517 | ||
518 | /* flush the write-combining mapped buffer */ | |
519 | wmb(); | |
520 | ||
521 | } else { | |
522 | mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL); | |
523 | } | |
f62b8bb8 AV |
524 | |
525 | sq->bf_offset ^= sq->bf_buf_size; | |
526 | } | |
527 | ||
528 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
529 | { | |
530 | struct mlx5_core_cq *mcq; | |
531 | ||
532 | mcq = &cq->mcq; | |
533 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
534 | } | |
535 | ||
536 | extern const struct ethtool_ops mlx5e_ethtool_ops; | |
58d52291 | 537 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |