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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
d8bec2b2 MKL |
54 | #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
55 | #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
56 | ||
f62b8bb8 AV |
57 | #define MLX5E_MAX_NUM_TC 8 |
58 | ||
e842b100 | 59 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
60 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
61 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
62 | ||
e842b100 | 63 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
64 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
65 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
66 | ||
461017cb | 67 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 68 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
69 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
70 | ||
1bfecfca SM |
71 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
72 | ||
f32f5bd2 DJ |
73 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
74 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
75 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
76 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
77 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
78 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
79 | ||
7e426671 | 80 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
81 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
82 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
83 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
84 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
85 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
86 | |
87 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
ec8b9981 TT |
88 | #define MLX5E_REQUIRED_MTTS(wqes) \ |
89 | (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
90 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) | |
fe4c988b | 91 | |
bc77b240 | 92 | #define MLX5_UMR_ALIGN (2048) |
461017cb TT |
93 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
94 | ||
d9a40271 | 95 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
96 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
97 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
98 | ||
f62b8bb8 | 99 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 100 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
101 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
102 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
103 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
104 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 105 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 106 | |
936896e9 AS |
107 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
108 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 109 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 110 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 111 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
112 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
113 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 114 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 115 | |
f10b7cc7 SM |
116 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
117 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
118 | ||
b5503b99 SM |
119 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
120 | #define MLX5E_XDP_IHS_DS_COUNT \ | |
121 | DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS) | |
122 | #define MLX5E_XDP_TX_DS_COUNT \ | |
b70149dd | 123 | ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) |
b5503b99 SM |
124 | #define MLX5E_XDP_TX_WQEBBS \ |
125 | DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS) | |
126 | ||
86d722ad | 127 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 128 | |
461017cb TT |
129 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
130 | { | |
131 | switch (wq_type) { | |
132 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
133 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
134 | wq_size / 2); | |
135 | default: | |
136 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
137 | wq_size / 2); | |
138 | } | |
139 | } | |
140 | ||
141 | static inline int mlx5_min_log_rq_size(int wq_type) | |
142 | { | |
143 | switch (wq_type) { | |
144 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
145 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
146 | default: | |
147 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
148 | } | |
149 | } | |
150 | ||
151 | static inline int mlx5_max_log_rq_size(int wq_type) | |
152 | { | |
153 | switch (wq_type) { | |
154 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
155 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
156 | default: | |
157 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
158 | } | |
159 | } | |
160 | ||
2f48af12 TT |
161 | struct mlx5e_tx_wqe { |
162 | struct mlx5_wqe_ctrl_seg ctrl; | |
163 | struct mlx5_wqe_eth_seg eth; | |
164 | }; | |
165 | ||
166 | struct mlx5e_rx_wqe { | |
167 | struct mlx5_wqe_srq_next_seg next; | |
168 | struct mlx5_wqe_data_seg data; | |
169 | }; | |
86d722ad | 170 | |
bc77b240 TT |
171 | struct mlx5e_umr_wqe { |
172 | struct mlx5_wqe_ctrl_seg ctrl; | |
173 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
174 | struct mlx5_mkey_seg mkc; | |
175 | struct mlx5_wqe_data_seg data; | |
176 | }; | |
177 | ||
d605d668 KH |
178 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
179 | ||
4e59e288 | 180 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 181 | "rx_cqe_moder", |
9bcc8606 | 182 | "rx_cqe_compress", |
4e59e288 GP |
183 | }; |
184 | ||
185 | enum mlx5e_priv_flag { | |
9908aa29 | 186 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
9bcc8606 | 187 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1), |
4e59e288 GP |
188 | }; |
189 | ||
59ece1c9 SD |
190 | #define MLX5E_SET_PFLAG(priv, pflag, enable) \ |
191 | do { \ | |
192 | if (enable) \ | |
193 | (priv)->params.pflags |= (pflag); \ | |
194 | else \ | |
195 | (priv)->params.pflags &= ~(pflag); \ | |
4e59e288 GP |
196 | } while (0) |
197 | ||
59ece1c9 SD |
198 | #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag))) |
199 | ||
08fb1dac SM |
200 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
201 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
202 | #endif |
203 | ||
9908aa29 TT |
204 | struct mlx5e_cq_moder { |
205 | u16 usec; | |
206 | u16 pkts; | |
207 | }; | |
208 | ||
f62b8bb8 AV |
209 | struct mlx5e_params { |
210 | u8 log_sq_size; | |
461017cb | 211 | u8 rq_wq_type; |
d9d9f156 TT |
212 | u8 mpwqe_log_stride_sz; |
213 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
214 | u8 log_rq_size; |
215 | u16 num_channels; | |
f62b8bb8 | 216 | u8 num_tc; |
9908aa29 | 217 | u8 rx_cq_period_mode; |
9bcc8606 | 218 | bool rx_cqe_compress_def; |
9908aa29 TT |
219 | struct mlx5e_cq_moder rx_cq_moderation; |
220 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 221 | u16 min_rx_wqes; |
f62b8bb8 AV |
222 | bool lro_en; |
223 | u32 lro_wqe_sz; | |
58d52291 | 224 | u16 tx_max_inline; |
cff92d7c | 225 | u8 tx_min_inline_mode; |
2d75b2bc AS |
226 | u8 rss_hfunc; |
227 | u8 toeplitz_hash_key[40]; | |
228 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 229 | bool vlan_strip_disable; |
cb3c7fd4 | 230 | bool rx_am_enabled; |
2b029556 | 231 | u32 lro_timeout; |
59ece1c9 | 232 | u32 pflags; |
f62b8bb8 AV |
233 | }; |
234 | ||
3a6a931d HN |
235 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
236 | struct mlx5e_cee_config { | |
237 | /* bw pct for priority group */ | |
238 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
239 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
240 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
241 | bool pfc_enable; | |
242 | }; | |
243 | ||
244 | enum { | |
245 | MLX5_DCB_CHG_RESET, | |
246 | MLX5_DCB_NO_CHG, | |
247 | MLX5_DCB_CHG_NO_RESET, | |
248 | }; | |
249 | ||
250 | struct mlx5e_dcbx { | |
e207b7e9 | 251 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 252 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
820c2c5e HN |
253 | |
254 | /* The only setting that cannot be read from FW */ | |
255 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
3a6a931d HN |
256 | }; |
257 | #endif | |
258 | ||
ef9814de EBE |
259 | struct mlx5e_tstamp { |
260 | rwlock_t lock; | |
261 | struct cyclecounter cycles; | |
262 | struct timecounter clock; | |
263 | struct hwtstamp_config hwtstamp_config; | |
264 | u32 nominal_c_mult; | |
265 | unsigned long overflow_period; | |
266 | struct delayed_work overflow_work; | |
267 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
268 | struct ptp_clock *ptp; |
269 | struct ptp_clock_info ptp_info; | |
ee7f1220 | 270 | u8 *pps_pin_caps; |
ef9814de EBE |
271 | }; |
272 | ||
f62b8bb8 | 273 | enum { |
c0f1147d | 274 | MLX5E_RQ_STATE_ENABLED, |
bc77b240 | 275 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 276 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
277 | }; |
278 | ||
f62b8bb8 AV |
279 | struct mlx5e_cq { |
280 | /* data path - accessed per cqe */ | |
281 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
282 | |
283 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 284 | u16 event_ctr; |
f62b8bb8 AV |
285 | struct napi_struct *napi; |
286 | struct mlx5_core_cq mcq; | |
287 | struct mlx5e_channel *channel; | |
50cfa25a | 288 | struct mlx5e_priv *priv; |
f62b8bb8 | 289 | |
7219ab34 TT |
290 | /* cqe decompression */ |
291 | struct mlx5_cqe64 title; | |
292 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
293 | u8 mini_arr_idx; | |
294 | u16 decmprs_left; | |
295 | u16 decmprs_wqe_counter; | |
296 | ||
f62b8bb8 | 297 | /* control */ |
1c1b5228 | 298 | struct mlx5_frag_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
299 | } ____cacheline_aligned_in_smp; |
300 | ||
2f48af12 TT |
301 | struct mlx5e_rq; |
302 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
303 | struct mlx5_cqe64 *cqe); | |
304 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
305 | u16 ix); | |
306 | ||
6cd392a0 DJ |
307 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix); |
308 | ||
461017cb TT |
309 | struct mlx5e_dma_info { |
310 | struct page *page; | |
311 | dma_addr_t addr; | |
312 | }; | |
313 | ||
cb3c7fd4 GR |
314 | struct mlx5e_rx_am_stats { |
315 | int ppms; /* packets per msec */ | |
316 | int epms; /* events per msec */ | |
317 | }; | |
318 | ||
319 | struct mlx5e_rx_am_sample { | |
320 | ktime_t time; | |
321 | unsigned int pkt_ctr; | |
322 | u16 event_ctr; | |
323 | }; | |
324 | ||
325 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
326 | u8 state; | |
327 | struct mlx5e_rx_am_stats prev_stats; | |
328 | struct mlx5e_rx_am_sample start_sample; | |
329 | struct work_struct work; | |
330 | u8 profile_ix; | |
331 | u8 mode; | |
332 | u8 tune_state; | |
333 | u8 steps_right; | |
334 | u8 steps_left; | |
335 | u8 tired; | |
336 | }; | |
337 | ||
4415a031 TT |
338 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
339 | * or a MPWQE (for striding rq). | |
340 | */ | |
341 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
342 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
343 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
344 | struct mlx5e_page_cache { | |
345 | u32 head; | |
346 | u32 tail; | |
347 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
348 | }; | |
349 | ||
f62b8bb8 AV |
350 | struct mlx5e_rq { |
351 | /* data path */ | |
352 | struct mlx5_wq_ll wq; | |
1bfecfca | 353 | |
21c59685 SM |
354 | union { |
355 | struct mlx5e_dma_info *dma_info; | |
356 | struct { | |
357 | struct mlx5e_mpw_info *info; | |
358 | void *mtt_no_align; | |
21c59685 SM |
359 | } mpwqe; |
360 | }; | |
1bfecfca SM |
361 | struct { |
362 | u8 page_order; | |
363 | u32 wqe_sz; /* wqe data buffer size */ | |
b5503b99 | 364 | u8 map_dir; /* dma map direction */ |
1bfecfca | 365 | } buff; |
bc77b240 | 366 | __be32 mkey_be; |
f62b8bb8 AV |
367 | |
368 | struct device *pdev; | |
369 | struct net_device *netdev; | |
ef9814de | 370 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
371 | struct mlx5e_rq_stats stats; |
372 | struct mlx5e_cq cq; | |
4415a031 TT |
373 | struct mlx5e_page_cache page_cache; |
374 | ||
2f48af12 TT |
375 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
376 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 377 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
378 | |
379 | unsigned long state; | |
380 | int ix; | |
d8bec2b2 | 381 | u16 rx_headroom; |
f62b8bb8 | 382 | |
cb3c7fd4 | 383 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
86994156 | 384 | struct bpf_prog *xdp_prog; |
cb3c7fd4 | 385 | |
f62b8bb8 AV |
386 | /* control */ |
387 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 388 | u8 wq_type; |
d9d9f156 TT |
389 | u32 mpwqe_stride_sz; |
390 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
391 | u32 rqn; |
392 | struct mlx5e_channel *channel; | |
50cfa25a | 393 | struct mlx5e_priv *priv; |
ec8b9981 | 394 | struct mlx5_core_mkey umr_mkey; |
f62b8bb8 AV |
395 | } ____cacheline_aligned_in_smp; |
396 | ||
bc77b240 TT |
397 | struct mlx5e_umr_dma_info { |
398 | __be64 *mtt; | |
bc77b240 | 399 | dma_addr_t mtt_addr; |
7e426671 TT |
400 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
401 | struct mlx5e_umr_wqe wqe; | |
bc77b240 TT |
402 | }; |
403 | ||
404 | struct mlx5e_mpw_info { | |
7e426671 | 405 | struct mlx5e_umr_dma_info umr; |
bc77b240 TT |
406 | u16 consumed_strides; |
407 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
bc77b240 TT |
408 | }; |
409 | ||
34802a42 | 410 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
411 | u32 num_bytes; |
412 | u8 num_wqebbs; | |
413 | u8 num_dma; | |
414 | }; | |
415 | ||
d4e28cbd AS |
416 | enum mlx5e_dma_map_type { |
417 | MLX5E_DMA_MAP_SINGLE, | |
418 | MLX5E_DMA_MAP_PAGE | |
419 | }; | |
420 | ||
f62b8bb8 | 421 | struct mlx5e_sq_dma { |
d4e28cbd AS |
422 | dma_addr_t addr; |
423 | u32 size; | |
424 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
425 | }; |
426 | ||
427 | enum { | |
c0f1147d | 428 | MLX5E_SQ_STATE_ENABLED, |
0ba42241 | 429 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
430 | }; |
431 | ||
b5503b99 | 432 | struct mlx5e_sq_wqe_info { |
d3c9bc27 TT |
433 | u8 opcode; |
434 | u8 num_wqebbs; | |
435 | }; | |
436 | ||
f10b7cc7 SM |
437 | enum mlx5e_sq_type { |
438 | MLX5E_SQ_TXQ, | |
b5503b99 SM |
439 | MLX5E_SQ_ICO, |
440 | MLX5E_SQ_XDP | |
f10b7cc7 SM |
441 | }; |
442 | ||
f62b8bb8 AV |
443 | struct mlx5e_sq { |
444 | /* data path */ | |
445 | ||
446 | /* dirtied @completion */ | |
447 | u16 cc; | |
448 | u32 dma_fifo_cc; | |
449 | ||
450 | /* dirtied @xmit */ | |
451 | u16 pc ____cacheline_aligned_in_smp; | |
452 | u32 dma_fifo_pc; | |
88a85f99 AS |
453 | u16 bf_offset; |
454 | u16 prev_cc; | |
455 | u8 bf_budget; | |
f62b8bb8 AV |
456 | struct mlx5e_sq_stats stats; |
457 | ||
458 | struct mlx5e_cq cq; | |
459 | ||
f10b7cc7 SM |
460 | /* pointers to per tx element info: write@xmit, read@completion */ |
461 | union { | |
462 | struct { | |
463 | struct sk_buff **skb; | |
464 | struct mlx5e_sq_dma *dma_fifo; | |
465 | struct mlx5e_tx_wqe_info *wqe_info; | |
466 | } txq; | |
b5503b99 SM |
467 | struct mlx5e_sq_wqe_info *ico_wqe; |
468 | struct { | |
469 | struct mlx5e_sq_wqe_info *wqe_info; | |
470 | struct mlx5e_dma_info *di; | |
35b510e2 | 471 | bool doorbell; |
b5503b99 | 472 | } xdp; |
f10b7cc7 | 473 | } db; |
f62b8bb8 AV |
474 | |
475 | /* read only */ | |
476 | struct mlx5_wq_cyc wq; | |
477 | u32 dma_fifo_mask; | |
8ca967ab | 478 | void __iomem *uar_map; |
f62b8bb8 AV |
479 | struct netdev_queue *txq; |
480 | u32 sqn; | |
88a85f99 | 481 | u16 bf_buf_size; |
12be4b21 | 482 | u16 max_inline; |
ae76715d | 483 | u8 min_inline_mode; |
12be4b21 | 484 | u16 edge; |
f62b8bb8 | 485 | struct device *pdev; |
ef9814de | 486 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
487 | __be32 mkey_be; |
488 | unsigned long state; | |
489 | ||
490 | /* control path */ | |
491 | struct mlx5_wq_ctrl wq_ctrl; | |
30aa60b3 | 492 | struct mlx5_sq_bfreg bfreg; |
f62b8bb8 AV |
493 | struct mlx5e_channel *channel; |
494 | int tc; | |
507f0c81 | 495 | u32 rate_limit; |
f10b7cc7 | 496 | u8 type; |
f62b8bb8 AV |
497 | } ____cacheline_aligned_in_smp; |
498 | ||
499 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
500 | { | |
501 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
502 | (sq->cc == sq->pc)); | |
503 | } | |
504 | ||
505 | enum channel_flags { | |
506 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
507 | }; | |
508 | ||
509 | struct mlx5e_channel { | |
510 | /* data path */ | |
511 | struct mlx5e_rq rq; | |
b5503b99 | 512 | struct mlx5e_sq xdp_sq; |
f62b8bb8 | 513 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; |
d3c9bc27 | 514 | struct mlx5e_sq icosq; /* internal control operations */ |
b5503b99 | 515 | bool xdp; |
f62b8bb8 AV |
516 | struct napi_struct napi; |
517 | struct device *pdev; | |
518 | struct net_device *netdev; | |
519 | __be32 mkey_be; | |
520 | u8 num_tc; | |
521 | unsigned long flags; | |
522 | ||
523 | /* control */ | |
524 | struct mlx5e_priv *priv; | |
525 | int ix; | |
526 | int cpu; | |
527 | }; | |
528 | ||
529 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
530 | MLX5E_TT_IPV4_TCP, |
531 | MLX5E_TT_IPV6_TCP, | |
532 | MLX5E_TT_IPV4_UDP, | |
533 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
534 | MLX5E_TT_IPV4_IPSEC_AH, |
535 | MLX5E_TT_IPV6_IPSEC_AH, | |
536 | MLX5E_TT_IPV4_IPSEC_ESP, | |
537 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
538 | MLX5E_TT_IPV4, |
539 | MLX5E_TT_IPV6, | |
540 | MLX5E_TT_ANY, | |
541 | MLX5E_NUM_TT, | |
1da36696 | 542 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
543 | }; |
544 | ||
acff797c | 545 | enum { |
e0f46eb9 | 546 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
547 | MLX5E_STATE_OPENED, |
548 | MLX5E_STATE_DESTROYING, | |
549 | }; | |
550 | ||
551 | struct mlx5e_vxlan_db { | |
552 | spinlock_t lock; /* protect vxlan table */ | |
553 | struct radix_tree_root tree; | |
554 | }; | |
555 | ||
33cfaaa8 | 556 | struct mlx5e_l2_rule { |
f62b8bb8 | 557 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 558 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
559 | }; |
560 | ||
acff797c MG |
561 | struct mlx5e_flow_table { |
562 | int num_groups; | |
563 | struct mlx5_flow_table *t; | |
564 | struct mlx5_flow_group **g; | |
565 | }; | |
566 | ||
33cfaaa8 | 567 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 568 | |
acff797c MG |
569 | struct mlx5e_tc_table { |
570 | struct mlx5_flow_table *t; | |
571 | ||
572 | struct rhashtable_params ht_params; | |
573 | struct rhashtable ht; | |
f62b8bb8 AV |
574 | }; |
575 | ||
acff797c MG |
576 | struct mlx5e_vlan_table { |
577 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 578 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
74491de9 MB |
579 | struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID]; |
580 | struct mlx5_flow_handle *untagged_rule; | |
8a271746 MHY |
581 | struct mlx5_flow_handle *any_cvlan_rule; |
582 | struct mlx5_flow_handle *any_svlan_rule; | |
583 | bool filter_disabled; | |
f62b8bb8 AV |
584 | }; |
585 | ||
33cfaaa8 MG |
586 | struct mlx5e_l2_table { |
587 | struct mlx5e_flow_table ft; | |
588 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
589 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
590 | struct mlx5e_l2_rule broadcast; | |
591 | struct mlx5e_l2_rule allmulti; | |
592 | struct mlx5e_l2_rule promisc; | |
593 | bool broadcast_enabled; | |
594 | bool allmulti_enabled; | |
595 | bool promisc_enabled; | |
596 | }; | |
597 | ||
598 | /* L3/L4 traffic type classifier */ | |
599 | struct mlx5e_ttc_table { | |
600 | struct mlx5e_flow_table ft; | |
74491de9 | 601 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
33cfaaa8 MG |
602 | }; |
603 | ||
18c908e4 MG |
604 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
605 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
606 | struct arfs_table { |
607 | struct mlx5e_flow_table ft; | |
74491de9 | 608 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 609 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
610 | }; |
611 | ||
612 | enum arfs_type { | |
613 | ARFS_IPV4_TCP, | |
614 | ARFS_IPV6_TCP, | |
615 | ARFS_IPV4_UDP, | |
616 | ARFS_IPV6_UDP, | |
617 | ARFS_NUM_TYPES, | |
618 | }; | |
619 | ||
620 | struct mlx5e_arfs_tables { | |
621 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
622 | /* Protect aRFS rules list */ |
623 | spinlock_t arfs_lock; | |
624 | struct list_head rules; | |
625 | int last_filter_id; | |
626 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
627 | }; |
628 | ||
629 | /* NIC prio FTS */ | |
630 | enum { | |
631 | MLX5E_VLAN_FT_LEVEL = 0, | |
632 | MLX5E_L2_FT_LEVEL, | |
633 | MLX5E_TTC_FT_LEVEL, | |
634 | MLX5E_ARFS_FT_LEVEL | |
635 | }; | |
636 | ||
6dc6071c MG |
637 | struct mlx5e_ethtool_table { |
638 | struct mlx5_flow_table *ft; | |
639 | int num_rules; | |
640 | }; | |
641 | ||
1174fce8 | 642 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
643 | #define ETHTOOL_NUM_L2_FTS 4 |
644 | ||
645 | struct mlx5e_ethtool_steering { | |
1174fce8 | 646 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
647 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
648 | struct list_head rules; | |
649 | int tot_num_rules; | |
650 | }; | |
651 | ||
acff797c MG |
652 | struct mlx5e_flow_steering { |
653 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 654 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
655 | struct mlx5e_tc_table tc; |
656 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
657 | struct mlx5e_l2_table l2; |
658 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 659 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
660 | }; |
661 | ||
398f3351 | 662 | struct mlx5e_rqt { |
1da36696 | 663 | u32 rqtn; |
398f3351 HHZ |
664 | bool enabled; |
665 | }; | |
666 | ||
667 | struct mlx5e_tir { | |
668 | u32 tirn; | |
669 | struct mlx5e_rqt rqt; | |
670 | struct list_head list; | |
1da36696 TT |
671 | }; |
672 | ||
acff797c MG |
673 | enum { |
674 | MLX5E_TC_PRIO = 0, | |
675 | MLX5E_NIC_PRIO | |
676 | }; | |
677 | ||
6bfd390b HHZ |
678 | struct mlx5e_profile { |
679 | void (*init)(struct mlx5_core_dev *mdev, | |
680 | struct net_device *netdev, | |
127ea380 | 681 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
682 | void (*cleanup)(struct mlx5e_priv *priv); |
683 | int (*init_rx)(struct mlx5e_priv *priv); | |
684 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
685 | int (*init_tx)(struct mlx5e_priv *priv); | |
686 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
687 | void (*enable)(struct mlx5e_priv *priv); | |
688 | void (*disable)(struct mlx5e_priv *priv); | |
689 | void (*update_stats)(struct mlx5e_priv *priv); | |
690 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
691 | int max_tc; | |
692 | }; | |
693 | ||
f62b8bb8 AV |
694 | struct mlx5e_priv { |
695 | /* priv data path fields - start */ | |
03289b88 | 696 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 697 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
86994156 | 698 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
699 | /* priv data path fields - end */ |
700 | ||
701 | unsigned long state; | |
702 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 703 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
704 | |
705 | struct mlx5e_channel **channel; | |
706 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
398f3351 | 707 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
708 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
709 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 710 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 711 | |
acff797c | 712 | struct mlx5e_flow_steering fs; |
b3f63c3d | 713 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
714 | |
715 | struct mlx5e_params params; | |
7bb29755 | 716 | struct workqueue_struct *wq; |
f62b8bb8 AV |
717 | struct work_struct update_carrier_work; |
718 | struct work_struct set_rx_mode_work; | |
3947ca18 | 719 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
720 | struct delayed_work update_stats_work; |
721 | ||
722 | struct mlx5_core_dev *mdev; | |
723 | struct net_device *netdev; | |
724 | struct mlx5e_stats stats; | |
ef9814de | 725 | struct mlx5e_tstamp tstamp; |
593cf338 | 726 | u16 q_counter; |
3a6a931d HN |
727 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
728 | struct mlx5e_dcbx dcbx; | |
729 | #endif | |
730 | ||
6bfd390b | 731 | const struct mlx5e_profile *profile; |
127ea380 | 732 | void *ppriv; |
f62b8bb8 AV |
733 | }; |
734 | ||
665bc539 GP |
735 | void mlx5e_build_ptys2ethtool_map(void); |
736 | ||
12be4b21 | 737 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
738 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
739 | void *accel_priv, select_queue_fallback_t fallback); | |
740 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
741 | |
742 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
743 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
744 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 745 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 746 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
b5503b99 | 747 | void mlx5e_free_sq_descs(struct mlx5e_sq *sq); |
461017cb | 748 | |
4415a031 TT |
749 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
750 | bool recycle); | |
2f48af12 | 751 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 752 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 753 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 754 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 755 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
756 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
757 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
758 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
759 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
760 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
761 | ||
cb3c7fd4 GR |
762 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
763 | void mlx5e_rx_am_work(struct work_struct *work); | |
764 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
765 | ||
f62b8bb8 AV |
766 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
767 | ||
acff797c MG |
768 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
769 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 770 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 771 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
772 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
773 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
774 | u64 *buf); | |
f913a72a MG |
775 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
776 | int location); | |
777 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
778 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
779 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
780 | struct ethtool_rx_flow_spec *fs); | |
781 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
782 | int location); | |
783 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
784 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
785 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
786 | ||
ef9814de EBE |
787 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
788 | struct skb_shared_hwtstamps *hwts); | |
789 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
790 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
ee7f1220 EE |
791 | void mlx5e_pps_event_handler(struct mlx5e_priv *priv, |
792 | struct ptp_clock_event *event); | |
ef9814de EBE |
793 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); |
794 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
5eb0249b | 795 | void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 796 | |
f62b8bb8 AV |
797 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
798 | u16 vid); | |
799 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
800 | u16 vid); | |
801 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
802 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 803 | |
36350114 GP |
804 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
805 | ||
1da36696 | 806 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
a100ff3e GP |
807 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc, |
808 | enum mlx5e_traffic_types tt); | |
2d75b2bc | 809 | |
f62b8bb8 AV |
810 | int mlx5e_open_locked(struct net_device *netdev); |
811 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
812 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
813 | u32 *indirection_rqt, int len, | |
85082dba | 814 | int num_channels); |
b797a684 | 815 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 816 | |
9908aa29 TT |
817 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
818 | u8 cq_period_mode); | |
6dc4b54e | 819 | void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type); |
9908aa29 | 820 | |
f62b8bb8 | 821 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
bc77b240 | 822 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 823 | { |
30aa60b3 | 824 | u16 ofst = sq->bf_offset; |
88a85f99 | 825 | |
f62b8bb8 AV |
826 | /* ensure wqe is visible to device before updating doorbell record */ |
827 | dma_wmb(); | |
828 | ||
829 | *sq->wq.db = cpu_to_be32(sq->pc); | |
830 | ||
831 | /* ensure doorbell record is visible to device before ringing the | |
832 | * doorbell | |
833 | */ | |
834 | wmb(); | |
0ba42241 | 835 | if (bf_sz) |
8ca967ab | 836 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 837 | else |
8ca967ab | 838 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
839 | /* flush the write-combining mapped buffer */ |
840 | wmb(); | |
f62b8bb8 AV |
841 | |
842 | sq->bf_offset ^= sq->bf_buf_size; | |
843 | } | |
844 | ||
845 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
846 | { | |
847 | struct mlx5_core_cq *mcq; | |
848 | ||
849 | mcq = &cq->mcq; | |
5fe9dec0 | 850 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
851 | } |
852 | ||
7e426671 TT |
853 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
854 | { | |
ec8b9981 | 855 | return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
7e426671 TT |
856 | } |
857 | ||
f62b8bb8 | 858 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
859 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
860 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
861 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 862 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
08fb1dac SM |
863 | #endif |
864 | ||
1cabe6b0 MG |
865 | #ifndef CONFIG_RFS_ACCEL |
866 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
867 | { | |
868 | return 0; | |
869 | } | |
870 | ||
871 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
872 | |
873 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
874 | { | |
9eb78923 | 875 | return -EOPNOTSUPP; |
45bf454a MG |
876 | } |
877 | ||
878 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
879 | { | |
9eb78923 | 880 | return -EOPNOTSUPP; |
45bf454a | 881 | } |
1cabe6b0 MG |
882 | #else |
883 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
884 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
885 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
886 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
887 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
888 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
889 | #endif |
890 | ||
58d52291 | 891 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
892 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
893 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
894 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
895 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
896 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
897 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
0952da79 SM |
898 | int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev, |
899 | bool enable_uc_lb); | |
1afff42c | 900 | |
cb67b832 HHZ |
901 | struct mlx5_eswitch_rep; |
902 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
903 | struct mlx5_eswitch_rep *rep); | |
904 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
905 | struct mlx5_eswitch_rep *rep); | |
906 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
907 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
908 | struct mlx5_eswitch_rep *rep); | |
909 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
910 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
911 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
f5f82476 | 912 | void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
370bad0f | 913 | void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv); |
cb67b832 HHZ |
914 | |
915 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
916 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
917 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
918 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
919 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
920 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
921 | int mlx5e_close(struct net_device *netdev); | |
922 | int mlx5e_open(struct net_device *netdev); | |
923 | void mlx5e_update_stats_work(struct work_struct *work); | |
26e59d80 MHY |
924 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
925 | const struct mlx5e_profile *profile, | |
926 | void *ppriv); | |
cb67b832 | 927 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); |
26e59d80 MHY |
928 | int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); |
929 | void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); | |
2b029556 | 930 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); |
cb67b832 | 931 | |
370bad0f OG |
932 | int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, |
933 | void *sp); | |
934 | bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id); | |
935 | ||
936 | bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv); | |
937 | bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv); | |
1afff42c | 938 | #endif /* __MLX5_EN_H__ */ |