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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
d8bec2b2 MKL |
54 | #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
55 | #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
56 | ||
f62b8bb8 AV |
57 | #define MLX5E_MAX_NUM_TC 8 |
58 | ||
e842b100 | 59 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
60 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
61 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
62 | ||
e842b100 | 63 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
64 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
65 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
66 | ||
461017cb | 67 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 68 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
69 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
70 | ||
1bfecfca SM |
71 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
72 | ||
f32f5bd2 DJ |
73 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
74 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
75 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
76 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
77 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
78 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
79 | ||
7e426671 | 80 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
81 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
82 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
83 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
84 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
85 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
86 | |
87 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
ec8b9981 TT |
88 | #define MLX5E_REQUIRED_MTTS(wqes) \ |
89 | (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
90 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) | |
fe4c988b | 91 | |
bc77b240 | 92 | #define MLX5_UMR_ALIGN (2048) |
461017cb TT |
93 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
94 | ||
d9a40271 | 95 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
96 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
97 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
98 | ||
f62b8bb8 | 99 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 100 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
101 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
102 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
103 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
104 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 105 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 106 | |
936896e9 AS |
107 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
108 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 109 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 110 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 111 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
112 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
113 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
114 | ||
f10b7cc7 SM |
115 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
116 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
117 | ||
b5503b99 | 118 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
b5503b99 | 119 | #define MLX5E_XDP_TX_DS_COUNT \ |
b70149dd | 120 | ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) |
b5503b99 | 121 | |
86d722ad | 122 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 123 | |
461017cb TT |
124 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
125 | { | |
126 | switch (wq_type) { | |
127 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
128 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
129 | wq_size / 2); | |
130 | default: | |
131 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
132 | wq_size / 2); | |
133 | } | |
134 | } | |
135 | ||
136 | static inline int mlx5_min_log_rq_size(int wq_type) | |
137 | { | |
138 | switch (wq_type) { | |
139 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
140 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
141 | default: | |
142 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
143 | } | |
144 | } | |
145 | ||
146 | static inline int mlx5_max_log_rq_size(int wq_type) | |
147 | { | |
148 | switch (wq_type) { | |
149 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
150 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
151 | default: | |
152 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
153 | } | |
154 | } | |
155 | ||
2f48af12 TT |
156 | struct mlx5e_tx_wqe { |
157 | struct mlx5_wqe_ctrl_seg ctrl; | |
158 | struct mlx5_wqe_eth_seg eth; | |
159 | }; | |
160 | ||
161 | struct mlx5e_rx_wqe { | |
162 | struct mlx5_wqe_srq_next_seg next; | |
163 | struct mlx5_wqe_data_seg data; | |
164 | }; | |
86d722ad | 165 | |
bc77b240 TT |
166 | struct mlx5e_umr_wqe { |
167 | struct mlx5_wqe_ctrl_seg ctrl; | |
168 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
169 | struct mlx5_mkey_seg mkc; | |
170 | struct mlx5_wqe_data_seg data; | |
171 | }; | |
172 | ||
d605d668 KH |
173 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
174 | ||
4e59e288 | 175 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 176 | "rx_cqe_moder", |
9bcc8606 | 177 | "rx_cqe_compress", |
4e59e288 GP |
178 | }; |
179 | ||
180 | enum mlx5e_priv_flag { | |
9908aa29 | 181 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
9bcc8606 | 182 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1), |
4e59e288 GP |
183 | }; |
184 | ||
59ece1c9 SD |
185 | #define MLX5E_SET_PFLAG(priv, pflag, enable) \ |
186 | do { \ | |
187 | if (enable) \ | |
188 | (priv)->params.pflags |= (pflag); \ | |
189 | else \ | |
190 | (priv)->params.pflags &= ~(pflag); \ | |
4e59e288 GP |
191 | } while (0) |
192 | ||
59ece1c9 SD |
193 | #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag))) |
194 | ||
08fb1dac SM |
195 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
196 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
197 | #endif |
198 | ||
9908aa29 TT |
199 | struct mlx5e_cq_moder { |
200 | u16 usec; | |
201 | u16 pkts; | |
202 | }; | |
203 | ||
f62b8bb8 AV |
204 | struct mlx5e_params { |
205 | u8 log_sq_size; | |
461017cb | 206 | u8 rq_wq_type; |
d9d9f156 TT |
207 | u8 mpwqe_log_stride_sz; |
208 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
209 | u8 log_rq_size; |
210 | u16 num_channels; | |
f62b8bb8 | 211 | u8 num_tc; |
9908aa29 | 212 | u8 rx_cq_period_mode; |
9bcc8606 | 213 | bool rx_cqe_compress_def; |
9908aa29 TT |
214 | struct mlx5e_cq_moder rx_cq_moderation; |
215 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 216 | u16 min_rx_wqes; |
f62b8bb8 AV |
217 | bool lro_en; |
218 | u32 lro_wqe_sz; | |
58d52291 | 219 | u16 tx_max_inline; |
cff92d7c | 220 | u8 tx_min_inline_mode; |
2d75b2bc AS |
221 | u8 rss_hfunc; |
222 | u8 toeplitz_hash_key[40]; | |
223 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 224 | bool vlan_strip_disable; |
cb3c7fd4 | 225 | bool rx_am_enabled; |
2b029556 | 226 | u32 lro_timeout; |
59ece1c9 | 227 | u32 pflags; |
f62b8bb8 AV |
228 | }; |
229 | ||
3a6a931d HN |
230 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
231 | struct mlx5e_cee_config { | |
232 | /* bw pct for priority group */ | |
233 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
234 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
235 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
236 | bool pfc_enable; | |
237 | }; | |
238 | ||
239 | enum { | |
240 | MLX5_DCB_CHG_RESET, | |
241 | MLX5_DCB_NO_CHG, | |
242 | MLX5_DCB_CHG_NO_RESET, | |
243 | }; | |
244 | ||
245 | struct mlx5e_dcbx { | |
e207b7e9 | 246 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 247 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
820c2c5e HN |
248 | |
249 | /* The only setting that cannot be read from FW */ | |
250 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
3a6a931d HN |
251 | }; |
252 | #endif | |
253 | ||
ef9814de EBE |
254 | struct mlx5e_tstamp { |
255 | rwlock_t lock; | |
256 | struct cyclecounter cycles; | |
257 | struct timecounter clock; | |
258 | struct hwtstamp_config hwtstamp_config; | |
259 | u32 nominal_c_mult; | |
260 | unsigned long overflow_period; | |
261 | struct delayed_work overflow_work; | |
262 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
263 | struct ptp_clock *ptp; |
264 | struct ptp_clock_info ptp_info; | |
ee7f1220 | 265 | u8 *pps_pin_caps; |
ef9814de EBE |
266 | }; |
267 | ||
f62b8bb8 | 268 | enum { |
c0f1147d | 269 | MLX5E_RQ_STATE_ENABLED, |
bc77b240 | 270 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 271 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
272 | }; |
273 | ||
f62b8bb8 AV |
274 | struct mlx5e_cq { |
275 | /* data path - accessed per cqe */ | |
276 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
277 | |
278 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 279 | u16 event_ctr; |
f62b8bb8 AV |
280 | struct napi_struct *napi; |
281 | struct mlx5_core_cq mcq; | |
282 | struct mlx5e_channel *channel; | |
50cfa25a | 283 | struct mlx5e_priv *priv; |
f62b8bb8 | 284 | |
7219ab34 TT |
285 | /* cqe decompression */ |
286 | struct mlx5_cqe64 title; | |
287 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
288 | u8 mini_arr_idx; | |
289 | u16 decmprs_left; | |
290 | u16 decmprs_wqe_counter; | |
291 | ||
f62b8bb8 | 292 | /* control */ |
1c1b5228 | 293 | struct mlx5_frag_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
294 | } ____cacheline_aligned_in_smp; |
295 | ||
eba2db2b SM |
296 | struct mlx5e_tx_wqe_info { |
297 | u32 num_bytes; | |
298 | u8 num_wqebbs; | |
299 | u8 num_dma; | |
300 | }; | |
301 | ||
302 | enum mlx5e_dma_map_type { | |
303 | MLX5E_DMA_MAP_SINGLE, | |
304 | MLX5E_DMA_MAP_PAGE | |
305 | }; | |
306 | ||
307 | struct mlx5e_sq_dma { | |
308 | dma_addr_t addr; | |
309 | u32 size; | |
310 | enum mlx5e_dma_map_type type; | |
311 | }; | |
312 | ||
313 | enum { | |
314 | MLX5E_SQ_STATE_ENABLED, | |
315 | }; | |
316 | ||
317 | struct mlx5e_sq_wqe_info { | |
318 | u8 opcode; | |
319 | u8 num_wqebbs; | |
320 | }; | |
2f48af12 | 321 | |
31391048 | 322 | struct mlx5e_txqsq { |
eba2db2b SM |
323 | /* data path */ |
324 | ||
325 | /* dirtied @completion */ | |
326 | u16 cc; | |
327 | u32 dma_fifo_cc; | |
328 | ||
329 | /* dirtied @xmit */ | |
330 | u16 pc ____cacheline_aligned_in_smp; | |
331 | u32 dma_fifo_pc; | |
332 | struct mlx5e_sq_stats stats; | |
333 | ||
334 | struct mlx5e_cq cq; | |
335 | ||
31391048 SM |
336 | /* write@xmit, read@completion */ |
337 | struct { | |
338 | struct sk_buff **skb; | |
339 | struct mlx5e_sq_dma *dma_fifo; | |
340 | struct mlx5e_tx_wqe_info *wqe_info; | |
eba2db2b SM |
341 | } db; |
342 | ||
343 | /* read only */ | |
344 | struct mlx5_wq_cyc wq; | |
345 | u32 dma_fifo_mask; | |
346 | void __iomem *uar_map; | |
347 | struct netdev_queue *txq; | |
348 | u32 sqn; | |
349 | u16 max_inline; | |
350 | u8 min_inline_mode; | |
351 | u16 edge; | |
352 | struct device *pdev; | |
353 | struct mlx5e_tstamp *tstamp; | |
354 | __be32 mkey_be; | |
355 | unsigned long state; | |
356 | ||
357 | /* control path */ | |
358 | struct mlx5_wq_ctrl wq_ctrl; | |
359 | struct mlx5e_channel *channel; | |
360 | int tc; | |
acc6c595 | 361 | int txq_ix; |
eba2db2b | 362 | u32 rate_limit; |
31391048 SM |
363 | } ____cacheline_aligned_in_smp; |
364 | ||
365 | struct mlx5e_xdpsq { | |
366 | /* data path */ | |
367 | ||
368 | /* dirtied @rx completion */ | |
369 | u16 cc; | |
370 | u16 pc; | |
371 | ||
372 | struct mlx5e_cq cq; | |
373 | ||
374 | /* write@xmit, read@completion */ | |
375 | struct { | |
376 | struct mlx5e_dma_info *di; | |
377 | bool doorbell; | |
378 | } db; | |
379 | ||
380 | /* read only */ | |
381 | struct mlx5_wq_cyc wq; | |
382 | void __iomem *uar_map; | |
383 | u32 sqn; | |
384 | struct device *pdev; | |
385 | __be32 mkey_be; | |
386 | u8 min_inline_mode; | |
387 | unsigned long state; | |
388 | ||
389 | /* control path */ | |
390 | struct mlx5_wq_ctrl wq_ctrl; | |
391 | struct mlx5e_channel *channel; | |
392 | } ____cacheline_aligned_in_smp; | |
393 | ||
394 | struct mlx5e_icosq { | |
395 | /* data path */ | |
396 | ||
397 | /* dirtied @completion */ | |
398 | u16 cc; | |
399 | ||
400 | /* dirtied @xmit */ | |
401 | u16 pc ____cacheline_aligned_in_smp; | |
402 | u32 dma_fifo_pc; | |
403 | u16 prev_cc; | |
404 | ||
405 | struct mlx5e_cq cq; | |
406 | ||
407 | /* write@xmit, read@completion */ | |
408 | struct { | |
409 | struct mlx5e_sq_wqe_info *ico_wqe; | |
410 | } db; | |
411 | ||
412 | /* read only */ | |
413 | struct mlx5_wq_cyc wq; | |
414 | void __iomem *uar_map; | |
415 | u32 sqn; | |
416 | u16 edge; | |
417 | struct device *pdev; | |
418 | __be32 mkey_be; | |
419 | unsigned long state; | |
420 | ||
421 | /* control path */ | |
422 | struct mlx5_wq_ctrl wq_ctrl; | |
423 | struct mlx5e_channel *channel; | |
eba2db2b SM |
424 | } ____cacheline_aligned_in_smp; |
425 | ||
864b2d71 SM |
426 | static inline bool |
427 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 428 | { |
864b2d71 | 429 | return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc)); |
eba2db2b | 430 | } |
6cd392a0 | 431 | |
461017cb TT |
432 | struct mlx5e_dma_info { |
433 | struct page *page; | |
434 | dma_addr_t addr; | |
435 | }; | |
436 | ||
eba2db2b SM |
437 | struct mlx5e_umr_dma_info { |
438 | __be64 *mtt; | |
439 | dma_addr_t mtt_addr; | |
440 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; | |
441 | struct mlx5e_umr_wqe wqe; | |
442 | }; | |
443 | ||
444 | struct mlx5e_mpw_info { | |
445 | struct mlx5e_umr_dma_info umr; | |
446 | u16 consumed_strides; | |
447 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
448 | }; | |
449 | ||
cb3c7fd4 GR |
450 | struct mlx5e_rx_am_stats { |
451 | int ppms; /* packets per msec */ | |
452 | int epms; /* events per msec */ | |
453 | }; | |
454 | ||
455 | struct mlx5e_rx_am_sample { | |
456 | ktime_t time; | |
457 | unsigned int pkt_ctr; | |
458 | u16 event_ctr; | |
459 | }; | |
460 | ||
461 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
462 | u8 state; | |
463 | struct mlx5e_rx_am_stats prev_stats; | |
464 | struct mlx5e_rx_am_sample start_sample; | |
465 | struct work_struct work; | |
466 | u8 profile_ix; | |
467 | u8 mode; | |
468 | u8 tune_state; | |
469 | u8 steps_right; | |
470 | u8 steps_left; | |
471 | u8 tired; | |
472 | }; | |
473 | ||
4415a031 TT |
474 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
475 | * or a MPWQE (for striding rq). | |
476 | */ | |
477 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
478 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
479 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
480 | struct mlx5e_page_cache { | |
481 | u32 head; | |
482 | u32 tail; | |
483 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
484 | }; | |
485 | ||
eba2db2b SM |
486 | struct mlx5e_rq; |
487 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
488 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16); | |
489 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); | |
490 | ||
f62b8bb8 AV |
491 | struct mlx5e_rq { |
492 | /* data path */ | |
493 | struct mlx5_wq_ll wq; | |
1bfecfca | 494 | |
21c59685 SM |
495 | union { |
496 | struct mlx5e_dma_info *dma_info; | |
497 | struct { | |
498 | struct mlx5e_mpw_info *info; | |
499 | void *mtt_no_align; | |
21c59685 SM |
500 | } mpwqe; |
501 | }; | |
1bfecfca SM |
502 | struct { |
503 | u8 page_order; | |
504 | u32 wqe_sz; /* wqe data buffer size */ | |
b5503b99 | 505 | u8 map_dir; /* dma map direction */ |
1bfecfca | 506 | } buff; |
bc77b240 | 507 | __be32 mkey_be; |
f62b8bb8 AV |
508 | |
509 | struct device *pdev; | |
510 | struct net_device *netdev; | |
ef9814de | 511 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
512 | struct mlx5e_rq_stats stats; |
513 | struct mlx5e_cq cq; | |
4415a031 TT |
514 | struct mlx5e_page_cache page_cache; |
515 | ||
2f48af12 TT |
516 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
517 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 518 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
519 | |
520 | unsigned long state; | |
521 | int ix; | |
d8bec2b2 | 522 | u16 rx_headroom; |
f62b8bb8 | 523 | |
cb3c7fd4 | 524 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
31871f87 SM |
525 | |
526 | /* XDP */ | |
86994156 | 527 | struct bpf_prog *xdp_prog; |
31391048 | 528 | struct mlx5e_xdpsq xdpsq; |
cb3c7fd4 | 529 | |
f62b8bb8 AV |
530 | /* control */ |
531 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 532 | u8 wq_type; |
d9d9f156 TT |
533 | u32 mpwqe_stride_sz; |
534 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
535 | u32 rqn; |
536 | struct mlx5e_channel *channel; | |
50cfa25a | 537 | struct mlx5e_priv *priv; |
ec8b9981 | 538 | struct mlx5_core_mkey umr_mkey; |
f62b8bb8 AV |
539 | } ____cacheline_aligned_in_smp; |
540 | ||
f62b8bb8 AV |
541 | enum channel_flags { |
542 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
543 | }; | |
544 | ||
545 | struct mlx5e_channel { | |
546 | /* data path */ | |
547 | struct mlx5e_rq rq; | |
31391048 SM |
548 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
549 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 550 | bool xdp; |
f62b8bb8 AV |
551 | struct napi_struct napi; |
552 | struct device *pdev; | |
553 | struct net_device *netdev; | |
554 | __be32 mkey_be; | |
555 | u8 num_tc; | |
556 | unsigned long flags; | |
557 | ||
558 | /* control */ | |
559 | struct mlx5e_priv *priv; | |
560 | int ix; | |
561 | int cpu; | |
562 | }; | |
563 | ||
ff9c852f SM |
564 | struct mlx5e_channels { |
565 | struct mlx5e_channel **c; | |
566 | unsigned int num; | |
567 | }; | |
568 | ||
f62b8bb8 | 569 | enum mlx5e_traffic_types { |
5a6f8aef AS |
570 | MLX5E_TT_IPV4_TCP, |
571 | MLX5E_TT_IPV6_TCP, | |
572 | MLX5E_TT_IPV4_UDP, | |
573 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
574 | MLX5E_TT_IPV4_IPSEC_AH, |
575 | MLX5E_TT_IPV6_IPSEC_AH, | |
576 | MLX5E_TT_IPV4_IPSEC_ESP, | |
577 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
578 | MLX5E_TT_IPV4, |
579 | MLX5E_TT_IPV6, | |
580 | MLX5E_TT_ANY, | |
581 | MLX5E_NUM_TT, | |
1da36696 | 582 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
583 | }; |
584 | ||
acff797c | 585 | enum { |
e0f46eb9 | 586 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
587 | MLX5E_STATE_OPENED, |
588 | MLX5E_STATE_DESTROYING, | |
589 | }; | |
590 | ||
591 | struct mlx5e_vxlan_db { | |
592 | spinlock_t lock; /* protect vxlan table */ | |
593 | struct radix_tree_root tree; | |
594 | }; | |
595 | ||
33cfaaa8 | 596 | struct mlx5e_l2_rule { |
f62b8bb8 | 597 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 598 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
599 | }; |
600 | ||
acff797c MG |
601 | struct mlx5e_flow_table { |
602 | int num_groups; | |
603 | struct mlx5_flow_table *t; | |
604 | struct mlx5_flow_group **g; | |
605 | }; | |
606 | ||
33cfaaa8 | 607 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 608 | |
acff797c MG |
609 | struct mlx5e_tc_table { |
610 | struct mlx5_flow_table *t; | |
611 | ||
612 | struct rhashtable_params ht_params; | |
613 | struct rhashtable ht; | |
f62b8bb8 AV |
614 | }; |
615 | ||
acff797c MG |
616 | struct mlx5e_vlan_table { |
617 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 618 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
74491de9 MB |
619 | struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID]; |
620 | struct mlx5_flow_handle *untagged_rule; | |
8a271746 MHY |
621 | struct mlx5_flow_handle *any_cvlan_rule; |
622 | struct mlx5_flow_handle *any_svlan_rule; | |
623 | bool filter_disabled; | |
f62b8bb8 AV |
624 | }; |
625 | ||
33cfaaa8 MG |
626 | struct mlx5e_l2_table { |
627 | struct mlx5e_flow_table ft; | |
628 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
629 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
630 | struct mlx5e_l2_rule broadcast; | |
631 | struct mlx5e_l2_rule allmulti; | |
632 | struct mlx5e_l2_rule promisc; | |
633 | bool broadcast_enabled; | |
634 | bool allmulti_enabled; | |
635 | bool promisc_enabled; | |
636 | }; | |
637 | ||
638 | /* L3/L4 traffic type classifier */ | |
639 | struct mlx5e_ttc_table { | |
640 | struct mlx5e_flow_table ft; | |
74491de9 | 641 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
33cfaaa8 MG |
642 | }; |
643 | ||
18c908e4 MG |
644 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
645 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
646 | struct arfs_table { |
647 | struct mlx5e_flow_table ft; | |
74491de9 | 648 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 649 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
650 | }; |
651 | ||
652 | enum arfs_type { | |
653 | ARFS_IPV4_TCP, | |
654 | ARFS_IPV6_TCP, | |
655 | ARFS_IPV4_UDP, | |
656 | ARFS_IPV6_UDP, | |
657 | ARFS_NUM_TYPES, | |
658 | }; | |
659 | ||
660 | struct mlx5e_arfs_tables { | |
661 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
662 | /* Protect aRFS rules list */ |
663 | spinlock_t arfs_lock; | |
664 | struct list_head rules; | |
665 | int last_filter_id; | |
666 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
667 | }; |
668 | ||
669 | /* NIC prio FTS */ | |
670 | enum { | |
671 | MLX5E_VLAN_FT_LEVEL = 0, | |
672 | MLX5E_L2_FT_LEVEL, | |
673 | MLX5E_TTC_FT_LEVEL, | |
674 | MLX5E_ARFS_FT_LEVEL | |
675 | }; | |
676 | ||
6dc6071c MG |
677 | struct mlx5e_ethtool_table { |
678 | struct mlx5_flow_table *ft; | |
679 | int num_rules; | |
680 | }; | |
681 | ||
1174fce8 | 682 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
683 | #define ETHTOOL_NUM_L2_FTS 4 |
684 | ||
685 | struct mlx5e_ethtool_steering { | |
1174fce8 | 686 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
687 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
688 | struct list_head rules; | |
689 | int tot_num_rules; | |
690 | }; | |
691 | ||
acff797c MG |
692 | struct mlx5e_flow_steering { |
693 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 694 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
695 | struct mlx5e_tc_table tc; |
696 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
697 | struct mlx5e_l2_table l2; |
698 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 699 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
700 | }; |
701 | ||
398f3351 | 702 | struct mlx5e_rqt { |
1da36696 | 703 | u32 rqtn; |
398f3351 HHZ |
704 | bool enabled; |
705 | }; | |
706 | ||
707 | struct mlx5e_tir { | |
708 | u32 tirn; | |
709 | struct mlx5e_rqt rqt; | |
710 | struct list_head list; | |
1da36696 TT |
711 | }; |
712 | ||
acff797c MG |
713 | enum { |
714 | MLX5E_TC_PRIO = 0, | |
715 | MLX5E_NIC_PRIO | |
716 | }; | |
717 | ||
6bfd390b HHZ |
718 | struct mlx5e_profile { |
719 | void (*init)(struct mlx5_core_dev *mdev, | |
720 | struct net_device *netdev, | |
127ea380 | 721 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
722 | void (*cleanup)(struct mlx5e_priv *priv); |
723 | int (*init_rx)(struct mlx5e_priv *priv); | |
724 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
725 | int (*init_tx)(struct mlx5e_priv *priv); | |
726 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
727 | void (*enable)(struct mlx5e_priv *priv); | |
728 | void (*disable)(struct mlx5e_priv *priv); | |
729 | void (*update_stats)(struct mlx5e_priv *priv); | |
730 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
731 | int max_tc; | |
732 | }; | |
733 | ||
f62b8bb8 AV |
734 | struct mlx5e_priv { |
735 | /* priv data path fields - start */ | |
acc6c595 SM |
736 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
737 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
86994156 | 738 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
739 | /* priv data path fields - end */ |
740 | ||
741 | unsigned long state; | |
742 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 743 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 744 | |
ff9c852f | 745 | struct mlx5e_channels channels; |
f62b8bb8 | 746 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 747 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
748 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
749 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 750 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 751 | |
acff797c | 752 | struct mlx5e_flow_steering fs; |
b3f63c3d | 753 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
754 | |
755 | struct mlx5e_params params; | |
7bb29755 | 756 | struct workqueue_struct *wq; |
f62b8bb8 AV |
757 | struct work_struct update_carrier_work; |
758 | struct work_struct set_rx_mode_work; | |
3947ca18 | 759 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
760 | struct delayed_work update_stats_work; |
761 | ||
762 | struct mlx5_core_dev *mdev; | |
763 | struct net_device *netdev; | |
764 | struct mlx5e_stats stats; | |
ef9814de | 765 | struct mlx5e_tstamp tstamp; |
593cf338 | 766 | u16 q_counter; |
3a6a931d HN |
767 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
768 | struct mlx5e_dcbx dcbx; | |
769 | #endif | |
770 | ||
6bfd390b | 771 | const struct mlx5e_profile *profile; |
127ea380 | 772 | void *ppriv; |
f62b8bb8 AV |
773 | }; |
774 | ||
665bc539 GP |
775 | void mlx5e_build_ptys2ethtool_map(void); |
776 | ||
f62b8bb8 AV |
777 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
778 | void *accel_priv, select_queue_fallback_t fallback); | |
779 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
780 | |
781 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
782 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
783 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 784 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 785 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
1c4bf940 | 786 | bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq); |
31391048 SM |
787 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
788 | void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq); | |
461017cb | 789 | |
4415a031 TT |
790 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
791 | bool recycle); | |
2f48af12 | 792 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 793 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 794 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 795 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 796 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
797 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
798 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
799 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
800 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
801 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
802 | ||
cb3c7fd4 GR |
803 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
804 | void mlx5e_rx_am_work(struct work_struct *work); | |
805 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
806 | ||
f62b8bb8 AV |
807 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
808 | ||
acff797c MG |
809 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
810 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 811 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 812 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
813 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
814 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
815 | u64 *buf); | |
f913a72a MG |
816 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
817 | int location); | |
818 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
819 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
820 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
821 | struct ethtool_rx_flow_spec *fs); | |
822 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
823 | int location); | |
824 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
825 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
826 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
827 | ||
ef9814de EBE |
828 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
829 | struct skb_shared_hwtstamps *hwts); | |
830 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
831 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
ee7f1220 EE |
832 | void mlx5e_pps_event_handler(struct mlx5e_priv *priv, |
833 | struct ptp_clock_event *event); | |
ef9814de EBE |
834 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); |
835 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
5eb0249b | 836 | void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 837 | |
f62b8bb8 AV |
838 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
839 | u16 vid); | |
840 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
841 | u16 vid); | |
842 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
843 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 844 | |
ff9c852f | 845 | int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd); |
36350114 | 846 | |
a5f97fee SM |
847 | struct mlx5e_redirect_rqt_param { |
848 | bool is_rss; | |
849 | union { | |
850 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
851 | struct { | |
852 | u8 hfunc; | |
853 | struct mlx5e_channels *channels; | |
854 | } rss; /* RSS data */ | |
855 | }; | |
856 | }; | |
857 | ||
858 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
859 | struct mlx5e_redirect_rqt_param rrp); | |
a100ff3e GP |
860 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc, |
861 | enum mlx5e_traffic_types tt); | |
2d75b2bc | 862 | |
f62b8bb8 AV |
863 | int mlx5e_open_locked(struct net_device *netdev); |
864 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
865 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
866 | u32 *indirection_rqt, int len, | |
85082dba | 867 | int num_channels); |
b797a684 | 868 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 869 | |
9908aa29 TT |
870 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
871 | u8 cq_period_mode); | |
6dc4b54e | 872 | void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type); |
9908aa29 | 873 | |
864b2d71 SM |
874 | static inline |
875 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 876 | { |
864b2d71 SM |
877 | u16 pi = *pc & wq->sz_m1; |
878 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
879 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
880 | ||
881 | memset(cseg, 0, sizeof(*cseg)); | |
882 | ||
883 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
884 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
885 | ||
886 | (*pc)++; | |
887 | ||
888 | return wqe; | |
889 | } | |
890 | ||
891 | static inline | |
892 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
893 | void __iomem *uar_map, | |
894 | struct mlx5_wqe_ctrl_seg *ctrl) | |
895 | { | |
896 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
897 | /* ensure wqe is visible to device before updating doorbell record */ |
898 | dma_wmb(); | |
899 | ||
864b2d71 | 900 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
901 | |
902 | /* ensure doorbell record is visible to device before ringing the | |
903 | * doorbell | |
904 | */ | |
905 | wmb(); | |
f62b8bb8 | 906 | |
864b2d71 | 907 | mlx5_write64((__be32 *)ctrl, uar_map, NULL); |
f62b8bb8 AV |
908 | } |
909 | ||
910 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
911 | { | |
912 | struct mlx5_core_cq *mcq; | |
913 | ||
914 | mcq = &cq->mcq; | |
5fe9dec0 | 915 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
916 | } |
917 | ||
7e426671 TT |
918 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
919 | { | |
ec8b9981 | 920 | return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
7e426671 TT |
921 | } |
922 | ||
f62b8bb8 | 923 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
924 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
925 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
926 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 927 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
08fb1dac SM |
928 | #endif |
929 | ||
1cabe6b0 MG |
930 | #ifndef CONFIG_RFS_ACCEL |
931 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
932 | { | |
933 | return 0; | |
934 | } | |
935 | ||
936 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
937 | |
938 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
939 | { | |
9eb78923 | 940 | return -EOPNOTSUPP; |
45bf454a MG |
941 | } |
942 | ||
943 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
944 | { | |
9eb78923 | 945 | return -EOPNOTSUPP; |
45bf454a | 946 | } |
1cabe6b0 MG |
947 | #else |
948 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
949 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
950 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
951 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
952 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
953 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
954 | #endif |
955 | ||
58d52291 | 956 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
957 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
958 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
959 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
960 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
961 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
962 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 963 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 964 | |
cb67b832 HHZ |
965 | struct mlx5_eswitch_rep; |
966 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
967 | struct mlx5_eswitch_rep *rep); | |
968 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
969 | struct mlx5_eswitch_rep *rep); | |
970 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
971 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
972 | struct mlx5_eswitch_rep *rep); | |
973 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
974 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
975 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
f5f82476 | 976 | void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
370bad0f | 977 | void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv); |
cb67b832 HHZ |
978 | |
979 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
980 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
981 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
982 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
983 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
984 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
985 | int mlx5e_close(struct net_device *netdev); | |
986 | int mlx5e_open(struct net_device *netdev); | |
987 | void mlx5e_update_stats_work(struct work_struct *work); | |
26e59d80 MHY |
988 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
989 | const struct mlx5e_profile *profile, | |
990 | void *ppriv); | |
cb67b832 | 991 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); |
26e59d80 MHY |
992 | int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); |
993 | void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); | |
2b029556 | 994 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); |
cb67b832 | 995 | |
370bad0f OG |
996 | int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, |
997 | void *sp); | |
998 | bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id); | |
999 | ||
1000 | bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv); | |
1001 | bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv); | |
1afff42c | 1002 | #endif /* __MLX5_EN_H__ */ |