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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 47 | #include <linux/mlx5/fs.h> |
e8f887ac | 48 | #include <linux/rhashtable.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4f75da36 | 51 | #include <linux/dim.h> |
8ff57c18 | 52 | #include <linux/bits.h> |
f62b8bb8 | 53 | #include "wq.h" |
f62b8bb8 | 54 | #include "mlx5_core.h" |
9218b44d | 55 | #include "en_stats.h" |
fe6d86b3 | 56 | #include "en/fs.h" |
cef35af3 | 57 | #include "lib/hv_vhca.h" |
f62b8bb8 | 58 | |
4d8fcf21 | 59 | extern const struct net_device_ops mlx5e_netdev_ops; |
60bbf7ee JDB |
60 | struct page_pool; |
61 | ||
bb909416 IL |
62 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
63 | #define MLX5E_METADATA_ETHER_LEN 8 | |
64 | ||
1cabe6b0 MG |
65 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
66 | ||
c139dbfd ES |
67 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
68 | ||
472a1e44 TT |
69 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
70 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 71 | |
0696d608 | 72 | #define MLX5E_MAX_PRIORITY 8 |
2a5e7a13 | 73 | #define MLX5E_MAX_DSCP 64 |
f62b8bb8 AV |
74 | #define MLX5E_MAX_NUM_TC 8 |
75 | ||
1bfecfca | 76 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
77 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
78 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 79 | |
94816278 TT |
80 | #define MLX5E_RX_MAX_HEAD (256) |
81 | ||
f32f5bd2 DJ |
82 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
83 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
84 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
85 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
94816278 TT |
86 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ |
87 | MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) | |
f32f5bd2 | 88 | |
7e426671 | 89 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
90 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
91 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
92 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
93 | |
94 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
73281b78 | 95 | #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) |
b8a98a4c | 96 | #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS)) |
73281b78 TT |
97 | #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) |
98 | #define MLX5E_MAX_RQ_NUM_MTTS \ | |
99 | ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ | |
100 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) | |
101 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ | |
102 | (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) | |
103 | #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ | |
104 | (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ | |
105 | (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) | |
106 | ||
069d1146 TT |
107 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
108 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
109 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
110 | ||
73281b78 TT |
111 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
112 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
113 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
114 | ||
069d1146 | 115 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 TT |
116 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
117 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ | |
118 | MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) | |
119 | ||
120 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 121 | |
d9a40271 | 122 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
123 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
124 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
125 | ||
f62b8bb8 | 126 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 127 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
128 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
129 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 130 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
131 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
132 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 133 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 134 | |
936896e9 AS |
135 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
136 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 137 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
57c7fce1 | 138 | #define MLX5E_MAX_NUM_CHANNELS MLX5E_INDIR_RQT_SIZE |
507f0c81 | 139 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 | 140 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
db05815b | 141 | #define MLX5E_TX_XSK_POLL_BUDGET 64 |
db75373c | 142 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 143 | |
ea3886ca TT |
144 | #define MLX5E_UMR_WQE_INLINE_SZ \ |
145 | (sizeof(struct mlx5e_umr_wqe) + \ | |
146 | ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ | |
147 | MLX5_UMR_MTT_ALIGNMENT)) | |
148 | #define MLX5E_UMR_WQEBBS \ | |
149 | (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) | |
2f48af12 | 150 | |
79c48764 GP |
151 | #define MLX5E_MSG_LEVEL NETIF_MSG_LINK |
152 | ||
153 | #define mlx5e_dbg(mlevel, priv, format, ...) \ | |
154 | do { \ | |
155 | if (NETIF_MSG_##mlevel & (priv)->msglevel) \ | |
156 | netdev_warn(priv->netdev, format, \ | |
157 | ##__VA_ARGS__); \ | |
158 | } while (0) | |
159 | ||
db05815b MM |
160 | enum mlx5e_rq_group { |
161 | MLX5E_RQ_GROUP_REGULAR, | |
162 | MLX5E_RQ_GROUP_XSK, | |
694826e3 | 163 | #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g) |
db05815b | 164 | }; |
79c48764 | 165 | |
45f171b1 MM |
166 | static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) |
167 | { | |
168 | if (mlx5_lag_is_lacp_owner(mdev)) | |
169 | return 1; | |
170 | ||
171 | return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); | |
172 | } | |
173 | ||
461017cb TT |
174 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
175 | { | |
176 | switch (wq_type) { | |
177 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
178 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
179 | wq_size / 2); | |
180 | default: | |
181 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
182 | wq_size / 2); | |
183 | } | |
184 | } | |
185 | ||
779d986d | 186 | /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ |
48935bbb SM |
187 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
188 | { | |
189 | return is_kdump_kernel() ? | |
190 | MLX5E_MIN_NUM_CHANNELS : | |
f2f3df55 | 191 | min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS); |
48935bbb SM |
192 | } |
193 | ||
2f48af12 TT |
194 | struct mlx5e_tx_wqe { |
195 | struct mlx5_wqe_ctrl_seg ctrl; | |
a9bc3390 TT |
196 | union { |
197 | struct { | |
198 | struct mlx5_wqe_eth_seg eth; | |
199 | struct mlx5_wqe_data_seg data[0]; | |
200 | }; | |
201 | u8 tls_progress_params_ctx[0]; | |
202 | }; | |
2f48af12 TT |
203 | }; |
204 | ||
99cbfa93 | 205 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 206 | struct mlx5_wqe_srq_next_seg next; |
99cbfa93 TT |
207 | struct mlx5_wqe_data_seg data[0]; |
208 | }; | |
209 | ||
210 | struct mlx5e_rx_wqe_cyc { | |
211 | struct mlx5_wqe_data_seg data[0]; | |
2f48af12 | 212 | }; |
86d722ad | 213 | |
bc77b240 TT |
214 | struct mlx5e_umr_wqe { |
215 | struct mlx5_wqe_ctrl_seg ctrl; | |
216 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
217 | struct mlx5_mkey_seg mkc; | |
d2ead1f3 TT |
218 | union { |
219 | struct mlx5_mtt inline_mtts[0]; | |
220 | u8 tls_static_params_ctx[0]; | |
221 | }; | |
bc77b240 TT |
222 | }; |
223 | ||
d605d668 KH |
224 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
225 | ||
4e59e288 | 226 | enum mlx5e_priv_flag { |
8ff57c18 TT |
227 | MLX5E_PFLAG_RX_CQE_BASED_MODER, |
228 | MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
229 | MLX5E_PFLAG_RX_CQE_COMPRESS, | |
230 | MLX5E_PFLAG_RX_STRIDING_RQ, | |
231 | MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, | |
6277053a | 232 | MLX5E_PFLAG_XDP_TX_MPWQE, |
8ff57c18 | 233 | MLX5E_NUM_PFLAGS, /* Keep last */ |
4e59e288 GP |
234 | }; |
235 | ||
6a9764ef | 236 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
237 | do { \ |
238 | if (enable) \ | |
8ff57c18 | 239 | (params)->pflags |= BIT(pflag); \ |
59ece1c9 | 240 | else \ |
8ff57c18 | 241 | (params)->pflags &= ~(BIT(pflag)); \ |
4e59e288 GP |
242 | } while (0) |
243 | ||
8ff57c18 | 244 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) |
59ece1c9 | 245 | |
08fb1dac SM |
246 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
247 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
248 | #endif |
249 | ||
f62b8bb8 AV |
250 | struct mlx5e_params { |
251 | u8 log_sq_size; | |
461017cb | 252 | u8 rq_wq_type; |
73281b78 | 253 | u8 log_rq_mtu_frames; |
f62b8bb8 | 254 | u16 num_channels; |
f62b8bb8 | 255 | u8 num_tc; |
9bcc8606 | 256 | bool rx_cqe_compress_def; |
69dad68d | 257 | bool tunneled_offload_en; |
8960b389 TG |
258 | struct dim_cq_moder rx_cq_moderation; |
259 | struct dim_cq_moder tx_cq_moderation; | |
f62b8bb8 | 260 | bool lro_en; |
cff92d7c | 261 | u8 tx_min_inline_mode; |
36350114 | 262 | bool vlan_strip_disable; |
102722fc | 263 | bool scatter_fcs_en; |
9a317425 | 264 | bool rx_dim_enabled; |
cbce4f44 | 265 | bool tx_dim_enabled; |
2b029556 | 266 | u32 lro_timeout; |
59ece1c9 | 267 | u32 pflags; |
6a9764ef | 268 | struct bpf_prog *xdp_prog; |
db05815b | 269 | struct mlx5e_xsk *xsk; |
472a1e44 TT |
270 | unsigned int sw_mtu; |
271 | int hard_mtu; | |
f62b8bb8 AV |
272 | }; |
273 | ||
3a6a931d HN |
274 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
275 | struct mlx5e_cee_config { | |
276 | /* bw pct for priority group */ | |
277 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
278 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
279 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
280 | bool pfc_enable; | |
281 | }; | |
282 | ||
283 | enum { | |
284 | MLX5_DCB_CHG_RESET, | |
285 | MLX5_DCB_NO_CHG, | |
286 | MLX5_DCB_CHG_NO_RESET, | |
287 | }; | |
288 | ||
289 | struct mlx5e_dcbx { | |
e207b7e9 | 290 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 291 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
2a5e7a13 | 292 | u8 dscp_app_cnt; |
820c2c5e HN |
293 | |
294 | /* The only setting that cannot be read from FW */ | |
295 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
9e10bf1d | 296 | u8 cap; |
0696d608 HN |
297 | |
298 | /* Buffer configuration */ | |
ecdf2dad | 299 | bool manual_buffer; |
0696d608 HN |
300 | u32 cable_len; |
301 | u32 xoff; | |
3a6a931d | 302 | }; |
2a5e7a13 HN |
303 | |
304 | struct mlx5e_dcbx_dp { | |
305 | u8 dscp2prio[MLX5E_MAX_DSCP]; | |
306 | u8 trust_state; | |
307 | }; | |
3a6a931d HN |
308 | #endif |
309 | ||
f62b8bb8 | 310 | enum { |
c0f1147d | 311 | MLX5E_RQ_STATE_ENABLED, |
8276ea13 | 312 | MLX5E_RQ_STATE_RECOVERING, |
cb3c7fd4 | 313 | MLX5E_RQ_STATE_AM, |
b856df28 | 314 | MLX5E_RQ_STATE_NO_CSUM_COMPLETE, |
db849faa | 315 | MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ |
f62b8bb8 AV |
316 | }; |
317 | ||
f62b8bb8 AV |
318 | struct mlx5e_cq { |
319 | /* data path - accessed per cqe */ | |
320 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
321 | |
322 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 323 | u16 event_ctr; |
f62b8bb8 AV |
324 | struct napi_struct *napi; |
325 | struct mlx5_core_cq mcq; | |
326 | struct mlx5e_channel *channel; | |
327 | ||
79d356ef TT |
328 | /* control */ |
329 | struct mlx5_core_dev *mdev; | |
330 | struct mlx5_wq_ctrl wq_ctrl; | |
331 | } ____cacheline_aligned_in_smp; | |
332 | ||
333 | struct mlx5e_cq_decomp { | |
7219ab34 TT |
334 | /* cqe decompression */ |
335 | struct mlx5_cqe64 title; | |
336 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
337 | u8 mini_arr_idx; | |
79d356ef TT |
338 | u16 left; |
339 | u16 wqe_counter; | |
f62b8bb8 AV |
340 | } ____cacheline_aligned_in_smp; |
341 | ||
eba2db2b | 342 | struct mlx5e_tx_wqe_info { |
77bdf895 | 343 | struct sk_buff *skb; |
eba2db2b SM |
344 | u32 num_bytes; |
345 | u8 num_wqebbs; | |
346 | u8 num_dma; | |
d2ead1f3 | 347 | #ifdef CONFIG_MLX5_EN_TLS |
f45da371 | 348 | struct page *resync_dump_frag_page; |
d2ead1f3 | 349 | #endif |
eba2db2b SM |
350 | }; |
351 | ||
352 | enum mlx5e_dma_map_type { | |
353 | MLX5E_DMA_MAP_SINGLE, | |
354 | MLX5E_DMA_MAP_PAGE | |
355 | }; | |
356 | ||
357 | struct mlx5e_sq_dma { | |
358 | dma_addr_t addr; | |
359 | u32 size; | |
360 | enum mlx5e_dma_map_type type; | |
361 | }; | |
362 | ||
363 | enum { | |
364 | MLX5E_SQ_STATE_ENABLED, | |
db75373c | 365 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 366 | MLX5E_SQ_STATE_IPSEC, |
cbce4f44 | 367 | MLX5E_SQ_STATE_AM, |
bf239741 | 368 | MLX5E_SQ_STATE_TLS, |
b431302e | 369 | MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, |
eba2db2b SM |
370 | }; |
371 | ||
372 | struct mlx5e_sq_wqe_info { | |
373 | u8 opcode; | |
ed084fb6 MM |
374 | |
375 | /* Auxiliary data for different opcodes. */ | |
376 | union { | |
377 | struct { | |
378 | struct mlx5e_rq *rq; | |
379 | } umr; | |
380 | }; | |
eba2db2b | 381 | }; |
2f48af12 | 382 | |
31391048 | 383 | struct mlx5e_txqsq { |
eba2db2b SM |
384 | /* data path */ |
385 | ||
386 | /* dirtied @completion */ | |
387 | u16 cc; | |
388 | u32 dma_fifo_cc; | |
8960b389 | 389 | struct dim dim; /* Adaptive Moderation */ |
eba2db2b SM |
390 | |
391 | /* dirtied @xmit */ | |
392 | u16 pc ____cacheline_aligned_in_smp; | |
393 | u32 dma_fifo_pc; | |
eba2db2b SM |
394 | |
395 | struct mlx5e_cq cq; | |
396 | ||
eba2db2b SM |
397 | /* read only */ |
398 | struct mlx5_wq_cyc wq; | |
399 | u32 dma_fifo_mask; | |
05909bab | 400 | struct mlx5e_sq_stats *stats; |
9a3956da TT |
401 | struct { |
402 | struct mlx5e_sq_dma *dma_fifo; | |
403 | struct mlx5e_tx_wqe_info *wqe_info; | |
404 | } db; | |
eba2db2b SM |
405 | void __iomem *uar_map; |
406 | struct netdev_queue *txq; | |
407 | u32 sqn; | |
01614d4f | 408 | u16 stop_room; |
eba2db2b | 409 | u8 min_inline_mode; |
eba2db2b | 410 | struct device *pdev; |
eba2db2b SM |
411 | __be32 mkey_be; |
412 | unsigned long state; | |
84d1bb2b | 413 | unsigned int hw_mtu; |
7c39afb3 FD |
414 | struct hwtstamp_config *tstamp; |
415 | struct mlx5_clock *clock; | |
eba2db2b SM |
416 | |
417 | /* control path */ | |
418 | struct mlx5_wq_ctrl wq_ctrl; | |
419 | struct mlx5e_channel *channel; | |
57c70d87 | 420 | int ch_ix; |
acc6c595 | 421 | int txq_ix; |
eba2db2b | 422 | u32 rate_limit; |
de8650a8 | 423 | struct work_struct recover_work; |
31391048 SM |
424 | } ____cacheline_aligned_in_smp; |
425 | ||
c94e4f11 | 426 | struct mlx5e_dma_info { |
db05815b MM |
427 | dma_addr_t addr; |
428 | union { | |
429 | struct page *page; | |
430 | struct { | |
431 | u64 handle; | |
432 | void *data; | |
433 | } xsk; | |
434 | }; | |
c94e4f11 TT |
435 | }; |
436 | ||
d963fa15 MM |
437 | /* XDP packets can be transmitted in different ways. On completion, we need to |
438 | * distinguish between them to clean up things in a proper way. | |
439 | */ | |
440 | enum mlx5e_xdp_xmit_mode { | |
441 | /* An xdp_frame was transmitted due to either XDP_REDIRECT from another | |
442 | * device or XDP_TX from an XSK RQ. The frame has to be unmapped and | |
443 | * returned. | |
444 | */ | |
445 | MLX5E_XDP_XMIT_MODE_FRAME, | |
446 | ||
447 | /* The xdp_frame was created in place as a result of XDP_TX from a | |
448 | * regular RQ. No DMA remapping happened, and the page belongs to us. | |
449 | */ | |
450 | MLX5E_XDP_XMIT_MODE_PAGE, | |
451 | ||
452 | /* No xdp_frame was created at all, the transmit happened from a UMEM | |
453 | * page. The UMEM Completion Ring producer pointer has to be increased. | |
454 | */ | |
455 | MLX5E_XDP_XMIT_MODE_XSK, | |
c94e4f11 TT |
456 | }; |
457 | ||
458 | struct mlx5e_xdp_info { | |
d963fa15 MM |
459 | enum mlx5e_xdp_xmit_mode mode; |
460 | union { | |
461 | struct { | |
462 | struct xdp_frame *xdpf; | |
463 | dma_addr_t dma_addr; | |
464 | } frame; | |
465 | struct { | |
b9673cf5 | 466 | struct mlx5e_rq *rq; |
d963fa15 MM |
467 | struct mlx5e_dma_info di; |
468 | } page; | |
469 | }; | |
470 | }; | |
471 | ||
472 | struct mlx5e_xdp_xmit_data { | |
473 | dma_addr_t dma_addr; | |
474 | void *data; | |
475 | u32 len; | |
c94e4f11 TT |
476 | }; |
477 | ||
fea28dd6 TT |
478 | struct mlx5e_xdp_info_fifo { |
479 | struct mlx5e_xdp_info *xi; | |
480 | u32 *cc; | |
481 | u32 *pc; | |
482 | u32 mask; | |
483 | }; | |
484 | ||
1feeab80 TT |
485 | struct mlx5e_xdp_wqe_info { |
486 | u8 num_wqebbs; | |
c2273219 | 487 | u8 num_pkts; |
1feeab80 TT |
488 | }; |
489 | ||
5e0d2eef TT |
490 | struct mlx5e_xdp_mpwqe { |
491 | /* Current MPWQE session */ | |
492 | struct mlx5e_tx_wqe *wqe; | |
493 | u8 ds_count; | |
c2273219 | 494 | u8 pkt_count; |
c2273219 | 495 | u8 inline_on; |
5e0d2eef TT |
496 | }; |
497 | ||
498 | struct mlx5e_xdpsq; | |
db05815b | 499 | typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); |
d963fa15 MM |
500 | typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, |
501 | struct mlx5e_xdp_xmit_data *, | |
db05815b MM |
502 | struct mlx5e_xdp_info *, |
503 | int); | |
d963fa15 | 504 | |
31391048 SM |
505 | struct mlx5e_xdpsq { |
506 | /* data path */ | |
507 | ||
dac0d15f | 508 | /* dirtied @completion */ |
fea28dd6 | 509 | u32 xdpi_fifo_cc; |
31391048 | 510 | u16 cc; |
31391048 | 511 | |
dac0d15f | 512 | /* dirtied @xmit */ |
fea28dd6 TT |
513 | u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; |
514 | u16 pc; | |
b8180392 | 515 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
5e0d2eef | 516 | struct mlx5e_xdp_mpwqe mpwqe; |
31391048 | 517 | |
dac0d15f | 518 | struct mlx5e_cq cq; |
31391048 SM |
519 | |
520 | /* read only */ | |
db05815b | 521 | struct xdp_umem *umem; |
31391048 | 522 | struct mlx5_wq_cyc wq; |
890388ad | 523 | struct mlx5e_xdpsq_stats *stats; |
db05815b | 524 | mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; |
5e0d2eef | 525 | mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; |
dac0d15f | 526 | struct { |
1feeab80 | 527 | struct mlx5e_xdp_wqe_info *wqe_info; |
fea28dd6 | 528 | struct mlx5e_xdp_info_fifo xdpi_fifo; |
dac0d15f | 529 | } db; |
31391048 SM |
530 | void __iomem *uar_map; |
531 | u32 sqn; | |
532 | struct device *pdev; | |
533 | __be32 mkey_be; | |
534 | u8 min_inline_mode; | |
535 | unsigned long state; | |
c94e4f11 | 536 | unsigned int hw_mtu; |
31391048 SM |
537 | |
538 | /* control path */ | |
539 | struct mlx5_wq_ctrl wq_ctrl; | |
540 | struct mlx5e_channel *channel; | |
541 | } ____cacheline_aligned_in_smp; | |
542 | ||
543 | struct mlx5e_icosq { | |
544 | /* data path */ | |
fd9b4be8 TT |
545 | u16 cc; |
546 | u16 pc; | |
31391048 | 547 | |
fd9b4be8 | 548 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
31391048 SM |
549 | struct mlx5e_cq cq; |
550 | ||
551 | /* write@xmit, read@completion */ | |
552 | struct { | |
553 | struct mlx5e_sq_wqe_info *ico_wqe; | |
554 | } db; | |
555 | ||
556 | /* read only */ | |
557 | struct mlx5_wq_cyc wq; | |
558 | void __iomem *uar_map; | |
559 | u32 sqn; | |
31391048 SM |
560 | unsigned long state; |
561 | ||
562 | /* control path */ | |
563 | struct mlx5_wq_ctrl wq_ctrl; | |
564 | struct mlx5e_channel *channel; | |
be5323c8 AL |
565 | |
566 | struct work_struct recover_work; | |
eba2db2b SM |
567 | } ____cacheline_aligned_in_smp; |
568 | ||
accd5883 | 569 | struct mlx5e_wqe_frag_info { |
069d1146 | 570 | struct mlx5e_dma_info *di; |
accd5883 | 571 | u32 offset; |
069d1146 | 572 | bool last_in_page; |
accd5883 TT |
573 | }; |
574 | ||
eba2db2b | 575 | struct mlx5e_umr_dma_info { |
eba2db2b | 576 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
eba2db2b SM |
577 | }; |
578 | ||
579 | struct mlx5e_mpw_info { | |
580 | struct mlx5e_umr_dma_info umr; | |
581 | u16 consumed_strides; | |
22f45398 | 582 | DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
eba2db2b SM |
583 | }; |
584 | ||
069d1146 TT |
585 | #define MLX5E_MAX_RX_FRAGS 4 |
586 | ||
4415a031 TT |
587 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
588 | * or a MPWQE (for striding rq). | |
589 | */ | |
590 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
591 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
29c2849e | 592 | #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) |
4415a031 TT |
593 | struct mlx5e_page_cache { |
594 | u32 head; | |
595 | u32 tail; | |
596 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
597 | }; | |
598 | ||
eba2db2b SM |
599 | struct mlx5e_rq; |
600 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
601 | typedef struct sk_buff * |
602 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
603 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
604 | typedef struct sk_buff * |
605 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
606 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
7cc6d77b | 607 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b SM |
608 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
609 | ||
121e8927 | 610 | enum mlx5e_rq_flag { |
f03590f7 | 611 | MLX5E_RQ_FLAG_XDP_XMIT, |
15143bf5 | 612 | MLX5E_RQ_FLAG_XDP_REDIRECT, |
121e8927 TT |
613 | }; |
614 | ||
069d1146 TT |
615 | struct mlx5e_rq_frag_info { |
616 | int frag_size; | |
617 | int frag_stride; | |
618 | }; | |
619 | ||
620 | struct mlx5e_rq_frags_info { | |
621 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
622 | u8 num_frags; | |
623 | u8 log_num_frags; | |
624 | u8 wqe_bulk; | |
625 | }; | |
626 | ||
f62b8bb8 AV |
627 | struct mlx5e_rq { |
628 | /* data path */ | |
21c59685 | 629 | union { |
accd5883 | 630 | struct { |
069d1146 TT |
631 | struct mlx5_wq_cyc wq; |
632 | struct mlx5e_wqe_frag_info *frags; | |
633 | struct mlx5e_dma_info *di; | |
634 | struct mlx5e_rq_frags_info info; | |
635 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 636 | } wqe; |
21c59685 | 637 | struct { |
422d4c40 | 638 | struct mlx5_wq_ll wq; |
b8a98a4c | 639 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 640 | struct mlx5e_mpw_info *info; |
619a8f2a | 641 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
b45d8b50 | 642 | u16 num_strides; |
fd9b4be8 | 643 | u16 actual_wq_head; |
89e89f7a | 644 | u8 log_stride_sz; |
fd9b4be8 TT |
645 | u8 umr_in_progress; |
646 | u8 umr_last_bulk; | |
ed084fb6 | 647 | u8 umr_completed; |
21c59685 SM |
648 | } mpwqe; |
649 | }; | |
1bfecfca | 650 | struct { |
db05815b | 651 | u16 umem_headroom; |
b45d8b50 | 652 | u16 headroom; |
b5503b99 | 653 | u8 map_dir; /* dma map direction */ |
1bfecfca | 654 | } buff; |
f62b8bb8 | 655 | |
7cc6d77b | 656 | struct mlx5e_channel *channel; |
f62b8bb8 AV |
657 | struct device *pdev; |
658 | struct net_device *netdev; | |
05909bab | 659 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 660 | struct mlx5e_cq cq; |
79d356ef | 661 | struct mlx5e_cq_decomp cqd; |
4415a031 | 662 | struct mlx5e_page_cache page_cache; |
7c39afb3 FD |
663 | struct hwtstamp_config *tstamp; |
664 | struct mlx5_clock *clock; | |
4415a031 | 665 | |
2f48af12 | 666 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 667 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 668 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
669 | |
670 | unsigned long state; | |
671 | int ix; | |
0073c8f7 | 672 | unsigned int hw_mtu; |
f62b8bb8 | 673 | |
8960b389 | 674 | struct dim dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
675 | |
676 | /* XDP */ | |
86994156 | 677 | struct bpf_prog *xdp_prog; |
b9673cf5 | 678 | struct mlx5e_xdpsq *xdpsq; |
121e8927 | 679 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 680 | struct page_pool *page_pool; |
cb3c7fd4 | 681 | |
db05815b MM |
682 | /* AF_XDP zero-copy */ |
683 | struct zero_copy_allocator zca; | |
684 | struct xdp_umem *umem; | |
685 | ||
8276ea13 AL |
686 | struct work_struct recover_work; |
687 | ||
f62b8bb8 AV |
688 | /* control */ |
689 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 690 | __be32 mkey_be; |
461017cb | 691 | u8 wq_type; |
f62b8bb8 | 692 | u32 rqn; |
a43b25da | 693 | struct mlx5_core_dev *mdev; |
ec8b9981 | 694 | struct mlx5_core_mkey umr_mkey; |
0ddf5432 JDB |
695 | |
696 | /* XDP read-mostly */ | |
697 | struct xdp_rxq_info xdp_rxq; | |
f62b8bb8 AV |
698 | } ____cacheline_aligned_in_smp; |
699 | ||
db05815b MM |
700 | enum mlx5e_channel_state { |
701 | MLX5E_CHANNEL_STATE_XSK, | |
702 | MLX5E_CHANNEL_NUM_STATES | |
703 | }; | |
704 | ||
f62b8bb8 AV |
705 | struct mlx5e_channel { |
706 | /* data path */ | |
707 | struct mlx5e_rq rq; | |
b9673cf5 | 708 | struct mlx5e_xdpsq rq_xdpsq; |
31391048 SM |
709 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
710 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 711 | bool xdp; |
f62b8bb8 AV |
712 | struct napi_struct napi; |
713 | struct device *pdev; | |
714 | struct net_device *netdev; | |
715 | __be32 mkey_be; | |
716 | u8 num_tc; | |
45f171b1 | 717 | u8 lag_port; |
f62b8bb8 | 718 | |
58b99ee3 TT |
719 | /* XDP_REDIRECT */ |
720 | struct mlx5e_xdpsq xdpsq; | |
721 | ||
db05815b MM |
722 | /* AF_XDP zero-copy */ |
723 | struct mlx5e_rq xskrq; | |
724 | struct mlx5e_xdpsq xsksq; | |
725 | struct mlx5e_icosq xskicosq; | |
726 | /* xskicosq can be accessed from any CPU - the spinlock protects it. */ | |
727 | spinlock_t xskicosq_lock; | |
728 | ||
a8c2eb15 TT |
729 | /* data path - accessed per napi poll */ |
730 | struct irq_desc *irq_desc; | |
05909bab | 731 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
732 | |
733 | /* control */ | |
734 | struct mlx5e_priv *priv; | |
a43b25da | 735 | struct mlx5_core_dev *mdev; |
7c39afb3 | 736 | struct hwtstamp_config *tstamp; |
db05815b | 737 | DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); |
f62b8bb8 | 738 | int ix; |
231243c8 | 739 | int cpu; |
f62b8bb8 AV |
740 | }; |
741 | ||
ff9c852f SM |
742 | struct mlx5e_channels { |
743 | struct mlx5e_channel **c; | |
744 | unsigned int num; | |
6a9764ef | 745 | struct mlx5e_params params; |
ff9c852f SM |
746 | }; |
747 | ||
05909bab EBE |
748 | struct mlx5e_channel_stats { |
749 | struct mlx5e_ch_stats ch; | |
750 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
751 | struct mlx5e_rq_stats rq; | |
db05815b | 752 | struct mlx5e_rq_stats xskrq; |
890388ad | 753 | struct mlx5e_xdpsq_stats rq_xdpsq; |
58b99ee3 | 754 | struct mlx5e_xdpsq_stats xdpsq; |
db05815b | 755 | struct mlx5e_xdpsq_stats xsksq; |
05909bab EBE |
756 | } ____cacheline_aligned_in_smp; |
757 | ||
acff797c | 758 | enum { |
acff797c MG |
759 | MLX5E_STATE_OPENED, |
760 | MLX5E_STATE_DESTROYING, | |
407e17b1 | 761 | MLX5E_STATE_XDP_TX_ENABLED, |
9cf88808 | 762 | MLX5E_STATE_XDP_ACTIVE, |
acff797c MG |
763 | }; |
764 | ||
398f3351 | 765 | struct mlx5e_rqt { |
1da36696 | 766 | u32 rqtn; |
398f3351 HHZ |
767 | bool enabled; |
768 | }; | |
769 | ||
770 | struct mlx5e_tir { | |
771 | u32 tirn; | |
772 | struct mlx5e_rqt rqt; | |
773 | struct list_head list; | |
1da36696 TT |
774 | }; |
775 | ||
acff797c MG |
776 | enum { |
777 | MLX5E_TC_PRIO = 0, | |
778 | MLX5E_NIC_PRIO | |
779 | }; | |
780 | ||
bbeb53b8 AL |
781 | struct mlx5e_rss_params { |
782 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
756c4160 | 783 | u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS]; |
bbeb53b8 AL |
784 | u8 toeplitz_hash_key[40]; |
785 | u8 hfunc; | |
786 | }; | |
787 | ||
de8650a8 EBE |
788 | struct mlx5e_modify_sq_param { |
789 | int curr_state; | |
790 | int next_state; | |
791 | int rl_update; | |
792 | int rl_index; | |
793 | }; | |
794 | ||
cef35af3 EBE |
795 | #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) |
796 | struct mlx5e_hv_vhca_stats_agent { | |
797 | struct mlx5_hv_vhca_agent *agent; | |
798 | struct delayed_work work; | |
799 | u16 delay; | |
800 | void *buf; | |
801 | }; | |
802 | #endif | |
803 | ||
db05815b MM |
804 | struct mlx5e_xsk { |
805 | /* UMEMs are stored separately from channels, because we don't want to | |
806 | * lose them when channels are recreated. The kernel also stores UMEMs, | |
807 | * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs, | |
808 | * so rely on our mechanism. | |
809 | */ | |
810 | struct xdp_umem **umems; | |
811 | u16 refcnt; | |
812 | bool ever_used; | |
813 | }; | |
814 | ||
3909a12e MM |
815 | /* Temporary storage for variables that are allocated when struct mlx5e_priv is |
816 | * initialized, and used where we can't allocate them because that functions | |
817 | * must not fail. Use with care and make sure the same variable is not used | |
818 | * simultaneously by multiple users. | |
819 | */ | |
820 | struct mlx5e_scratchpad { | |
821 | cpumask_var_t cpumask; | |
822 | }; | |
823 | ||
f62b8bb8 AV |
824 | struct mlx5e_priv { |
825 | /* priv data path fields - start */ | |
acc6c595 | 826 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
c55d8b10 | 827 | int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
2a5e7a13 HN |
828 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
829 | struct mlx5e_dcbx_dp dcbx_dp; | |
830 | #endif | |
f62b8bb8 AV |
831 | /* priv data path fields - end */ |
832 | ||
79c48764 | 833 | u32 msglevel; |
f62b8bb8 AV |
834 | unsigned long state; |
835 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 836 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 837 | |
ff9c852f | 838 | struct mlx5e_channels channels; |
45f171b1 | 839 | u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC]; |
398f3351 | 840 | struct mlx5e_rqt indir_rqt; |
724b2aa1 | 841 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
7b3722fa | 842 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; |
724b2aa1 | 843 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; |
db05815b | 844 | struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS]; |
bbeb53b8 | 845 | struct mlx5e_rss_params rss_params; |
507f0c81 | 846 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 847 | |
acff797c | 848 | struct mlx5e_flow_steering fs; |
f62b8bb8 | 849 | |
7bb29755 | 850 | struct workqueue_struct *wq; |
f62b8bb8 AV |
851 | struct work_struct update_carrier_work; |
852 | struct work_struct set_rx_mode_work; | |
3947ca18 | 853 | struct work_struct tx_timeout_work; |
cdeef2b1 | 854 | struct work_struct update_stats_work; |
5c7e8bbb ED |
855 | struct work_struct monitor_counters_work; |
856 | struct mlx5_nb monitor_counters_nb; | |
f62b8bb8 AV |
857 | |
858 | struct mlx5_core_dev *mdev; | |
859 | struct net_device *netdev; | |
860 | struct mlx5e_stats stats; | |
05909bab | 861 | struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS]; |
694826e3 | 862 | u16 max_nch; |
05909bab | 863 | u8 max_opened_tc; |
7c39afb3 | 864 | struct hwtstamp_config tstamp; |
7cbaf9a3 MS |
865 | u16 q_counter; |
866 | u16 drop_rq_q_counter; | |
7cffaddd SM |
867 | struct notifier_block events_nb; |
868 | ||
3a6a931d HN |
869 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
870 | struct mlx5e_dcbx dcbx; | |
871 | #endif | |
872 | ||
6bfd390b | 873 | const struct mlx5e_profile *profile; |
127ea380 | 874 | void *ppriv; |
547eede0 IT |
875 | #ifdef CONFIG_MLX5_EN_IPSEC |
876 | struct mlx5e_ipsec *ipsec; | |
877 | #endif | |
43585a41 IL |
878 | #ifdef CONFIG_MLX5_EN_TLS |
879 | struct mlx5e_tls *tls; | |
880 | #endif | |
de8650a8 | 881 | struct devlink_health_reporter *tx_reporter; |
9032e719 | 882 | struct devlink_health_reporter *rx_reporter; |
c6acd629 | 883 | struct devlink_port dl_phy_port; |
db05815b | 884 | struct mlx5e_xsk xsk; |
cef35af3 EBE |
885 | #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) |
886 | struct mlx5e_hv_vhca_stats_agent stats_agent; | |
887 | #endif | |
3909a12e | 888 | struct mlx5e_scratchpad scratchpad; |
f62b8bb8 AV |
889 | }; |
890 | ||
a43b25da | 891 | struct mlx5e_profile { |
182570b2 | 892 | int (*init)(struct mlx5_core_dev *mdev, |
a43b25da SM |
893 | struct net_device *netdev, |
894 | const struct mlx5e_profile *profile, void *ppriv); | |
895 | void (*cleanup)(struct mlx5e_priv *priv); | |
896 | int (*init_rx)(struct mlx5e_priv *priv); | |
897 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
898 | int (*init_tx)(struct mlx5e_priv *priv); | |
899 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
900 | void (*enable)(struct mlx5e_priv *priv); | |
901 | void (*disable)(struct mlx5e_priv *priv); | |
a90f88fe | 902 | int (*update_rx)(struct mlx5e_priv *priv); |
a43b25da | 903 | void (*update_stats)(struct mlx5e_priv *priv); |
7ca42c80 | 904 | void (*update_carrier)(struct mlx5e_priv *priv); |
3460c184 | 905 | unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); |
f0ff8e8c | 906 | mlx5e_stats_grp_t *stats_grps; |
20fd0c19 SM |
907 | struct { |
908 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
909 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
910 | } rx_handlers; | |
a43b25da | 911 | int max_tc; |
694826e3 | 912 | u8 rq_groups; |
a43b25da SM |
913 | }; |
914 | ||
665bc539 GP |
915 | void mlx5e_build_ptys2ethtool_map(void); |
916 | ||
f62b8bb8 | 917 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
a350ecce | 918 | struct net_device *sb_dev); |
f62b8bb8 | 919 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); |
bf239741 | 920 | netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
3c31ff22 | 921 | struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more); |
f62b8bb8 | 922 | |
63d26b49 | 923 | void mlx5e_trigger_irq(struct mlx5e_icosq *sq); |
4e0e2ea1 | 924 | void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe); |
f62b8bb8 AV |
925 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); |
926 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 927 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 928 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
31391048 | 929 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
461017cb | 930 | |
9032e719 AL |
931 | static inline u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq) |
932 | { | |
933 | switch (rq->wq_type) { | |
934 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
935 | return mlx5_wq_ll_get_size(&rq->mpwqe.wq); | |
936 | default: | |
937 | return mlx5_wq_cyc_get_size(&rq->wqe.wq); | |
938 | } | |
939 | } | |
940 | ||
941 | static inline u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq) | |
942 | { | |
943 | switch (rq->wq_type) { | |
944 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
945 | return rq->mpwqe.wq.cur_sz; | |
946 | default: | |
947 | return rq->wqe.wq.cur_sz; | |
948 | } | |
949 | } | |
950 | ||
2ccb0a79 TT |
951 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); |
952 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, | |
953 | struct mlx5e_params *params); | |
954 | ||
159d2131 | 955 | void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info); |
db05815b MM |
956 | void mlx5e_page_release_dynamic(struct mlx5e_rq *rq, |
957 | struct mlx5e_dma_info *dma_info, | |
958 | bool recycle); | |
2f48af12 | 959 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 960 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 961 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
ed084fb6 | 962 | void mlx5e_poll_ico_cq(struct mlx5e_cq *cq); |
7cc6d77b | 963 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); |
6cd392a0 DJ |
964 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
965 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
619a8f2a TT |
966 | struct sk_buff * |
967 | mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
968 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
969 | struct sk_buff * | |
970 | mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
971 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
972 | struct sk_buff * |
973 | mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
974 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
975 | struct sk_buff * | |
976 | mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
977 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
f62b8bb8 | 978 | |
d9ee0491 | 979 | void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); |
b832d4fd | 980 | void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); |
f62b8bb8 | 981 | |
33cfaaa8 | 982 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
d605d668 KH |
983 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
984 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
985 | u64 *buf); | |
f62b8bb8 AV |
986 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
987 | ||
1170fbd8 FD |
988 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
989 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 990 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 991 | |
f62b8bb8 AV |
992 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
993 | u16 vid); | |
994 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
995 | u16 vid); | |
237f258c | 996 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 997 | |
a5f97fee SM |
998 | struct mlx5e_redirect_rqt_param { |
999 | bool is_rss; | |
1000 | union { | |
1001 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
1002 | struct { | |
1003 | u8 hfunc; | |
1004 | struct mlx5e_channels *channels; | |
1005 | } rss; /* RSS data */ | |
1006 | }; | |
1007 | }; | |
1008 | ||
1009 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
1010 | struct mlx5e_redirect_rqt_param rrp); | |
bbeb53b8 | 1011 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params, |
d930ac79 | 1012 | const struct mlx5e_tirc_config *ttconfig, |
7b3722fa | 1013 | void *tirc, bool inner); |
080d1b17 | 1014 | void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen); |
d930ac79 | 1015 | struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt); |
2d75b2bc | 1016 | |
db05815b MM |
1017 | struct mlx5e_xsk_param; |
1018 | ||
1019 | struct mlx5e_rq_param; | |
1020 | int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params, | |
1021 | struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk, | |
1022 | struct xdp_umem *umem, struct mlx5e_rq *rq); | |
1023 | int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); | |
1024 | void mlx5e_deactivate_rq(struct mlx5e_rq *rq); | |
1025 | void mlx5e_close_rq(struct mlx5e_rq *rq); | |
1026 | ||
1027 | struct mlx5e_sq_param; | |
1028 | int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, | |
1029 | struct mlx5e_sq_param *param, struct mlx5e_icosq *sq); | |
1030 | void mlx5e_close_icosq(struct mlx5e_icosq *sq); | |
1031 | int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, | |
1032 | struct mlx5e_sq_param *param, struct xdp_umem *umem, | |
1033 | struct mlx5e_xdpsq *sq, bool is_redirect); | |
1034 | void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); | |
1035 | ||
1036 | struct mlx5e_cq_param; | |
c4cde580 | 1037 | int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder, |
db05815b MM |
1038 | struct mlx5e_cq_param *param, struct mlx5e_cq *cq); |
1039 | void mlx5e_close_cq(struct mlx5e_cq *cq); | |
1040 | ||
f62b8bb8 AV |
1041 | int mlx5e_open_locked(struct net_device *netdev); |
1042 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
1043 | |
1044 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
1045 | struct mlx5e_channels *chs); | |
1046 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 | 1047 | |
dca147b3 | 1048 | /* Function pointer to be used to modify HW or kernel settings while |
2e20a151 SM |
1049 | * switching channels |
1050 | */ | |
b9ab5d0e MM |
1051 | typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); |
1052 | #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ | |
1053 | int fn##_ctx(struct mlx5e_priv *priv, void *context) \ | |
1054 | { \ | |
1055 | return fn(priv); \ | |
1056 | } | |
484c1ada | 1057 | int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); |
877662e2 TT |
1058 | int mlx5e_safe_switch_channels(struct mlx5e_priv *priv, |
1059 | struct mlx5e_channels *new_chs, | |
b9ab5d0e MM |
1060 | mlx5e_fp_preactivate preactivate, |
1061 | void *context); | |
fe867cac | 1062 | int mlx5e_num_channels_changed(struct mlx5e_priv *priv); |
b9ab5d0e | 1063 | int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); |
603f4a45 SM |
1064 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
1065 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 1066 | |
d4b6c488 | 1067 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba | 1068 | int num_channels); |
0088cbbc TG |
1069 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, |
1070 | u8 cq_period_mode); | |
9908aa29 TT |
1071 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
1072 | u8 cq_period_mode); | |
2ccb0a79 | 1073 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params); |
696a97cf | 1074 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 1075 | struct mlx5e_params *params); |
be5323c8 AL |
1076 | int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state); |
1077 | void mlx5e_activate_rq(struct mlx5e_rq *rq); | |
1078 | void mlx5e_deactivate_rq(struct mlx5e_rq *rq); | |
1079 | void mlx5e_free_rx_descs(struct mlx5e_rq *rq); | |
1080 | void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); | |
1081 | void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); | |
9908aa29 | 1082 | |
de8650a8 EBE |
1083 | int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
1084 | struct mlx5e_modify_sq_param *p); | |
1085 | void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); | |
1086 | void mlx5e_tx_disable_queue(struct netdev_queue *txq); | |
1087 | ||
e3cfc7e6 MS |
1088 | static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) |
1089 | { | |
1090 | return MLX5_CAP_ETH(mdev, swp) && | |
1091 | MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); | |
1092 | } | |
1093 | ||
f62b8bb8 | 1094 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
1095 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
1096 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
1097 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 1098 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
2a5e7a13 HN |
1099 | void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv); |
1100 | void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv); | |
08fb1dac SM |
1101 | #endif |
1102 | ||
724b2aa1 HHZ |
1103 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
1104 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
1105 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
1106 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
1107 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1108 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 1109 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 1110 | |
bc81b9d3 | 1111 | /* common netdev helpers */ |
1462e48d RD |
1112 | void mlx5e_create_q_counters(struct mlx5e_priv *priv); |
1113 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); | |
1114 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, | |
1115 | struct mlx5e_rq *drop_rq); | |
1116 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); | |
1117 | ||
8f493ffd SM |
1118 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1119 | ||
46dc933c OG |
1120 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); |
1121 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); | |
8f493ffd | 1122 | |
db05815b MM |
1123 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs); |
1124 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs); | |
1125 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs); | |
1126 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs); | |
8f493ffd SM |
1127 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
1128 | ||
2b257a6e | 1129 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); |
5426a0b2 SM |
1130 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); |
1131 | ||
cb67b832 | 1132 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
3c145626 | 1133 | void mlx5e_destroy_tises(struct mlx5e_priv *priv); |
a90f88fe | 1134 | int mlx5e_update_nic_rx(struct mlx5e_priv *priv); |
b36cdb42 | 1135 | void mlx5e_update_carrier(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1136 | int mlx5e_close(struct net_device *netdev); |
1137 | int mlx5e_open(struct net_device *netdev); | |
5c7e8bbb | 1138 | void mlx5e_update_ndo_stats(struct mlx5e_priv *priv); |
cb67b832 | 1139 | |
cdeef2b1 | 1140 | void mlx5e_queue_update_stats(struct mlx5e_priv *priv); |
3f6d08d1 OG |
1141 | int mlx5e_bits_invert(unsigned long a, int size); |
1142 | ||
d9ee0491 | 1143 | int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); |
b9ab5d0e | 1144 | int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); |
250a42b6 | 1145 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
b9ab5d0e | 1146 | mlx5e_fp_preactivate preactivate); |
250a42b6 | 1147 | |
076b0936 ES |
1148 | /* ethtool helpers */ |
1149 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1150 | struct ethtool_drvinfo *drvinfo); | |
1151 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1152 | uint32_t stringset, uint8_t *data); | |
1153 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1154 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1155 | struct ethtool_stats *stats, u64 *data); | |
1156 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1157 | struct ethtool_ringparam *param); | |
1158 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1159 | struct ethtool_ringparam *param); | |
1160 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1161 | struct ethtool_channels *ch); | |
1162 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1163 | struct ethtool_channels *ch); | |
1164 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1165 | struct ethtool_coalesce *coal); | |
1166 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1167 | struct ethtool_coalesce *coal); | |
371289b6 OG |
1168 | int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, |
1169 | struct ethtool_link_ksettings *link_ksettings); | |
1170 | int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, | |
1171 | const struct ethtool_link_ksettings *link_ksettings); | |
a5355de8 OG |
1172 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); |
1173 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); | |
3844b07e FD |
1174 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1175 | struct ethtool_ts_info *info); | |
f43d48d1 EBE |
1176 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1177 | struct ethtool_flash *flash); | |
371289b6 OG |
1178 | void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, |
1179 | struct ethtool_pauseparam *pauseparam); | |
1180 | int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, | |
1181 | struct ethtool_pauseparam *pauseparam); | |
076b0936 | 1182 | |
2c3b5bee | 1183 | /* mlx5e generic netdev management API */ |
519a0bf5 SM |
1184 | int mlx5e_netdev_init(struct net_device *netdev, |
1185 | struct mlx5e_priv *priv, | |
1186 | struct mlx5_core_dev *mdev, | |
1187 | const struct mlx5e_profile *profile, | |
1188 | void *ppriv); | |
182570b2 | 1189 | void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv); |
2c3b5bee SM |
1190 | struct net_device* |
1191 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
779d986d | 1192 | int nch, void *ppriv); |
2c3b5bee SM |
1193 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); |
1194 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1195 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
6d7ee2ed | 1196 | void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); |
57c7fce1 | 1197 | void mlx5e_build_nic_params(struct mlx5e_priv *priv, |
db05815b | 1198 | struct mlx5e_xsk *xsk, |
bbeb53b8 | 1199 | struct mlx5e_rss_params *rss_params, |
8f493ffd | 1200 | struct mlx5e_params *params, |
57c7fce1 | 1201 | u16 mtu); |
749359f4 GT |
1202 | void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, |
1203 | struct mlx5e_params *params); | |
bbeb53b8 AL |
1204 | void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params, |
1205 | u16 num_channels); | |
9a317425 | 1206 | void mlx5e_rx_dim_work(struct work_struct *work); |
cbce4f44 | 1207 | void mlx5e_tx_dim_work(struct work_struct *work); |
073caf50 OG |
1208 | |
1209 | void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti); | |
1210 | void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti); | |
1211 | netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
1212 | struct net_device *netdev, | |
1213 | netdev_features_t features); | |
d3cbd425 | 1214 | int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); |
073caf50 OG |
1215 | #ifdef CONFIG_MLX5_ESWITCH |
1216 | int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); | |
1217 | int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); | |
1218 | int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); | |
1219 | int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); | |
1220 | #endif | |
1afff42c | 1221 | #endif /* __MLX5_EN_H__ */ |