]>
Commit | Line | Data |
---|---|---|
f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/if_vlan.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/mlx5/driver.h> | |
36 | #include <linux/mlx5/qp.h> | |
37 | #include <linux/mlx5/cq.h> | |
d18a9470 | 38 | #include <linux/mlx5/vport.h> |
f62b8bb8 AV |
39 | #include "wq.h" |
40 | #include "transobj.h" | |
41 | #include "mlx5_core.h" | |
42 | ||
43 | #define MLX5E_MAX_NUM_TC 8 | |
44 | ||
e842b100 | 45 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
46 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
47 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
48 | ||
e842b100 | 49 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
50 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
51 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
52 | ||
d9a40271 | 53 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 AV |
54 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
55 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
56 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
57 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
58 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
f62b8bb8 | 59 | |
936896e9 AS |
60 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
61 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
62 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
f62b8bb8 AV |
63 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
64 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 65 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 66 | |
86d722ad MG |
67 | #define MLX5E_NUM_MAIN_GROUPS 9 |
68 | ||
f62b8bb8 AV |
69 | static const char vport_strings[][ETH_GSTRING_LEN] = { |
70 | /* vport statistics */ | |
71 | "rx_packets", | |
72 | "rx_bytes", | |
73 | "tx_packets", | |
74 | "tx_bytes", | |
75 | "rx_error_packets", | |
76 | "rx_error_bytes", | |
77 | "tx_error_packets", | |
78 | "tx_error_bytes", | |
79 | "rx_unicast_packets", | |
80 | "rx_unicast_bytes", | |
81 | "tx_unicast_packets", | |
82 | "tx_unicast_bytes", | |
83 | "rx_multicast_packets", | |
84 | "rx_multicast_bytes", | |
85 | "tx_multicast_packets", | |
86 | "tx_multicast_bytes", | |
87 | "rx_broadcast_packets", | |
88 | "rx_broadcast_bytes", | |
89 | "tx_broadcast_packets", | |
90 | "tx_broadcast_bytes", | |
91 | ||
92 | /* SW counters */ | |
93 | "tso_packets", | |
94 | "tso_bytes", | |
95 | "lro_packets", | |
96 | "lro_bytes", | |
97 | "rx_csum_good", | |
98 | "rx_csum_none", | |
bbceefce | 99 | "rx_csum_sw", |
f62b8bb8 AV |
100 | "tx_csum_offload", |
101 | "tx_queue_stopped", | |
102 | "tx_queue_wake", | |
103 | "tx_queue_dropped", | |
104 | "rx_wqe_err", | |
105 | }; | |
106 | ||
107 | struct mlx5e_vport_stats { | |
108 | /* HW counters */ | |
109 | u64 rx_packets; | |
110 | u64 rx_bytes; | |
111 | u64 tx_packets; | |
112 | u64 tx_bytes; | |
113 | u64 rx_error_packets; | |
114 | u64 rx_error_bytes; | |
115 | u64 tx_error_packets; | |
116 | u64 tx_error_bytes; | |
117 | u64 rx_unicast_packets; | |
118 | u64 rx_unicast_bytes; | |
119 | u64 tx_unicast_packets; | |
120 | u64 tx_unicast_bytes; | |
121 | u64 rx_multicast_packets; | |
122 | u64 rx_multicast_bytes; | |
123 | u64 tx_multicast_packets; | |
124 | u64 tx_multicast_bytes; | |
125 | u64 rx_broadcast_packets; | |
126 | u64 rx_broadcast_bytes; | |
127 | u64 tx_broadcast_packets; | |
128 | u64 tx_broadcast_bytes; | |
129 | ||
130 | /* SW counters */ | |
131 | u64 tso_packets; | |
132 | u64 tso_bytes; | |
133 | u64 lro_packets; | |
134 | u64 lro_bytes; | |
135 | u64 rx_csum_good; | |
136 | u64 rx_csum_none; | |
bbceefce | 137 | u64 rx_csum_sw; |
f62b8bb8 AV |
138 | u64 tx_csum_offload; |
139 | u64 tx_queue_stopped; | |
140 | u64 tx_queue_wake; | |
141 | u64 tx_queue_dropped; | |
142 | u64 rx_wqe_err; | |
143 | ||
bbceefce | 144 | #define NUM_VPORT_COUNTERS 32 |
f62b8bb8 AV |
145 | }; |
146 | ||
efea389d GP |
147 | static const char pport_strings[][ETH_GSTRING_LEN] = { |
148 | /* IEEE802.3 counters */ | |
149 | "frames_tx", | |
150 | "frames_rx", | |
151 | "check_seq_err", | |
152 | "alignment_err", | |
153 | "octets_tx", | |
154 | "octets_received", | |
155 | "multicast_xmitted", | |
156 | "broadcast_xmitted", | |
157 | "multicast_rx", | |
158 | "broadcast_rx", | |
159 | "in_range_len_errors", | |
160 | "out_of_range_len", | |
161 | "too_long_errors", | |
162 | "symbol_err", | |
163 | "mac_control_tx", | |
164 | "mac_control_rx", | |
165 | "unsupported_op_rx", | |
166 | "pause_ctrl_rx", | |
167 | "pause_ctrl_tx", | |
168 | ||
169 | /* RFC2863 counters */ | |
170 | "in_octets", | |
171 | "in_ucast_pkts", | |
172 | "in_discards", | |
173 | "in_errors", | |
174 | "in_unknown_protos", | |
175 | "out_octets", | |
176 | "out_ucast_pkts", | |
177 | "out_discards", | |
178 | "out_errors", | |
179 | "in_multicast_pkts", | |
180 | "in_broadcast_pkts", | |
181 | "out_multicast_pkts", | |
182 | "out_broadcast_pkts", | |
183 | ||
184 | /* RFC2819 counters */ | |
185 | "drop_events", | |
186 | "octets", | |
187 | "pkts", | |
188 | "broadcast_pkts", | |
189 | "multicast_pkts", | |
190 | "crc_align_errors", | |
191 | "undersize_pkts", | |
192 | "oversize_pkts", | |
193 | "fragments", | |
194 | "jabbers", | |
195 | "collisions", | |
196 | "p64octets", | |
197 | "p65to127octets", | |
198 | "p128to255octets", | |
199 | "p256to511octets", | |
200 | "p512to1023octets", | |
201 | "p1024to1518octets", | |
202 | "p1519to2047octets", | |
203 | "p2048to4095octets", | |
204 | "p4096to8191octets", | |
205 | "p8192to10239octets", | |
206 | }; | |
207 | ||
208 | #define NUM_IEEE_802_3_COUNTERS 19 | |
209 | #define NUM_RFC_2863_COUNTERS 13 | |
210 | #define NUM_RFC_2819_COUNTERS 21 | |
211 | #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \ | |
212 | NUM_RFC_2863_COUNTERS + \ | |
213 | NUM_RFC_2819_COUNTERS) | |
214 | ||
215 | struct mlx5e_pport_stats { | |
216 | __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS]; | |
217 | __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS]; | |
218 | __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS]; | |
219 | }; | |
220 | ||
f62b8bb8 AV |
221 | static const char rq_stats_strings[][ETH_GSTRING_LEN] = { |
222 | "packets", | |
223 | "csum_none", | |
bbceefce | 224 | "csum_sw", |
f62b8bb8 AV |
225 | "lro_packets", |
226 | "lro_bytes", | |
227 | "wqe_err" | |
228 | }; | |
229 | ||
230 | struct mlx5e_rq_stats { | |
231 | u64 packets; | |
232 | u64 csum_none; | |
bbceefce | 233 | u64 csum_sw; |
f62b8bb8 AV |
234 | u64 lro_packets; |
235 | u64 lro_bytes; | |
236 | u64 wqe_err; | |
bbceefce | 237 | #define NUM_RQ_STATS 6 |
f62b8bb8 AV |
238 | }; |
239 | ||
240 | static const char sq_stats_strings[][ETH_GSTRING_LEN] = { | |
241 | "packets", | |
242 | "tso_packets", | |
243 | "tso_bytes", | |
244 | "csum_offload_none", | |
245 | "stopped", | |
246 | "wake", | |
247 | "dropped", | |
248 | "nop" | |
249 | }; | |
250 | ||
251 | struct mlx5e_sq_stats { | |
252 | u64 packets; | |
253 | u64 tso_packets; | |
254 | u64 tso_bytes; | |
255 | u64 csum_offload_none; | |
256 | u64 stopped; | |
257 | u64 wake; | |
258 | u64 dropped; | |
259 | u64 nop; | |
260 | #define NUM_SQ_STATS 8 | |
261 | }; | |
262 | ||
263 | struct mlx5e_stats { | |
264 | struct mlx5e_vport_stats vport; | |
efea389d | 265 | struct mlx5e_pport_stats pport; |
f62b8bb8 AV |
266 | }; |
267 | ||
268 | struct mlx5e_params { | |
269 | u8 log_sq_size; | |
270 | u8 log_rq_size; | |
271 | u16 num_channels; | |
272 | u8 default_vlan_prio; | |
273 | u8 num_tc; | |
274 | u16 rx_cq_moderation_usec; | |
275 | u16 rx_cq_moderation_pkts; | |
276 | u16 tx_cq_moderation_usec; | |
277 | u16 tx_cq_moderation_pkts; | |
278 | u16 min_rx_wqes; | |
f62b8bb8 AV |
279 | bool lro_en; |
280 | u32 lro_wqe_sz; | |
58d52291 | 281 | u16 tx_max_inline; |
2d75b2bc AS |
282 | u8 rss_hfunc; |
283 | u8 toeplitz_hash_key[40]; | |
284 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
f62b8bb8 AV |
285 | }; |
286 | ||
287 | enum { | |
288 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
289 | }; | |
290 | ||
291 | enum cq_flags { | |
292 | MLX5E_CQ_HAS_CQES = 1, | |
293 | }; | |
294 | ||
295 | struct mlx5e_cq { | |
296 | /* data path - accessed per cqe */ | |
297 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
298 | unsigned long flags; |
299 | ||
300 | /* data path - accessed per napi poll */ | |
301 | struct napi_struct *napi; | |
302 | struct mlx5_core_cq mcq; | |
303 | struct mlx5e_channel *channel; | |
50cfa25a | 304 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
305 | |
306 | /* control */ | |
307 | struct mlx5_wq_ctrl wq_ctrl; | |
308 | } ____cacheline_aligned_in_smp; | |
309 | ||
310 | struct mlx5e_rq { | |
311 | /* data path */ | |
312 | struct mlx5_wq_ll wq; | |
313 | u32 wqe_sz; | |
314 | struct sk_buff **skb; | |
315 | ||
316 | struct device *pdev; | |
317 | struct net_device *netdev; | |
318 | struct mlx5e_rq_stats stats; | |
319 | struct mlx5e_cq cq; | |
320 | ||
321 | unsigned long state; | |
322 | int ix; | |
323 | ||
324 | /* control */ | |
325 | struct mlx5_wq_ctrl wq_ctrl; | |
326 | u32 rqn; | |
327 | struct mlx5e_channel *channel; | |
50cfa25a | 328 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
329 | } ____cacheline_aligned_in_smp; |
330 | ||
34802a42 | 331 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
332 | u32 num_bytes; |
333 | u8 num_wqebbs; | |
334 | u8 num_dma; | |
335 | }; | |
336 | ||
d4e28cbd AS |
337 | enum mlx5e_dma_map_type { |
338 | MLX5E_DMA_MAP_SINGLE, | |
339 | MLX5E_DMA_MAP_PAGE | |
340 | }; | |
341 | ||
f62b8bb8 | 342 | struct mlx5e_sq_dma { |
d4e28cbd AS |
343 | dma_addr_t addr; |
344 | u32 size; | |
345 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
346 | }; |
347 | ||
348 | enum { | |
349 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
350 | }; | |
351 | ||
352 | struct mlx5e_sq { | |
353 | /* data path */ | |
354 | ||
355 | /* dirtied @completion */ | |
356 | u16 cc; | |
357 | u32 dma_fifo_cc; | |
358 | ||
359 | /* dirtied @xmit */ | |
360 | u16 pc ____cacheline_aligned_in_smp; | |
361 | u32 dma_fifo_pc; | |
88a85f99 AS |
362 | u16 bf_offset; |
363 | u16 prev_cc; | |
364 | u8 bf_budget; | |
f62b8bb8 AV |
365 | struct mlx5e_sq_stats stats; |
366 | ||
367 | struct mlx5e_cq cq; | |
368 | ||
369 | /* pointers to per packet info: write@xmit, read@completion */ | |
370 | struct sk_buff **skb; | |
371 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 372 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
373 | |
374 | /* read only */ | |
375 | struct mlx5_wq_cyc wq; | |
376 | u32 dma_fifo_mask; | |
377 | void __iomem *uar_map; | |
88a85f99 | 378 | void __iomem *uar_bf_map; |
f62b8bb8 AV |
379 | struct netdev_queue *txq; |
380 | u32 sqn; | |
88a85f99 | 381 | u16 bf_buf_size; |
12be4b21 SM |
382 | u16 max_inline; |
383 | u16 edge; | |
f62b8bb8 AV |
384 | struct device *pdev; |
385 | __be32 mkey_be; | |
386 | unsigned long state; | |
387 | ||
388 | /* control path */ | |
389 | struct mlx5_wq_ctrl wq_ctrl; | |
390 | struct mlx5_uar uar; | |
391 | struct mlx5e_channel *channel; | |
392 | int tc; | |
393 | } ____cacheline_aligned_in_smp; | |
394 | ||
395 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
396 | { | |
397 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
398 | (sq->cc == sq->pc)); | |
399 | } | |
400 | ||
401 | enum channel_flags { | |
402 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
403 | }; | |
404 | ||
405 | struct mlx5e_channel { | |
406 | /* data path */ | |
407 | struct mlx5e_rq rq; | |
408 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
409 | struct napi_struct napi; | |
410 | struct device *pdev; | |
411 | struct net_device *netdev; | |
412 | __be32 mkey_be; | |
413 | u8 num_tc; | |
414 | unsigned long flags; | |
415 | ||
416 | /* control */ | |
417 | struct mlx5e_priv *priv; | |
418 | int ix; | |
419 | int cpu; | |
420 | }; | |
421 | ||
422 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
423 | MLX5E_TT_IPV4_TCP, |
424 | MLX5E_TT_IPV6_TCP, | |
425 | MLX5E_TT_IPV4_UDP, | |
426 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
427 | MLX5E_TT_IPV4_IPSEC_AH, |
428 | MLX5E_TT_IPV6_IPSEC_AH, | |
429 | MLX5E_TT_IPV4_IPSEC_ESP, | |
430 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
431 | MLX5E_TT_IPV4, |
432 | MLX5E_TT_IPV6, | |
433 | MLX5E_TT_ANY, | |
434 | MLX5E_NUM_TT, | |
f62b8bb8 AV |
435 | }; |
436 | ||
4cbeaff5 AS |
437 | enum mlx5e_rqt_ix { |
438 | MLX5E_INDIRECTION_RQT, | |
439 | MLX5E_SINGLE_RQ_RQT, | |
440 | MLX5E_NUM_RQT, | |
f62b8bb8 AV |
441 | }; |
442 | ||
443 | struct mlx5e_eth_addr_info { | |
444 | u8 addr[ETH_ALEN + 2]; | |
445 | u32 tt_vec; | |
86d722ad | 446 | struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; |
f62b8bb8 AV |
447 | }; |
448 | ||
449 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) | |
450 | ||
451 | struct mlx5e_eth_addr_db { | |
452 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
453 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
454 | struct mlx5e_eth_addr_info broadcast; | |
455 | struct mlx5e_eth_addr_info allmulti; | |
456 | struct mlx5e_eth_addr_info promisc; | |
457 | bool broadcast_enabled; | |
458 | bool allmulti_enabled; | |
459 | bool promisc_enabled; | |
460 | }; | |
461 | ||
462 | enum { | |
463 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, | |
464 | MLX5E_STATE_OPENED, | |
9b37b07f | 465 | MLX5E_STATE_DESTROYING, |
f62b8bb8 AV |
466 | }; |
467 | ||
468 | struct mlx5e_vlan_db { | |
aad9e6e4 | 469 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
470 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
471 | struct mlx5_flow_rule *untagged_rule; | |
472 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
473 | bool filter_disabled; |
474 | }; | |
475 | ||
476 | struct mlx5e_flow_table { | |
86d722ad MG |
477 | int num_groups; |
478 | struct mlx5_flow_table *t; | |
479 | struct mlx5_flow_group **g; | |
480 | }; | |
481 | ||
482 | struct mlx5e_flow_tables { | |
483 | struct mlx5_flow_namespace *ns; | |
484 | struct mlx5e_flow_table vlan; | |
485 | struct mlx5e_flow_table main; | |
f62b8bb8 AV |
486 | }; |
487 | ||
488 | struct mlx5e_priv { | |
489 | /* priv data path fields - start */ | |
f62b8bb8 | 490 | int default_vlan_prio; |
03289b88 | 491 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 492 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
493 | /* priv data path fields - end */ |
494 | ||
495 | unsigned long state; | |
496 | struct mutex state_lock; /* Protects Interface state */ | |
497 | struct mlx5_uar cq_uar; | |
498 | u32 pdn; | |
3191e05f | 499 | u32 tdn; |
f62b8bb8 | 500 | struct mlx5_core_mr mr; |
50cfa25a | 501 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
502 | |
503 | struct mlx5e_channel **channel; | |
504 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
4cbeaff5 | 505 | u32 rqtn[MLX5E_NUM_RQT]; |
f62b8bb8 AV |
506 | u32 tirn[MLX5E_NUM_TT]; |
507 | ||
86d722ad | 508 | struct mlx5e_flow_tables fts; |
f62b8bb8 AV |
509 | struct mlx5e_eth_addr_db eth_addr; |
510 | struct mlx5e_vlan_db vlan; | |
511 | ||
512 | struct mlx5e_params params; | |
513 | spinlock_t async_events_spinlock; /* sync hw events */ | |
514 | struct work_struct update_carrier_work; | |
515 | struct work_struct set_rx_mode_work; | |
516 | struct delayed_work update_stats_work; | |
517 | ||
518 | struct mlx5_core_dev *mdev; | |
519 | struct net_device *netdev; | |
520 | struct mlx5e_stats stats; | |
521 | }; | |
522 | ||
523 | #define MLX5E_NET_IP_ALIGN 2 | |
524 | ||
525 | struct mlx5e_tx_wqe { | |
526 | struct mlx5_wqe_ctrl_seg ctrl; | |
527 | struct mlx5_wqe_eth_seg eth; | |
528 | }; | |
529 | ||
530 | struct mlx5e_rx_wqe { | |
531 | struct mlx5_wqe_srq_next_seg next; | |
532 | struct mlx5_wqe_data_seg data; | |
533 | }; | |
534 | ||
535 | enum mlx5e_link_mode { | |
536 | MLX5E_1000BASE_CX_SGMII = 0, | |
537 | MLX5E_1000BASE_KX = 1, | |
538 | MLX5E_10GBASE_CX4 = 2, | |
539 | MLX5E_10GBASE_KX4 = 3, | |
540 | MLX5E_10GBASE_KR = 4, | |
541 | MLX5E_20GBASE_KR2 = 5, | |
542 | MLX5E_40GBASE_CR4 = 6, | |
543 | MLX5E_40GBASE_KR4 = 7, | |
544 | MLX5E_56GBASE_R4 = 8, | |
545 | MLX5E_10GBASE_CR = 12, | |
546 | MLX5E_10GBASE_SR = 13, | |
547 | MLX5E_10GBASE_ER = 14, | |
548 | MLX5E_40GBASE_SR4 = 15, | |
549 | MLX5E_40GBASE_LR4 = 16, | |
550 | MLX5E_100GBASE_CR4 = 20, | |
551 | MLX5E_100GBASE_SR4 = 21, | |
552 | MLX5E_100GBASE_KR4 = 22, | |
553 | MLX5E_100GBASE_LR4 = 23, | |
554 | MLX5E_100BASE_TX = 24, | |
555 | MLX5E_100BASE_T = 25, | |
556 | MLX5E_10GBASE_T = 26, | |
557 | MLX5E_25GBASE_CR = 27, | |
558 | MLX5E_25GBASE_KR = 28, | |
559 | MLX5E_25GBASE_SR = 29, | |
560 | MLX5E_50GBASE_CR2 = 30, | |
561 | MLX5E_50GBASE_KR2 = 31, | |
562 | MLX5E_LINK_MODES_NUMBER, | |
563 | }; | |
564 | ||
565 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
566 | ||
12be4b21 | 567 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
568 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
569 | void *accel_priv, select_queue_fallback_t fallback); | |
570 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
571 | |
572 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
573 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
574 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
575 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq); | |
44fb6fbb | 576 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
f62b8bb8 AV |
577 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
578 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); | |
579 | ||
580 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
581 | ||
40ab6a6e AS |
582 | int mlx5e_create_flow_tables(struct mlx5e_priv *priv); |
583 | void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv); | |
f62b8bb8 | 584 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); |
f62b8bb8 AV |
585 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
586 | ||
587 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, | |
588 | u16 vid); | |
589 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
590 | u16 vid); | |
591 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
592 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 593 | |
2d75b2bc AS |
594 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix); |
595 | ||
f62b8bb8 AV |
596 | int mlx5e_open_locked(struct net_device *netdev); |
597 | int mlx5e_close_locked(struct net_device *netdev); | |
f62b8bb8 AV |
598 | |
599 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
88a85f99 | 600 | struct mlx5e_tx_wqe *wqe, int bf_sz) |
f62b8bb8 | 601 | { |
88a85f99 AS |
602 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
603 | ||
f62b8bb8 AV |
604 | /* ensure wqe is visible to device before updating doorbell record */ |
605 | dma_wmb(); | |
606 | ||
607 | *sq->wq.db = cpu_to_be32(sq->pc); | |
608 | ||
609 | /* ensure doorbell record is visible to device before ringing the | |
610 | * doorbell | |
611 | */ | |
612 | wmb(); | |
613 | ||
88a85f99 AS |
614 | if (bf_sz) { |
615 | __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz); | |
616 | ||
617 | /* flush the write-combining mapped buffer */ | |
618 | wmb(); | |
619 | ||
620 | } else { | |
621 | mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL); | |
622 | } | |
f62b8bb8 AV |
623 | |
624 | sq->bf_offset ^= sq->bf_buf_size; | |
625 | } | |
626 | ||
627 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
628 | { | |
629 | struct mlx5_core_cq *mcq; | |
630 | ||
631 | mcq = &cq->mcq; | |
632 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
633 | } | |
634 | ||
3435ab59 AS |
635 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
636 | { | |
637 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
638 | MLX5E_MAX_NUM_CHANNELS); | |
639 | } | |
640 | ||
f62b8bb8 | 641 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
58d52291 | 642 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |