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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
d8bec2b2 MKL |
54 | #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
55 | #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
56 | ||
f62b8bb8 AV |
57 | #define MLX5E_MAX_NUM_TC 8 |
58 | ||
e842b100 | 59 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
60 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
61 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
62 | ||
e842b100 | 63 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
64 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
65 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
66 | ||
461017cb | 67 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 68 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
69 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
70 | ||
1bfecfca SM |
71 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
72 | ||
f32f5bd2 DJ |
73 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
74 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
75 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
76 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
77 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
78 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
79 | ||
7e426671 | 80 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
81 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
82 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
83 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
84 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
85 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
86 | |
87 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
ec8b9981 TT |
88 | #define MLX5E_REQUIRED_MTTS(wqes) \ |
89 | (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
90 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) | |
fe4c988b | 91 | |
bc77b240 | 92 | #define MLX5_UMR_ALIGN (2048) |
461017cb TT |
93 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
94 | ||
d9a40271 | 95 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
96 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
97 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
98 | ||
f62b8bb8 | 99 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 100 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
101 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
102 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
103 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
104 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 105 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 106 | |
936896e9 AS |
107 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
108 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 109 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 110 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 111 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
112 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
113 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
114 | ||
f10b7cc7 SM |
115 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
116 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
117 | ||
b5503b99 | 118 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
b5503b99 | 119 | #define MLX5E_XDP_TX_DS_COUNT \ |
b70149dd | 120 | ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) |
b5503b99 | 121 | |
86d722ad | 122 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 123 | |
461017cb TT |
124 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
125 | { | |
126 | switch (wq_type) { | |
127 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
128 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
129 | wq_size / 2); | |
130 | default: | |
131 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
132 | wq_size / 2); | |
133 | } | |
134 | } | |
135 | ||
136 | static inline int mlx5_min_log_rq_size(int wq_type) | |
137 | { | |
138 | switch (wq_type) { | |
139 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
140 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
141 | default: | |
142 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
143 | } | |
144 | } | |
145 | ||
146 | static inline int mlx5_max_log_rq_size(int wq_type) | |
147 | { | |
148 | switch (wq_type) { | |
149 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
150 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
151 | default: | |
152 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
153 | } | |
154 | } | |
155 | ||
2f48af12 TT |
156 | struct mlx5e_tx_wqe { |
157 | struct mlx5_wqe_ctrl_seg ctrl; | |
158 | struct mlx5_wqe_eth_seg eth; | |
159 | }; | |
160 | ||
161 | struct mlx5e_rx_wqe { | |
162 | struct mlx5_wqe_srq_next_seg next; | |
163 | struct mlx5_wqe_data_seg data; | |
164 | }; | |
86d722ad | 165 | |
bc77b240 TT |
166 | struct mlx5e_umr_wqe { |
167 | struct mlx5_wqe_ctrl_seg ctrl; | |
168 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
169 | struct mlx5_mkey_seg mkc; | |
170 | struct mlx5_wqe_data_seg data; | |
171 | }; | |
172 | ||
d605d668 KH |
173 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
174 | ||
4e59e288 | 175 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 176 | "rx_cqe_moder", |
9bcc8606 | 177 | "rx_cqe_compress", |
4e59e288 GP |
178 | }; |
179 | ||
180 | enum mlx5e_priv_flag { | |
9908aa29 | 181 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
9bcc8606 | 182 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1), |
4e59e288 GP |
183 | }; |
184 | ||
6a9764ef | 185 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
186 | do { \ |
187 | if (enable) \ | |
6a9764ef | 188 | (params)->pflags |= (pflag); \ |
59ece1c9 | 189 | else \ |
6a9764ef | 190 | (params)->pflags &= ~(pflag); \ |
4e59e288 GP |
191 | } while (0) |
192 | ||
6a9764ef | 193 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag))) |
59ece1c9 | 194 | |
08fb1dac SM |
195 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
196 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
197 | #endif |
198 | ||
9908aa29 TT |
199 | struct mlx5e_cq_moder { |
200 | u16 usec; | |
201 | u16 pkts; | |
202 | }; | |
203 | ||
f62b8bb8 AV |
204 | struct mlx5e_params { |
205 | u8 log_sq_size; | |
461017cb | 206 | u8 rq_wq_type; |
d9d9f156 TT |
207 | u8 mpwqe_log_stride_sz; |
208 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
209 | u8 log_rq_size; |
210 | u16 num_channels; | |
f62b8bb8 | 211 | u8 num_tc; |
9908aa29 | 212 | u8 rx_cq_period_mode; |
9bcc8606 | 213 | bool rx_cqe_compress_def; |
9908aa29 TT |
214 | struct mlx5e_cq_moder rx_cq_moderation; |
215 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 AV |
216 | bool lro_en; |
217 | u32 lro_wqe_sz; | |
58d52291 | 218 | u16 tx_max_inline; |
cff92d7c | 219 | u8 tx_min_inline_mode; |
2d75b2bc AS |
220 | u8 rss_hfunc; |
221 | u8 toeplitz_hash_key[40]; | |
222 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 223 | bool vlan_strip_disable; |
cb3c7fd4 | 224 | bool rx_am_enabled; |
2b029556 | 225 | u32 lro_timeout; |
59ece1c9 | 226 | u32 pflags; |
6a9764ef | 227 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
228 | }; |
229 | ||
3a6a931d HN |
230 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
231 | struct mlx5e_cee_config { | |
232 | /* bw pct for priority group */ | |
233 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
234 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
235 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
236 | bool pfc_enable; | |
237 | }; | |
238 | ||
239 | enum { | |
240 | MLX5_DCB_CHG_RESET, | |
241 | MLX5_DCB_NO_CHG, | |
242 | MLX5_DCB_CHG_NO_RESET, | |
243 | }; | |
244 | ||
245 | struct mlx5e_dcbx { | |
e207b7e9 | 246 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 247 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
820c2c5e HN |
248 | |
249 | /* The only setting that cannot be read from FW */ | |
250 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
3a6a931d HN |
251 | }; |
252 | #endif | |
253 | ||
ef9814de EBE |
254 | struct mlx5e_tstamp { |
255 | rwlock_t lock; | |
256 | struct cyclecounter cycles; | |
257 | struct timecounter clock; | |
258 | struct hwtstamp_config hwtstamp_config; | |
259 | u32 nominal_c_mult; | |
260 | unsigned long overflow_period; | |
261 | struct delayed_work overflow_work; | |
262 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
263 | struct ptp_clock *ptp; |
264 | struct ptp_clock_info ptp_info; | |
ee7f1220 | 265 | u8 *pps_pin_caps; |
ef9814de EBE |
266 | }; |
267 | ||
f62b8bb8 | 268 | enum { |
c0f1147d | 269 | MLX5E_RQ_STATE_ENABLED, |
bc77b240 | 270 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 271 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
272 | }; |
273 | ||
f62b8bb8 AV |
274 | struct mlx5e_cq { |
275 | /* data path - accessed per cqe */ | |
276 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
277 | |
278 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 279 | u16 event_ctr; |
f62b8bb8 AV |
280 | struct napi_struct *napi; |
281 | struct mlx5_core_cq mcq; | |
282 | struct mlx5e_channel *channel; | |
283 | ||
7219ab34 TT |
284 | /* cqe decompression */ |
285 | struct mlx5_cqe64 title; | |
286 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
287 | u8 mini_arr_idx; | |
288 | u16 decmprs_left; | |
289 | u16 decmprs_wqe_counter; | |
290 | ||
f62b8bb8 | 291 | /* control */ |
a43b25da | 292 | struct mlx5_core_dev *mdev; |
1c1b5228 | 293 | struct mlx5_frag_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
294 | } ____cacheline_aligned_in_smp; |
295 | ||
eba2db2b SM |
296 | struct mlx5e_tx_wqe_info { |
297 | u32 num_bytes; | |
298 | u8 num_wqebbs; | |
299 | u8 num_dma; | |
300 | }; | |
301 | ||
302 | enum mlx5e_dma_map_type { | |
303 | MLX5E_DMA_MAP_SINGLE, | |
304 | MLX5E_DMA_MAP_PAGE | |
305 | }; | |
306 | ||
307 | struct mlx5e_sq_dma { | |
308 | dma_addr_t addr; | |
309 | u32 size; | |
310 | enum mlx5e_dma_map_type type; | |
311 | }; | |
312 | ||
313 | enum { | |
314 | MLX5E_SQ_STATE_ENABLED, | |
315 | }; | |
316 | ||
317 | struct mlx5e_sq_wqe_info { | |
318 | u8 opcode; | |
319 | u8 num_wqebbs; | |
320 | }; | |
2f48af12 | 321 | |
31391048 | 322 | struct mlx5e_txqsq { |
eba2db2b SM |
323 | /* data path */ |
324 | ||
325 | /* dirtied @completion */ | |
326 | u16 cc; | |
327 | u32 dma_fifo_cc; | |
328 | ||
329 | /* dirtied @xmit */ | |
330 | u16 pc ____cacheline_aligned_in_smp; | |
331 | u32 dma_fifo_pc; | |
332 | struct mlx5e_sq_stats stats; | |
333 | ||
334 | struct mlx5e_cq cq; | |
335 | ||
31391048 SM |
336 | /* write@xmit, read@completion */ |
337 | struct { | |
338 | struct sk_buff **skb; | |
339 | struct mlx5e_sq_dma *dma_fifo; | |
340 | struct mlx5e_tx_wqe_info *wqe_info; | |
eba2db2b SM |
341 | } db; |
342 | ||
343 | /* read only */ | |
344 | struct mlx5_wq_cyc wq; | |
345 | u32 dma_fifo_mask; | |
346 | void __iomem *uar_map; | |
347 | struct netdev_queue *txq; | |
348 | u32 sqn; | |
349 | u16 max_inline; | |
350 | u8 min_inline_mode; | |
351 | u16 edge; | |
352 | struct device *pdev; | |
353 | struct mlx5e_tstamp *tstamp; | |
354 | __be32 mkey_be; | |
355 | unsigned long state; | |
356 | ||
357 | /* control path */ | |
358 | struct mlx5_wq_ctrl wq_ctrl; | |
359 | struct mlx5e_channel *channel; | |
acc6c595 | 360 | int txq_ix; |
eba2db2b | 361 | u32 rate_limit; |
31391048 SM |
362 | } ____cacheline_aligned_in_smp; |
363 | ||
364 | struct mlx5e_xdpsq { | |
365 | /* data path */ | |
366 | ||
367 | /* dirtied @rx completion */ | |
368 | u16 cc; | |
369 | u16 pc; | |
370 | ||
371 | struct mlx5e_cq cq; | |
372 | ||
373 | /* write@xmit, read@completion */ | |
374 | struct { | |
375 | struct mlx5e_dma_info *di; | |
376 | bool doorbell; | |
377 | } db; | |
378 | ||
379 | /* read only */ | |
380 | struct mlx5_wq_cyc wq; | |
381 | void __iomem *uar_map; | |
382 | u32 sqn; | |
383 | struct device *pdev; | |
384 | __be32 mkey_be; | |
385 | u8 min_inline_mode; | |
386 | unsigned long state; | |
387 | ||
388 | /* control path */ | |
389 | struct mlx5_wq_ctrl wq_ctrl; | |
390 | struct mlx5e_channel *channel; | |
391 | } ____cacheline_aligned_in_smp; | |
392 | ||
393 | struct mlx5e_icosq { | |
394 | /* data path */ | |
395 | ||
396 | /* dirtied @completion */ | |
397 | u16 cc; | |
398 | ||
399 | /* dirtied @xmit */ | |
400 | u16 pc ____cacheline_aligned_in_smp; | |
401 | u32 dma_fifo_pc; | |
402 | u16 prev_cc; | |
403 | ||
404 | struct mlx5e_cq cq; | |
405 | ||
406 | /* write@xmit, read@completion */ | |
407 | struct { | |
408 | struct mlx5e_sq_wqe_info *ico_wqe; | |
409 | } db; | |
410 | ||
411 | /* read only */ | |
412 | struct mlx5_wq_cyc wq; | |
413 | void __iomem *uar_map; | |
414 | u32 sqn; | |
415 | u16 edge; | |
416 | struct device *pdev; | |
417 | __be32 mkey_be; | |
418 | unsigned long state; | |
419 | ||
420 | /* control path */ | |
421 | struct mlx5_wq_ctrl wq_ctrl; | |
422 | struct mlx5e_channel *channel; | |
eba2db2b SM |
423 | } ____cacheline_aligned_in_smp; |
424 | ||
864b2d71 SM |
425 | static inline bool |
426 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 427 | { |
864b2d71 | 428 | return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc)); |
eba2db2b | 429 | } |
6cd392a0 | 430 | |
461017cb TT |
431 | struct mlx5e_dma_info { |
432 | struct page *page; | |
433 | dma_addr_t addr; | |
434 | }; | |
435 | ||
eba2db2b SM |
436 | struct mlx5e_umr_dma_info { |
437 | __be64 *mtt; | |
438 | dma_addr_t mtt_addr; | |
439 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; | |
440 | struct mlx5e_umr_wqe wqe; | |
441 | }; | |
442 | ||
443 | struct mlx5e_mpw_info { | |
444 | struct mlx5e_umr_dma_info umr; | |
445 | u16 consumed_strides; | |
446 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
447 | }; | |
448 | ||
cb3c7fd4 GR |
449 | struct mlx5e_rx_am_stats { |
450 | int ppms; /* packets per msec */ | |
451 | int epms; /* events per msec */ | |
452 | }; | |
453 | ||
454 | struct mlx5e_rx_am_sample { | |
455 | ktime_t time; | |
456 | unsigned int pkt_ctr; | |
457 | u16 event_ctr; | |
458 | }; | |
459 | ||
460 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
461 | u8 state; | |
462 | struct mlx5e_rx_am_stats prev_stats; | |
463 | struct mlx5e_rx_am_sample start_sample; | |
464 | struct work_struct work; | |
465 | u8 profile_ix; | |
466 | u8 mode; | |
467 | u8 tune_state; | |
468 | u8 steps_right; | |
469 | u8 steps_left; | |
470 | u8 tired; | |
471 | }; | |
472 | ||
4415a031 TT |
473 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
474 | * or a MPWQE (for striding rq). | |
475 | */ | |
476 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
477 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
478 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
479 | struct mlx5e_page_cache { | |
480 | u32 head; | |
481 | u32 tail; | |
482 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
483 | }; | |
484 | ||
eba2db2b SM |
485 | struct mlx5e_rq; |
486 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
487 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16); | |
488 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); | |
489 | ||
f62b8bb8 AV |
490 | struct mlx5e_rq { |
491 | /* data path */ | |
492 | struct mlx5_wq_ll wq; | |
1bfecfca | 493 | |
21c59685 SM |
494 | union { |
495 | struct mlx5e_dma_info *dma_info; | |
496 | struct { | |
497 | struct mlx5e_mpw_info *info; | |
498 | void *mtt_no_align; | |
21c59685 SM |
499 | } mpwqe; |
500 | }; | |
1bfecfca SM |
501 | struct { |
502 | u8 page_order; | |
503 | u32 wqe_sz; /* wqe data buffer size */ | |
b5503b99 | 504 | u8 map_dir; /* dma map direction */ |
1bfecfca | 505 | } buff; |
bc77b240 | 506 | __be32 mkey_be; |
f62b8bb8 AV |
507 | |
508 | struct device *pdev; | |
509 | struct net_device *netdev; | |
ef9814de | 510 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
511 | struct mlx5e_rq_stats stats; |
512 | struct mlx5e_cq cq; | |
4415a031 TT |
513 | struct mlx5e_page_cache page_cache; |
514 | ||
2f48af12 TT |
515 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
516 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 517 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
518 | |
519 | unsigned long state; | |
520 | int ix; | |
d8bec2b2 | 521 | u16 rx_headroom; |
f62b8bb8 | 522 | |
cb3c7fd4 | 523 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
31871f87 SM |
524 | |
525 | /* XDP */ | |
86994156 | 526 | struct bpf_prog *xdp_prog; |
31391048 | 527 | struct mlx5e_xdpsq xdpsq; |
cb3c7fd4 | 528 | |
f62b8bb8 AV |
529 | /* control */ |
530 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 531 | u8 wq_type; |
d9d9f156 TT |
532 | u32 mpwqe_stride_sz; |
533 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
534 | u32 rqn; |
535 | struct mlx5e_channel *channel; | |
a43b25da | 536 | struct mlx5_core_dev *mdev; |
ec8b9981 | 537 | struct mlx5_core_mkey umr_mkey; |
f62b8bb8 AV |
538 | } ____cacheline_aligned_in_smp; |
539 | ||
f62b8bb8 AV |
540 | enum channel_flags { |
541 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
542 | }; | |
543 | ||
544 | struct mlx5e_channel { | |
545 | /* data path */ | |
546 | struct mlx5e_rq rq; | |
31391048 SM |
547 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
548 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 549 | bool xdp; |
f62b8bb8 AV |
550 | struct napi_struct napi; |
551 | struct device *pdev; | |
552 | struct net_device *netdev; | |
553 | __be32 mkey_be; | |
554 | u8 num_tc; | |
555 | unsigned long flags; | |
556 | ||
557 | /* control */ | |
558 | struct mlx5e_priv *priv; | |
a43b25da SM |
559 | struct mlx5_core_dev *mdev; |
560 | struct mlx5e_tstamp *tstamp; | |
f62b8bb8 AV |
561 | int ix; |
562 | int cpu; | |
563 | }; | |
564 | ||
ff9c852f SM |
565 | struct mlx5e_channels { |
566 | struct mlx5e_channel **c; | |
567 | unsigned int num; | |
6a9764ef | 568 | struct mlx5e_params params; |
ff9c852f SM |
569 | }; |
570 | ||
f62b8bb8 | 571 | enum mlx5e_traffic_types { |
5a6f8aef AS |
572 | MLX5E_TT_IPV4_TCP, |
573 | MLX5E_TT_IPV6_TCP, | |
574 | MLX5E_TT_IPV4_UDP, | |
575 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
576 | MLX5E_TT_IPV4_IPSEC_AH, |
577 | MLX5E_TT_IPV6_IPSEC_AH, | |
578 | MLX5E_TT_IPV4_IPSEC_ESP, | |
579 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
580 | MLX5E_TT_IPV4, |
581 | MLX5E_TT_IPV6, | |
582 | MLX5E_TT_ANY, | |
583 | MLX5E_NUM_TT, | |
1da36696 | 584 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
585 | }; |
586 | ||
acff797c | 587 | enum { |
e0f46eb9 | 588 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
589 | MLX5E_STATE_OPENED, |
590 | MLX5E_STATE_DESTROYING, | |
591 | }; | |
592 | ||
593 | struct mlx5e_vxlan_db { | |
594 | spinlock_t lock; /* protect vxlan table */ | |
595 | struct radix_tree_root tree; | |
596 | }; | |
597 | ||
33cfaaa8 | 598 | struct mlx5e_l2_rule { |
f62b8bb8 | 599 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 600 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
601 | }; |
602 | ||
acff797c MG |
603 | struct mlx5e_flow_table { |
604 | int num_groups; | |
605 | struct mlx5_flow_table *t; | |
606 | struct mlx5_flow_group **g; | |
607 | }; | |
608 | ||
33cfaaa8 | 609 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 610 | |
acff797c MG |
611 | struct mlx5e_tc_table { |
612 | struct mlx5_flow_table *t; | |
613 | ||
614 | struct rhashtable_params ht_params; | |
615 | struct rhashtable ht; | |
f62b8bb8 AV |
616 | }; |
617 | ||
acff797c MG |
618 | struct mlx5e_vlan_table { |
619 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 620 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
74491de9 MB |
621 | struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID]; |
622 | struct mlx5_flow_handle *untagged_rule; | |
8a271746 MHY |
623 | struct mlx5_flow_handle *any_cvlan_rule; |
624 | struct mlx5_flow_handle *any_svlan_rule; | |
625 | bool filter_disabled; | |
f62b8bb8 AV |
626 | }; |
627 | ||
33cfaaa8 MG |
628 | struct mlx5e_l2_table { |
629 | struct mlx5e_flow_table ft; | |
630 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
631 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
632 | struct mlx5e_l2_rule broadcast; | |
633 | struct mlx5e_l2_rule allmulti; | |
634 | struct mlx5e_l2_rule promisc; | |
635 | bool broadcast_enabled; | |
636 | bool allmulti_enabled; | |
637 | bool promisc_enabled; | |
638 | }; | |
639 | ||
640 | /* L3/L4 traffic type classifier */ | |
641 | struct mlx5e_ttc_table { | |
642 | struct mlx5e_flow_table ft; | |
74491de9 | 643 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
33cfaaa8 MG |
644 | }; |
645 | ||
18c908e4 MG |
646 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
647 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
648 | struct arfs_table { |
649 | struct mlx5e_flow_table ft; | |
74491de9 | 650 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 651 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
652 | }; |
653 | ||
654 | enum arfs_type { | |
655 | ARFS_IPV4_TCP, | |
656 | ARFS_IPV6_TCP, | |
657 | ARFS_IPV4_UDP, | |
658 | ARFS_IPV6_UDP, | |
659 | ARFS_NUM_TYPES, | |
660 | }; | |
661 | ||
662 | struct mlx5e_arfs_tables { | |
663 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
664 | /* Protect aRFS rules list */ |
665 | spinlock_t arfs_lock; | |
666 | struct list_head rules; | |
667 | int last_filter_id; | |
668 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
669 | }; |
670 | ||
671 | /* NIC prio FTS */ | |
672 | enum { | |
673 | MLX5E_VLAN_FT_LEVEL = 0, | |
674 | MLX5E_L2_FT_LEVEL, | |
675 | MLX5E_TTC_FT_LEVEL, | |
676 | MLX5E_ARFS_FT_LEVEL | |
677 | }; | |
678 | ||
6dc6071c MG |
679 | struct mlx5e_ethtool_table { |
680 | struct mlx5_flow_table *ft; | |
681 | int num_rules; | |
682 | }; | |
683 | ||
1174fce8 | 684 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
685 | #define ETHTOOL_NUM_L2_FTS 4 |
686 | ||
687 | struct mlx5e_ethtool_steering { | |
1174fce8 | 688 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
689 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
690 | struct list_head rules; | |
691 | int tot_num_rules; | |
692 | }; | |
693 | ||
acff797c MG |
694 | struct mlx5e_flow_steering { |
695 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 696 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
697 | struct mlx5e_tc_table tc; |
698 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
699 | struct mlx5e_l2_table l2; |
700 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 701 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
702 | }; |
703 | ||
398f3351 | 704 | struct mlx5e_rqt { |
1da36696 | 705 | u32 rqtn; |
398f3351 HHZ |
706 | bool enabled; |
707 | }; | |
708 | ||
709 | struct mlx5e_tir { | |
710 | u32 tirn; | |
711 | struct mlx5e_rqt rqt; | |
712 | struct list_head list; | |
1da36696 TT |
713 | }; |
714 | ||
acff797c MG |
715 | enum { |
716 | MLX5E_TC_PRIO = 0, | |
717 | MLX5E_NIC_PRIO | |
718 | }; | |
719 | ||
f62b8bb8 AV |
720 | struct mlx5e_priv { |
721 | /* priv data path fields - start */ | |
acc6c595 SM |
722 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
723 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
f62b8bb8 AV |
724 | /* priv data path fields - end */ |
725 | ||
726 | unsigned long state; | |
727 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 728 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 729 | |
ff9c852f | 730 | struct mlx5e_channels channels; |
f62b8bb8 | 731 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 732 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
733 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
734 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 735 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 736 | |
acff797c | 737 | struct mlx5e_flow_steering fs; |
b3f63c3d | 738 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 | 739 | |
7bb29755 | 740 | struct workqueue_struct *wq; |
f62b8bb8 AV |
741 | struct work_struct update_carrier_work; |
742 | struct work_struct set_rx_mode_work; | |
3947ca18 | 743 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
744 | struct delayed_work update_stats_work; |
745 | ||
746 | struct mlx5_core_dev *mdev; | |
747 | struct net_device *netdev; | |
748 | struct mlx5e_stats stats; | |
ef9814de | 749 | struct mlx5e_tstamp tstamp; |
593cf338 | 750 | u16 q_counter; |
3a6a931d HN |
751 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
752 | struct mlx5e_dcbx dcbx; | |
753 | #endif | |
754 | ||
6bfd390b | 755 | const struct mlx5e_profile *profile; |
127ea380 | 756 | void *ppriv; |
f62b8bb8 AV |
757 | }; |
758 | ||
a43b25da SM |
759 | struct mlx5e_profile { |
760 | void (*init)(struct mlx5_core_dev *mdev, | |
761 | struct net_device *netdev, | |
762 | const struct mlx5e_profile *profile, void *ppriv); | |
763 | void (*cleanup)(struct mlx5e_priv *priv); | |
764 | int (*init_rx)(struct mlx5e_priv *priv); | |
765 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
766 | int (*init_tx)(struct mlx5e_priv *priv); | |
767 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
768 | void (*enable)(struct mlx5e_priv *priv); | |
769 | void (*disable)(struct mlx5e_priv *priv); | |
770 | void (*update_stats)(struct mlx5e_priv *priv); | |
771 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
772 | int max_tc; | |
773 | }; | |
774 | ||
665bc539 GP |
775 | void mlx5e_build_ptys2ethtool_map(void); |
776 | ||
f62b8bb8 AV |
777 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
778 | void *accel_priv, select_queue_fallback_t fallback); | |
779 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
780 | |
781 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
782 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
783 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 784 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 785 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
1c4bf940 | 786 | bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq); |
31391048 SM |
787 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
788 | void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq); | |
461017cb | 789 | |
4415a031 TT |
790 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
791 | bool recycle); | |
2f48af12 | 792 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 793 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 794 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 795 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 796 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
797 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
798 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
799 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
800 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
801 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
802 | ||
cb3c7fd4 GR |
803 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
804 | void mlx5e_rx_am_work(struct work_struct *work); | |
805 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
806 | ||
f62b8bb8 AV |
807 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
808 | ||
acff797c MG |
809 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
810 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 811 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 812 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
813 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
814 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
815 | u64 *buf); | |
f913a72a MG |
816 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
817 | int location); | |
818 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
819 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
820 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
821 | struct ethtool_rx_flow_spec *fs); | |
822 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
823 | int location); | |
824 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
825 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
826 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
827 | ||
ef9814de EBE |
828 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
829 | struct skb_shared_hwtstamps *hwts); | |
830 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
831 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
ee7f1220 EE |
832 | void mlx5e_pps_event_handler(struct mlx5e_priv *priv, |
833 | struct ptp_clock_event *event); | |
ef9814de EBE |
834 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); |
835 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
be7e87f9 | 836 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 837 | |
f62b8bb8 AV |
838 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
839 | u16 vid); | |
840 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
841 | u16 vid); | |
842 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
843 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 844 | |
ff9c852f | 845 | int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd); |
36350114 | 846 | |
a5f97fee SM |
847 | struct mlx5e_redirect_rqt_param { |
848 | bool is_rss; | |
849 | union { | |
850 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
851 | struct { | |
852 | u8 hfunc; | |
853 | struct mlx5e_channels *channels; | |
854 | } rss; /* RSS data */ | |
855 | }; | |
856 | }; | |
857 | ||
858 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
859 | struct mlx5e_redirect_rqt_param rrp); | |
6a9764ef SM |
860 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
861 | enum mlx5e_traffic_types tt, | |
862 | void *tirc); | |
2d75b2bc | 863 | |
f62b8bb8 AV |
864 | int mlx5e_open_locked(struct net_device *netdev); |
865 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
866 | |
867 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
868 | struct mlx5e_channels *chs); | |
869 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
870 | |
871 | /* Function pointer to be used to modify WH settings while | |
872 | * switching channels | |
873 | */ | |
874 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
55c2503d | 875 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
876 | struct mlx5e_channels *new_chs, |
877 | mlx5e_fp_hw_modify hw_modify); | |
55c2503d | 878 | |
d8c9660d TT |
879 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
880 | u32 *indirection_rqt, int len, | |
85082dba | 881 | int num_channels); |
b797a684 | 882 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 883 | |
9908aa29 TT |
884 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
885 | u8 cq_period_mode); | |
6a9764ef SM |
886 | void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, |
887 | struct mlx5e_params *params, u8 rq_type); | |
9908aa29 | 888 | |
864b2d71 SM |
889 | static inline |
890 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 891 | { |
864b2d71 SM |
892 | u16 pi = *pc & wq->sz_m1; |
893 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
894 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
895 | ||
896 | memset(cseg, 0, sizeof(*cseg)); | |
897 | ||
898 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
899 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
900 | ||
901 | (*pc)++; | |
902 | ||
903 | return wqe; | |
904 | } | |
905 | ||
906 | static inline | |
907 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
908 | void __iomem *uar_map, | |
909 | struct mlx5_wqe_ctrl_seg *ctrl) | |
910 | { | |
911 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
912 | /* ensure wqe is visible to device before updating doorbell record */ |
913 | dma_wmb(); | |
914 | ||
864b2d71 | 915 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
916 | |
917 | /* ensure doorbell record is visible to device before ringing the | |
918 | * doorbell | |
919 | */ | |
920 | wmb(); | |
f62b8bb8 | 921 | |
864b2d71 | 922 | mlx5_write64((__be32 *)ctrl, uar_map, NULL); |
f62b8bb8 AV |
923 | } |
924 | ||
925 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
926 | { | |
927 | struct mlx5_core_cq *mcq; | |
928 | ||
929 | mcq = &cq->mcq; | |
5fe9dec0 | 930 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
931 | } |
932 | ||
7e426671 TT |
933 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
934 | { | |
ec8b9981 | 935 | return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
7e426671 TT |
936 | } |
937 | ||
f62b8bb8 | 938 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
939 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
940 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
941 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 942 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
08fb1dac SM |
943 | #endif |
944 | ||
1cabe6b0 MG |
945 | #ifndef CONFIG_RFS_ACCEL |
946 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
947 | { | |
948 | return 0; | |
949 | } | |
950 | ||
951 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
952 | |
953 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
954 | { | |
9eb78923 | 955 | return -EOPNOTSUPP; |
45bf454a MG |
956 | } |
957 | ||
958 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
959 | { | |
9eb78923 | 960 | return -EOPNOTSUPP; |
45bf454a | 961 | } |
1cabe6b0 MG |
962 | #else |
963 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
964 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
965 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
966 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
967 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
968 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
969 | #endif |
970 | ||
58d52291 | 971 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
972 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
973 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
974 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
975 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
976 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
977 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 978 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 979 | |
cb67b832 HHZ |
980 | struct mlx5_eswitch_rep; |
981 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
982 | struct mlx5_eswitch_rep *rep); | |
983 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
984 | struct mlx5_eswitch_rep *rep); | |
985 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
986 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
987 | struct mlx5_eswitch_rep *rep); | |
988 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
989 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
990 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
f5f82476 | 991 | void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
370bad0f | 992 | void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv); |
cb67b832 HHZ |
993 | |
994 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
995 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
996 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
997 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
998 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
999 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
1000 | int mlx5e_close(struct net_device *netdev); | |
1001 | int mlx5e_open(struct net_device *netdev); | |
1002 | void mlx5e_update_stats_work(struct work_struct *work); | |
26e59d80 MHY |
1003 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
1004 | const struct mlx5e_profile *profile, | |
1005 | void *ppriv); | |
cb67b832 | 1006 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); |
26e59d80 MHY |
1007 | int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); |
1008 | void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); | |
2b029556 | 1009 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); |
cb67b832 | 1010 | |
370bad0f OG |
1011 | int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, |
1012 | void *sp); | |
1013 | bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id); | |
1014 | ||
1015 | bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv); | |
1016 | bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv); | |
1afff42c | 1017 | #endif /* __MLX5_EN_H__ */ |