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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
e8f887ac | 47 | #include <linux/rhashtable.h> |
cb67b832 | 48 | #include <net/switchdev.h> |
f62b8bb8 | 49 | #include "wq.h" |
f62b8bb8 | 50 | #include "mlx5_core.h" |
9218b44d | 51 | #include "en_stats.h" |
f62b8bb8 | 52 | |
1cabe6b0 MG |
53 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
54 | ||
c139dbfd ES |
55 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
56 | ||
57 | #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu)) | |
58 | #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu)) | |
d8bec2b2 | 59 | |
f62b8bb8 AV |
60 | #define MLX5E_MAX_NUM_TC 8 |
61 | ||
e842b100 | 62 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
63 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
64 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
65 | ||
e842b100 | 66 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
67 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
68 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
69 | ||
461017cb | 70 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 71 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
72 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
73 | ||
1bfecfca | 74 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
75 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
76 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 77 | |
f32f5bd2 DJ |
78 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
79 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
80 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
81 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
82 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
83 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
84 | ||
7e426671 | 85 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
86 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
87 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
88 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
89 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
90 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
91 | |
92 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
ec8b9981 TT |
93 | #define MLX5E_REQUIRED_MTTS(wqes) \ |
94 | (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
95 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) | |
fe4c988b | 96 | |
bc77b240 | 97 | #define MLX5_UMR_ALIGN (2048) |
cbad8cdd | 98 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256) |
461017cb | 99 | |
d9a40271 | 100 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
101 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
102 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
103 | ||
f62b8bb8 | 104 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 105 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
106 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
107 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
108 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
109 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 110 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 111 | |
936896e9 AS |
112 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
113 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 114 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 115 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 116 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
117 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
118 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
119 | ||
f10b7cc7 SM |
120 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
121 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
122 | ||
b5503b99 | 123 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
b5503b99 | 124 | #define MLX5E_XDP_TX_DS_COUNT \ |
b70149dd | 125 | ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) |
b5503b99 | 126 | |
86d722ad | 127 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 128 | |
461017cb TT |
129 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
130 | { | |
131 | switch (wq_type) { | |
132 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
133 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
134 | wq_size / 2); | |
135 | default: | |
136 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
137 | wq_size / 2); | |
138 | } | |
139 | } | |
140 | ||
141 | static inline int mlx5_min_log_rq_size(int wq_type) | |
142 | { | |
143 | switch (wq_type) { | |
144 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
145 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
146 | default: | |
147 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
148 | } | |
149 | } | |
150 | ||
151 | static inline int mlx5_max_log_rq_size(int wq_type) | |
152 | { | |
153 | switch (wq_type) { | |
154 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
155 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
156 | default: | |
157 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
158 | } | |
159 | } | |
160 | ||
48935bbb SM |
161 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
162 | { | |
163 | return is_kdump_kernel() ? | |
164 | MLX5E_MIN_NUM_CHANNELS : | |
165 | min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
166 | MLX5E_MAX_NUM_CHANNELS); | |
167 | } | |
168 | ||
2f48af12 TT |
169 | struct mlx5e_tx_wqe { |
170 | struct mlx5_wqe_ctrl_seg ctrl; | |
171 | struct mlx5_wqe_eth_seg eth; | |
172 | }; | |
173 | ||
174 | struct mlx5e_rx_wqe { | |
175 | struct mlx5_wqe_srq_next_seg next; | |
176 | struct mlx5_wqe_data_seg data; | |
177 | }; | |
86d722ad | 178 | |
bc77b240 TT |
179 | struct mlx5e_umr_wqe { |
180 | struct mlx5_wqe_ctrl_seg ctrl; | |
181 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
182 | struct mlx5_mkey_seg mkc; | |
183 | struct mlx5_wqe_data_seg data; | |
184 | }; | |
185 | ||
d605d668 KH |
186 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
187 | ||
4e59e288 | 188 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 189 | "rx_cqe_moder", |
9bcc8606 | 190 | "rx_cqe_compress", |
4e59e288 GP |
191 | }; |
192 | ||
193 | enum mlx5e_priv_flag { | |
9908aa29 | 194 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
9bcc8606 | 195 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1), |
4e59e288 GP |
196 | }; |
197 | ||
6a9764ef | 198 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
199 | do { \ |
200 | if (enable) \ | |
6a9764ef | 201 | (params)->pflags |= (pflag); \ |
59ece1c9 | 202 | else \ |
6a9764ef | 203 | (params)->pflags &= ~(pflag); \ |
4e59e288 GP |
204 | } while (0) |
205 | ||
6a9764ef | 206 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag))) |
59ece1c9 | 207 | |
08fb1dac SM |
208 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
209 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
210 | #endif |
211 | ||
9908aa29 TT |
212 | struct mlx5e_cq_moder { |
213 | u16 usec; | |
214 | u16 pkts; | |
215 | }; | |
216 | ||
f62b8bb8 AV |
217 | struct mlx5e_params { |
218 | u8 log_sq_size; | |
461017cb | 219 | u8 rq_wq_type; |
bce2b2bf | 220 | u16 rq_headroom; |
d9d9f156 TT |
221 | u8 mpwqe_log_stride_sz; |
222 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
223 | u8 log_rq_size; |
224 | u16 num_channels; | |
f62b8bb8 | 225 | u8 num_tc; |
9908aa29 | 226 | u8 rx_cq_period_mode; |
9bcc8606 | 227 | bool rx_cqe_compress_def; |
9908aa29 TT |
228 | struct mlx5e_cq_moder rx_cq_moderation; |
229 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 AV |
230 | bool lro_en; |
231 | u32 lro_wqe_sz; | |
58d52291 | 232 | u16 tx_max_inline; |
cff92d7c | 233 | u8 tx_min_inline_mode; |
2d75b2bc AS |
234 | u8 rss_hfunc; |
235 | u8 toeplitz_hash_key[40]; | |
236 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 237 | bool vlan_strip_disable; |
102722fc | 238 | bool scatter_fcs_en; |
cb3c7fd4 | 239 | bool rx_am_enabled; |
2b029556 | 240 | u32 lro_timeout; |
59ece1c9 | 241 | u32 pflags; |
6a9764ef | 242 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
243 | }; |
244 | ||
3a6a931d HN |
245 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
246 | struct mlx5e_cee_config { | |
247 | /* bw pct for priority group */ | |
248 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
249 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
250 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
251 | bool pfc_enable; | |
252 | }; | |
253 | ||
254 | enum { | |
255 | MLX5_DCB_CHG_RESET, | |
256 | MLX5_DCB_NO_CHG, | |
257 | MLX5_DCB_CHG_NO_RESET, | |
258 | }; | |
259 | ||
260 | struct mlx5e_dcbx { | |
e207b7e9 | 261 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 262 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
820c2c5e HN |
263 | |
264 | /* The only setting that cannot be read from FW */ | |
265 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
3a6a931d HN |
266 | }; |
267 | #endif | |
268 | ||
4272f9b8 EE |
269 | #define MAX_PIN_NUM 8 |
270 | struct mlx5e_pps { | |
271 | u8 pin_caps[MAX_PIN_NUM]; | |
272 | struct work_struct out_work; | |
273 | u64 start[MAX_PIN_NUM]; | |
cf503308 | 274 | u8 enabled; |
4272f9b8 EE |
275 | }; |
276 | ||
ef9814de EBE |
277 | struct mlx5e_tstamp { |
278 | rwlock_t lock; | |
279 | struct cyclecounter cycles; | |
280 | struct timecounter clock; | |
281 | struct hwtstamp_config hwtstamp_config; | |
282 | u32 nominal_c_mult; | |
283 | unsigned long overflow_period; | |
284 | struct delayed_work overflow_work; | |
285 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
286 | struct ptp_clock *ptp; |
287 | struct ptp_clock_info ptp_info; | |
4272f9b8 | 288 | struct mlx5e_pps pps_info; |
ef9814de EBE |
289 | }; |
290 | ||
f62b8bb8 | 291 | enum { |
c0f1147d | 292 | MLX5E_RQ_STATE_ENABLED, |
bc77b240 | 293 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 294 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
295 | }; |
296 | ||
f62b8bb8 AV |
297 | struct mlx5e_cq { |
298 | /* data path - accessed per cqe */ | |
299 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
300 | |
301 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 302 | u16 event_ctr; |
f62b8bb8 AV |
303 | struct napi_struct *napi; |
304 | struct mlx5_core_cq mcq; | |
305 | struct mlx5e_channel *channel; | |
306 | ||
7219ab34 TT |
307 | /* cqe decompression */ |
308 | struct mlx5_cqe64 title; | |
309 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
310 | u8 mini_arr_idx; | |
311 | u16 decmprs_left; | |
312 | u16 decmprs_wqe_counter; | |
313 | ||
f62b8bb8 | 314 | /* control */ |
a43b25da | 315 | struct mlx5_core_dev *mdev; |
1c1b5228 | 316 | struct mlx5_frag_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
317 | } ____cacheline_aligned_in_smp; |
318 | ||
eba2db2b | 319 | struct mlx5e_tx_wqe_info { |
77bdf895 | 320 | struct sk_buff *skb; |
eba2db2b SM |
321 | u32 num_bytes; |
322 | u8 num_wqebbs; | |
323 | u8 num_dma; | |
324 | }; | |
325 | ||
326 | enum mlx5e_dma_map_type { | |
327 | MLX5E_DMA_MAP_SINGLE, | |
328 | MLX5E_DMA_MAP_PAGE | |
329 | }; | |
330 | ||
331 | struct mlx5e_sq_dma { | |
332 | dma_addr_t addr; | |
333 | u32 size; | |
334 | enum mlx5e_dma_map_type type; | |
335 | }; | |
336 | ||
337 | enum { | |
338 | MLX5E_SQ_STATE_ENABLED, | |
2ac9cfe7 | 339 | MLX5E_SQ_STATE_IPSEC, |
eba2db2b SM |
340 | }; |
341 | ||
342 | struct mlx5e_sq_wqe_info { | |
343 | u8 opcode; | |
344 | u8 num_wqebbs; | |
345 | }; | |
2f48af12 | 346 | |
31391048 | 347 | struct mlx5e_txqsq { |
eba2db2b SM |
348 | /* data path */ |
349 | ||
350 | /* dirtied @completion */ | |
351 | u16 cc; | |
352 | u32 dma_fifo_cc; | |
353 | ||
354 | /* dirtied @xmit */ | |
355 | u16 pc ____cacheline_aligned_in_smp; | |
356 | u32 dma_fifo_pc; | |
357 | struct mlx5e_sq_stats stats; | |
358 | ||
359 | struct mlx5e_cq cq; | |
360 | ||
31391048 SM |
361 | /* write@xmit, read@completion */ |
362 | struct { | |
31391048 SM |
363 | struct mlx5e_sq_dma *dma_fifo; |
364 | struct mlx5e_tx_wqe_info *wqe_info; | |
eba2db2b SM |
365 | } db; |
366 | ||
367 | /* read only */ | |
368 | struct mlx5_wq_cyc wq; | |
369 | u32 dma_fifo_mask; | |
370 | void __iomem *uar_map; | |
371 | struct netdev_queue *txq; | |
372 | u32 sqn; | |
373 | u16 max_inline; | |
374 | u8 min_inline_mode; | |
375 | u16 edge; | |
376 | struct device *pdev; | |
377 | struct mlx5e_tstamp *tstamp; | |
378 | __be32 mkey_be; | |
379 | unsigned long state; | |
380 | ||
381 | /* control path */ | |
382 | struct mlx5_wq_ctrl wq_ctrl; | |
383 | struct mlx5e_channel *channel; | |
acc6c595 | 384 | int txq_ix; |
eba2db2b | 385 | u32 rate_limit; |
31391048 SM |
386 | } ____cacheline_aligned_in_smp; |
387 | ||
388 | struct mlx5e_xdpsq { | |
389 | /* data path */ | |
390 | ||
391 | /* dirtied @rx completion */ | |
392 | u16 cc; | |
393 | u16 pc; | |
394 | ||
395 | struct mlx5e_cq cq; | |
396 | ||
397 | /* write@xmit, read@completion */ | |
398 | struct { | |
399 | struct mlx5e_dma_info *di; | |
400 | bool doorbell; | |
401 | } db; | |
402 | ||
403 | /* read only */ | |
404 | struct mlx5_wq_cyc wq; | |
405 | void __iomem *uar_map; | |
406 | u32 sqn; | |
407 | struct device *pdev; | |
408 | __be32 mkey_be; | |
409 | u8 min_inline_mode; | |
410 | unsigned long state; | |
411 | ||
412 | /* control path */ | |
413 | struct mlx5_wq_ctrl wq_ctrl; | |
414 | struct mlx5e_channel *channel; | |
415 | } ____cacheline_aligned_in_smp; | |
416 | ||
417 | struct mlx5e_icosq { | |
418 | /* data path */ | |
419 | ||
420 | /* dirtied @completion */ | |
421 | u16 cc; | |
422 | ||
423 | /* dirtied @xmit */ | |
424 | u16 pc ____cacheline_aligned_in_smp; | |
425 | u32 dma_fifo_pc; | |
426 | u16 prev_cc; | |
427 | ||
428 | struct mlx5e_cq cq; | |
429 | ||
430 | /* write@xmit, read@completion */ | |
431 | struct { | |
432 | struct mlx5e_sq_wqe_info *ico_wqe; | |
433 | } db; | |
434 | ||
435 | /* read only */ | |
436 | struct mlx5_wq_cyc wq; | |
437 | void __iomem *uar_map; | |
438 | u32 sqn; | |
439 | u16 edge; | |
440 | struct device *pdev; | |
441 | __be32 mkey_be; | |
442 | unsigned long state; | |
443 | ||
444 | /* control path */ | |
445 | struct mlx5_wq_ctrl wq_ctrl; | |
446 | struct mlx5e_channel *channel; | |
eba2db2b SM |
447 | } ____cacheline_aligned_in_smp; |
448 | ||
864b2d71 SM |
449 | static inline bool |
450 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 451 | { |
864b2d71 | 452 | return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc)); |
eba2db2b | 453 | } |
6cd392a0 | 454 | |
461017cb TT |
455 | struct mlx5e_dma_info { |
456 | struct page *page; | |
457 | dma_addr_t addr; | |
458 | }; | |
459 | ||
accd5883 TT |
460 | struct mlx5e_wqe_frag_info { |
461 | struct mlx5e_dma_info di; | |
462 | u32 offset; | |
463 | }; | |
464 | ||
eba2db2b SM |
465 | struct mlx5e_umr_dma_info { |
466 | __be64 *mtt; | |
467 | dma_addr_t mtt_addr; | |
468 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; | |
469 | struct mlx5e_umr_wqe wqe; | |
470 | }; | |
471 | ||
472 | struct mlx5e_mpw_info { | |
473 | struct mlx5e_umr_dma_info umr; | |
474 | u16 consumed_strides; | |
475 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
476 | }; | |
477 | ||
cb3c7fd4 GR |
478 | struct mlx5e_rx_am_stats { |
479 | int ppms; /* packets per msec */ | |
c3164d2f | 480 | int bpms; /* bytes per msec */ |
cb3c7fd4 GR |
481 | int epms; /* events per msec */ |
482 | }; | |
483 | ||
484 | struct mlx5e_rx_am_sample { | |
53acd76c TG |
485 | ktime_t time; |
486 | u32 pkt_ctr; | |
487 | u32 byte_ctr; | |
488 | u16 event_ctr; | |
cb3c7fd4 GR |
489 | }; |
490 | ||
491 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
492 | u8 state; | |
493 | struct mlx5e_rx_am_stats prev_stats; | |
494 | struct mlx5e_rx_am_sample start_sample; | |
495 | struct work_struct work; | |
496 | u8 profile_ix; | |
497 | u8 mode; | |
498 | u8 tune_state; | |
499 | u8 steps_right; | |
500 | u8 steps_left; | |
501 | u8 tired; | |
502 | }; | |
503 | ||
4415a031 TT |
504 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
505 | * or a MPWQE (for striding rq). | |
506 | */ | |
507 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
508 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
509 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
510 | struct mlx5e_page_cache { | |
511 | u32 head; | |
512 | u32 tail; | |
513 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
514 | }; | |
515 | ||
eba2db2b SM |
516 | struct mlx5e_rq; |
517 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
518 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16); | |
519 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); | |
520 | ||
f62b8bb8 AV |
521 | struct mlx5e_rq { |
522 | /* data path */ | |
523 | struct mlx5_wq_ll wq; | |
1bfecfca | 524 | |
21c59685 | 525 | union { |
accd5883 TT |
526 | struct { |
527 | struct mlx5e_wqe_frag_info *frag_info; | |
528 | u32 frag_sz; /* max possible skb frag_sz */ | |
529 | bool page_reuse; | |
530 | bool xdp_xmit; | |
531 | } wqe; | |
21c59685 SM |
532 | struct { |
533 | struct mlx5e_mpw_info *info; | |
534 | void *mtt_no_align; | |
21c59685 SM |
535 | } mpwqe; |
536 | }; | |
1bfecfca SM |
537 | struct { |
538 | u8 page_order; | |
539 | u32 wqe_sz; /* wqe data buffer size */ | |
b5503b99 | 540 | u8 map_dir; /* dma map direction */ |
1bfecfca | 541 | } buff; |
bc77b240 | 542 | __be32 mkey_be; |
f62b8bb8 AV |
543 | |
544 | struct device *pdev; | |
545 | struct net_device *netdev; | |
ef9814de | 546 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
547 | struct mlx5e_rq_stats stats; |
548 | struct mlx5e_cq cq; | |
4415a031 TT |
549 | struct mlx5e_page_cache page_cache; |
550 | ||
2f48af12 TT |
551 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
552 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 553 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
554 | |
555 | unsigned long state; | |
556 | int ix; | |
d8bec2b2 | 557 | u16 rx_headroom; |
f62b8bb8 | 558 | |
cb3c7fd4 | 559 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
31871f87 SM |
560 | |
561 | /* XDP */ | |
86994156 | 562 | struct bpf_prog *xdp_prog; |
31391048 | 563 | struct mlx5e_xdpsq xdpsq; |
cb3c7fd4 | 564 | |
f62b8bb8 AV |
565 | /* control */ |
566 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 567 | u8 wq_type; |
d9d9f156 TT |
568 | u32 mpwqe_stride_sz; |
569 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
570 | u32 rqn; |
571 | struct mlx5e_channel *channel; | |
a43b25da | 572 | struct mlx5_core_dev *mdev; |
ec8b9981 | 573 | struct mlx5_core_mkey umr_mkey; |
f62b8bb8 AV |
574 | } ____cacheline_aligned_in_smp; |
575 | ||
f62b8bb8 AV |
576 | enum channel_flags { |
577 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
578 | }; | |
579 | ||
580 | struct mlx5e_channel { | |
581 | /* data path */ | |
582 | struct mlx5e_rq rq; | |
31391048 SM |
583 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
584 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 585 | bool xdp; |
f62b8bb8 AV |
586 | struct napi_struct napi; |
587 | struct device *pdev; | |
588 | struct net_device *netdev; | |
589 | __be32 mkey_be; | |
590 | u8 num_tc; | |
591 | unsigned long flags; | |
592 | ||
593 | /* control */ | |
594 | struct mlx5e_priv *priv; | |
a43b25da SM |
595 | struct mlx5_core_dev *mdev; |
596 | struct mlx5e_tstamp *tstamp; | |
f62b8bb8 AV |
597 | int ix; |
598 | int cpu; | |
599 | }; | |
600 | ||
ff9c852f SM |
601 | struct mlx5e_channels { |
602 | struct mlx5e_channel **c; | |
603 | unsigned int num; | |
6a9764ef | 604 | struct mlx5e_params params; |
ff9c852f SM |
605 | }; |
606 | ||
f62b8bb8 | 607 | enum mlx5e_traffic_types { |
5a6f8aef AS |
608 | MLX5E_TT_IPV4_TCP, |
609 | MLX5E_TT_IPV6_TCP, | |
610 | MLX5E_TT_IPV4_UDP, | |
611 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
612 | MLX5E_TT_IPV4_IPSEC_AH, |
613 | MLX5E_TT_IPV6_IPSEC_AH, | |
614 | MLX5E_TT_IPV4_IPSEC_ESP, | |
615 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
616 | MLX5E_TT_IPV4, |
617 | MLX5E_TT_IPV6, | |
618 | MLX5E_TT_ANY, | |
619 | MLX5E_NUM_TT, | |
1da36696 | 620 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
621 | }; |
622 | ||
acff797c | 623 | enum { |
e0f46eb9 | 624 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
625 | MLX5E_STATE_OPENED, |
626 | MLX5E_STATE_DESTROYING, | |
627 | }; | |
628 | ||
629 | struct mlx5e_vxlan_db { | |
630 | spinlock_t lock; /* protect vxlan table */ | |
631 | struct radix_tree_root tree; | |
632 | }; | |
633 | ||
33cfaaa8 | 634 | struct mlx5e_l2_rule { |
f62b8bb8 | 635 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 636 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
637 | }; |
638 | ||
acff797c MG |
639 | struct mlx5e_flow_table { |
640 | int num_groups; | |
641 | struct mlx5_flow_table *t; | |
642 | struct mlx5_flow_group **g; | |
643 | }; | |
644 | ||
33cfaaa8 | 645 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 646 | |
acff797c MG |
647 | struct mlx5e_tc_table { |
648 | struct mlx5_flow_table *t; | |
649 | ||
650 | struct rhashtable_params ht_params; | |
651 | struct rhashtable ht; | |
11c9c548 OG |
652 | |
653 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); | |
f62b8bb8 AV |
654 | }; |
655 | ||
acff797c MG |
656 | struct mlx5e_vlan_table { |
657 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 658 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
74491de9 MB |
659 | struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID]; |
660 | struct mlx5_flow_handle *untagged_rule; | |
8a271746 MHY |
661 | struct mlx5_flow_handle *any_cvlan_rule; |
662 | struct mlx5_flow_handle *any_svlan_rule; | |
663 | bool filter_disabled; | |
f62b8bb8 AV |
664 | }; |
665 | ||
33cfaaa8 MG |
666 | struct mlx5e_l2_table { |
667 | struct mlx5e_flow_table ft; | |
668 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
669 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
670 | struct mlx5e_l2_rule broadcast; | |
671 | struct mlx5e_l2_rule allmulti; | |
672 | struct mlx5e_l2_rule promisc; | |
673 | bool broadcast_enabled; | |
674 | bool allmulti_enabled; | |
675 | bool promisc_enabled; | |
676 | }; | |
677 | ||
678 | /* L3/L4 traffic type classifier */ | |
679 | struct mlx5e_ttc_table { | |
680 | struct mlx5e_flow_table ft; | |
74491de9 | 681 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
33cfaaa8 MG |
682 | }; |
683 | ||
18c908e4 MG |
684 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
685 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
686 | struct arfs_table { |
687 | struct mlx5e_flow_table ft; | |
74491de9 | 688 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 689 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
690 | }; |
691 | ||
692 | enum arfs_type { | |
693 | ARFS_IPV4_TCP, | |
694 | ARFS_IPV6_TCP, | |
695 | ARFS_IPV4_UDP, | |
696 | ARFS_IPV6_UDP, | |
697 | ARFS_NUM_TYPES, | |
698 | }; | |
699 | ||
700 | struct mlx5e_arfs_tables { | |
701 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
702 | /* Protect aRFS rules list */ |
703 | spinlock_t arfs_lock; | |
704 | struct list_head rules; | |
705 | int last_filter_id; | |
706 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
707 | }; |
708 | ||
709 | /* NIC prio FTS */ | |
710 | enum { | |
711 | MLX5E_VLAN_FT_LEVEL = 0, | |
712 | MLX5E_L2_FT_LEVEL, | |
713 | MLX5E_TTC_FT_LEVEL, | |
714 | MLX5E_ARFS_FT_LEVEL | |
715 | }; | |
716 | ||
6dc6071c MG |
717 | struct mlx5e_ethtool_table { |
718 | struct mlx5_flow_table *ft; | |
719 | int num_rules; | |
720 | }; | |
721 | ||
1174fce8 | 722 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
723 | #define ETHTOOL_NUM_L2_FTS 4 |
724 | ||
725 | struct mlx5e_ethtool_steering { | |
1174fce8 | 726 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
727 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
728 | struct list_head rules; | |
729 | int tot_num_rules; | |
730 | }; | |
731 | ||
acff797c MG |
732 | struct mlx5e_flow_steering { |
733 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 734 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
735 | struct mlx5e_tc_table tc; |
736 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
737 | struct mlx5e_l2_table l2; |
738 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 739 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
740 | }; |
741 | ||
398f3351 | 742 | struct mlx5e_rqt { |
1da36696 | 743 | u32 rqtn; |
398f3351 HHZ |
744 | bool enabled; |
745 | }; | |
746 | ||
747 | struct mlx5e_tir { | |
748 | u32 tirn; | |
749 | struct mlx5e_rqt rqt; | |
750 | struct list_head list; | |
1da36696 TT |
751 | }; |
752 | ||
acff797c MG |
753 | enum { |
754 | MLX5E_TC_PRIO = 0, | |
755 | MLX5E_NIC_PRIO | |
756 | }; | |
757 | ||
f62b8bb8 AV |
758 | struct mlx5e_priv { |
759 | /* priv data path fields - start */ | |
acc6c595 SM |
760 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
761 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
f62b8bb8 AV |
762 | /* priv data path fields - end */ |
763 | ||
764 | unsigned long state; | |
765 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 766 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 767 | |
ff9c852f | 768 | struct mlx5e_channels channels; |
f62b8bb8 | 769 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 770 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
771 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
772 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 773 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
c139dbfd | 774 | int hard_mtu; |
f62b8bb8 | 775 | |
acff797c | 776 | struct mlx5e_flow_steering fs; |
b3f63c3d | 777 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 | 778 | |
7bb29755 | 779 | struct workqueue_struct *wq; |
f62b8bb8 AV |
780 | struct work_struct update_carrier_work; |
781 | struct work_struct set_rx_mode_work; | |
3947ca18 | 782 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
783 | struct delayed_work update_stats_work; |
784 | ||
785 | struct mlx5_core_dev *mdev; | |
786 | struct net_device *netdev; | |
787 | struct mlx5e_stats stats; | |
ef9814de | 788 | struct mlx5e_tstamp tstamp; |
593cf338 | 789 | u16 q_counter; |
3a6a931d HN |
790 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
791 | struct mlx5e_dcbx dcbx; | |
792 | #endif | |
793 | ||
6bfd390b | 794 | const struct mlx5e_profile *profile; |
127ea380 | 795 | void *ppriv; |
547eede0 IT |
796 | #ifdef CONFIG_MLX5_EN_IPSEC |
797 | struct mlx5e_ipsec *ipsec; | |
798 | #endif | |
f62b8bb8 AV |
799 | }; |
800 | ||
a43b25da SM |
801 | struct mlx5e_profile { |
802 | void (*init)(struct mlx5_core_dev *mdev, | |
803 | struct net_device *netdev, | |
804 | const struct mlx5e_profile *profile, void *ppriv); | |
805 | void (*cleanup)(struct mlx5e_priv *priv); | |
806 | int (*init_rx)(struct mlx5e_priv *priv); | |
807 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
808 | int (*init_tx)(struct mlx5e_priv *priv); | |
809 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
810 | void (*enable)(struct mlx5e_priv *priv); | |
811 | void (*disable)(struct mlx5e_priv *priv); | |
812 | void (*update_stats)(struct mlx5e_priv *priv); | |
7ca42c80 | 813 | void (*update_carrier)(struct mlx5e_priv *priv); |
a43b25da | 814 | int (*max_nch)(struct mlx5_core_dev *mdev); |
20fd0c19 SM |
815 | struct { |
816 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
817 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
818 | } rx_handlers; | |
a43b25da SM |
819 | int max_tc; |
820 | }; | |
821 | ||
665bc539 GP |
822 | void mlx5e_build_ptys2ethtool_map(void); |
823 | ||
f62b8bb8 AV |
824 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
825 | void *accel_priv, select_queue_fallback_t fallback); | |
826 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
827 | |
828 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
829 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
830 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 831 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 832 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
1c4bf940 | 833 | bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq); |
31391048 SM |
834 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
835 | void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq); | |
461017cb | 836 | |
4415a031 TT |
837 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
838 | bool recycle); | |
2f48af12 | 839 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 840 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 841 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 842 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 843 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
844 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
845 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
846 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
847 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 | 848 | |
cb3c7fd4 GR |
849 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
850 | void mlx5e_rx_am_work(struct work_struct *work); | |
851 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
852 | ||
3834a5e6 | 853 | void mlx5e_update_stats(struct mlx5e_priv *priv, bool full); |
f62b8bb8 | 854 | |
acff797c MG |
855 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
856 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 857 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 858 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
859 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
860 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
861 | u64 *buf); | |
f913a72a MG |
862 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
863 | int location); | |
864 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
865 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
866 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
867 | struct ethtool_rx_flow_spec *fs); | |
868 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
869 | int location); | |
870 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
871 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
872 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
873 | ||
ef9814de EBE |
874 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
875 | struct skb_shared_hwtstamps *hwts); | |
876 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
877 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
ee7f1220 EE |
878 | void mlx5e_pps_event_handler(struct mlx5e_priv *priv, |
879 | struct ptp_clock_event *event); | |
1170fbd8 FD |
880 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
881 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 882 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 883 | |
f62b8bb8 AV |
884 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
885 | u16 vid); | |
886 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
887 | u16 vid); | |
888 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
889 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 890 | |
a5f97fee SM |
891 | struct mlx5e_redirect_rqt_param { |
892 | bool is_rss; | |
893 | union { | |
894 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
895 | struct { | |
896 | u8 hfunc; | |
897 | struct mlx5e_channels *channels; | |
898 | } rss; /* RSS data */ | |
899 | }; | |
900 | }; | |
901 | ||
902 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
903 | struct mlx5e_redirect_rqt_param rrp); | |
6a9764ef SM |
904 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
905 | enum mlx5e_traffic_types tt, | |
906 | void *tirc); | |
2d75b2bc | 907 | |
f62b8bb8 AV |
908 | int mlx5e_open_locked(struct net_device *netdev); |
909 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
910 | |
911 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
912 | struct mlx5e_channels *chs); | |
913 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
914 | |
915 | /* Function pointer to be used to modify WH settings while | |
916 | * switching channels | |
917 | */ | |
918 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
55c2503d | 919 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
920 | struct mlx5e_channels *new_chs, |
921 | mlx5e_fp_hw_modify hw_modify); | |
603f4a45 SM |
922 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
923 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 924 | |
d8c9660d TT |
925 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
926 | u32 *indirection_rqt, int len, | |
85082dba | 927 | int num_channels); |
b797a684 | 928 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 929 | |
9908aa29 TT |
930 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
931 | u8 cq_period_mode); | |
6a9764ef SM |
932 | void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, |
933 | struct mlx5e_params *params, u8 rq_type); | |
9908aa29 | 934 | |
864b2d71 SM |
935 | static inline |
936 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 937 | { |
864b2d71 SM |
938 | u16 pi = *pc & wq->sz_m1; |
939 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
940 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
941 | ||
942 | memset(cseg, 0, sizeof(*cseg)); | |
943 | ||
944 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
945 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
946 | ||
947 | (*pc)++; | |
948 | ||
949 | return wqe; | |
950 | } | |
951 | ||
952 | static inline | |
953 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
954 | void __iomem *uar_map, | |
955 | struct mlx5_wqe_ctrl_seg *ctrl) | |
956 | { | |
957 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
958 | /* ensure wqe is visible to device before updating doorbell record */ |
959 | dma_wmb(); | |
960 | ||
864b2d71 | 961 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
962 | |
963 | /* ensure doorbell record is visible to device before ringing the | |
964 | * doorbell | |
965 | */ | |
966 | wmb(); | |
f62b8bb8 | 967 | |
864b2d71 | 968 | mlx5_write64((__be32 *)ctrl, uar_map, NULL); |
f62b8bb8 AV |
969 | } |
970 | ||
971 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
972 | { | |
973 | struct mlx5_core_cq *mcq; | |
974 | ||
975 | mcq = &cq->mcq; | |
5fe9dec0 | 976 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
977 | } |
978 | ||
7e426671 TT |
979 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
980 | { | |
ec8b9981 | 981 | return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
7e426671 TT |
982 | } |
983 | ||
f62b8bb8 | 984 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
985 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
986 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
987 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 988 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
08fb1dac SM |
989 | #endif |
990 | ||
1cabe6b0 MG |
991 | #ifndef CONFIG_RFS_ACCEL |
992 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
993 | { | |
994 | return 0; | |
995 | } | |
996 | ||
997 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
998 | |
999 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
1000 | { | |
9eb78923 | 1001 | return -EOPNOTSUPP; |
45bf454a MG |
1002 | } |
1003 | ||
1004 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
1005 | { | |
9eb78923 | 1006 | return -EOPNOTSUPP; |
45bf454a | 1007 | } |
1cabe6b0 MG |
1008 | #else |
1009 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
1010 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
1011 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
1012 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
1013 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
1014 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
1015 | #endif |
1016 | ||
58d52291 | 1017 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
1018 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
1019 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
1020 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
1021 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
1022 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1023 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 1024 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 1025 | |
bc81b9d3 | 1026 | /* common netdev helpers */ |
8f493ffd SM |
1027 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1028 | ||
1029 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv); | |
1030 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv); | |
1031 | ||
cb67b832 | 1032 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); |
8f493ffd | 1033 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1034 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); |
1035 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
8f493ffd SM |
1036 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
1037 | ||
50854114 | 1038 | int mlx5e_create_ttc_table(struct mlx5e_priv *priv); |
bc81b9d3 SM |
1039 | void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv); |
1040 | ||
5426a0b2 SM |
1041 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
1042 | u32 underlay_qpn, u32 *tisn); | |
1043 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); | |
1044 | ||
cb67b832 HHZ |
1045 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
1046 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
1047 | int mlx5e_close(struct net_device *netdev); | |
1048 | int mlx5e_open(struct net_device *netdev); | |
1049 | void mlx5e_update_stats_work(struct work_struct *work); | |
2b029556 | 1050 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); |
cb67b832 | 1051 | |
076b0936 ES |
1052 | /* ethtool helpers */ |
1053 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1054 | struct ethtool_drvinfo *drvinfo); | |
1055 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1056 | uint32_t stringset, uint8_t *data); | |
1057 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1058 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1059 | struct ethtool_stats *stats, u64 *data); | |
1060 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1061 | struct ethtool_ringparam *param); | |
1062 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1063 | struct ethtool_ringparam *param); | |
1064 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1065 | struct ethtool_channels *ch); | |
1066 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1067 | struct ethtool_channels *ch); | |
1068 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1069 | struct ethtool_coalesce *coal); | |
1070 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1071 | struct ethtool_coalesce *coal); | |
3844b07e FD |
1072 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1073 | struct ethtool_ts_info *info); | |
3ffaabec OG |
1074 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1075 | struct ethtool_flash *flash); | |
076b0936 | 1076 | |
2c3b5bee SM |
1077 | /* mlx5e generic netdev management API */ |
1078 | struct net_device* | |
1079 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
1080 | void *ppriv); | |
1081 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); | |
1082 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1083 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
8f493ffd SM |
1084 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
1085 | struct mlx5e_params *params, | |
1086 | u16 max_channels); | |
2c3b5bee | 1087 | |
1afff42c | 1088 | #endif /* __MLX5_EN_H__ */ |