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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
cb67b832 | 47 | #include <net/switchdev.h> |
f62b8bb8 | 48 | #include "wq.h" |
f62b8bb8 | 49 | #include "mlx5_core.h" |
9218b44d | 50 | #include "en_stats.h" |
f62b8bb8 | 51 | |
1cabe6b0 MG |
52 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
53 | ||
f62b8bb8 AV |
54 | #define MLX5E_MAX_NUM_TC 8 |
55 | ||
e842b100 | 56 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
57 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
58 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
59 | ||
e842b100 | 60 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
61 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
62 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
63 | ||
461017cb | 64 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
7e426671 | 65 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
66 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
67 | ||
1bfecfca SM |
68 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
69 | ||
461017cb | 70 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 | 71 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
7e426671 | 72 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
73 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
74 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
75 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
76 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
77 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
78 | |
79 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
80 | #define MLX5E_REQUIRED_MTTS(rqs, wqes)\ | |
81 | (rqs * wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
82 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) <= U16_MAX) | |
83 | ||
bc77b240 | 84 | #define MLX5_UMR_ALIGN (2048) |
461017cb TT |
85 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
86 | ||
d9a40271 | 87 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 | 88 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 89 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
90 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
91 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
92 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
93 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 94 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 95 | |
936896e9 AS |
96 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
97 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
98 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
507f0c81 | 99 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
100 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
101 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 102 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 103 | |
f10b7cc7 SM |
104 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
105 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
106 | ||
86d722ad | 107 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 108 | |
461017cb TT |
109 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
110 | { | |
111 | switch (wq_type) { | |
112 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
113 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
114 | wq_size / 2); | |
115 | default: | |
116 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
117 | wq_size / 2); | |
118 | } | |
119 | } | |
120 | ||
121 | static inline int mlx5_min_log_rq_size(int wq_type) | |
122 | { | |
123 | switch (wq_type) { | |
124 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
125 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
126 | default: | |
127 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
128 | } | |
129 | } | |
130 | ||
131 | static inline int mlx5_max_log_rq_size(int wq_type) | |
132 | { | |
133 | switch (wq_type) { | |
134 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
135 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
136 | default: | |
137 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
138 | } | |
139 | } | |
140 | ||
cff92d7c HHZ |
141 | enum { |
142 | MLX5E_INLINE_MODE_L2, | |
143 | MLX5E_INLINE_MODE_VPORT_CONTEXT, | |
144 | MLX5_INLINE_MODE_NOT_REQUIRED, | |
145 | }; | |
146 | ||
2f48af12 TT |
147 | struct mlx5e_tx_wqe { |
148 | struct mlx5_wqe_ctrl_seg ctrl; | |
149 | struct mlx5_wqe_eth_seg eth; | |
150 | }; | |
151 | ||
152 | struct mlx5e_rx_wqe { | |
153 | struct mlx5_wqe_srq_next_seg next; | |
154 | struct mlx5_wqe_data_seg data; | |
155 | }; | |
86d722ad | 156 | |
bc77b240 TT |
157 | struct mlx5e_umr_wqe { |
158 | struct mlx5_wqe_ctrl_seg ctrl; | |
159 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
160 | struct mlx5_mkey_seg mkc; | |
161 | struct mlx5_wqe_data_seg data; | |
162 | }; | |
163 | ||
4e59e288 | 164 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 165 | "rx_cqe_moder", |
4e59e288 GP |
166 | }; |
167 | ||
168 | enum mlx5e_priv_flag { | |
9908aa29 | 169 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
4e59e288 GP |
170 | }; |
171 | ||
172 | #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \ | |
173 | do { \ | |
174 | if (enable) \ | |
175 | priv->pflags |= pflag; \ | |
176 | else \ | |
177 | priv->pflags &= ~pflag; \ | |
178 | } while (0) | |
179 | ||
08fb1dac SM |
180 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
181 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
182 | #endif |
183 | ||
9908aa29 TT |
184 | struct mlx5e_cq_moder { |
185 | u16 usec; | |
186 | u16 pkts; | |
187 | }; | |
188 | ||
f62b8bb8 AV |
189 | struct mlx5e_params { |
190 | u8 log_sq_size; | |
461017cb | 191 | u8 rq_wq_type; |
d9d9f156 TT |
192 | u8 mpwqe_log_stride_sz; |
193 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
194 | u8 log_rq_size; |
195 | u16 num_channels; | |
f62b8bb8 | 196 | u8 num_tc; |
9908aa29 | 197 | u8 rx_cq_period_mode; |
7219ab34 TT |
198 | bool rx_cqe_compress_admin; |
199 | bool rx_cqe_compress; | |
9908aa29 TT |
200 | struct mlx5e_cq_moder rx_cq_moderation; |
201 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 | 202 | u16 min_rx_wqes; |
f62b8bb8 AV |
203 | bool lro_en; |
204 | u32 lro_wqe_sz; | |
58d52291 | 205 | u16 tx_max_inline; |
cff92d7c | 206 | u8 tx_min_inline_mode; |
2d75b2bc AS |
207 | u8 rss_hfunc; |
208 | u8 toeplitz_hash_key[40]; | |
209 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 210 | bool vlan_strip_disable; |
08fb1dac SM |
211 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
212 | struct ieee_ets ets; | |
213 | #endif | |
cb3c7fd4 | 214 | bool rx_am_enabled; |
f62b8bb8 AV |
215 | }; |
216 | ||
ef9814de EBE |
217 | struct mlx5e_tstamp { |
218 | rwlock_t lock; | |
219 | struct cyclecounter cycles; | |
220 | struct timecounter clock; | |
221 | struct hwtstamp_config hwtstamp_config; | |
222 | u32 nominal_c_mult; | |
223 | unsigned long overflow_period; | |
224 | struct delayed_work overflow_work; | |
225 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
226 | struct ptp_clock *ptp; |
227 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
228 | }; |
229 | ||
f62b8bb8 | 230 | enum { |
f2fde18c | 231 | MLX5E_RQ_STATE_FLUSH, |
bc77b240 | 232 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
cb3c7fd4 | 233 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
234 | }; |
235 | ||
f62b8bb8 AV |
236 | struct mlx5e_cq { |
237 | /* data path - accessed per cqe */ | |
238 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
239 | |
240 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 241 | u16 event_ctr; |
f62b8bb8 AV |
242 | struct napi_struct *napi; |
243 | struct mlx5_core_cq mcq; | |
244 | struct mlx5e_channel *channel; | |
50cfa25a | 245 | struct mlx5e_priv *priv; |
f62b8bb8 | 246 | |
7219ab34 TT |
247 | /* cqe decompression */ |
248 | struct mlx5_cqe64 title; | |
249 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
250 | u8 mini_arr_idx; | |
251 | u16 decmprs_left; | |
252 | u16 decmprs_wqe_counter; | |
253 | ||
f62b8bb8 AV |
254 | /* control */ |
255 | struct mlx5_wq_ctrl wq_ctrl; | |
256 | } ____cacheline_aligned_in_smp; | |
257 | ||
2f48af12 TT |
258 | struct mlx5e_rq; |
259 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
260 | struct mlx5_cqe64 *cqe); | |
261 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
262 | u16 ix); | |
263 | ||
6cd392a0 DJ |
264 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix); |
265 | ||
461017cb TT |
266 | struct mlx5e_dma_info { |
267 | struct page *page; | |
268 | dma_addr_t addr; | |
269 | }; | |
270 | ||
cb3c7fd4 GR |
271 | struct mlx5e_rx_am_stats { |
272 | int ppms; /* packets per msec */ | |
273 | int epms; /* events per msec */ | |
274 | }; | |
275 | ||
276 | struct mlx5e_rx_am_sample { | |
277 | ktime_t time; | |
278 | unsigned int pkt_ctr; | |
279 | u16 event_ctr; | |
280 | }; | |
281 | ||
282 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
283 | u8 state; | |
284 | struct mlx5e_rx_am_stats prev_stats; | |
285 | struct mlx5e_rx_am_sample start_sample; | |
286 | struct work_struct work; | |
287 | u8 profile_ix; | |
288 | u8 mode; | |
289 | u8 tune_state; | |
290 | u8 steps_right; | |
291 | u8 steps_left; | |
292 | u8 tired; | |
293 | }; | |
294 | ||
4415a031 TT |
295 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
296 | * or a MPWQE (for striding rq). | |
297 | */ | |
298 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
299 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
300 | #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) | |
301 | struct mlx5e_page_cache { | |
302 | u32 head; | |
303 | u32 tail; | |
304 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
305 | }; | |
306 | ||
f62b8bb8 AV |
307 | struct mlx5e_rq { |
308 | /* data path */ | |
309 | struct mlx5_wq_ll wq; | |
1bfecfca | 310 | |
21c59685 SM |
311 | union { |
312 | struct mlx5e_dma_info *dma_info; | |
313 | struct { | |
314 | struct mlx5e_mpw_info *info; | |
315 | void *mtt_no_align; | |
316 | u32 mtt_offset; | |
317 | } mpwqe; | |
318 | }; | |
1bfecfca SM |
319 | struct { |
320 | u8 page_order; | |
321 | u32 wqe_sz; /* wqe data buffer size */ | |
322 | } buff; | |
bc77b240 | 323 | __be32 mkey_be; |
f62b8bb8 AV |
324 | |
325 | struct device *pdev; | |
326 | struct net_device *netdev; | |
ef9814de | 327 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
328 | struct mlx5e_rq_stats stats; |
329 | struct mlx5e_cq cq; | |
4415a031 TT |
330 | struct mlx5e_page_cache page_cache; |
331 | ||
2f48af12 TT |
332 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
333 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 334 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
335 | |
336 | unsigned long state; | |
337 | int ix; | |
338 | ||
cb3c7fd4 | 339 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
86994156 | 340 | struct bpf_prog *xdp_prog; |
cb3c7fd4 | 341 | |
f62b8bb8 AV |
342 | /* control */ |
343 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 344 | u8 wq_type; |
d9d9f156 TT |
345 | u32 mpwqe_stride_sz; |
346 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
347 | u32 rqn; |
348 | struct mlx5e_channel *channel; | |
50cfa25a | 349 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
350 | } ____cacheline_aligned_in_smp; |
351 | ||
bc77b240 TT |
352 | struct mlx5e_umr_dma_info { |
353 | __be64 *mtt; | |
bc77b240 | 354 | dma_addr_t mtt_addr; |
7e426671 TT |
355 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
356 | struct mlx5e_umr_wqe wqe; | |
bc77b240 TT |
357 | }; |
358 | ||
359 | struct mlx5e_mpw_info { | |
7e426671 | 360 | struct mlx5e_umr_dma_info umr; |
bc77b240 TT |
361 | u16 consumed_strides; |
362 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
bc77b240 TT |
363 | }; |
364 | ||
34802a42 | 365 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
366 | u32 num_bytes; |
367 | u8 num_wqebbs; | |
368 | u8 num_dma; | |
369 | }; | |
370 | ||
d4e28cbd AS |
371 | enum mlx5e_dma_map_type { |
372 | MLX5E_DMA_MAP_SINGLE, | |
373 | MLX5E_DMA_MAP_PAGE | |
374 | }; | |
375 | ||
f62b8bb8 | 376 | struct mlx5e_sq_dma { |
d4e28cbd AS |
377 | dma_addr_t addr; |
378 | u32 size; | |
379 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
380 | }; |
381 | ||
382 | enum { | |
6e8dd6d6 | 383 | MLX5E_SQ_STATE_FLUSH, |
0ba42241 | 384 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
385 | }; |
386 | ||
d3c9bc27 TT |
387 | struct mlx5e_ico_wqe_info { |
388 | u8 opcode; | |
389 | u8 num_wqebbs; | |
390 | }; | |
391 | ||
f10b7cc7 SM |
392 | enum mlx5e_sq_type { |
393 | MLX5E_SQ_TXQ, | |
394 | MLX5E_SQ_ICO | |
395 | }; | |
396 | ||
f62b8bb8 AV |
397 | struct mlx5e_sq { |
398 | /* data path */ | |
399 | ||
400 | /* dirtied @completion */ | |
401 | u16 cc; | |
402 | u32 dma_fifo_cc; | |
403 | ||
404 | /* dirtied @xmit */ | |
405 | u16 pc ____cacheline_aligned_in_smp; | |
406 | u32 dma_fifo_pc; | |
88a85f99 AS |
407 | u16 bf_offset; |
408 | u16 prev_cc; | |
409 | u8 bf_budget; | |
f62b8bb8 AV |
410 | struct mlx5e_sq_stats stats; |
411 | ||
412 | struct mlx5e_cq cq; | |
413 | ||
f10b7cc7 SM |
414 | /* pointers to per tx element info: write@xmit, read@completion */ |
415 | union { | |
416 | struct { | |
417 | struct sk_buff **skb; | |
418 | struct mlx5e_sq_dma *dma_fifo; | |
419 | struct mlx5e_tx_wqe_info *wqe_info; | |
420 | } txq; | |
421 | struct mlx5e_ico_wqe_info *ico_wqe; | |
422 | } db; | |
f62b8bb8 AV |
423 | |
424 | /* read only */ | |
425 | struct mlx5_wq_cyc wq; | |
426 | u32 dma_fifo_mask; | |
427 | void __iomem *uar_map; | |
428 | struct netdev_queue *txq; | |
429 | u32 sqn; | |
88a85f99 | 430 | u16 bf_buf_size; |
12be4b21 | 431 | u16 max_inline; |
ae76715d | 432 | u8 min_inline_mode; |
12be4b21 | 433 | u16 edge; |
f62b8bb8 | 434 | struct device *pdev; |
ef9814de | 435 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
436 | __be32 mkey_be; |
437 | unsigned long state; | |
438 | ||
439 | /* control path */ | |
440 | struct mlx5_wq_ctrl wq_ctrl; | |
441 | struct mlx5_uar uar; | |
442 | struct mlx5e_channel *channel; | |
443 | int tc; | |
507f0c81 | 444 | u32 rate_limit; |
f10b7cc7 | 445 | u8 type; |
f62b8bb8 AV |
446 | } ____cacheline_aligned_in_smp; |
447 | ||
448 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
449 | { | |
450 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
451 | (sq->cc == sq->pc)); | |
452 | } | |
453 | ||
454 | enum channel_flags { | |
455 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
456 | }; | |
457 | ||
458 | struct mlx5e_channel { | |
459 | /* data path */ | |
460 | struct mlx5e_rq rq; | |
461 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
d3c9bc27 | 462 | struct mlx5e_sq icosq; /* internal control operations */ |
f62b8bb8 AV |
463 | struct napi_struct napi; |
464 | struct device *pdev; | |
465 | struct net_device *netdev; | |
466 | __be32 mkey_be; | |
467 | u8 num_tc; | |
468 | unsigned long flags; | |
469 | ||
470 | /* control */ | |
471 | struct mlx5e_priv *priv; | |
472 | int ix; | |
473 | int cpu; | |
474 | }; | |
475 | ||
476 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
477 | MLX5E_TT_IPV4_TCP, |
478 | MLX5E_TT_IPV6_TCP, | |
479 | MLX5E_TT_IPV4_UDP, | |
480 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
481 | MLX5E_TT_IPV4_IPSEC_AH, |
482 | MLX5E_TT_IPV6_IPSEC_AH, | |
483 | MLX5E_TT_IPV4_IPSEC_ESP, | |
484 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
485 | MLX5E_TT_IPV4, |
486 | MLX5E_TT_IPV6, | |
487 | MLX5E_TT_ANY, | |
488 | MLX5E_NUM_TT, | |
1da36696 | 489 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
490 | }; |
491 | ||
acff797c | 492 | enum { |
e0f46eb9 | 493 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
494 | MLX5E_STATE_OPENED, |
495 | MLX5E_STATE_DESTROYING, | |
496 | }; | |
497 | ||
498 | struct mlx5e_vxlan_db { | |
499 | spinlock_t lock; /* protect vxlan table */ | |
500 | struct radix_tree_root tree; | |
501 | }; | |
502 | ||
33cfaaa8 | 503 | struct mlx5e_l2_rule { |
f62b8bb8 | 504 | u8 addr[ETH_ALEN + 2]; |
33cfaaa8 | 505 | struct mlx5_flow_rule *rule; |
f62b8bb8 AV |
506 | }; |
507 | ||
acff797c MG |
508 | struct mlx5e_flow_table { |
509 | int num_groups; | |
510 | struct mlx5_flow_table *t; | |
511 | struct mlx5_flow_group **g; | |
512 | }; | |
513 | ||
33cfaaa8 | 514 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 515 | |
acff797c MG |
516 | struct mlx5e_tc_table { |
517 | struct mlx5_flow_table *t; | |
518 | ||
519 | struct rhashtable_params ht_params; | |
520 | struct rhashtable ht; | |
f62b8bb8 AV |
521 | }; |
522 | ||
acff797c MG |
523 | struct mlx5e_vlan_table { |
524 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 525 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
526 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
527 | struct mlx5_flow_rule *untagged_rule; | |
528 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
529 | bool filter_disabled; |
530 | }; | |
531 | ||
33cfaaa8 MG |
532 | struct mlx5e_l2_table { |
533 | struct mlx5e_flow_table ft; | |
534 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
535 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
536 | struct mlx5e_l2_rule broadcast; | |
537 | struct mlx5e_l2_rule allmulti; | |
538 | struct mlx5e_l2_rule promisc; | |
539 | bool broadcast_enabled; | |
540 | bool allmulti_enabled; | |
541 | bool promisc_enabled; | |
542 | }; | |
543 | ||
544 | /* L3/L4 traffic type classifier */ | |
545 | struct mlx5e_ttc_table { | |
546 | struct mlx5e_flow_table ft; | |
547 | struct mlx5_flow_rule *rules[MLX5E_NUM_TT]; | |
548 | }; | |
549 | ||
18c908e4 MG |
550 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
551 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
552 | struct arfs_table { |
553 | struct mlx5e_flow_table ft; | |
554 | struct mlx5_flow_rule *default_rule; | |
18c908e4 | 555 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
556 | }; |
557 | ||
558 | enum arfs_type { | |
559 | ARFS_IPV4_TCP, | |
560 | ARFS_IPV6_TCP, | |
561 | ARFS_IPV4_UDP, | |
562 | ARFS_IPV6_UDP, | |
563 | ARFS_NUM_TYPES, | |
564 | }; | |
565 | ||
566 | struct mlx5e_arfs_tables { | |
567 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
568 | /* Protect aRFS rules list */ |
569 | spinlock_t arfs_lock; | |
570 | struct list_head rules; | |
571 | int last_filter_id; | |
572 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
573 | }; |
574 | ||
575 | /* NIC prio FTS */ | |
576 | enum { | |
577 | MLX5E_VLAN_FT_LEVEL = 0, | |
578 | MLX5E_L2_FT_LEVEL, | |
579 | MLX5E_TTC_FT_LEVEL, | |
580 | MLX5E_ARFS_FT_LEVEL | |
581 | }; | |
582 | ||
6dc6071c MG |
583 | struct mlx5e_ethtool_table { |
584 | struct mlx5_flow_table *ft; | |
585 | int num_rules; | |
586 | }; | |
587 | ||
1174fce8 | 588 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
589 | #define ETHTOOL_NUM_L2_FTS 4 |
590 | ||
591 | struct mlx5e_ethtool_steering { | |
1174fce8 | 592 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
593 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
594 | struct list_head rules; | |
595 | int tot_num_rules; | |
596 | }; | |
597 | ||
acff797c MG |
598 | struct mlx5e_flow_steering { |
599 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 600 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
601 | struct mlx5e_tc_table tc; |
602 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
603 | struct mlx5e_l2_table l2; |
604 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 605 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
606 | }; |
607 | ||
398f3351 | 608 | struct mlx5e_rqt { |
1da36696 | 609 | u32 rqtn; |
398f3351 HHZ |
610 | bool enabled; |
611 | }; | |
612 | ||
613 | struct mlx5e_tir { | |
614 | u32 tirn; | |
615 | struct mlx5e_rqt rqt; | |
616 | struct list_head list; | |
1da36696 TT |
617 | }; |
618 | ||
acff797c MG |
619 | enum { |
620 | MLX5E_TC_PRIO = 0, | |
621 | MLX5E_NIC_PRIO | |
622 | }; | |
623 | ||
6bfd390b HHZ |
624 | struct mlx5e_profile { |
625 | void (*init)(struct mlx5_core_dev *mdev, | |
626 | struct net_device *netdev, | |
127ea380 | 627 | const struct mlx5e_profile *profile, void *ppriv); |
6bfd390b HHZ |
628 | void (*cleanup)(struct mlx5e_priv *priv); |
629 | int (*init_rx)(struct mlx5e_priv *priv); | |
630 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
631 | int (*init_tx)(struct mlx5e_priv *priv); | |
632 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
633 | void (*enable)(struct mlx5e_priv *priv); | |
634 | void (*disable)(struct mlx5e_priv *priv); | |
635 | void (*update_stats)(struct mlx5e_priv *priv); | |
636 | int (*max_nch)(struct mlx5_core_dev *mdev); | |
637 | int max_tc; | |
638 | }; | |
639 | ||
f62b8bb8 AV |
640 | struct mlx5e_priv { |
641 | /* priv data path fields - start */ | |
03289b88 | 642 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 643 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
86994156 | 644 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
645 | /* priv data path fields - end */ |
646 | ||
647 | unsigned long state; | |
648 | struct mutex state_lock; /* Protects Interface state */ | |
bc77b240 | 649 | struct mlx5_core_mkey umr_mkey; |
50cfa25a | 650 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
651 | |
652 | struct mlx5e_channel **channel; | |
653 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
398f3351 | 654 | struct mlx5e_rqt indir_rqt; |
724b2aa1 HHZ |
655 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
656 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
507f0c81 | 657 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 658 | |
acff797c | 659 | struct mlx5e_flow_steering fs; |
b3f63c3d | 660 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
661 | |
662 | struct mlx5e_params params; | |
7bb29755 | 663 | struct workqueue_struct *wq; |
f62b8bb8 AV |
664 | struct work_struct update_carrier_work; |
665 | struct work_struct set_rx_mode_work; | |
3947ca18 | 666 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
667 | struct delayed_work update_stats_work; |
668 | ||
4e59e288 | 669 | u32 pflags; |
f62b8bb8 AV |
670 | struct mlx5_core_dev *mdev; |
671 | struct net_device *netdev; | |
672 | struct mlx5e_stats stats; | |
ef9814de | 673 | struct mlx5e_tstamp tstamp; |
593cf338 | 674 | u16 q_counter; |
6bfd390b | 675 | const struct mlx5e_profile *profile; |
127ea380 | 676 | void *ppriv; |
f62b8bb8 AV |
677 | }; |
678 | ||
665bc539 GP |
679 | void mlx5e_build_ptys2ethtool_map(void); |
680 | ||
12be4b21 | 681 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
682 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
683 | void *accel_priv, select_queue_fallback_t fallback); | |
684 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
685 | |
686 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
687 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
688 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 689 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 690 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
29429f33 | 691 | void mlx5e_free_tx_descs(struct mlx5e_sq *sq); |
461017cb | 692 | |
4415a031 TT |
693 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
694 | bool recycle); | |
2f48af12 | 695 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 696 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 697 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 698 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
7e426671 | 699 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
700 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
701 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 TT |
702 | void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); |
703 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
704 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
705 | ||
cb3c7fd4 GR |
706 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
707 | void mlx5e_rx_am_work(struct work_struct *work); | |
708 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
709 | ||
f62b8bb8 AV |
710 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
711 | ||
acff797c MG |
712 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
713 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 714 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 715 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
f913a72a MG |
716 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
717 | int location); | |
718 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
719 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
720 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
721 | struct ethtool_rx_flow_spec *fs); | |
722 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
723 | int location); | |
724 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
725 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
726 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
727 | ||
ef9814de EBE |
728 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
729 | struct skb_shared_hwtstamps *hwts); | |
730 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
731 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
732 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
733 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 734 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 735 | |
f62b8bb8 AV |
736 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
737 | u16 vid); | |
738 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
739 | u16 vid); | |
740 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
741 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 742 | |
36350114 GP |
743 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
744 | ||
1da36696 | 745 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 746 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 747 | |
f62b8bb8 AV |
748 | int mlx5e_open_locked(struct net_device *netdev); |
749 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
750 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
751 | u32 *indirection_rqt, int len, | |
85082dba | 752 | int num_channels); |
b797a684 | 753 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 754 | |
9908aa29 TT |
755 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
756 | u8 cq_period_mode); | |
757 | ||
f62b8bb8 | 758 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
bc77b240 | 759 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 760 | { |
88a85f99 AS |
761 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
762 | ||
f62b8bb8 AV |
763 | /* ensure wqe is visible to device before updating doorbell record */ |
764 | dma_wmb(); | |
765 | ||
766 | *sq->wq.db = cpu_to_be32(sq->pc); | |
767 | ||
768 | /* ensure doorbell record is visible to device before ringing the | |
769 | * doorbell | |
770 | */ | |
771 | wmb(); | |
0ba42241 | 772 | if (bf_sz) |
bc77b240 | 773 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 774 | else |
bc77b240 | 775 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
776 | /* flush the write-combining mapped buffer */ |
777 | wmb(); | |
f62b8bb8 AV |
778 | |
779 | sq->bf_offset ^= sq->bf_buf_size; | |
780 | } | |
781 | ||
782 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
783 | { | |
784 | struct mlx5_core_cq *mcq; | |
785 | ||
786 | mcq = &cq->mcq; | |
787 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
788 | } | |
789 | ||
7e426671 TT |
790 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
791 | { | |
21c59685 | 792 | return rq->mpwqe.mtt_offset + |
7e426671 TT |
793 | wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
794 | } | |
795 | ||
3435ab59 AS |
796 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
797 | { | |
798 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
799 | MLX5E_MAX_NUM_CHANNELS); | |
800 | } | |
801 | ||
f62b8bb8 | 802 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
803 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
804 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
805 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
806 | #endif | |
807 | ||
1cabe6b0 MG |
808 | #ifndef CONFIG_RFS_ACCEL |
809 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
810 | { | |
811 | return 0; | |
812 | } | |
813 | ||
814 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
815 | |
816 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
817 | { | |
818 | return -ENOTSUPP; | |
819 | } | |
820 | ||
821 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
822 | { | |
823 | return -ENOTSUPP; | |
824 | } | |
1cabe6b0 MG |
825 | #else |
826 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
827 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
828 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
829 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
830 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
831 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
832 | #endif |
833 | ||
58d52291 | 834 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
835 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
836 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
837 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
838 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
839 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
840 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
724b2aa1 | 841 | int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev); |
1afff42c | 842 | |
cb67b832 HHZ |
843 | struct mlx5_eswitch_rep; |
844 | int mlx5e_vport_rep_load(struct mlx5_eswitch *esw, | |
845 | struct mlx5_eswitch_rep *rep); | |
846 | void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw, | |
847 | struct mlx5_eswitch_rep *rep); | |
848 | int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep); | |
849 | void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw, | |
850 | struct mlx5_eswitch_rep *rep); | |
851 | int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv); | |
852 | void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv); | |
853 | int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr); | |
854 | ||
855 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); | |
856 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); | |
857 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
858 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
859 | int mlx5e_create_tises(struct mlx5e_priv *priv); | |
860 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
861 | int mlx5e_close(struct net_device *netdev); | |
862 | int mlx5e_open(struct net_device *netdev); | |
863 | void mlx5e_update_stats_work(struct work_struct *work); | |
26e59d80 MHY |
864 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
865 | const struct mlx5e_profile *profile, | |
866 | void *ppriv); | |
cb67b832 | 867 | void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv); |
26e59d80 MHY |
868 | int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); |
869 | void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); | |
cb67b832 HHZ |
870 | struct rtnl_link_stats64 * |
871 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); | |
872 | ||
1afff42c | 873 | #endif /* __MLX5_EN_H__ */ |