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Merge remote-tracking branch 'regulator/fix/max77802' into regulator-linus
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
34
35static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
37{
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
40
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK		 45 "%d.%d.%04d (%.16s)",
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
47 mdev->board_id);
f62b8bb8
AV		 48 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
49 sizeof(drvinfo->bus_info));
50}
51
665bc539
GP		 52struct ptys2ethtool_config {
53 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
54 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8 55 u32 speed;
f62b8bb8
AV		 56};
57
665bc539
GP		 58static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
59
60#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
61 ({ \
62 struct ptys2ethtool_config *cfg; \
63 const unsigned int modes[] = { __VA_ARGS__ }; \
64 unsigned int i; \
65 cfg = &ptys2ethtool_table[reg_]; \
66 cfg->speed = speed_; \
67 bitmap_zero(cfg->supported, \
68 __ETHTOOL_LINK_MODE_MASK_NBITS); \
69 bitmap_zero(cfg->advertised, \
70 __ETHTOOL_LINK_MODE_MASK_NBITS); \
71 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
72 __set_bit(modes[i], cfg->supported); \
73 __set_bit(modes[i], cfg->advertised); \
74 } \
75 })
76
77void mlx5e_build_ptys2ethtool_map(void)
78{
79 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
80 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
81 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
82 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
83 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
84 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
85 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
86 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
87 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
88 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
89 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
90 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
91 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
92 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
94 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
96 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
98 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
100 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
102 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
104 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
106 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
108 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
110 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
112 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
114 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
116 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
118 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
120 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
122 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
124 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
126 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
128 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
129}
130
cf678570
GP		 131static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
132{
133 struct mlx5_core_dev *mdev = priv->mdev;
134 u8 pfc_en_tx;
135 u8 pfc_en_rx;
136 int err;
137
138 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
139
140 return err ? 0 : pfc_en_tx | pfc_en_rx;
141}
142
e989d5a5
GP		 143static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
144{
145 struct mlx5_core_dev *mdev = priv->mdev;
146 u32 rx_pause;
147 u32 tx_pause;
148 int err;
149
150 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
151
152 return err ? false : rx_pause | tx_pause;
153}
154
593cf338 155#define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
ff9c852f 156#define MLX5E_NUM_RQ_STATS(priv) (NUM_RQ_STATS * (priv)->channels.num)
9218b44d 157#define MLX5E_NUM_SQ_STATS(priv) \
6a9764ef 158 (NUM_SQ_STATS * (priv)->channels.num * (priv)->channels.params.num_tc)
ed80ec4c 159#define MLX5E_NUM_PFC_COUNTERS(priv) \
e989d5a5
GP		 160 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
161 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
593cf338 162
f62b8bb8
AV		 163static int mlx5e_get_sset_count(struct net_device *dev, int sset)
164{
165 struct mlx5e_priv *priv = netdev_priv(dev);
166
167 switch (sset) {
168 case ETH_SS_STATS:
9218b44d 169 return NUM_SW_COUNTERS +
593cf338 170 MLX5E_NUM_Q_CNTRS(priv) +
5db0a4f6 171 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
0f7f3481 172 NUM_PCIE_COUNTERS(priv) +
9218b44d 173 MLX5E_NUM_RQ_STATS(priv) +
cf678570 174 MLX5E_NUM_SQ_STATS(priv) +
bedb7c90
HN		 175 MLX5E_NUM_PFC_COUNTERS(priv) +
176 ARRAY_SIZE(mlx5e_pme_status_desc) +
177 ARRAY_SIZE(mlx5e_pme_error_desc);
178
4e59e288
GP		 179 case ETH_SS_PRIV_FLAGS:
180 return ARRAY_SIZE(mlx5e_priv_flags);
d605d668
KH		 181 case ETH_SS_TEST:
182 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 183 /* fallthrough */
184 default:
185 return -EOPNOTSUPP;
186 }
187}
188
9218b44d
GP		 189static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
190{
cf678570
GP		 191 int i, j, tc, prio, idx = 0;
192 unsigned long pfc_combined;
9218b44d
GP		 193
194 /* SW counters */
195 for (i = 0; i < NUM_SW_COUNTERS; i++)
bfe6d8d1 196 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
9218b44d
GP		 197
198 /* Q counters */
199 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
bfe6d8d1 200 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
9218b44d
GP		 201
202 /* VPORT counters */
203 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
204 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 205 vport_stats_desc[i].format);
9218b44d
GP		 206
207 /* PPORT counters */
208 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
209 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 210 pport_802_3_stats_desc[i].format);
9218b44d
GP		 211
212 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
213 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 214 pport_2863_stats_desc[i].format);
9218b44d
GP		 215
216 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
217 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 218 pport_2819_stats_desc[i].format);
9218b44d 219
5db0a4f6
GP		 220 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
221 strcpy(data + (idx++) * ETH_GSTRING_LEN,
222 pport_phy_statistical_stats_desc[i].format);
223
0f7f3481
GP		 224 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
225 strcpy(data + (idx++) * ETH_GSTRING_LEN,
226 pcie_perf_stats_desc[i].format);
227
cf678570
GP		 228 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
229 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
bfe6d8d1
GP		 230 sprintf(data + (idx++) * ETH_GSTRING_LEN,
231 pport_per_prio_traffic_stats_desc[i].format, prio);
cf678570
GP		 232 }
233
234 pfc_combined = mlx5e_query_pfc_combined(priv);
235 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
236 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
e989d5a5
GP		 237 char pfc_string[ETH_GSTRING_LEN];
238
239 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
bfe6d8d1 240 sprintf(data + (idx++) * ETH_GSTRING_LEN,
e989d5a5
GP		 241 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
242 }
243 }
244
245 if (mlx5e_query_global_pause_combined(priv)) {
246 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
247 sprintf(data + (idx++) * ETH_GSTRING_LEN,
248 pport_per_prio_pfc_stats_desc[i].format, "global");
cf678570
GP		 249 }
250 }
251
bedb7c90
HN		 252 /* port module event counters */
253 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
254 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
255
256 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
257 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
258
9218b44d
GP		 259 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
260 return;
261
262 /* per channel counters */
ff9c852f 263 for (i = 0; i < priv->channels.num; i++)
9218b44d 264 for (j = 0; j < NUM_RQ_STATS; j++)
bfe6d8d1
GP		 265 sprintf(data + (idx++) * ETH_GSTRING_LEN,
266 rq_stats_desc[j].format, i);
9218b44d 267
6a9764ef 268 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 269 for (i = 0; i < priv->channels.num; i++)
9218b44d
GP		 270 for (j = 0; j < NUM_SQ_STATS; j++)
271 sprintf(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 272 sq_stats_desc[j].format,
acc6c595 273 priv->channel_tc2txq[i][tc]);
9218b44d
GP		 274}
275
f62b8bb8
AV		 276static void mlx5e_get_strings(struct net_device *dev,
277 uint32_t stringset, uint8_t *data)
278{
f62b8bb8 279 struct mlx5e_priv *priv = netdev_priv(dev);
4e59e288 280 int i;
f62b8bb8
AV		 281
282 switch (stringset) {
283 case ETH_SS_PRIV_FLAGS:
4e59e288
GP		 284 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
285 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV		 286 break;
287
288 case ETH_SS_TEST:
d605d668
KH		 289 for (i = 0; i < mlx5e_self_test_num(priv); i++)
290 strcpy(data + i * ETH_GSTRING_LEN,
291 mlx5e_self_tests[i]);
f62b8bb8
AV		 292 break;
293
294 case ETH_SS_STATS:
9218b44d 295 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 296 break;
297 }
298}
299
300static void mlx5e_get_ethtool_stats(struct net_device *dev,
301 struct ethtool_stats *stats, u64 *data)
302{
303 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f 304 struct mlx5e_channels *channels;
bedb7c90 305 struct mlx5_priv *mlx5_priv;
cf678570
GP		 306 int i, j, tc, prio, idx = 0;
307 unsigned long pfc_combined;
f62b8bb8
AV		 308
309 if (!data)
310 return;
311
312 mutex_lock(&priv->state_lock);
313 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
314 mlx5e_update_stats(priv);
ff9c852f 315 channels = &priv->channels;
f62b8bb8
AV		 316 mutex_unlock(&priv->state_lock);
317
9218b44d
GP		 318 for (i = 0; i < NUM_SW_COUNTERS; i++)
319 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
320 sw_stats_desc, i);
f62b8bb8 321
593cf338 322 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
9218b44d
GP		 323 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
324 q_stats_desc, i);
325
326 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
327 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
328 vport_stats_desc, i);
593cf338 329
9218b44d
GP		 330 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
331 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
332 pport_802_3_stats_desc, i);
333
334 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
335 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
336 pport_2863_stats_desc, i);
337
338 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
339 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
340 pport_2819_stats_desc, i);
341
5db0a4f6
GP		 342 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
343 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
344 pport_phy_statistical_stats_desc, i);
345
0f7f3481
GP		 346 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
347 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
348 pcie_perf_stats_desc, i);
349
cf678570
GP		 350 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
351 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
352 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
353 pport_per_prio_traffic_stats_desc, i);
354 }
355
356 pfc_combined = mlx5e_query_pfc_combined(priv);
357 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
358 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
359 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
360 pport_per_prio_pfc_stats_desc, i);
361 }
362 }
363
e989d5a5
GP		 364 if (mlx5e_query_global_pause_combined(priv)) {
365 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
366 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
4e39883d 367 pport_per_prio_pfc_stats_desc, i);
e989d5a5
GP		 368 }
369 }
370
bedb7c90
HN		 371 /* port module event counters */
372 mlx5_priv = &priv->mdev->priv;
373 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
374 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
375 mlx5e_pme_status_desc, i);
376
377 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
378 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
379 mlx5e_pme_error_desc, i);
380
9218b44d
GP		 381 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
382 return;
efea389d 383
f62b8bb8 384 /* per channel counters */
ff9c852f 385 for (i = 0; i < channels->num; i++)
f62b8bb8 386 for (j = 0; j < NUM_RQ_STATS; j++)
9218b44d 387 data[idx++] =
ff9c852f 388 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
9218b44d 389 rq_stats_desc, j);
f62b8bb8 390
6a9764ef 391 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 392 for (i = 0; i < channels->num; i++)
f62b8bb8 393 for (j = 0; j < NUM_SQ_STATS; j++)
ff9c852f 394 data[idx++] = MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
9218b44d 395 sq_stats_desc, j);
f62b8bb8
AV		 396}
397
cc8e9ebf
EBE		 398static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
399 int num_wqe)
400{
401 int packets_per_wqe;
402 int stride_size;
403 int num_strides;
404 int wqe_size;
405
406 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
407 return num_wqe;
408
6a9764ef
SM		 409 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
410 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 411 wqe_size = stride_size * num_strides;
412
413 packets_per_wqe = wqe_size /
414 ALIGN(ETH_DATA_LEN, stride_size);
415 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
416}
417
418static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
419 int num_packets)
420{
421 int packets_per_wqe;
422 int stride_size;
423 int num_strides;
424 int wqe_size;
425 int num_wqes;
426
427 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
428 return num_packets;
429
6a9764ef
SM		 430 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
431 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 432 wqe_size = stride_size * num_strides;
433
434 num_packets = (1 << order_base_2(num_packets));
435
436 packets_per_wqe = wqe_size /
437 ALIGN(ETH_DATA_LEN, stride_size);
438 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
439 return 1 << (order_base_2(num_wqes));
440}
441
f62b8bb8
AV		 442static void mlx5e_get_ringparam(struct net_device *dev,
443 struct ethtool_ringparam *param)
444{
445 struct mlx5e_priv *priv = netdev_priv(dev);
6a9764ef 446 int rq_wq_type = priv->channels.params.rq_wq_type;
f62b8bb8 447
cc8e9ebf
EBE		 448 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
449 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8 450 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
cc8e9ebf 451 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
6a9764ef
SM		 452 1 << priv->channels.params.log_rq_size);
453 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 454}
455
456static int mlx5e_set_ringparam(struct net_device *dev,
457 struct ethtool_ringparam *param)
458{
459 struct mlx5e_priv *priv = netdev_priv(dev);
6a9764ef 460 int rq_wq_type = priv->channels.params.rq_wq_type;
546f18ed 461 struct mlx5e_channels new_channels = {};
cc8e9ebf
EBE		 462 u32 rx_pending_wqes;
463 u32 min_rq_size;
464 u32 max_rq_size;
f62b8bb8
AV		 465 u8 log_rq_size;
466 u8 log_sq_size;
fe4c988b 467 u32 num_mtts;
f62b8bb8
AV		 468 int err = 0;
469
470 if (param->rx_jumbo_pending) {
471 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
472 __func__);
473 return -EINVAL;
474 }
475 if (param->rx_mini_pending) {
476 netdev_info(dev, "%s: rx_mini_pending not supported\n",
477 __func__);
478 return -EINVAL;
479 }
cc8e9ebf
EBE		 480
481 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
482 1 << mlx5_min_log_rq_size(rq_wq_type));
483 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
484 1 << mlx5_max_log_rq_size(rq_wq_type));
485 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
486 param->rx_pending);
487
488 if (param->rx_pending < min_rq_size) {
f62b8bb8
AV		 489 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
490 __func__, param->rx_pending,
cc8e9ebf 491 min_rq_size);
f62b8bb8
AV		 492 return -EINVAL;
493 }
cc8e9ebf 494 if (param->rx_pending > max_rq_size) {
f62b8bb8
AV		 495 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
496 __func__, param->rx_pending,
cc8e9ebf 497 max_rq_size);
f62b8bb8
AV		 498 return -EINVAL;
499 }
fe4c988b 500
ec8b9981 501 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
6a9764ef 502 if (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
fe4c988b
SM		 503 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
504 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
505 __func__, param->rx_pending);
506 return -EINVAL;
507 }
508
f62b8bb8
AV		 509 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
510 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
511 __func__, param->tx_pending,
512 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
513 return -EINVAL;
514 }
515 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
516 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
517 __func__, param->tx_pending,
518 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
519 return -EINVAL;
520 }
521
cc8e9ebf 522 log_rq_size = order_base_2(rx_pending_wqes);
f62b8bb8 523 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 524
6a9764ef
SM		 525 if (log_rq_size == priv->channels.params.log_rq_size &&
526 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 527 return 0;
528
529 mutex_lock(&priv->state_lock);
98e81b0a 530
546f18ed
SM		 531 new_channels.params = priv->channels.params;
532 new_channels.params.log_rq_size = log_rq_size;
533 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 534
546f18ed
SM		 535 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
536 priv->channels.params = new_channels.params;
537 goto unlock;
538 }
98e81b0a 539
546f18ed
SM		 540 err = mlx5e_open_channels(priv, &new_channels);
541 if (err)
542 goto unlock;
543
2e20a151 544 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 545
546f18ed 546unlock:
f62b8bb8
AV		 547 mutex_unlock(&priv->state_lock);
548
549 return err;
550}
551
552static void mlx5e_get_channels(struct net_device *dev,
553 struct ethtool_channels *ch)
554{
555 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 556
b4e029da 557 ch->max_combined = priv->profile->max_nch(priv->mdev);
6a9764ef 558 ch->combined_count = priv->channels.params.num_channels;
f62b8bb8
AV		 559}
560
561static int mlx5e_set_channels(struct net_device *dev,
562 struct ethtool_channels *ch)
563{
564 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 565 unsigned int count = ch->combined_count;
55c2503d 566 struct mlx5e_channels new_channels = {};
45bf454a 567 bool arfs_enabled;
f62b8bb8
AV		 568 int err = 0;
569
570 if (!count) {
571 netdev_info(dev, "%s: combined_count=0 not supported\n",
572 __func__);
573 return -EINVAL;
574 }
f62b8bb8 575
6a9764ef 576 if (priv->channels.params.num_channels == count)
f62b8bb8
AV		 577 return 0;
578
579 mutex_lock(&priv->state_lock);
98e81b0a 580
55c2503d
SM		 581 new_channels.params = priv->channels.params;
582 new_channels.params.num_channels = count;
583 mlx5e_build_default_indir_rqt(priv->mdev, new_channels.params.indirection_rqt,
584 MLX5E_INDIR_RQT_SIZE, count);
585
586 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
587 priv->channels.params = new_channels.params;
588 goto out;
589 }
590
591 /* Create fresh channels with new parameters */
592 err = mlx5e_open_channels(priv, &new_channels);
593 if (err)
594 goto out;
98e81b0a 595
45bf454a
MG		 596 arfs_enabled = dev->features & NETIF_F_NTUPLE;
597 if (arfs_enabled)
598 mlx5e_arfs_disable(priv);
599
55c2503d 600 /* Switch to new channels, set new parameters and close old ones */
2e20a151 601 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
45bf454a
MG		 602
603 if (arfs_enabled) {
604 err = mlx5e_arfs_enable(priv);
605 if (err)
606 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
607 __func__, err);
608 }
98e81b0a 609
45bf454a 610out:
f62b8bb8
AV		 611 mutex_unlock(&priv->state_lock);
612
613 return err;
614}
615
616static int mlx5e_get_coalesce(struct net_device *netdev,
617 struct ethtool_coalesce *coal)
618{
619 struct mlx5e_priv *priv = netdev_priv(netdev);
620
7524a5d8 621 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 622 return -EOPNOTSUPP;
7524a5d8 623
6a9764ef
SM		 624 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
625 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
626 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
627 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
628 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_am_enabled;
f62b8bb8
AV		 629
630 return 0;
631}
632
546f18ed
SM		 633static void
634mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 635{
f62b8bb8 636 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 637 int tc;
638 int i;
639
ff9c852f
SM		 640 for (i = 0; i < priv->channels.num; ++i) {
641 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 642
643 for (tc = 0; tc < c->num_tc; tc++) {
644 mlx5_core_modify_cq_moderation(mdev,
645 &c->sq[tc].cq.mcq,
646 coal->tx_coalesce_usecs,
647 coal->tx_max_coalesced_frames);
648 }
649
650 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
651 coal->rx_coalesce_usecs,
652 coal->rx_max_coalesced_frames);
653 }
546f18ed 654}
f62b8bb8 655
546f18ed
SM		 656static int mlx5e_set_coalesce(struct net_device *netdev,
657 struct ethtool_coalesce *coal)
658{
659 struct mlx5e_priv *priv = netdev_priv(netdev);
660 struct mlx5_core_dev *mdev = priv->mdev;
661 struct mlx5e_channels new_channels = {};
662 int err = 0;
663 bool reset;
cb3c7fd4 664
546f18ed
SM		 665 if (!MLX5_CAP_GEN(mdev, cq_moderation))
666 return -EOPNOTSUPP;
667
668 mutex_lock(&priv->state_lock);
669 new_channels.params = priv->channels.params;
670
671 new_channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
672 new_channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
673 new_channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
674 new_channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
675 new_channels.params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
676
677 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
678 priv->channels.params = new_channels.params;
679 goto out;
680 }
681 /* we are opened */
682
683 reset = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_am_enabled;
684 if (!reset) {
685 mlx5e_set_priv_channels_coalesce(priv, coal);
686 priv->channels.params = new_channels.params;
687 goto out;
688 }
689
690 /* open fresh channels with new coal parameters */
691 err = mlx5e_open_channels(priv, &new_channels);
692 if (err)
693 goto out;
694
2e20a151 695 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
546f18ed
SM		 696
697out:
2fcb92fb 698 mutex_unlock(&priv->state_lock);
cb3c7fd4 699 return err;
f62b8bb8
AV		 700}
701
665bc539
GP		 702static void ptys2ethtool_supported_link(unsigned long *supported_modes,
703 u32 eth_proto_cap)
f62b8bb8 704{
7abc2110 705 unsigned long proto_cap = eth_proto_cap;
665bc539 706 int proto;
f62b8bb8 707
7abc2110 708 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 709 bitmap_or(supported_modes, supported_modes,
710 ptys2ethtool_table[proto].supported,
711 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 712}
713
665bc539
GP		 714static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
715 u32 eth_proto_cap)
f62b8bb8 716{
7abc2110 717 unsigned long proto_cap = eth_proto_cap;
665bc539 718 int proto;
f62b8bb8 719
7abc2110 720 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 721 bitmap_or(advertising_modes, advertising_modes,
722 ptys2ethtool_table[proto].advertised,
723 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 724}
725
665bc539
GP		 726static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
727 u32 eth_proto_cap)
f62b8bb8
AV		 728{
729 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
730 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
731 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
732 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
733 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
734 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
665bc539 735 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
f62b8bb8
AV		 736 }
737
738 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
739 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
740 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
741 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
742 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
665bc539 743 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
f62b8bb8 744 }
f62b8bb8
AV		 745}
746
b797a684
SM		 747int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
748{
749 u32 max_speed = 0;
750 u32 proto_cap;
751 int err;
752 int i;
753
754 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
755 if (err)
756 return err;
757
758 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
759 if (proto_cap & MLX5E_PROT_MASK(i))
760 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
761
762 *speed = max_speed;
763 return 0;
764}
765
f62b8bb8
AV		 766static void get_speed_duplex(struct net_device *netdev,
767 u32 eth_proto_oper,
665bc539 768 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 769{
770 int i;
771 u32 speed = SPEED_UNKNOWN;
772 u8 duplex = DUPLEX_UNKNOWN;
773
774 if (!netif_carrier_ok(netdev))
775 goto out;
776
777 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
778 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
779 speed = ptys2ethtool_table[i].speed;
780 duplex = DUPLEX_FULL;
781 break;
782 }
783 }
784out:
665bc539
GP		 785 link_ksettings->base.speed = speed;
786 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 787}
788
665bc539
GP		 789static void get_supported(u32 eth_proto_cap,
790 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 791{
665bc539
GP		 792 unsigned long *supported = link_ksettings->link_modes.supported;
793
794 ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
795 ptys2ethtool_supported_link(supported, eth_proto_cap);
796 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV		 797}
798
799static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP		 800 u8 rx_pause,
801 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 802{
665bc539
GP		 803 unsigned long *advertising = link_ksettings->link_modes.advertising;
804
805 ptys2ethtool_adver_link(advertising, eth_proto_cap);
e3c19503 806 if (rx_pause)
665bc539
GP		 807 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
808 if (tx_pause ^ rx_pause)
809 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 810}
811
812static u8 get_connector_port(u32 eth_proto)
813{
814 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
815 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
816 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
817 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
818 return PORT_FIBRE;
819 }
820
821 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
822 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
823 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
824 return PORT_DA;
825 }
826
827 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
828 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
829 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
830 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
831 return PORT_NONE;
832 }
833
834 return PORT_OTHER;
835}
836
665bc539
GP		 837static void get_lp_advertising(u32 eth_proto_lp,
838 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 839{
665bc539
GP		 840 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
841
842 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV		 843}
844
665bc539
GP		 845static int mlx5e_get_link_ksettings(struct net_device *netdev,
846 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 847{
848 struct mlx5e_priv *priv = netdev_priv(netdev);
849 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 850 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
b383b544
GP		 851 u32 rx_pause = 0;
852 u32 tx_pause = 0;
f62b8bb8
AV		 853 u32 eth_proto_cap;
854 u32 eth_proto_admin;
855 u32 eth_proto_lp;
856 u32 eth_proto_oper;
52244d96
GP		 857 u8 an_disable_admin;
858 u8 an_status;
f62b8bb8
AV		 859 int err;
860
a05bdefa 861 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 862 if (err) {
863 netdev_err(netdev, "%s: query port ptys failed: %d\n",
864 __func__, err);
865 goto err_query_ptys;
866 }
867
52244d96
GP		 868 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
869 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
870 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
871 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
872 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
873 an_status = MLX5_GET(ptys_reg, out, an_status);
f62b8bb8 874
b383b544
GP		 875 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
876
665bc539
GP		 877 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
878 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 879
665bc539 880 get_supported(eth_proto_cap, link_ksettings);
b383b544 881 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
665bc539 882 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 883
884 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
885
665bc539
GP		 886 link_ksettings->base.port = get_connector_port(eth_proto_oper);
887 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 888
52244d96
GP		 889 if (an_status == MLX5_AN_COMPLETE)
890 ethtool_link_ksettings_add_link_mode(link_ksettings,
891 lp_advertising, Autoneg);
892
893 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
894 AUTONEG_ENABLE;
895 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
896 Autoneg);
897 if (!an_disable_admin)
898 ethtool_link_ksettings_add_link_mode(link_ksettings,
899 advertising, Autoneg);
900
f62b8bb8
AV		 901err_query_ptys:
902 return err;
903}
904
665bc539 905static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 906{
907 u32 i, ptys_modes = 0;
908
909 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP		 910 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
911 link_modes,
912 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 913 ptys_modes |= MLX5E_PROT_MASK(i);
914 }
915
916 return ptys_modes;
917}
918
919static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
920{
921 u32 i, speed_links = 0;
922
923 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
924 if (ptys2ethtool_table[i].speed == speed)
925 speed_links |= MLX5E_PROT_MASK(i);
926 }
927
928 return speed_links;
929}
930
665bc539
GP		 931static int mlx5e_set_link_ksettings(struct net_device *netdev,
932 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 933{
934 struct mlx5e_priv *priv = netdev_priv(netdev);
935 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP		 936 u32 eth_proto_cap, eth_proto_admin;
937 bool an_changes = false;
938 u8 an_disable_admin;
939 u8 an_disable_cap;
940 bool an_disable;
f62b8bb8 941 u32 link_modes;
52244d96 942 u8 an_status;
f62b8bb8 943 u32 speed;
f62b8bb8
AV		 944 int err;
945
665bc539 946 speed = link_ksettings->base.speed;
f62b8bb8 947
665bc539
GP		 948 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
949 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
f62b8bb8
AV		 950 mlx5e_ethtool2ptys_speed_link(speed);
951
952 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
953 if (err) {
954 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
955 __func__, err);
956 goto out;
957 }
958
959 link_modes = link_modes & eth_proto_cap;
960 if (!link_modes) {
961 netdev_err(netdev, "%s: Not supported link mode(s) requested",
962 __func__);
963 err = -EINVAL;
964 goto out;
965 }
966
967 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
968 if (err) {
969 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
970 __func__, err);
971 goto out;
972 }
973
52244d96
GP		 974 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
975 &an_disable_cap, &an_disable_admin);
976
977 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
978 an_changes = ((!an_disable && an_disable_admin) ||
979 (an_disable && !an_disable_admin));
980
981 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV		 982 goto out;
983
52244d96 984 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 985 mlx5_toggle_port_link(mdev);
f62b8bb8 986
f62b8bb8
AV		 987out:
988 return err;
989}
990
2d75b2bc
AS		 991static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
992{
993 struct mlx5e_priv *priv = netdev_priv(netdev);
994
6a9764ef 995 return sizeof(priv->channels.params.toeplitz_hash_key);
2d75b2bc
AS		 996}
997
998static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
999{
1000 return MLX5E_INDIR_RQT_SIZE;
1001}
1002
2be6967c
SM		 1003static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1004 u8 *hfunc)
1005{
1006 struct mlx5e_priv *priv = netdev_priv(netdev);
1007
2d75b2bc 1008 if (indir)
6a9764ef
SM		 1009 memcpy(indir, priv->channels.params.indirection_rqt,
1010 sizeof(priv->channels.params.indirection_rqt));
2d75b2bc
AS		 1011
1012 if (key)
6a9764ef
SM		 1013 memcpy(key, priv->channels.params.toeplitz_hash_key,
1014 sizeof(priv->channels.params.toeplitz_hash_key));
2d75b2bc 1015
2be6967c 1016 if (hfunc)
6a9764ef 1017 *hfunc = priv->channels.params.rss_hfunc;
2be6967c
SM		 1018
1019 return 0;
1020}
1021
bdfc028d
TT		 1022static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
1023{
bdfc028d 1024 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
a100ff3e
GP		 1025 struct mlx5_core_dev *mdev = priv->mdev;
1026 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
1027 int tt;
bdfc028d
TT		 1028
1029 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
bdfc028d 1030
a100ff3e
GP		 1031 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1032 memset(tirc, 0, ctxlen);
6a9764ef 1033 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
a100ff3e
GP		 1034 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
1035 }
bdfc028d
TT		 1036}
1037
98e81b0a 1038static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1039 const u8 *key, const u8 hfunc)
1040{
98e81b0a 1041 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d 1042 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1043 bool hash_changed = false;
bdfc028d 1044 void *in;
2be6967c 1045
2d75b2bc
AS		 1046 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1047 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1048 (hfunc != ETH_RSS_HASH_TOP))
1049 return -EINVAL;
1050
bdfc028d
TT		 1051 in = mlx5_vzalloc(inlen);
1052 if (!in)
1053 return -ENOMEM;
1054
2be6967c
SM		 1055 mutex_lock(&priv->state_lock);
1056
1d3398fa 1057 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
6a9764ef
SM		 1058 hfunc != priv->channels.params.rss_hfunc) {
1059 priv->channels.params.rss_hfunc = hfunc;
1d3398fa
GP		 1060 hash_changed = true;
1061 }
1062
a5f97fee 1063 if (indir) {
6a9764ef
SM		 1064 memcpy(priv->channels.params.indirection_rqt, indir,
1065 sizeof(priv->channels.params.indirection_rqt));
a5f97fee
SM		 1066
1067 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1068 u32 rqtn = priv->indir_rqt.rqtn;
1069 struct mlx5e_redirect_rqt_param rrp = {
1070 .is_rss = true,
e270e966
AM		 1071 {
1072 .rss = {
1073 .hfunc = priv->channels.params.rss_hfunc,
1074 .channels = &priv->channels,
1075 },
1076 },
a5f97fee
SM		 1077 };
1078
1079 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1080 }
1081 }
1082
1d3398fa 1083 if (key) {
6a9764ef
SM		 1084 memcpy(priv->channels.params.toeplitz_hash_key, key,
1085 sizeof(priv->channels.params.toeplitz_hash_key));
1d3398fa 1086 hash_changed = hash_changed ||
6a9764ef 1087 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1088 }
2d75b2bc 1089
1d3398fa
GP		 1090 if (hash_changed)
1091 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1092
2be6967c
SM		 1093 mutex_unlock(&priv->state_lock);
1094
bdfc028d
TT		 1095 kvfree(in);
1096
1097 return 0;
2be6967c
SM		 1098}
1099
2d75b2bc
AS		 1100static int mlx5e_get_rxnfc(struct net_device *netdev,
1101 struct ethtool_rxnfc *info, u32 *rule_locs)
1102{
1103 struct mlx5e_priv *priv = netdev_priv(netdev);
1104 int err = 0;
1105
1106 switch (info->cmd) {
1107 case ETHTOOL_GRXRINGS:
6a9764ef 1108 info->data = priv->channels.params.num_channels;
2d75b2bc 1109 break;
f913a72a
MG		 1110 case ETHTOOL_GRXCLSRLCNT:
1111 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1112 break;
1113 case ETHTOOL_GRXCLSRULE:
1114 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1115 break;
1116 case ETHTOOL_GRXCLSRLALL:
1117 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1118 break;
2d75b2bc
AS		 1119 default:
1120 err = -EOPNOTSUPP;
1121 break;
1122 }
1123
1124 return err;
1125}
1126
58d52291
AS		 1127static int mlx5e_get_tunable(struct net_device *dev,
1128 const struct ethtool_tunable *tuna,
1129 void *data)
1130{
1131 const struct mlx5e_priv *priv = netdev_priv(dev);
1132 int err = 0;
1133
1134 switch (tuna->id) {
1135 case ETHTOOL_TX_COPYBREAK:
6a9764ef 1136 *(u32 *)data = priv->channels.params.tx_max_inline;
58d52291
AS		 1137 break;
1138 default:
1139 err = -EINVAL;
1140 break;
1141 }
1142
1143 return err;
1144}
1145
1146static int mlx5e_set_tunable(struct net_device *dev,
1147 const struct ethtool_tunable *tuna,
1148 const void *data)
1149{
1150 struct mlx5e_priv *priv = netdev_priv(dev);
1151 struct mlx5_core_dev *mdev = priv->mdev;
546f18ed 1152 struct mlx5e_channels new_channels = {};
58d52291 1153 int err = 0;
546f18ed
SM		 1154 u32 val;
1155
1156 mutex_lock(&priv->state_lock);
58d52291
AS		 1157
1158 switch (tuna->id) {
1159 case ETHTOOL_TX_COPYBREAK:
1160 val = *(u32 *)data;
1161 if (val > mlx5e_get_max_inline_cap(mdev)) {
1162 err = -EINVAL;
1163 break;
1164 }
1165
546f18ed
SM		 1166 new_channels.params = priv->channels.params;
1167 new_channels.params.tx_max_inline = val;
98e81b0a 1168
546f18ed
SM		 1169 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1170 priv->channels.params = new_channels.params;
1171 break;
1172 }
98e81b0a 1173
546f18ed
SM		 1174 err = mlx5e_open_channels(priv, &new_channels);
1175 if (err)
1176 break;
2e20a151 1177 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 1178
58d52291
AS		 1179 break;
1180 default:
1181 err = -EINVAL;
1182 break;
1183 }
1184
546f18ed 1185 mutex_unlock(&priv->state_lock);
58d52291
AS		 1186 return err;
1187}
1188
3c2d18ef
AS		 1189static void mlx5e_get_pauseparam(struct net_device *netdev,
1190 struct ethtool_pauseparam *pauseparam)
1191{
1192 struct mlx5e_priv *priv = netdev_priv(netdev);
1193 struct mlx5_core_dev *mdev = priv->mdev;
1194 int err;
1195
1196 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1197 &pauseparam->tx_pause);
1198 if (err) {
1199 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1200 __func__, err);
1201 }
1202}
1203
1204static int mlx5e_set_pauseparam(struct net_device *netdev,
1205 struct ethtool_pauseparam *pauseparam)
1206{
1207 struct mlx5e_priv *priv = netdev_priv(netdev);
1208 struct mlx5_core_dev *mdev = priv->mdev;
1209 int err;
1210
1211 if (pauseparam->autoneg)
1212 return -EINVAL;
1213
1214 err = mlx5_set_port_pause(mdev,
1215 pauseparam->rx_pause ? 1 : 0,
1216 pauseparam->tx_pause ? 1 : 0);
1217 if (err) {
1218 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1219 __func__, err);
1220 }
1221
1222 return err;
1223}
1224
ef9814de
EBE		 1225static int mlx5e_get_ts_info(struct net_device *dev,
1226 struct ethtool_ts_info *info)
1227{
1228 struct mlx5e_priv *priv = netdev_priv(dev);
1229 int ret;
1230
1231 ret = ethtool_op_get_ts_info(dev, info);
1232 if (ret)
1233 return ret;
1234
3d8c38af
EBE		 1235 info->phc_index = priv->tstamp.ptp ?
1236 ptp_clock_index(priv->tstamp.ptp) : -1;
ef9814de
EBE		 1237
1238 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1239 return 0;
1240
1241 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1242 SOF_TIMESTAMPING_RX_HARDWARE |
1243 SOF_TIMESTAMPING_RAW_HARDWARE;
1244
f0b38117
MD		 1245 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1246 BIT(HWTSTAMP_TX_ON);
ef9814de 1247
f0b38117
MD		 1248 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1249 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE		 1250
1251 return 0;
1252}
1253
928cfe87
TT		 1254static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1255{
1256 __u32 ret = 0;
1257
1258 if (MLX5_CAP_GEN(mdev, wol_g))
1259 ret |= WAKE_MAGIC;
1260
1261 if (MLX5_CAP_GEN(mdev, wol_s))
1262 ret |= WAKE_MAGICSECURE;
1263
1264 if (MLX5_CAP_GEN(mdev, wol_a))
1265 ret |= WAKE_ARP;
1266
1267 if (MLX5_CAP_GEN(mdev, wol_b))
1268 ret |= WAKE_BCAST;
1269
1270 if (MLX5_CAP_GEN(mdev, wol_m))
1271 ret |= WAKE_MCAST;
1272
1273 if (MLX5_CAP_GEN(mdev, wol_u))
1274 ret |= WAKE_UCAST;
1275
1276 if (MLX5_CAP_GEN(mdev, wol_p))
1277 ret |= WAKE_PHY;
1278
1279 return ret;
1280}
1281
1282static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1283{
1284 __u32 ret = 0;
1285
1286 if (mode & MLX5_WOL_MAGIC)
1287 ret |= WAKE_MAGIC;
1288
1289 if (mode & MLX5_WOL_SECURED_MAGIC)
1290 ret |= WAKE_MAGICSECURE;
1291
1292 if (mode & MLX5_WOL_ARP)
1293 ret |= WAKE_ARP;
1294
1295 if (mode & MLX5_WOL_BROADCAST)
1296 ret |= WAKE_BCAST;
1297
1298 if (mode & MLX5_WOL_MULTICAST)
1299 ret |= WAKE_MCAST;
1300
1301 if (mode & MLX5_WOL_UNICAST)
1302 ret |= WAKE_UCAST;
1303
1304 if (mode & MLX5_WOL_PHY_ACTIVITY)
1305 ret |= WAKE_PHY;
1306
1307 return ret;
1308}
1309
1310static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1311{
1312 u8 ret = 0;
1313
1314 if (mode & WAKE_MAGIC)
1315 ret |= MLX5_WOL_MAGIC;
1316
1317 if (mode & WAKE_MAGICSECURE)
1318 ret |= MLX5_WOL_SECURED_MAGIC;
1319
1320 if (mode & WAKE_ARP)
1321 ret |= MLX5_WOL_ARP;
1322
1323 if (mode & WAKE_BCAST)
1324 ret |= MLX5_WOL_BROADCAST;
1325
1326 if (mode & WAKE_MCAST)
1327 ret |= MLX5_WOL_MULTICAST;
1328
1329 if (mode & WAKE_UCAST)
1330 ret |= MLX5_WOL_UNICAST;
1331
1332 if (mode & WAKE_PHY)
1333 ret |= MLX5_WOL_PHY_ACTIVITY;
1334
1335 return ret;
1336}
1337
1338static void mlx5e_get_wol(struct net_device *netdev,
1339 struct ethtool_wolinfo *wol)
1340{
1341 struct mlx5e_priv *priv = netdev_priv(netdev);
1342 struct mlx5_core_dev *mdev = priv->mdev;
1343 u8 mlx5_wol_mode;
1344 int err;
1345
1346 memset(wol, 0, sizeof(*wol));
1347
1348 wol->supported = mlx5e_get_wol_supported(mdev);
1349 if (!wol->supported)
1350 return;
1351
1352 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1353 if (err)
1354 return;
1355
1356 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1357}
1358
1359static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1360{
1361 struct mlx5e_priv *priv = netdev_priv(netdev);
1362 struct mlx5_core_dev *mdev = priv->mdev;
1363 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1364 u32 mlx5_wol_mode;
1365
1366 if (!wol_supported)
9eb78923 1367 return -EOPNOTSUPP;
928cfe87
TT		 1368
1369 if (wol->wolopts & ~wol_supported)
1370 return -EINVAL;
1371
1372 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1373
1374 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1375}
1376
da54d24e
GP		 1377static int mlx5e_set_phys_id(struct net_device *dev,
1378 enum ethtool_phys_id_state state)
1379{
1380 struct mlx5e_priv *priv = netdev_priv(dev);
1381 struct mlx5_core_dev *mdev = priv->mdev;
1382 u16 beacon_duration;
1383
1384 if (!MLX5_CAP_GEN(mdev, beacon_led))
1385 return -EOPNOTSUPP;
1386
1387 switch (state) {
1388 case ETHTOOL_ID_ACTIVE:
1389 beacon_duration = MLX5_BEACON_DURATION_INF;
1390 break;
1391 case ETHTOOL_ID_INACTIVE:
1392 beacon_duration = MLX5_BEACON_DURATION_OFF;
1393 break;
1394 default:
1395 return -EOPNOTSUPP;
1396 }
1397
1398 return mlx5_set_port_beacon(mdev, beacon_duration);
1399}
1400
bb64143e
GP		 1401static int mlx5e_get_module_info(struct net_device *netdev,
1402 struct ethtool_modinfo *modinfo)
1403{
1404 struct mlx5e_priv *priv = netdev_priv(netdev);
1405 struct mlx5_core_dev *dev = priv->mdev;
1406 int size_read = 0;
1407 u8 data[4];
1408
1409 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1410 if (size_read < 2)
1411 return -EIO;
1412
1413 /* data[0] = identifier byte */
1414 switch (data[0]) {
1415 case MLX5_MODULE_ID_QSFP:
1416 modinfo->type = ETH_MODULE_SFF_8436;
1417 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1418 break;
1419 case MLX5_MODULE_ID_QSFP_PLUS:
1420 case MLX5_MODULE_ID_QSFP28:
1421 /* data[1] = revision id */
1422 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1423 modinfo->type = ETH_MODULE_SFF_8636;
1424 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1425 } else {
1426 modinfo->type = ETH_MODULE_SFF_8436;
1427 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1428 }
1429 break;
1430 case MLX5_MODULE_ID_SFP:
1431 modinfo->type = ETH_MODULE_SFF_8472;
1432 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1433 break;
1434 default:
1435 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1436 __func__, data[0]);
1437 return -EINVAL;
1438 }
1439
1440 return 0;
1441}
1442
1443static int mlx5e_get_module_eeprom(struct net_device *netdev,
1444 struct ethtool_eeprom *ee,
1445 u8 *data)
1446{
1447 struct mlx5e_priv *priv = netdev_priv(netdev);
1448 struct mlx5_core_dev *mdev = priv->mdev;
1449 int offset = ee->offset;
1450 int size_read;
1451 int i = 0;
1452
1453 if (!ee->len)
1454 return -EINVAL;
1455
1456 memset(data, 0, ee->len);
1457
1458 while (i < ee->len) {
1459 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1460 data + i);
1461
1462 if (!size_read)
1463 /* Done reading */
1464 return 0;
1465
1466 if (size_read < 0) {
1467 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1468 __func__, size_read);
1469 return 0;
1470 }
1471
1472 i += size_read;
1473 offset += size_read;
1474 }
1475
1476 return 0;
1477}
1478
4e59e288
GP		 1479typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1480
9908aa29 1481static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
4e59e288 1482{
9908aa29
TT		 1483 struct mlx5e_priv *priv = netdev_priv(netdev);
1484 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1485 struct mlx5e_channels new_channels = {};
9908aa29
TT		 1486 bool rx_mode_changed;
1487 u8 rx_cq_period_mode;
1488 int err = 0;
9908aa29
TT		 1489
1490 rx_cq_period_mode = enable ?
1491 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1492 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
6a9764ef 1493 rx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;
9908aa29
TT		 1494
1495 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1496 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1497 return -EOPNOTSUPP;
9908aa29
TT		 1498
1499 if (!rx_mode_changed)
1500 return 0;
1501
be7e87f9
SM		 1502 new_channels.params = priv->channels.params;
1503 mlx5e_set_rx_cq_mode_params(&new_channels.params, rx_cq_period_mode);
9908aa29 1504
be7e87f9
SM		 1505 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1506 priv->channels.params = new_channels.params;
1507 return 0;
1508 }
1509
1510 err = mlx5e_open_channels(priv, &new_channels);
1511 if (err)
1512 return err;
9908aa29 1513
2e20a151 1514 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9
SM		 1515 return 0;
1516}
9908aa29 1517
be7e87f9
SM		 1518int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1519{
1520 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1521 struct mlx5e_channels new_channels = {};
1522 int err = 0;
1523
1524 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1525 return new_val ? -EOPNOTSUPP : 0;
1526
1527 if (curr_val == new_val)
1528 return 0;
1529
1530 new_channels.params = priv->channels.params;
1531 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1532
1533 mlx5e_set_rq_type_params(priv->mdev, &new_channels.params,
1534 new_channels.params.rq_wq_type);
1535
1536 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1537 priv->channels.params = new_channels.params;
1538 return 0;
1539 }
1540
1541 err = mlx5e_open_channels(priv, &new_channels);
1542 if (err)
1543 return err;
1544
2e20a151 1545 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9 1546 return 0;
4e59e288
GP		 1547}
1548
9bcc8606
SD		 1549static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1550 bool enable)
1551{
1552 struct mlx5e_priv *priv = netdev_priv(netdev);
1553 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1554
1555 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1556 return -EOPNOTSUPP;
9bcc8606
SD		 1557
1558 if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1559 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1560 return -EINVAL;
1561 }
1562
5eb0249b 1563 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1564 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1565
5eb0249b 1566 return 0;
9bcc8606
SD		 1567}
1568
4e59e288
GP		 1569static int mlx5e_handle_pflag(struct net_device *netdev,
1570 u32 wanted_flags,
1571 enum mlx5e_priv_flag flag,
1572 mlx5e_pflag_handler pflag_handler)
1573{
1574 struct mlx5e_priv *priv = netdev_priv(netdev);
1575 bool enable = !!(wanted_flags & flag);
6a9764ef 1576 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1577 int err;
1578
1579 if (!(changes & flag))
1580 return 0;
1581
1582 err = pflag_handler(netdev, enable);
1583 if (err) {
1584 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1585 enable ? "Enable" : "Disable", flag, err);
1586 return err;
1587 }
1588
6a9764ef 1589 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1590 return 0;
1591}
1592
1593static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1594{
1595 struct mlx5e_priv *priv = netdev_priv(netdev);
1596 int err;
1597
1598 mutex_lock(&priv->state_lock);
9908aa29
TT		 1599 err = mlx5e_handle_pflag(netdev, pflags,
1600 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1601 set_pflag_rx_cqe_based_moder);
9bcc8606
SD		 1602 if (err)
1603 goto out;
4e59e288 1604
9bcc8606
SD		 1605 err = mlx5e_handle_pflag(netdev, pflags,
1606 MLX5E_PFLAG_RX_CQE_COMPRESS,
1607 set_pflag_rx_cqe_compress);
1608
1609out:
4e59e288 1610 mutex_unlock(&priv->state_lock);
9bcc8606 1611 return err;
4e59e288
GP		 1612}
1613
1614static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1615{
1616 struct mlx5e_priv *priv = netdev_priv(netdev);
1617
6a9764ef 1618 return priv->channels.params.pflags;
4e59e288
GP		 1619}
1620
6dc6071c
MG		 1621static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1622{
1623 int err = 0;
1624 struct mlx5e_priv *priv = netdev_priv(dev);
1625
1626 switch (cmd->cmd) {
1627 case ETHTOOL_SRXCLSRLINS:
1628 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1629 break;
1630 case ETHTOOL_SRXCLSRLDEL:
1631 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1632 break;
1633 default:
1634 err = -EOPNOTSUPP;
1635 break;
1636 }
1637
1638 return err;
1639}
1640
f62b8bb8
AV		 1641const struct ethtool_ops mlx5e_ethtool_ops = {
1642 .get_drvinfo = mlx5e_get_drvinfo,
1643 .get_link = ethtool_op_get_link,
1644 .get_strings = mlx5e_get_strings,
1645 .get_sset_count = mlx5e_get_sset_count,
1646 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1647 .get_ringparam = mlx5e_get_ringparam,
1648 .set_ringparam = mlx5e_set_ringparam,
1649 .get_channels = mlx5e_get_channels,
1650 .set_channels = mlx5e_set_channels,
1651 .get_coalesce = mlx5e_get_coalesce,
1652 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1653 .get_link_ksettings = mlx5e_get_link_ksettings,
1654 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1655 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1656 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1657 .get_rxfh = mlx5e_get_rxfh,
1658 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1659 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1660 .set_rxnfc = mlx5e_set_rxnfc,
58d52291
AS		 1661 .get_tunable = mlx5e_get_tunable,
1662 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1663 .get_pauseparam = mlx5e_get_pauseparam,
1664 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1665 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1666 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1667 .get_wol = mlx5e_get_wol,
1668 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1669 .get_module_info = mlx5e_get_module_info,
1670 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1671 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1672 .set_priv_flags = mlx5e_set_priv_flags,
1673 .self_test = mlx5e_self_test,
f62b8bb8 1674};
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