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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV
1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
34
076b0936
ES
35void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
36 struct ethtool_drvinfo *drvinfo)
f62b8bb8 37{
f62b8bb8
AV
38 struct mlx5_core_dev *mdev = priv->mdev;
39
40 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
7913d205 41 strlcpy(drvinfo->version, DRIVER_VERSION,
f62b8bb8
AV
42 sizeof(drvinfo->version));
43 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK
44 "%d.%d.%04d (%.16s)",
45 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
46 mdev->board_id);
f62b8bb8
AV
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
49}
50
076b0936
ES
51static void mlx5e_get_drvinfo(struct net_device *dev,
52 struct ethtool_drvinfo *drvinfo)
53{
54 struct mlx5e_priv *priv = netdev_priv(dev);
55
56 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
57}
58
665bc539
GP
59struct ptys2ethtool_config {
60 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
61 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8 62 u32 speed;
f62b8bb8
AV
63};
64
665bc539
GP
65static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
66
67#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
68 ({ \
69 struct ptys2ethtool_config *cfg; \
70 const unsigned int modes[] = { __VA_ARGS__ }; \
71 unsigned int i; \
72 cfg = &ptys2ethtool_table[reg_]; \
73 cfg->speed = speed_; \
74 bitmap_zero(cfg->supported, \
75 __ETHTOOL_LINK_MODE_MASK_NBITS); \
76 bitmap_zero(cfg->advertised, \
77 __ETHTOOL_LINK_MODE_MASK_NBITS); \
78 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
79 __set_bit(modes[i], cfg->supported); \
80 __set_bit(modes[i], cfg->advertised); \
81 } \
82 })
83
84void mlx5e_build_ptys2ethtool_map(void)
85{
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
87 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
89 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
91 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
93 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
95 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
97 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
99 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
101 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
103 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
105 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
107 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
109 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
111 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
113 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
115 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
117 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
119 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
121 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
123 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
125 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
127 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
129 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
131 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
133 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
135 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
136}
137
076b0936 138int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
f62b8bb8 139{
c0752f2b
KH
140 int i, num_stats = 0;
141
f62b8bb8
AV
142 switch (sset) {
143 case ETH_SS_STATS:
c0752f2b
KH
144 for (i = 0; i < mlx5e_num_stats_grps; i++)
145 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
1fe85006 146 return num_stats;
4e59e288
GP
147 case ETH_SS_PRIV_FLAGS:
148 return ARRAY_SIZE(mlx5e_priv_flags);
d605d668
KH
149 case ETH_SS_TEST:
150 return mlx5e_self_test_num(priv);
f62b8bb8
AV
151 /* fallthrough */
152 default:
153 return -EOPNOTSUPP;
154 }
155}
156
076b0936
ES
157static int mlx5e_get_sset_count(struct net_device *dev, int sset)
158{
159 struct mlx5e_priv *priv = netdev_priv(dev);
160
161 return mlx5e_ethtool_get_sset_count(priv, sset);
162}
163
c045deef 164static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
9218b44d 165{
1fe85006 166 int i, idx = 0;
9218b44d 167
c0752f2b
KH
168 for (i = 0; i < mlx5e_num_stats_grps; i++)
169 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
9218b44d
GP
170}
171
c045deef 172void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
f62b8bb8 173{
4e59e288 174 int i;
f62b8bb8
AV
175
176 switch (stringset) {
177 case ETH_SS_PRIV_FLAGS:
4e59e288
GP
178 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
179 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV
180 break;
181
182 case ETH_SS_TEST:
d605d668
KH
183 for (i = 0; i < mlx5e_self_test_num(priv); i++)
184 strcpy(data + i * ETH_GSTRING_LEN,
185 mlx5e_self_tests[i]);
f62b8bb8
AV
186 break;
187
188 case ETH_SS_STATS:
9218b44d 189 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV
190 break;
191 }
192}
193
c045deef 194static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
f62b8bb8
AV
195{
196 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES
197
198 mlx5e_ethtool_get_strings(priv, stringset, data);
199}
200
201void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
202 struct ethtool_stats *stats, u64 *data)
203{
1fe85006 204 int i, idx = 0;
f62b8bb8
AV
205
206 if (!data)
207 return;
208
209 mutex_lock(&priv->state_lock);
e556f6dd 210 mlx5e_update_stats(priv, true);
f62b8bb8
AV
211 mutex_unlock(&priv->state_lock);
212
c0752f2b
KH
213 for (i = 0; i < mlx5e_num_stats_grps; i++)
214 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
f62b8bb8
AV
215}
216
076b0936
ES
217static void mlx5e_get_ethtool_stats(struct net_device *dev,
218 struct ethtool_stats *stats,
219 u64 *data)
220{
221 struct mlx5e_priv *priv = netdev_priv(dev);
222
223 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
224}
225
cc8e9ebf
EBE
226static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
227 int num_wqe)
228{
229 int packets_per_wqe;
230 int stride_size;
231 int num_strides;
232 int wqe_size;
233
234 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
235 return num_wqe;
236
6a9764ef
SM
237 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
238 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE
239 wqe_size = stride_size * num_strides;
240
241 packets_per_wqe = wqe_size /
242 ALIGN(ETH_DATA_LEN, stride_size);
243 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
244}
245
246static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
247 int num_packets)
248{
249 int packets_per_wqe;
250 int stride_size;
251 int num_strides;
252 int wqe_size;
253 int num_wqes;
254
255 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
256 return num_packets;
257
6a9764ef
SM
258 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
259 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE
260 wqe_size = stride_size * num_strides;
261
262 num_packets = (1 << order_base_2(num_packets));
263
264 packets_per_wqe = wqe_size /
265 ALIGN(ETH_DATA_LEN, stride_size);
266 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
267 return 1 << (order_base_2(num_wqes));
268}
269
076b0936
ES
270void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
271 struct ethtool_ringparam *param)
f62b8bb8 272{
6a9764ef 273 int rq_wq_type = priv->channels.params.rq_wq_type;
f62b8bb8 274
cc8e9ebf
EBE
275 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
276 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8 277 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
cc8e9ebf 278 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
6a9764ef
SM
279 1 << priv->channels.params.log_rq_size);
280 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV
281}
282
076b0936
ES
283static void mlx5e_get_ringparam(struct net_device *dev,
284 struct ethtool_ringparam *param)
f62b8bb8
AV
285{
286 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES
287
288 mlx5e_ethtool_get_ringparam(priv, param);
289}
290
291int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
292 struct ethtool_ringparam *param)
293{
6a9764ef 294 int rq_wq_type = priv->channels.params.rq_wq_type;
546f18ed 295 struct mlx5e_channels new_channels = {};
cc8e9ebf
EBE
296 u32 rx_pending_wqes;
297 u32 min_rq_size;
298 u32 max_rq_size;
f62b8bb8
AV
299 u8 log_rq_size;
300 u8 log_sq_size;
fe4c988b 301 u32 num_mtts;
f62b8bb8
AV
302 int err = 0;
303
304 if (param->rx_jumbo_pending) {
076b0936 305 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
f62b8bb8
AV
306 __func__);
307 return -EINVAL;
308 }
309 if (param->rx_mini_pending) {
076b0936 310 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
f62b8bb8
AV
311 __func__);
312 return -EINVAL;
313 }
cc8e9ebf
EBE
314
315 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
316 1 << mlx5_min_log_rq_size(rq_wq_type));
317 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
318 1 << mlx5_max_log_rq_size(rq_wq_type));
319 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
320 param->rx_pending);
321
322 if (param->rx_pending < min_rq_size) {
076b0936 323 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
f62b8bb8 324 __func__, param->rx_pending,
cc8e9ebf 325 min_rq_size);
f62b8bb8
AV
326 return -EINVAL;
327 }
cc8e9ebf 328 if (param->rx_pending > max_rq_size) {
076b0936 329 netdev_info(priv->netdev, "%s: rx_pending (%d) > max (%d)\n",
f62b8bb8 330 __func__, param->rx_pending,
cc8e9ebf 331 max_rq_size);
f62b8bb8
AV
332 return -EINVAL;
333 }
fe4c988b 334
ec8b9981 335 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
6a9764ef 336 if (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
fe4c988b 337 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
076b0936 338 netdev_info(priv->netdev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
fe4c988b
SM
339 __func__, param->rx_pending);
340 return -EINVAL;
341 }
342
f62b8bb8 343 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
076b0936 344 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
f62b8bb8
AV
345 __func__, param->tx_pending,
346 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
347 return -EINVAL;
348 }
349 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
076b0936 350 netdev_info(priv->netdev, "%s: tx_pending (%d) > max (%d)\n",
f62b8bb8
AV
351 __func__, param->tx_pending,
352 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
353 return -EINVAL;
354 }
355
cc8e9ebf 356 log_rq_size = order_base_2(rx_pending_wqes);
f62b8bb8 357 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 358
6a9764ef
SM
359 if (log_rq_size == priv->channels.params.log_rq_size &&
360 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV
361 return 0;
362
363 mutex_lock(&priv->state_lock);
98e81b0a 364
546f18ed
SM
365 new_channels.params = priv->channels.params;
366 new_channels.params.log_rq_size = log_rq_size;
367 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 368
546f18ed
SM
369 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
370 priv->channels.params = new_channels.params;
371 goto unlock;
372 }
98e81b0a 373
546f18ed
SM
374 err = mlx5e_open_channels(priv, &new_channels);
375 if (err)
376 goto unlock;
377
2e20a151 378 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 379
546f18ed 380unlock:
f62b8bb8
AV
381 mutex_unlock(&priv->state_lock);
382
383 return err;
384}
385
076b0936
ES
386static int mlx5e_set_ringparam(struct net_device *dev,
387 struct ethtool_ringparam *param)
f62b8bb8
AV
388{
389 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 390
076b0936
ES
391 return mlx5e_ethtool_set_ringparam(priv, param);
392}
393
394void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
395 struct ethtool_channels *ch)
396{
b4e029da 397 ch->max_combined = priv->profile->max_nch(priv->mdev);
6a9764ef 398 ch->combined_count = priv->channels.params.num_channels;
f62b8bb8
AV
399}
400
076b0936
ES
401static void mlx5e_get_channels(struct net_device *dev,
402 struct ethtool_channels *ch)
f62b8bb8
AV
403{
404 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES
405
406 mlx5e_ethtool_get_channels(priv, ch);
407}
408
409int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
410 struct ethtool_channels *ch)
411{
f62b8bb8 412 unsigned int count = ch->combined_count;
55c2503d 413 struct mlx5e_channels new_channels = {};
45bf454a 414 bool arfs_enabled;
f62b8bb8
AV
415 int err = 0;
416
417 if (!count) {
076b0936 418 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
f62b8bb8
AV
419 __func__);
420 return -EINVAL;
421 }
f62b8bb8 422
6a9764ef 423 if (priv->channels.params.num_channels == count)
f62b8bb8
AV
424 return 0;
425
426 mutex_lock(&priv->state_lock);
98e81b0a 427
55c2503d
SM
428 new_channels.params = priv->channels.params;
429 new_channels.params.num_channels = count;
5a8e1267 430 if (!netif_is_rxfh_configured(priv->netdev))
d4b6c488 431 mlx5e_build_default_indir_rqt(new_channels.params.indirection_rqt,
5a8e1267 432 MLX5E_INDIR_RQT_SIZE, count);
55c2503d
SM
433
434 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
435 priv->channels.params = new_channels.params;
436 goto out;
437 }
438
439 /* Create fresh channels with new parameters */
440 err = mlx5e_open_channels(priv, &new_channels);
441 if (err)
442 goto out;
98e81b0a 443
076b0936 444 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
45bf454a
MG
445 if (arfs_enabled)
446 mlx5e_arfs_disable(priv);
447
55c2503d 448 /* Switch to new channels, set new parameters and close old ones */
2e20a151 449 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
45bf454a
MG
450
451 if (arfs_enabled) {
452 err = mlx5e_arfs_enable(priv);
453 if (err)
076b0936 454 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
45bf454a
MG
455 __func__, err);
456 }
98e81b0a 457
45bf454a 458out:
f62b8bb8
AV
459 mutex_unlock(&priv->state_lock);
460
461 return err;
462}
463
076b0936
ES
464static int mlx5e_set_channels(struct net_device *dev,
465 struct ethtool_channels *ch)
f62b8bb8 466{
076b0936
ES
467 struct mlx5e_priv *priv = netdev_priv(dev);
468
469 return mlx5e_ethtool_set_channels(priv, ch);
470}
f62b8bb8 471
076b0936
ES
472int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
473 struct ethtool_coalesce *coal)
474{
7524a5d8 475 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 476 return -EOPNOTSUPP;
7524a5d8 477
6a9764ef
SM
478 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
479 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
480 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
481 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
482 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_am_enabled;
f62b8bb8
AV
483
484 return 0;
485}
486
076b0936
ES
487static int mlx5e_get_coalesce(struct net_device *netdev,
488 struct ethtool_coalesce *coal)
489{
490 struct mlx5e_priv *priv = netdev_priv(netdev);
491
492 return mlx5e_ethtool_get_coalesce(priv, coal);
493}
494
546f18ed
SM
495static void
496mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 497{
f62b8bb8 498 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV
499 int tc;
500 int i;
501
ff9c852f
SM
502 for (i = 0; i < priv->channels.num; ++i) {
503 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV
504
505 for (tc = 0; tc < c->num_tc; tc++) {
506 mlx5_core_modify_cq_moderation(mdev,
507 &c->sq[tc].cq.mcq,
508 coal->tx_coalesce_usecs,
509 coal->tx_max_coalesced_frames);
510 }
511
512 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
513 coal->rx_coalesce_usecs,
514 coal->rx_max_coalesced_frames);
515 }
546f18ed 516}
f62b8bb8 517
076b0936
ES
518int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
519 struct ethtool_coalesce *coal)
546f18ed 520{
546f18ed
SM
521 struct mlx5_core_dev *mdev = priv->mdev;
522 struct mlx5e_channels new_channels = {};
523 int err = 0;
524 bool reset;
cb3c7fd4 525
546f18ed
SM
526 if (!MLX5_CAP_GEN(mdev, cq_moderation))
527 return -EOPNOTSUPP;
528
529 mutex_lock(&priv->state_lock);
530 new_channels.params = priv->channels.params;
531
532 new_channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
533 new_channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
534 new_channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
535 new_channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
536 new_channels.params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
537
538 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
539 priv->channels.params = new_channels.params;
540 goto out;
541 }
542 /* we are opened */
543
544 reset = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_am_enabled;
545 if (!reset) {
546 mlx5e_set_priv_channels_coalesce(priv, coal);
547 priv->channels.params = new_channels.params;
548 goto out;
549 }
550
551 /* open fresh channels with new coal parameters */
552 err = mlx5e_open_channels(priv, &new_channels);
553 if (err)
554 goto out;
555
2e20a151 556 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
546f18ed
SM
557
558out:
2fcb92fb 559 mutex_unlock(&priv->state_lock);
cb3c7fd4 560 return err;
f62b8bb8
AV
561}
562
076b0936
ES
563static int mlx5e_set_coalesce(struct net_device *netdev,
564 struct ethtool_coalesce *coal)
565{
566 struct mlx5e_priv *priv = netdev_priv(netdev);
567
568 return mlx5e_ethtool_set_coalesce(priv, coal);
569}
570
665bc539
GP
571static void ptys2ethtool_supported_link(unsigned long *supported_modes,
572 u32 eth_proto_cap)
f62b8bb8 573{
7abc2110 574 unsigned long proto_cap = eth_proto_cap;
665bc539 575 int proto;
f62b8bb8 576
7abc2110 577 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP
578 bitmap_or(supported_modes, supported_modes,
579 ptys2ethtool_table[proto].supported,
580 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV
581}
582
665bc539
GP
583static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
584 u32 eth_proto_cap)
f62b8bb8 585{
7abc2110 586 unsigned long proto_cap = eth_proto_cap;
665bc539 587 int proto;
f62b8bb8 588
7abc2110 589 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP
590 bitmap_or(advertising_modes, advertising_modes,
591 ptys2ethtool_table[proto].advertised,
592 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV
593}
594
46e9d0b6
EBE
595static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
596 u32 eth_proto_cap,
597 u8 connector_type)
f62b8bb8 598{
46e9d0b6
EBE
599 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
600 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
601 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
602 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
603 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
604 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
605 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
606 ethtool_link_ksettings_add_link_mode(link_ksettings,
607 supported,
608 FIBRE);
609 ethtool_link_ksettings_add_link_mode(link_ksettings,
610 advertising,
611 FIBRE);
612 }
613
614 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
615 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
616 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
617 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
618 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
619 ethtool_link_ksettings_add_link_mode(link_ksettings,
620 supported,
621 Backplane);
622 ethtool_link_ksettings_add_link_mode(link_ksettings,
623 advertising,
624 Backplane);
625 }
626 return;
f62b8bb8
AV
627 }
628
46e9d0b6
EBE
629 switch (connector_type) {
630 case MLX5E_PORT_TP:
631 ethtool_link_ksettings_add_link_mode(link_ksettings,
632 supported, TP);
633 ethtool_link_ksettings_add_link_mode(link_ksettings,
634 advertising, TP);
635 break;
636 case MLX5E_PORT_AUI:
637 ethtool_link_ksettings_add_link_mode(link_ksettings,
638 supported, AUI);
639 ethtool_link_ksettings_add_link_mode(link_ksettings,
640 advertising, AUI);
641 break;
642 case MLX5E_PORT_BNC:
643 ethtool_link_ksettings_add_link_mode(link_ksettings,
644 supported, BNC);
645 ethtool_link_ksettings_add_link_mode(link_ksettings,
646 advertising, BNC);
647 break;
648 case MLX5E_PORT_MII:
649 ethtool_link_ksettings_add_link_mode(link_ksettings,
650 supported, MII);
651 ethtool_link_ksettings_add_link_mode(link_ksettings,
652 advertising, MII);
653 break;
654 case MLX5E_PORT_FIBRE:
655 ethtool_link_ksettings_add_link_mode(link_ksettings,
656 supported, FIBRE);
657 ethtool_link_ksettings_add_link_mode(link_ksettings,
658 advertising, FIBRE);
659 break;
660 case MLX5E_PORT_DA:
661 ethtool_link_ksettings_add_link_mode(link_ksettings,
662 supported, Backplane);
663 ethtool_link_ksettings_add_link_mode(link_ksettings,
664 advertising, Backplane);
665 break;
666 case MLX5E_PORT_NONE:
667 case MLX5E_PORT_OTHER:
668 default:
669 break;
f62b8bb8 670 }
f62b8bb8
AV
671}
672
b797a684
SM
673int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
674{
675 u32 max_speed = 0;
676 u32 proto_cap;
677 int err;
678 int i;
679
680 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
681 if (err)
682 return err;
683
684 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
685 if (proto_cap & MLX5E_PROT_MASK(i))
686 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
687
688 *speed = max_speed;
689 return 0;
690}
691
f62b8bb8
AV
692static void get_speed_duplex(struct net_device *netdev,
693 u32 eth_proto_oper,
665bc539 694 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV
695{
696 int i;
697 u32 speed = SPEED_UNKNOWN;
698 u8 duplex = DUPLEX_UNKNOWN;
699
700 if (!netif_carrier_ok(netdev))
701 goto out;
702
703 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
704 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
705 speed = ptys2ethtool_table[i].speed;
706 duplex = DUPLEX_FULL;
707 break;
708 }
709 }
710out:
665bc539
GP
711 link_ksettings->base.speed = speed;
712 link_ksettings->base.duplex = duplex;
f62b8bb8
AV
713}
714
665bc539
GP
715static void get_supported(u32 eth_proto_cap,
716 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 717{
665bc539
GP
718 unsigned long *supported = link_ksettings->link_modes.supported;
719
665bc539
GP
720 ptys2ethtool_supported_link(supported, eth_proto_cap);
721 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV
722}
723
724static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP
725 u8 rx_pause,
726 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 727{
665bc539
GP
728 unsigned long *advertising = link_ksettings->link_modes.advertising;
729
730 ptys2ethtool_adver_link(advertising, eth_proto_cap);
e3c19503 731 if (rx_pause)
665bc539
GP
732 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
733 if (tx_pause ^ rx_pause)
734 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV
735}
736
5b4793f8
EBE
737static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
738 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
739 [MLX5E_PORT_NONE] = PORT_NONE,
740 [MLX5E_PORT_TP] = PORT_TP,
741 [MLX5E_PORT_AUI] = PORT_AUI,
742 [MLX5E_PORT_BNC] = PORT_BNC,
743 [MLX5E_PORT_MII] = PORT_MII,
744 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
745 [MLX5E_PORT_DA] = PORT_DA,
746 [MLX5E_PORT_OTHER] = PORT_OTHER,
747 };
748
749static u8 get_connector_port(u32 eth_proto, u8 connector_type)
f62b8bb8 750{
5b4793f8
EBE
751 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
752 return ptys2connector_type[connector_type];
753
61bf2125
OG
754 if (eth_proto &
755 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
756 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
757 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
758 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
759 return PORT_FIBRE;
f62b8bb8
AV
760 }
761
61bf2125
OG
762 if (eth_proto &
763 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
764 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
765 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
766 return PORT_DA;
f62b8bb8
AV
767 }
768
61bf2125
OG
769 if (eth_proto &
770 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
771 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
772 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
773 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
774 return PORT_NONE;
f62b8bb8
AV
775 }
776
777 return PORT_OTHER;
778}
779
665bc539
GP
780static void get_lp_advertising(u32 eth_proto_lp,
781 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 782{
665bc539
GP
783 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
784
785 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV
786}
787
665bc539
GP
788static int mlx5e_get_link_ksettings(struct net_device *netdev,
789 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV
790{
791 struct mlx5e_priv *priv = netdev_priv(netdev);
792 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 793 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
b383b544
GP
794 u32 rx_pause = 0;
795 u32 tx_pause = 0;
f62b8bb8
AV
796 u32 eth_proto_cap;
797 u32 eth_proto_admin;
798 u32 eth_proto_lp;
799 u32 eth_proto_oper;
52244d96
GP
800 u8 an_disable_admin;
801 u8 an_status;
5b4793f8 802 u8 connector_type;
f62b8bb8
AV
803 int err;
804
a05bdefa 805 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV
806 if (err) {
807 netdev_err(netdev, "%s: query port ptys failed: %d\n",
808 __func__, err);
809 goto err_query_ptys;
810 }
811
52244d96
GP
812 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
813 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
814 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
815 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
816 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
817 an_status = MLX5_GET(ptys_reg, out, an_status);
5b4793f8 818 connector_type = MLX5_GET(ptys_reg, out, connector_type);
f62b8bb8 819
b383b544
GP
820 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
821
665bc539
GP
822 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
823 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 824
665bc539 825 get_supported(eth_proto_cap, link_ksettings);
b383b544 826 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
665bc539 827 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV
828
829 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
830
5b4793f8
EBE
831 link_ksettings->base.port = get_connector_port(eth_proto_oper,
832 connector_type);
46e9d0b6
EBE
833 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
834 connector_type);
665bc539 835 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 836
52244d96
GP
837 if (an_status == MLX5_AN_COMPLETE)
838 ethtool_link_ksettings_add_link_mode(link_ksettings,
839 lp_advertising, Autoneg);
840
841 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
842 AUTONEG_ENABLE;
843 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
844 Autoneg);
845 if (!an_disable_admin)
846 ethtool_link_ksettings_add_link_mode(link_ksettings,
847 advertising, Autoneg);
848
f62b8bb8
AV
849err_query_ptys:
850 return err;
851}
852
665bc539 853static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV
854{
855 u32 i, ptys_modes = 0;
856
857 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP
858 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
859 link_modes,
860 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV
861 ptys_modes |= MLX5E_PROT_MASK(i);
862 }
863
864 return ptys_modes;
865}
866
867static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
868{
869 u32 i, speed_links = 0;
870
871 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
872 if (ptys2ethtool_table[i].speed == speed)
873 speed_links |= MLX5E_PROT_MASK(i);
874 }
875
876 return speed_links;
877}
878
665bc539
GP
879static int mlx5e_set_link_ksettings(struct net_device *netdev,
880 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV
881{
882 struct mlx5e_priv *priv = netdev_priv(netdev);
883 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP
884 u32 eth_proto_cap, eth_proto_admin;
885 bool an_changes = false;
886 u8 an_disable_admin;
887 u8 an_disable_cap;
888 bool an_disable;
f62b8bb8 889 u32 link_modes;
52244d96 890 u8 an_status;
f62b8bb8 891 u32 speed;
f62b8bb8
AV
892 int err;
893
665bc539 894 speed = link_ksettings->base.speed;
f62b8bb8 895
665bc539
GP
896 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
897 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
f62b8bb8
AV
898 mlx5e_ethtool2ptys_speed_link(speed);
899
900 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
901 if (err) {
902 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
903 __func__, err);
904 goto out;
905 }
906
907 link_modes = link_modes & eth_proto_cap;
908 if (!link_modes) {
909 netdev_err(netdev, "%s: Not supported link mode(s) requested",
910 __func__);
911 err = -EINVAL;
912 goto out;
913 }
914
915 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
916 if (err) {
917 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
918 __func__, err);
919 goto out;
920 }
921
52244d96
GP
922 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
923 &an_disable_cap, &an_disable_admin);
924
925 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
926 an_changes = ((!an_disable && an_disable_admin) ||
927 (an_disable && !an_disable_admin));
928
929 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV
930 goto out;
931
52244d96 932 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 933 mlx5_toggle_port_link(mdev);
f62b8bb8 934
f62b8bb8
AV
935out:
936 return err;
937}
938
2d75b2bc
AS
939static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
940{
941 struct mlx5e_priv *priv = netdev_priv(netdev);
942
6a9764ef 943 return sizeof(priv->channels.params.toeplitz_hash_key);
2d75b2bc
AS
944}
945
946static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
947{
948 return MLX5E_INDIR_RQT_SIZE;
949}
950
2be6967c
SM
951static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
952 u8 *hfunc)
953{
954 struct mlx5e_priv *priv = netdev_priv(netdev);
955
2d75b2bc 956 if (indir)
6a9764ef
SM
957 memcpy(indir, priv->channels.params.indirection_rqt,
958 sizeof(priv->channels.params.indirection_rqt));
2d75b2bc
AS
959
960 if (key)
6a9764ef
SM
961 memcpy(key, priv->channels.params.toeplitz_hash_key,
962 sizeof(priv->channels.params.toeplitz_hash_key));
2d75b2bc 963
2be6967c 964 if (hfunc)
6a9764ef 965 *hfunc = priv->channels.params.rss_hfunc;
2be6967c
SM
966
967 return 0;
968}
969
bdfc028d
TT
970static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
971{
bdfc028d 972 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
a100ff3e
GP
973 struct mlx5_core_dev *mdev = priv->mdev;
974 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
975 int tt;
bdfc028d
TT
976
977 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
bdfc028d 978
a100ff3e
GP
979 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
980 memset(tirc, 0, ctxlen);
7b3722fa 981 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
a100ff3e
GP
982 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
983 }
7b3722fa
GP
984
985 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
986 return;
987
988 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
989 memset(tirc, 0, ctxlen);
990 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
991 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in, inlen);
992 }
bdfc028d
TT
993}
994
98e81b0a 995static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM
996 const u8 *key, const u8 hfunc)
997{
98e81b0a 998 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d 999 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1000 bool hash_changed = false;
bdfc028d 1001 void *in;
2be6967c 1002
2d75b2bc
AS
1003 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1004 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM
1005 (hfunc != ETH_RSS_HASH_TOP))
1006 return -EINVAL;
1007
1b9a07ee 1008 in = kvzalloc(inlen, GFP_KERNEL);
bdfc028d
TT
1009 if (!in)
1010 return -ENOMEM;
1011
2be6967c
SM
1012 mutex_lock(&priv->state_lock);
1013
1d3398fa 1014 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
6a9764ef
SM
1015 hfunc != priv->channels.params.rss_hfunc) {
1016 priv->channels.params.rss_hfunc = hfunc;
1d3398fa
GP
1017 hash_changed = true;
1018 }
1019
a5f97fee 1020 if (indir) {
6a9764ef
SM
1021 memcpy(priv->channels.params.indirection_rqt, indir,
1022 sizeof(priv->channels.params.indirection_rqt));
a5f97fee
SM
1023
1024 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1025 u32 rqtn = priv->indir_rqt.rqtn;
1026 struct mlx5e_redirect_rqt_param rrp = {
1027 .is_rss = true,
e270e966
AM
1028 {
1029 .rss = {
1030 .hfunc = priv->channels.params.rss_hfunc,
1031 .channels = &priv->channels,
1032 },
1033 },
a5f97fee
SM
1034 };
1035
1036 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1037 }
1038 }
1039
1d3398fa 1040 if (key) {
6a9764ef
SM
1041 memcpy(priv->channels.params.toeplitz_hash_key, key,
1042 sizeof(priv->channels.params.toeplitz_hash_key));
1d3398fa 1043 hash_changed = hash_changed ||
6a9764ef 1044 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1045 }
2d75b2bc 1046
1d3398fa
GP
1047 if (hash_changed)
1048 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1049
2be6967c
SM
1050 mutex_unlock(&priv->state_lock);
1051
bdfc028d
TT
1052 kvfree(in);
1053
1054 return 0;
2be6967c
SM
1055}
1056
2d75b2bc
AS
1057static int mlx5e_get_rxnfc(struct net_device *netdev,
1058 struct ethtool_rxnfc *info, u32 *rule_locs)
1059{
1060 struct mlx5e_priv *priv = netdev_priv(netdev);
1061 int err = 0;
1062
1063 switch (info->cmd) {
1064 case ETHTOOL_GRXRINGS:
6a9764ef 1065 info->data = priv->channels.params.num_channels;
2d75b2bc 1066 break;
f913a72a
MG
1067 case ETHTOOL_GRXCLSRLCNT:
1068 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1069 break;
1070 case ETHTOOL_GRXCLSRULE:
1071 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1072 break;
1073 case ETHTOOL_GRXCLSRLALL:
1074 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1075 break;
2d75b2bc
AS
1076 default:
1077 err = -EOPNOTSUPP;
1078 break;
1079 }
1080
1081 return err;
1082}
1083
58d52291
AS
1084static int mlx5e_get_tunable(struct net_device *dev,
1085 const struct ethtool_tunable *tuna,
1086 void *data)
1087{
1088 const struct mlx5e_priv *priv = netdev_priv(dev);
1089 int err = 0;
1090
1091 switch (tuna->id) {
1092 case ETHTOOL_TX_COPYBREAK:
6a9764ef 1093 *(u32 *)data = priv->channels.params.tx_max_inline;
58d52291
AS
1094 break;
1095 default:
1096 err = -EINVAL;
1097 break;
1098 }
1099
1100 return err;
1101}
1102
1103static int mlx5e_set_tunable(struct net_device *dev,
1104 const struct ethtool_tunable *tuna,
1105 const void *data)
1106{
1107 struct mlx5e_priv *priv = netdev_priv(dev);
1108 struct mlx5_core_dev *mdev = priv->mdev;
546f18ed 1109 struct mlx5e_channels new_channels = {};
58d52291 1110 int err = 0;
546f18ed
SM
1111 u32 val;
1112
1113 mutex_lock(&priv->state_lock);
58d52291
AS
1114
1115 switch (tuna->id) {
1116 case ETHTOOL_TX_COPYBREAK:
1117 val = *(u32 *)data;
1118 if (val > mlx5e_get_max_inline_cap(mdev)) {
1119 err = -EINVAL;
1120 break;
1121 }
1122
546f18ed
SM
1123 new_channels.params = priv->channels.params;
1124 new_channels.params.tx_max_inline = val;
98e81b0a 1125
546f18ed
SM
1126 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1127 priv->channels.params = new_channels.params;
1128 break;
1129 }
98e81b0a 1130
546f18ed
SM
1131 err = mlx5e_open_channels(priv, &new_channels);
1132 if (err)
1133 break;
2e20a151 1134 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 1135
58d52291
AS
1136 break;
1137 default:
1138 err = -EINVAL;
1139 break;
1140 }
1141
546f18ed 1142 mutex_unlock(&priv->state_lock);
58d52291
AS
1143 return err;
1144}
1145
3c2d18ef
AS
1146static void mlx5e_get_pauseparam(struct net_device *netdev,
1147 struct ethtool_pauseparam *pauseparam)
1148{
1149 struct mlx5e_priv *priv = netdev_priv(netdev);
1150 struct mlx5_core_dev *mdev = priv->mdev;
1151 int err;
1152
1153 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1154 &pauseparam->tx_pause);
1155 if (err) {
1156 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1157 __func__, err);
1158 }
1159}
1160
1161static int mlx5e_set_pauseparam(struct net_device *netdev,
1162 struct ethtool_pauseparam *pauseparam)
1163{
1164 struct mlx5e_priv *priv = netdev_priv(netdev);
1165 struct mlx5_core_dev *mdev = priv->mdev;
1166 int err;
1167
1168 if (pauseparam->autoneg)
1169 return -EINVAL;
1170
1171 err = mlx5_set_port_pause(mdev,
1172 pauseparam->rx_pause ? 1 : 0,
1173 pauseparam->tx_pause ? 1 : 0);
1174 if (err) {
1175 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1176 __func__, err);
1177 }
1178
1179 return err;
1180}
1181
3844b07e
FD
1182int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1183 struct ethtool_ts_info *info)
ef9814de 1184{
7c39afb3 1185 struct mlx5_core_dev *mdev = priv->mdev;
ef9814de
EBE
1186 int ret;
1187
3844b07e 1188 ret = ethtool_op_get_ts_info(priv->netdev, info);
ef9814de
EBE
1189 if (ret)
1190 return ret;
1191
7c39afb3
FD
1192 info->phc_index = mdev->clock.ptp ?
1193 ptp_clock_index(mdev->clock.ptp) : -1;
ef9814de
EBE
1194
1195 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1196 return 0;
1197
1198 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1199 SOF_TIMESTAMPING_RX_HARDWARE |
1200 SOF_TIMESTAMPING_RAW_HARDWARE;
1201
f0b38117
MD
1202 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1203 BIT(HWTSTAMP_TX_ON);
ef9814de 1204
f0b38117
MD
1205 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1206 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE
1207
1208 return 0;
1209}
1210
3844b07e
FD
1211static int mlx5e_get_ts_info(struct net_device *dev,
1212 struct ethtool_ts_info *info)
1213{
1214 struct mlx5e_priv *priv = netdev_priv(dev);
1215
1216 return mlx5e_ethtool_get_ts_info(priv, info);
1217}
1218
928cfe87
TT
1219static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1220{
1221 __u32 ret = 0;
1222
1223 if (MLX5_CAP_GEN(mdev, wol_g))
1224 ret |= WAKE_MAGIC;
1225
1226 if (MLX5_CAP_GEN(mdev, wol_s))
1227 ret |= WAKE_MAGICSECURE;
1228
1229 if (MLX5_CAP_GEN(mdev, wol_a))
1230 ret |= WAKE_ARP;
1231
1232 if (MLX5_CAP_GEN(mdev, wol_b))
1233 ret |= WAKE_BCAST;
1234
1235 if (MLX5_CAP_GEN(mdev, wol_m))
1236 ret |= WAKE_MCAST;
1237
1238 if (MLX5_CAP_GEN(mdev, wol_u))
1239 ret |= WAKE_UCAST;
1240
1241 if (MLX5_CAP_GEN(mdev, wol_p))
1242 ret |= WAKE_PHY;
1243
1244 return ret;
1245}
1246
1247static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1248{
1249 __u32 ret = 0;
1250
1251 if (mode & MLX5_WOL_MAGIC)
1252 ret |= WAKE_MAGIC;
1253
1254 if (mode & MLX5_WOL_SECURED_MAGIC)
1255 ret |= WAKE_MAGICSECURE;
1256
1257 if (mode & MLX5_WOL_ARP)
1258 ret |= WAKE_ARP;
1259
1260 if (mode & MLX5_WOL_BROADCAST)
1261 ret |= WAKE_BCAST;
1262
1263 if (mode & MLX5_WOL_MULTICAST)
1264 ret |= WAKE_MCAST;
1265
1266 if (mode & MLX5_WOL_UNICAST)
1267 ret |= WAKE_UCAST;
1268
1269 if (mode & MLX5_WOL_PHY_ACTIVITY)
1270 ret |= WAKE_PHY;
1271
1272 return ret;
1273}
1274
1275static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1276{
1277 u8 ret = 0;
1278
1279 if (mode & WAKE_MAGIC)
1280 ret |= MLX5_WOL_MAGIC;
1281
1282 if (mode & WAKE_MAGICSECURE)
1283 ret |= MLX5_WOL_SECURED_MAGIC;
1284
1285 if (mode & WAKE_ARP)
1286 ret |= MLX5_WOL_ARP;
1287
1288 if (mode & WAKE_BCAST)
1289 ret |= MLX5_WOL_BROADCAST;
1290
1291 if (mode & WAKE_MCAST)
1292 ret |= MLX5_WOL_MULTICAST;
1293
1294 if (mode & WAKE_UCAST)
1295 ret |= MLX5_WOL_UNICAST;
1296
1297 if (mode & WAKE_PHY)
1298 ret |= MLX5_WOL_PHY_ACTIVITY;
1299
1300 return ret;
1301}
1302
1303static void mlx5e_get_wol(struct net_device *netdev,
1304 struct ethtool_wolinfo *wol)
1305{
1306 struct mlx5e_priv *priv = netdev_priv(netdev);
1307 struct mlx5_core_dev *mdev = priv->mdev;
1308 u8 mlx5_wol_mode;
1309 int err;
1310
1311 memset(wol, 0, sizeof(*wol));
1312
1313 wol->supported = mlx5e_get_wol_supported(mdev);
1314 if (!wol->supported)
1315 return;
1316
1317 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1318 if (err)
1319 return;
1320
1321 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1322}
1323
1324static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1325{
1326 struct mlx5e_priv *priv = netdev_priv(netdev);
1327 struct mlx5_core_dev *mdev = priv->mdev;
1328 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1329 u32 mlx5_wol_mode;
1330
1331 if (!wol_supported)
9eb78923 1332 return -EOPNOTSUPP;
928cfe87
TT
1333
1334 if (wol->wolopts & ~wol_supported)
1335 return -EINVAL;
1336
1337 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1338
1339 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1340}
1341
79c48764
GP
1342static u32 mlx5e_get_msglevel(struct net_device *dev)
1343{
1344 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1345}
1346
1347static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1348{
1349 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1350}
1351
da54d24e
GP
1352static int mlx5e_set_phys_id(struct net_device *dev,
1353 enum ethtool_phys_id_state state)
1354{
1355 struct mlx5e_priv *priv = netdev_priv(dev);
1356 struct mlx5_core_dev *mdev = priv->mdev;
1357 u16 beacon_duration;
1358
1359 if (!MLX5_CAP_GEN(mdev, beacon_led))
1360 return -EOPNOTSUPP;
1361
1362 switch (state) {
1363 case ETHTOOL_ID_ACTIVE:
1364 beacon_duration = MLX5_BEACON_DURATION_INF;
1365 break;
1366 case ETHTOOL_ID_INACTIVE:
1367 beacon_duration = MLX5_BEACON_DURATION_OFF;
1368 break;
1369 default:
1370 return -EOPNOTSUPP;
1371 }
1372
1373 return mlx5_set_port_beacon(mdev, beacon_duration);
1374}
1375
bb64143e
GP
1376static int mlx5e_get_module_info(struct net_device *netdev,
1377 struct ethtool_modinfo *modinfo)
1378{
1379 struct mlx5e_priv *priv = netdev_priv(netdev);
1380 struct mlx5_core_dev *dev = priv->mdev;
1381 int size_read = 0;
1382 u8 data[4];
1383
1384 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1385 if (size_read < 2)
1386 return -EIO;
1387
1388 /* data[0] = identifier byte */
1389 switch (data[0]) {
1390 case MLX5_MODULE_ID_QSFP:
1391 modinfo->type = ETH_MODULE_SFF_8436;
1392 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1393 break;
1394 case MLX5_MODULE_ID_QSFP_PLUS:
1395 case MLX5_MODULE_ID_QSFP28:
1396 /* data[1] = revision id */
1397 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1398 modinfo->type = ETH_MODULE_SFF_8636;
1399 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1400 } else {
1401 modinfo->type = ETH_MODULE_SFF_8436;
1402 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1403 }
1404 break;
1405 case MLX5_MODULE_ID_SFP:
1406 modinfo->type = ETH_MODULE_SFF_8472;
1407 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1408 break;
1409 default:
1410 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1411 __func__, data[0]);
1412 return -EINVAL;
1413 }
1414
1415 return 0;
1416}
1417
1418static int mlx5e_get_module_eeprom(struct net_device *netdev,
1419 struct ethtool_eeprom *ee,
1420 u8 *data)
1421{
1422 struct mlx5e_priv *priv = netdev_priv(netdev);
1423 struct mlx5_core_dev *mdev = priv->mdev;
1424 int offset = ee->offset;
1425 int size_read;
1426 int i = 0;
1427
1428 if (!ee->len)
1429 return -EINVAL;
1430
1431 memset(data, 0, ee->len);
1432
1433 while (i < ee->len) {
1434 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1435 data + i);
1436
1437 if (!size_read)
1438 /* Done reading */
1439 return 0;
1440
1441 if (size_read < 0) {
1442 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1443 __func__, size_read);
1444 return 0;
1445 }
1446
1447 i += size_read;
1448 offset += size_read;
1449 }
1450
1451 return 0;
1452}
1453
4e59e288
GP
1454typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1455
0088cbbc
TG
1456static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1457 bool is_rx_cq)
4e59e288 1458{
9908aa29
TT
1459 struct mlx5e_priv *priv = netdev_priv(netdev);
1460 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1461 struct mlx5e_channels new_channels = {};
0088cbbc
TG
1462 bool mode_changed;
1463 u8 cq_period_mode, current_cq_period_mode;
9908aa29 1464 int err = 0;
9908aa29 1465
0088cbbc 1466 cq_period_mode = enable ?
9908aa29
TT
1467 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1468 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
0088cbbc
TG
1469 current_cq_period_mode = is_rx_cq ?
1470 priv->channels.params.rx_cq_moderation.cq_period_mode :
1471 priv->channels.params.tx_cq_moderation.cq_period_mode;
1472 mode_changed = cq_period_mode != current_cq_period_mode;
9908aa29 1473
0088cbbc 1474 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
9908aa29 1475 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1476 return -EOPNOTSUPP;
9908aa29 1477
0088cbbc 1478 if (!mode_changed)
9908aa29
TT
1479 return 0;
1480
be7e87f9 1481 new_channels.params = priv->channels.params;
0088cbbc
TG
1482 if (is_rx_cq)
1483 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1484 else
1485 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
9908aa29 1486
be7e87f9
SM
1487 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1488 priv->channels.params = new_channels.params;
1489 return 0;
1490 }
1491
1492 err = mlx5e_open_channels(priv, &new_channels);
1493 if (err)
1494 return err;
9908aa29 1495
2e20a151 1496 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9
SM
1497 return 0;
1498}
9908aa29 1499
0088cbbc
TG
1500static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1501{
1502 return set_pflag_cqe_based_moder(netdev, enable, false);
1503}
1504
1505static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1506{
1507 return set_pflag_cqe_based_moder(netdev, enable, true);
1508}
1509
be7e87f9
SM
1510int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1511{
1512 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1513 struct mlx5e_channels new_channels = {};
1514 int err = 0;
1515
1516 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1517 return new_val ? -EOPNOTSUPP : 0;
1518
1519 if (curr_val == new_val)
1520 return 0;
1521
1522 new_channels.params = priv->channels.params;
1523 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1524
696a97cf
EE
1525 new_channels.params.mpwqe_log_stride_sz =
1526 MLX5E_MPWQE_STRIDE_SZ(priv->mdev, new_val);
1527 new_channels.params.mpwqe_log_num_strides =
1528 MLX5_MPWRQ_LOG_WQE_SZ - new_channels.params.mpwqe_log_stride_sz;
be7e87f9
SM
1529
1530 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1531 priv->channels.params = new_channels.params;
1532 return 0;
1533 }
1534
1535 err = mlx5e_open_channels(priv, &new_channels);
1536 if (err)
1537 return err;
1538
2e20a151 1539 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
696a97cf
EE
1540 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1541 MLX5E_GET_PFLAG(&priv->channels.params,
1542 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1543
be7e87f9 1544 return 0;
4e59e288
GP
1545}
1546
9bcc8606
SD
1547static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1548 bool enable)
1549{
1550 struct mlx5e_priv *priv = netdev_priv(netdev);
1551 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD
1552
1553 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1554 return -EOPNOTSUPP;
9bcc8606 1555
7c39afb3 1556 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
9bcc8606
SD
1557 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1558 return -EINVAL;
1559 }
1560
5eb0249b 1561 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1562 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1563
5eb0249b 1564 return 0;
9bcc8606
SD
1565}
1566
4e59e288
GP
1567static int mlx5e_handle_pflag(struct net_device *netdev,
1568 u32 wanted_flags,
1569 enum mlx5e_priv_flag flag,
1570 mlx5e_pflag_handler pflag_handler)
1571{
1572 struct mlx5e_priv *priv = netdev_priv(netdev);
1573 bool enable = !!(wanted_flags & flag);
6a9764ef 1574 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP
1575 int err;
1576
1577 if (!(changes & flag))
1578 return 0;
1579
1580 err = pflag_handler(netdev, enable);
1581 if (err) {
1582 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1583 enable ? "Enable" : "Disable", flag, err);
1584 return err;
1585 }
1586
6a9764ef 1587 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP
1588 return 0;
1589}
1590
1591static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1592{
1593 struct mlx5e_priv *priv = netdev_priv(netdev);
1594 int err;
1595
1596 mutex_lock(&priv->state_lock);
9908aa29
TT
1597 err = mlx5e_handle_pflag(netdev, pflags,
1598 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1599 set_pflag_rx_cqe_based_moder);
9bcc8606
SD
1600 if (err)
1601 goto out;
4e59e288 1602
0088cbbc
TG
1603 err = mlx5e_handle_pflag(netdev, pflags,
1604 MLX5E_PFLAG_TX_CQE_BASED_MODER,
1605 set_pflag_tx_cqe_based_moder);
1606 if (err)
1607 goto out;
1608
9bcc8606
SD
1609 err = mlx5e_handle_pflag(netdev, pflags,
1610 MLX5E_PFLAG_RX_CQE_COMPRESS,
1611 set_pflag_rx_cqe_compress);
1612
1613out:
4e59e288 1614 mutex_unlock(&priv->state_lock);
9bcc8606 1615 return err;
4e59e288
GP
1616}
1617
1618static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1619{
1620 struct mlx5e_priv *priv = netdev_priv(netdev);
1621
6a9764ef 1622 return priv->channels.params.pflags;
4e59e288
GP
1623}
1624
6dc6071c
MG
1625static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1626{
1627 int err = 0;
1628 struct mlx5e_priv *priv = netdev_priv(dev);
1629
1630 switch (cmd->cmd) {
1631 case ETHTOOL_SRXCLSRLINS:
1632 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1633 break;
1634 case ETHTOOL_SRXCLSRLDEL:
1635 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1636 break;
1637 default:
1638 err = -EOPNOTSUPP;
1639 break;
1640 }
1641
1642 return err;
1643}
1644
3ffaabec
OG
1645int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1646 struct ethtool_flash *flash)
1647{
1648 struct mlx5_core_dev *mdev = priv->mdev;
1649 struct net_device *dev = priv->netdev;
1650 const struct firmware *fw;
1651 int err;
1652
1653 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1654 return -EOPNOTSUPP;
1655
1656 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1657 if (err)
1658 return err;
1659
1660 dev_hold(dev);
1661 rtnl_unlock();
1662
1663 err = mlx5_firmware_flash(mdev, fw);
1664 release_firmware(fw);
1665
1666 rtnl_lock();
1667 dev_put(dev);
1668 return err;
1669}
1670
1671static int mlx5e_flash_device(struct net_device *dev,
1672 struct ethtool_flash *flash)
1673{
1674 struct mlx5e_priv *priv = netdev_priv(dev);
1675
1676 return mlx5e_ethtool_flash_device(priv, flash);
1677}
1678
f62b8bb8
AV
1679const struct ethtool_ops mlx5e_ethtool_ops = {
1680 .get_drvinfo = mlx5e_get_drvinfo,
1681 .get_link = ethtool_op_get_link,
1682 .get_strings = mlx5e_get_strings,
1683 .get_sset_count = mlx5e_get_sset_count,
1684 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1685 .get_ringparam = mlx5e_get_ringparam,
1686 .set_ringparam = mlx5e_set_ringparam,
1687 .get_channels = mlx5e_get_channels,
1688 .set_channels = mlx5e_set_channels,
1689 .get_coalesce = mlx5e_get_coalesce,
1690 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP
1691 .get_link_ksettings = mlx5e_get_link_ksettings,
1692 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS
1693 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1694 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM
1695 .get_rxfh = mlx5e_get_rxfh,
1696 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1697 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1698 .set_rxnfc = mlx5e_set_rxnfc,
3ffaabec 1699 .flash_device = mlx5e_flash_device,
58d52291
AS
1700 .get_tunable = mlx5e_get_tunable,
1701 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS
1702 .get_pauseparam = mlx5e_get_pauseparam,
1703 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1704 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1705 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT
1706 .get_wol = mlx5e_get_wol,
1707 .set_wol = mlx5e_set_wol,
bb64143e
GP
1708 .get_module_info = mlx5e_get_module_info,
1709 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1710 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH
1711 .set_priv_flags = mlx5e_set_priv_flags,
1712 .self_test = mlx5e_self_test,
79c48764
GP
1713 .get_msglevel = mlx5e_get_msglevel,
1714 .set_msglevel = mlx5e_set_msglevel,
1715
f62b8bb8 1716};