]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/ethernet/mellanox/mlx5/core/en_main.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5e: IPoIB, Add ethtool support
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
b3f63c3d 42#include "vxlan.h"
f62b8bb8
AV		 43
44struct mlx5e_rq_param {
cb3c7fd4
GR		 45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
9908aa29 58 u8 cq_period_mode;
f62b8bb8
AV		 59};
60
61struct mlx5e_channel_param {
62 struct mlx5e_rq_param rq;
63 struct mlx5e_sq_param sq;
b5503b99 64 struct mlx5e_sq_param xdp_sq;
d3c9bc27 65 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
d3c9bc27 68 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 69};
70
2fc4bfb7
SM		 71static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
72{
73 return MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
76}
77
6a9764ef
SM		 78void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
79 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 80{
6a9764ef
SM		 81 params->rq_wq_type = rq_type;
82 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
83 switch (params->rq_wq_type) {
2fc4bfb7 84 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 85 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 86 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
87 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 88 params->mpwqe_log_stride_sz =
89 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
90 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
91 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
92 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
93 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 94 break;
95 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 96 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 97 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
98 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
4078e637
TT		 99
100 /* Extra room needed for build_skb */
6a9764ef 101 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
4078e637 102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 103 }
2fc4bfb7 104
6a9764ef
SM		 105 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(params->log_rq_size),
108 BIT(params->mpwqe_log_stride_sz),
109 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 110}
111
6a9764ef 112static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 113{
6a9764ef
SM		 114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
115 !params->xdp_prog ?
2fc4bfb7
SM		 116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 118 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 119}
120
f62b8bb8
AV		 121static void mlx5e_update_carrier(struct mlx5e_priv *priv)
122{
123 struct mlx5_core_dev *mdev = priv->mdev;
124 u8 port_state;
125
126 port_state = mlx5_query_vport_state(mdev,
e53eef63
OG		 127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
128 0);
f62b8bb8 129
87424ad5
SD		 130 if (port_state == VPORT_STATE_UP) {
131 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 132 netif_carrier_on(priv->netdev);
87424ad5
SD		 133 } else {
134 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 135 netif_carrier_off(priv->netdev);
87424ad5 136 }
f62b8bb8
AV		 137}
138
139static void mlx5e_update_carrier_work(struct work_struct *work)
140{
141 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
142 update_carrier_work);
143
144 mutex_lock(&priv->state_lock);
145 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
146 mlx5e_update_carrier(priv);
147 mutex_unlock(&priv->state_lock);
148}
149
3947ca18
DJ		 150static void mlx5e_tx_timeout_work(struct work_struct *work)
151{
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 tx_timeout_work);
154 int err;
155
156 rtnl_lock();
157 mutex_lock(&priv->state_lock);
158 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
159 goto unlock;
160 mlx5e_close_locked(priv->netdev);
161 err = mlx5e_open_locked(priv->netdev);
162 if (err)
163 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
164 err);
165unlock:
166 mutex_unlock(&priv->state_lock);
167 rtnl_unlock();
168}
169
9218b44d 170static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 171{
1510d728 172 struct mlx5e_sw_stats temp, *s = &temp;
f62b8bb8
AV		 173 struct mlx5e_rq_stats *rq_stats;
174 struct mlx5e_sq_stats *sq_stats;
9218b44d 175 u64 tx_offload_none = 0;
f62b8bb8
AV		 176 int i, j;
177
9218b44d 178 memset(s, 0, sizeof(*s));
ff9c852f
SM		 179 for (i = 0; i < priv->channels.num; i++) {
180 struct mlx5e_channel *c = priv->channels.c[i];
181
182 rq_stats = &c->rq.stats;
f62b8bb8 183
faf4478b
GP		 184 s->rx_packets += rq_stats->packets;
185 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 186 s->rx_lro_packets += rq_stats->lro_packets;
187 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 188 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 189 s->rx_csum_complete += rq_stats->csum_complete;
190 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 191 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 192 s->rx_xdp_tx += rq_stats->xdp_tx;
193 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 194 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 195 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 196 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 197 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
198 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 199 s->rx_cache_reuse += rq_stats->cache_reuse;
200 s->rx_cache_full += rq_stats->cache_full;
201 s->rx_cache_empty += rq_stats->cache_empty;
202 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 203
6a9764ef 204 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 205 sq_stats = &c->sq[j].stats;
f62b8bb8 206
faf4478b
GP		 207 s->tx_packets += sq_stats->packets;
208 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 209 s->tx_tso_packets += sq_stats->tso_packets;
210 s->tx_tso_bytes += sq_stats->tso_bytes;
211 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
212 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 213 s->tx_queue_stopped += sq_stats->stopped;
214 s->tx_queue_wake += sq_stats->wake;
215 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 216 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 217 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
218 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 219 }
220 }
221
9218b44d 222 /* Update calculated offload counters */
bfe6d8d1
GP		 223 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
224 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 225
bfe6d8d1 226 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 227 priv->stats.pport.phy_counters,
228 counter_set.phys_layer_cntrs.link_down_events);
1510d728 229 memcpy(&priv->stats.sw, s, sizeof(*s));
9218b44d
GP		 230}
231
232static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
233{
234 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
235 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 236 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 237 struct mlx5_core_dev *mdev = priv->mdev;
238
f62b8bb8
AV		 239 MLX5_SET(query_vport_counter_in, in, opcode,
240 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
241 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
242 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
243
9218b44d
GP		 244 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
245}
246
3834a5e6 247static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
9218b44d
GP		 248{
249 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
250 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 251 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
9218b44d 252 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 253 int prio;
9218b44d 254 void *out;
f62b8bb8 255
9218b44d 256 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 257
9218b44d
GP		 258 out = pstats->IEEE_802_3_counters;
259 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
260 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 261
3834a5e6
GP		 262 if (!full)
263 return;
264
9218b44d
GP		 265 out = pstats->RFC_2863_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
268
269 out = pstats->RFC_2819_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 272
121fcdc8
GP		 273 out = pstats->phy_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276
5db0a4f6
GP		 277 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
278 out = pstats->phy_statistical_counters;
279 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
280 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
281 }
282
cf678570
GP		 283 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
284 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
285 out = pstats->per_prio_counters[prio];
286 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
287 mlx5_core_access_reg(mdev, in, sz, out, sz,
288 MLX5_REG_PPCNT, 0, 0);
289 }
9218b44d
GP		 290}
291
292static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
293{
294 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
432609a4
GP		 295 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
296 int err;
9218b44d
GP		 297
298 if (!priv->q_counter)
299 return;
300
432609a4
GP		 301 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
302 if (err)
303 return;
304
305 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
9218b44d
GP		 306}
307
0f7f3481
GP		 308static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
309{
310 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
311 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 312 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
0f7f3481
GP		 313 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
314 void *out;
0f7f3481
GP		 315
316 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
317 return;
318
0f7f3481
GP		 319 out = pcie_stats->pcie_perf_counters;
320 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
321 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
0f7f3481
GP		 322}
323
3834a5e6 324void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
9218b44d 325{
3834a5e6
GP		 326 if (full)
327 mlx5e_update_pcie_counters(priv);
328 mlx5e_update_pport_counters(priv, full);
3dd69e3d
SM		 329 mlx5e_update_vport_counters(priv);
330 mlx5e_update_q_counter(priv);
121fcdc8 331 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 332}
333
3834a5e6
GP		 334static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
335{
336 mlx5e_update_stats(priv, false);
337}
338
cb67b832 339void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 340{
341 struct delayed_work *dwork = to_delayed_work(work);
342 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
343 update_stats_work);
344 mutex_lock(&priv->state_lock);
345 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 346 priv->profile->update_stats(priv);
7bb29755
MF		 347 queue_delayed_work(priv->wq, dwork,
348 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 349 }
350 mutex_unlock(&priv->state_lock);
351}
352
daa21560
TT		 353static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
354 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 355{
daa21560 356 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 357 struct ptp_clock_event ptp_event;
358 struct mlx5_eqe *eqe = NULL;
daa21560 359
e0f46eb9 360 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 361 return;
362
f62b8bb8
AV		 363 switch (event) {
364 case MLX5_DEV_EVENT_PORT_UP:
365 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 366 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 367 break;
ee7f1220
EE		 368 case MLX5_DEV_EVENT_PPS:
369 eqe = (struct mlx5_eqe *)param;
370 ptp_event.type = PTP_CLOCK_EXTTS;
371 ptp_event.index = eqe->data.pps.pin;
372 ptp_event.timestamp =
373 timecounter_cyc2time(&priv->tstamp.clock,
374 be64_to_cpu(eqe->data.pps.time_stamp));
375 mlx5e_pps_event_handler(vpriv, &ptp_event);
376 break;
f62b8bb8
AV		 377 default:
378 break;
379 }
380}
381
f62b8bb8
AV		 382static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
383{
e0f46eb9 384 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 385}
386
387static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
388{
e0f46eb9 389 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 390 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 391}
392
7e426671
TT		 393static inline int mlx5e_get_wqe_mtt_sz(void)
394{
395 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
396 * To avoid copying garbage after the mtt array, we allocate
397 * a little more.
398 */
399 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
400 MLX5_UMR_MTT_ALIGNMENT);
401}
402
31391048
SM		 403static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
404 struct mlx5e_icosq *sq,
405 struct mlx5e_umr_wqe *wqe,
406 u16 ix)
7e426671
TT		 407{
408 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
409 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
410 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 411 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 412 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
413 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
414
415 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
416 ds_cnt);
417 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
418 cseg->imm = rq->mkey_be;
419
420 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 421 ucseg->xlt_octowords =
7e426671
TT		 422 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
423 ucseg->bsf_octowords =
424 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
425 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
426
427 dseg->lkey = sq->mkey_be;
428 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
429}
430
431static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
432 struct mlx5e_channel *c)
433{
434 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
435 int mtt_sz = mlx5e_get_wqe_mtt_sz();
436 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
437 int i;
438
21c59685
SM		 439 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
440 GFP_KERNEL, cpu_to_node(c->cpu));
441 if (!rq->mpwqe.info)
7e426671
TT		 442 goto err_out;
443
444 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 445 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 446 cpu_to_node(c->cpu));
21c59685 447 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 448 goto err_free_wqe_info;
449
450 for (i = 0; i < wq_sz; i++) {
21c59685 451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 452
21c59685 453 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 454 MLX5_UMR_ALIGN);
455 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
456 PCI_DMA_TODEVICE);
457 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
458 goto err_unmap_mtts;
459
460 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
461 }
462
463 return 0;
464
465err_unmap_mtts:
466 while (--i >= 0) {
21c59685 467 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 468
469 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
470 PCI_DMA_TODEVICE);
471 }
21c59685 472 kfree(rq->mpwqe.mtt_no_align);
7e426671 473err_free_wqe_info:
21c59685 474 kfree(rq->mpwqe.info);
7e426671
TT		 475
476err_out:
477 return -ENOMEM;
478}
479
480static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
481{
482 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
483 int mtt_sz = mlx5e_get_wqe_mtt_sz();
484 int i;
485
486 for (i = 0; i < wq_sz; i++) {
21c59685 487 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 488
489 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
490 PCI_DMA_TODEVICE);
491 }
21c59685
SM		 492 kfree(rq->mpwqe.mtt_no_align);
493 kfree(rq->mpwqe.info);
7e426671
TT		 494}
495
a43b25da 496static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 497 u64 npages, u8 page_shift,
498 struct mlx5_core_mkey *umr_mkey)
3608ae77 499{
3608ae77
TT		 500 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
501 void *mkc;
502 u32 *in;
503 int err;
504
ec8b9981
TT		 505 if (!MLX5E_VALID_NUM_MTTS(npages))
506 return -EINVAL;
507
1b9a07ee 508 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 509 if (!in)
510 return -ENOMEM;
511
512 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
513
3608ae77
TT		 514 MLX5_SET(mkc, mkc, free, 1);
515 MLX5_SET(mkc, mkc, umr_en, 1);
516 MLX5_SET(mkc, mkc, lw, 1);
517 MLX5_SET(mkc, mkc, lr, 1);
518 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
519
520 MLX5_SET(mkc, mkc, qpn, 0xffffff);
521 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 522 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 523 MLX5_SET(mkc, mkc, translations_octword_size,
524 MLX5_MTT_OCTW(npages));
ec8b9981 525 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 526
ec8b9981 527 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 528
529 kvfree(in);
530 return err;
531}
532
a43b25da 533static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 534{
6a9764ef 535 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 536
a43b25da 537 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 538}
539
3b77235b 540static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 541 struct mlx5e_params *params,
542 struct mlx5e_rq_param *rqp,
3b77235b 543 struct mlx5e_rq *rq)
f62b8bb8 544{
a43b25da 545 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 546 void *rqc = rqp->rqc;
f62b8bb8 547 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 548 u32 byte_count;
1bfecfca
SM		 549 u32 frag_sz;
550 int npages;
f62b8bb8
AV		 551 int wq_sz;
552 int err;
553 int i;
554
6a9764ef 555 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 556
6a9764ef 557 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 558 &rq->wq_ctrl);
559 if (err)
560 return err;
561
562 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
563
564 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 565
6a9764ef 566 rq->wq_type = params->rq_wq_type;
7e426671
TT		 567 rq->pdev = c->pdev;
568 rq->netdev = c->netdev;
a43b25da 569 rq->tstamp = c->tstamp;
7e426671
TT		 570 rq->channel = c;
571 rq->ix = c->ix;
a43b25da 572 rq->mdev = mdev;
97bc402d 573
6a9764ef 574 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 575 if (IS_ERR(rq->xdp_prog)) {
576 err = PTR_ERR(rq->xdp_prog);
577 rq->xdp_prog = NULL;
578 goto err_rq_wq_destroy;
579 }
7e426671 580
d8bec2b2 581 if (rq->xdp_prog) {
b5503b99 582 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 583 rq->rx_headroom = XDP_PACKET_HEADROOM;
584 } else {
585 rq->buff.map_dir = DMA_FROM_DEVICE;
586 rq->rx_headroom = MLX5_RX_HEADROOM;
587 }
b5503b99 588
6a9764ef 589 switch (rq->wq_type) {
461017cb 590 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 591
461017cb 592 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 593 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 594
20fd0c19
SM		 595 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
596 if (!rq->handle_rx_cqe) {
597 err = -EINVAL;
598 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
599 goto err_rq_wq_destroy;
600 }
601
6a9764ef
SM		 602 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
603 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca
SM		 604
605 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
606 byte_count = rq->buff.wqe_sz;
ec8b9981 607
a43b25da 608 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 609 if (err)
610 goto err_rq_wq_destroy;
ec8b9981
TT		 611 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
612
613 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
614 if (err)
615 goto err_destroy_umr_mkey;
461017cb
TT		 616 break;
617 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 618 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
619 GFP_KERNEL, cpu_to_node(c->cpu));
620 if (!rq->dma_info) {
461017cb
TT		 621 err = -ENOMEM;
622 goto err_rq_wq_destroy;
623 }
461017cb 624 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 625 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 626
20fd0c19
SM		 627 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
628 if (!rq->handle_rx_cqe) {
629 kfree(rq->dma_info);
630 err = -EINVAL;
631 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
632 goto err_rq_wq_destroy;
633 }
634
6a9764ef
SM		 635 rq->buff.wqe_sz = params->lro_en ?
636 params->lro_wqe_sz :
a43b25da 637 MLX5E_SW2HW_MTU(c->netdev->mtu);
1bfecfca
SM		 638 byte_count = rq->buff.wqe_sz;
639
640 /* calc the required page order */
d8bec2b2 641 frag_sz = rq->rx_headroom +
1bfecfca
SM		 642 byte_count /* packet data */ +
643 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
644 frag_sz = SKB_DATA_ALIGN(frag_sz);
645
646 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
647 rq->buff.page_order = order_base_2(npages);
648
461017cb 649 byte_count |= MLX5_HW_START_PADDING;
7e426671 650 rq->mkey_be = c->mkey_be;
461017cb 651 }
f62b8bb8
AV		 652
653 for (i = 0; i < wq_sz; i++) {
654 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
655
461017cb 656 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 657 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 658 }
659
cb3c7fd4 660 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
6a9764ef 661 rq->am.mode = params->rx_cq_period_mode;
4415a031
TT		 662 rq->page_cache.head = 0;
663 rq->page_cache.tail = 0;
664
f62b8bb8
AV		 665 return 0;
666
ec8b9981
TT		 667err_destroy_umr_mkey:
668 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
669
f62b8bb8 670err_rq_wq_destroy:
97bc402d
DB		 671 if (rq->xdp_prog)
672 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 673 mlx5_wq_destroy(&rq->wq_ctrl);
674
675 return err;
676}
677
3b77235b 678static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 679{
4415a031
TT		 680 int i;
681
86994156
RS		 682 if (rq->xdp_prog)
683 bpf_prog_put(rq->xdp_prog);
684
461017cb
TT		 685 switch (rq->wq_type) {
686 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 687 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 688 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 689 break;
690 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 691 kfree(rq->dma_info);
461017cb
TT		 692 }
693
4415a031
TT		 694 for (i = rq->page_cache.head; i != rq->page_cache.tail;
695 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
696 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
697
698 mlx5e_page_release(rq, dma_info, false);
699 }
f62b8bb8
AV		 700 mlx5_wq_destroy(&rq->wq_ctrl);
701}
702
6a9764ef
SM		 703static int mlx5e_create_rq(struct mlx5e_rq *rq,
704 struct mlx5e_rq_param *param)
f62b8bb8 705{
a43b25da 706 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 707
708 void *in;
709 void *rqc;
710 void *wq;
711 int inlen;
712 int err;
713
714 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
715 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 716 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 717 if (!in)
718 return -ENOMEM;
719
720 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
721 wq = MLX5_ADDR_OF(rqc, rqc, wq);
722
723 memcpy(rqc, param->rqc, sizeof(param->rqc));
724
97de9f31 725 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 726 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 727 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 728 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 729 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
730
731 mlx5_fill_page_array(&rq->wq_ctrl.buf,
732 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
733
7db22ffb 734 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 735
736 kvfree(in);
737
738 return err;
739}
740
36350114
GP		 741static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
742 int next_state)
f62b8bb8
AV		 743{
744 struct mlx5e_channel *c = rq->channel;
a43b25da 745 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 746
747 void *in;
748 void *rqc;
749 int inlen;
750 int err;
751
752 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 753 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 754 if (!in)
755 return -ENOMEM;
756
757 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
758
759 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
760 MLX5_SET(rqc, rqc, state, next_state);
761
7db22ffb 762 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 763
764 kvfree(in);
765
766 return err;
767}
768
102722fc
GE		 769static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
770{
771 struct mlx5e_channel *c = rq->channel;
772 struct mlx5e_priv *priv = c->priv;
773 struct mlx5_core_dev *mdev = priv->mdev;
774
775 void *in;
776 void *rqc;
777 int inlen;
778 int err;
779
780 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 781 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 782 if (!in)
783 return -ENOMEM;
784
785 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
786
787 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
788 MLX5_SET64(modify_rq_in, in, modify_bitmask,
789 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
790 MLX5_SET(rqc, rqc, scatter_fcs, enable);
791 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
792
793 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
794
795 kvfree(in);
796
797 return err;
798}
799
36350114
GP		 800static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
801{
802 struct mlx5e_channel *c = rq->channel;
a43b25da 803 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 804 void *in;
805 void *rqc;
806 int inlen;
807 int err;
808
809 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 810 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 811 if (!in)
812 return -ENOMEM;
813
814 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
815
816 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 817 MLX5_SET64(modify_rq_in, in, modify_bitmask,
818 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 819 MLX5_SET(rqc, rqc, vsd, vsd);
820 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
821
822 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
823
824 kvfree(in);
825
826 return err;
827}
828
3b77235b 829static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 830{
a43b25da 831 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 832}
833
834static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
835{
01c196a2 836 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 837 struct mlx5e_channel *c = rq->channel;
a43b25da 838
f62b8bb8 839 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 840 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 841
01c196a2 842 while (time_before(jiffies, exp_time)) {
6a9764ef 843 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 844 return 0;
845
846 msleep(20);
847 }
848
a43b25da 849 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 850 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 851 return -ETIMEDOUT;
852}
853
f2fde18c
SM		 854static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
855{
856 struct mlx5_wq_ll *wq = &rq->wq;
857 struct mlx5e_rx_wqe *wqe;
858 __be16 wqe_ix_be;
859 u16 wqe_ix;
860
8484f9ed
SM		 861 /* UMR WQE (if in progress) is always at wq->head */
862 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 863 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 864
f2fde18c
SM		 865 while (!mlx5_wq_ll_is_empty(wq)) {
866 wqe_ix_be = *wq->tail_next;
867 wqe_ix = be16_to_cpu(wqe_ix_be);
868 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
869 rq->dealloc_wqe(rq, wqe_ix);
870 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
871 &wqe->next.next_wqe_index);
872 }
873}
874
f62b8bb8 875static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 876 struct mlx5e_params *params,
f62b8bb8
AV		 877 struct mlx5e_rq_param *param,
878 struct mlx5e_rq *rq)
879{
880 int err;
881
6a9764ef 882 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 883 if (err)
884 return err;
885
3b77235b 886 err = mlx5e_create_rq(rq, param);
f62b8bb8 887 if (err)
3b77235b 888 goto err_free_rq;
f62b8bb8 889
36350114 890 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 891 if (err)
3b77235b 892 goto err_destroy_rq;
f62b8bb8 893
6a9764ef 894 if (params->rx_am_enabled)
cb3c7fd4
GR		 895 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
896
f62b8bb8
AV		 897 return 0;
898
f62b8bb8
AV		 899err_destroy_rq:
900 mlx5e_destroy_rq(rq);
3b77235b
SM		 901err_free_rq:
902 mlx5e_free_rq(rq);
f62b8bb8
AV		 903
904 return err;
905}
906
acc6c595
SM		 907static void mlx5e_activate_rq(struct mlx5e_rq *rq)
908{
909 struct mlx5e_icosq *sq = &rq->channel->icosq;
910 u16 pi = sq->pc & sq->wq.sz_m1;
911 struct mlx5e_tx_wqe *nopwqe;
912
913 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
914 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
915 sq->db.ico_wqe[pi].num_wqebbs = 1;
916 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
917 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
918}
919
920static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 921{
c0f1147d 922 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 923 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 924}
cb3c7fd4 925
acc6c595
SM		 926static void mlx5e_close_rq(struct mlx5e_rq *rq)
927{
928 cancel_work_sync(&rq->am.work);
f62b8bb8 929 mlx5e_destroy_rq(rq);
3b77235b
SM		 930 mlx5e_free_rx_descs(rq);
931 mlx5e_free_rq(rq);
f62b8bb8
AV		 932}
933
31391048 934static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 935{
31391048 936 kfree(sq->db.di);
b5503b99
SM		 937}
938
31391048 939static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 940{
941 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
942
31391048 943 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 944 GFP_KERNEL, numa);
31391048
SM		 945 if (!sq->db.di) {
946 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 947 return -ENOMEM;
948 }
949
950 return 0;
951}
952
31391048 953static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 954 struct mlx5e_params *params,
31391048
SM		 955 struct mlx5e_sq_param *param,
956 struct mlx5e_xdpsq *sq)
957{
958 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 959 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 960 int err;
961
962 sq->pdev = c->pdev;
963 sq->mkey_be = c->mkey_be;
964 sq->channel = c;
965 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 966 sq->min_inline_mode = params->tx_min_inline_mode;
31391048
SM		 967
968 param->wq.db_numa_node = cpu_to_node(c->cpu);
969 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
970 if (err)
971 return err;
972 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
973
974 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
975 if (err)
976 goto err_sq_wq_destroy;
977
978 return 0;
979
980err_sq_wq_destroy:
981 mlx5_wq_destroy(&sq->wq_ctrl);
982
983 return err;
984}
985
986static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
987{
988 mlx5e_free_xdpsq_db(sq);
989 mlx5_wq_destroy(&sq->wq_ctrl);
990}
991
992static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 993{
f10b7cc7 994 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 995}
996
31391048 997static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 998{
999 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1000
1001 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1002 GFP_KERNEL, numa);
1003 if (!sq->db.ico_wqe)
1004 return -ENOMEM;
1005
1006 return 0;
1007}
1008
31391048 1009static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1010 struct mlx5e_sq_param *param,
1011 struct mlx5e_icosq *sq)
f10b7cc7 1012{
31391048 1013 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1014 struct mlx5_core_dev *mdev = c->mdev;
31391048 1015 int err;
f10b7cc7 1016
31391048
SM		 1017 sq->pdev = c->pdev;
1018 sq->mkey_be = c->mkey_be;
1019 sq->channel = c;
1020 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1021
31391048
SM		 1022 param->wq.db_numa_node = cpu_to_node(c->cpu);
1023 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1024 if (err)
1025 return err;
1026 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1027
31391048
SM		 1028 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1029 if (err)
1030 goto err_sq_wq_destroy;
1031
1032 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1033
1034 return 0;
31391048
SM		 1035
1036err_sq_wq_destroy:
1037 mlx5_wq_destroy(&sq->wq_ctrl);
1038
1039 return err;
f62b8bb8
AV		 1040}
1041
31391048 1042static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1043{
31391048
SM		 1044 mlx5e_free_icosq_db(sq);
1045 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1046}
1047
31391048 1048static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1049{
31391048
SM		 1050 kfree(sq->db.wqe_info);
1051 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 1052}
1053
31391048 1054static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1055{
31391048
SM		 1056 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1057 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1058
31391048
SM		 1059 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1060 GFP_KERNEL, numa);
1061 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1062 GFP_KERNEL, numa);
77bdf895 1063 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1064 mlx5e_free_txqsq_db(sq);
1065 return -ENOMEM;
b5503b99 1066 }
31391048
SM		 1067
1068 sq->dma_fifo_mask = df_sz - 1;
1069
1070 return 0;
b5503b99
SM		 1071}
1072
31391048 1073static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1074 int txq_ix,
6a9764ef 1075 struct mlx5e_params *params,
31391048
SM		 1076 struct mlx5e_sq_param *param,
1077 struct mlx5e_txqsq *sq)
f62b8bb8 1078{
31391048 1079 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1080 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1081 int err;
1082
f10b7cc7 1083 sq->pdev = c->pdev;
a43b25da 1084 sq->tstamp = c->tstamp;
f10b7cc7
SM		 1085 sq->mkey_be = c->mkey_be;
1086 sq->channel = c;
acc6c595 1087 sq->txq_ix = txq_ix;
aff26157 1088 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1089 sq->max_inline = params->tx_max_inline;
1090 sq->min_inline_mode = params->tx_min_inline_mode;
f10b7cc7 1091
311c7c71 1092 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1093 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1094 if (err)
aff26157 1095 return err;
31391048 1096 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1097
31391048 1098 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1099 if (err)
f62b8bb8
AV		 1100 goto err_sq_wq_destroy;
1101
31391048 1102 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1103
1104 return 0;
1105
1106err_sq_wq_destroy:
1107 mlx5_wq_destroy(&sq->wq_ctrl);
1108
f62b8bb8
AV		 1109 return err;
1110}
1111
31391048 1112static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1113{
31391048 1114 mlx5e_free_txqsq_db(sq);
f62b8bb8 1115 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1116}
1117
33ad9711
SM		 1118struct mlx5e_create_sq_param {
1119 struct mlx5_wq_ctrl *wq_ctrl;
1120 u32 cqn;
1121 u32 tisn;
1122 u8 tis_lst_sz;
1123 u8 min_inline_mode;
1124};
1125
a43b25da 1126static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1127 struct mlx5e_sq_param *param,
1128 struct mlx5e_create_sq_param *csp,
1129 u32 *sqn)
f62b8bb8 1130{
f62b8bb8
AV		 1131 void *in;
1132 void *sqc;
1133 void *wq;
1134 int inlen;
1135 int err;
1136
1137 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1138 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1139 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1140 if (!in)
1141 return -ENOMEM;
1142
1143 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1144 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1145
1146 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1147 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1148 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1149 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1150
1151 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1152 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1153
33ad9711 1154 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1155
1156 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1157 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1158 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1159 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1160 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1161
33ad9711 1162 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1163
33ad9711 1164 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1165
1166 kvfree(in);
1167
1168 return err;
1169}
1170
33ad9711
SM		 1171struct mlx5e_modify_sq_param {
1172 int curr_state;
1173 int next_state;
1174 bool rl_update;
1175 int rl_index;
1176};
1177
a43b25da 1178static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1179 struct mlx5e_modify_sq_param *p)
f62b8bb8 1180{
f62b8bb8
AV		 1181 void *in;
1182 void *sqc;
1183 int inlen;
1184 int err;
1185
1186 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1187 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1188 if (!in)
1189 return -ENOMEM;
1190
1191 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1192
33ad9711
SM		 1193 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1194 MLX5_SET(sqc, sqc, state, p->next_state);
1195 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1196 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1197 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1198 }
f62b8bb8 1199
33ad9711 1200 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1201
1202 kvfree(in);
1203
1204 return err;
1205}
1206
a43b25da 1207static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1208{
a43b25da 1209 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1210}
1211
a43b25da 1212static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1213 struct mlx5e_sq_param *param,
1214 struct mlx5e_create_sq_param *csp,
1215 u32 *sqn)
f62b8bb8 1216{
33ad9711 1217 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1218 int err;
1219
a43b25da 1220 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1221 if (err)
1222 return err;
1223
1224 msp.curr_state = MLX5_SQC_STATE_RST;
1225 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1226 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1227 if (err)
a43b25da 1228 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1229
1230 return err;
1231}
1232
7f859ecf
SM		 1233static int mlx5e_set_sq_maxrate(struct net_device *dev,
1234 struct mlx5e_txqsq *sq, u32 rate);
1235
31391048 1236static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1237 u32 tisn,
acc6c595 1238 int txq_ix,
6a9764ef 1239 struct mlx5e_params *params,
31391048
SM		 1240 struct mlx5e_sq_param *param,
1241 struct mlx5e_txqsq *sq)
1242{
1243 struct mlx5e_create_sq_param csp = {};
7f859ecf 1244 u32 tx_rate;
f62b8bb8
AV		 1245 int err;
1246
6a9764ef 1247 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1248 if (err)
1249 return err;
1250
a43b25da 1251 csp.tisn = tisn;
31391048 1252 csp.tis_lst_sz = 1;
33ad9711
SM		 1253 csp.cqn = sq->cq.mcq.cqn;
1254 csp.wq_ctrl = &sq->wq_ctrl;
1255 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1256 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1257 if (err)
31391048 1258 goto err_free_txqsq;
f62b8bb8 1259
a43b25da 1260 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1261 if (tx_rate)
a43b25da 1262 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1263
f62b8bb8
AV		 1264 return 0;
1265
31391048 1266err_free_txqsq:
3b77235b 1267 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1268 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1269
1270 return err;
1271}
1272
acc6c595
SM		 1273static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1274{
a43b25da 1275 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1276 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1277 netdev_tx_reset_queue(sq->txq);
1278 netif_tx_start_queue(sq->txq);
1279}
1280
f62b8bb8
AV		 1281static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1282{
1283 __netif_tx_lock_bh(txq);
1284 netif_tx_stop_queue(txq);
1285 __netif_tx_unlock_bh(txq);
1286}
1287
acc6c595 1288static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1289{
33ad9711 1290 struct mlx5e_channel *c = sq->channel;
33ad9711 1291
c0f1147d 1292 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1293 /* prevent netif_tx_wake_queue */
33ad9711 1294 napi_synchronize(&c->napi);
29429f33 1295
31391048 1296 netif_tx_disable_queue(sq->txq);
f62b8bb8 1297
31391048
SM		 1298 /* last doorbell out, godspeed .. */
1299 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1300 struct mlx5e_tx_wqe *nop;
864b2d71 1301
77bdf895 1302 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1303 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1304 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1305 }
acc6c595
SM		 1306}
1307
1308static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1309{
1310 struct mlx5e_channel *c = sq->channel;
a43b25da 1311 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1312
a43b25da 1313 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1314 if (sq->rate_limit)
1315 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1316 mlx5e_free_txqsq_descs(sq);
1317 mlx5e_free_txqsq(sq);
1318}
1319
1320static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1321 struct mlx5e_params *params,
31391048
SM		 1322 struct mlx5e_sq_param *param,
1323 struct mlx5e_icosq *sq)
1324{
1325 struct mlx5e_create_sq_param csp = {};
1326 int err;
1327
6a9764ef 1328 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1329 if (err)
1330 return err;
1331
1332 csp.cqn = sq->cq.mcq.cqn;
1333 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1334 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1335 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1336 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1337 if (err)
1338 goto err_free_icosq;
1339
1340 return 0;
1341
1342err_free_icosq:
1343 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1344 mlx5e_free_icosq(sq);
1345
1346 return err;
1347}
1348
1349static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1350{
1351 struct mlx5e_channel *c = sq->channel;
1352
1353 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1354 napi_synchronize(&c->napi);
1355
a43b25da 1356 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1357 mlx5e_free_icosq(sq);
1358}
1359
1360static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1361 struct mlx5e_params *params,
31391048
SM		 1362 struct mlx5e_sq_param *param,
1363 struct mlx5e_xdpsq *sq)
1364{
1365 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1366 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1367 unsigned int inline_hdr_sz = 0;
1368 int err;
1369 int i;
1370
6a9764ef 1371 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1372 if (err)
1373 return err;
1374
1375 csp.tis_lst_sz = 1;
a43b25da 1376 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1377 csp.cqn = sq->cq.mcq.cqn;
1378 csp.wq_ctrl = &sq->wq_ctrl;
1379 csp.min_inline_mode = sq->min_inline_mode;
1380 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1381 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1382 if (err)
1383 goto err_free_xdpsq;
1384
1385 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1386 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1387 ds_cnt++;
1388 }
1389
1390 /* Pre initialize fixed WQE fields */
1391 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1392 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1393 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1394 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1395 struct mlx5_wqe_data_seg *dseg;
1396
1397 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1398 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1399
1400 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1401 dseg->lkey = sq->mkey_be;
1402 }
1403
1404 return 0;
1405
1406err_free_xdpsq:
1407 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1408 mlx5e_free_xdpsq(sq);
1409
1410 return err;
1411}
1412
1413static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1414{
1415 struct mlx5e_channel *c = sq->channel;
1416
1417 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1418 napi_synchronize(&c->napi);
1419
a43b25da 1420 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1421 mlx5e_free_xdpsq_descs(sq);
1422 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1423}
1424
95b6c6a5
EBE		 1425static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1426 struct mlx5e_cq_param *param,
1427 struct mlx5e_cq *cq)
f62b8bb8 1428{
f62b8bb8
AV		 1429 struct mlx5_core_cq *mcq = &cq->mcq;
1430 int eqn_not_used;
0b6e26ce 1431 unsigned int irqn;
f62b8bb8
AV		 1432 int err;
1433 u32 i;
1434
f62b8bb8
AV		 1435 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1436 &cq->wq_ctrl);
1437 if (err)
1438 return err;
1439
1440 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1441
f62b8bb8
AV		 1442 mcq->cqe_sz = 64;
1443 mcq->set_ci_db = cq->wq_ctrl.db.db;
1444 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1445 *mcq->set_ci_db = 0;
1446 *mcq->arm_db = 0;
1447 mcq->vector = param->eq_ix;
1448 mcq->comp = mlx5e_completion_event;
1449 mcq->event = mlx5e_cq_error_event;
1450 mcq->irqn = irqn;
f62b8bb8
AV		 1451
1452 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1453 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1454
1455 cqe->op_own = 0xf1;
1456 }
1457
a43b25da 1458 cq->mdev = mdev;
f62b8bb8
AV		 1459
1460 return 0;
1461}
1462
95b6c6a5
EBE		 1463static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1464 struct mlx5e_cq_param *param,
1465 struct mlx5e_cq *cq)
1466{
1467 struct mlx5_core_dev *mdev = c->priv->mdev;
1468 int err;
1469
1470 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1471 param->wq.db_numa_node = cpu_to_node(c->cpu);
1472 param->eq_ix = c->ix;
1473
1474 err = mlx5e_alloc_cq_common(mdev, param, cq);
1475
1476 cq->napi = &c->napi;
1477 cq->channel = c;
1478
1479 return err;
1480}
1481
3b77235b 1482static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1483{
1c1b5228 1484 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1485}
1486
3b77235b 1487static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1488{
a43b25da 1489 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1490 struct mlx5_core_cq *mcq = &cq->mcq;
1491
1492 void *in;
1493 void *cqc;
1494 int inlen;
0b6e26ce 1495 unsigned int irqn_not_used;
f62b8bb8
AV		 1496 int eqn;
1497 int err;
1498
1499 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1500 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1501 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1502 if (!in)
1503 return -ENOMEM;
1504
1505 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1506
1507 memcpy(cqc, param->cqc, sizeof(param->cqc));
1508
1c1b5228
TT		 1509 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1510 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1511
1512 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1513
9908aa29 1514 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1515 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1516 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1517 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1518 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1519 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1520
1521 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1522
1523 kvfree(in);
1524
1525 if (err)
1526 return err;
1527
1528 mlx5e_cq_arm(cq);
1529
1530 return 0;
1531}
1532
3b77235b 1533static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1534{
a43b25da 1535 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1536}
1537
1538static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1539 struct mlx5e_cq_moder moder,
f62b8bb8 1540 struct mlx5e_cq_param *param,
6a9764ef 1541 struct mlx5e_cq *cq)
f62b8bb8 1542{
a43b25da 1543 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1544 int err;
f62b8bb8 1545
3b77235b 1546 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1547 if (err)
1548 return err;
1549
3b77235b 1550 err = mlx5e_create_cq(cq, param);
f62b8bb8 1551 if (err)
3b77235b 1552 goto err_free_cq;
f62b8bb8 1553
7524a5d8 1554 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1555 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1556 return 0;
1557
3b77235b
SM		 1558err_free_cq:
1559 mlx5e_free_cq(cq);
f62b8bb8
AV		 1560
1561 return err;
1562}
1563
1564static void mlx5e_close_cq(struct mlx5e_cq *cq)
1565{
f62b8bb8 1566 mlx5e_destroy_cq(cq);
3b77235b 1567 mlx5e_free_cq(cq);
f62b8bb8
AV		 1568}
1569
1570static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1571{
1572 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1573}
1574
1575static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1576 struct mlx5e_params *params,
f62b8bb8
AV		 1577 struct mlx5e_channel_param *cparam)
1578{
f62b8bb8
AV		 1579 int err;
1580 int tc;
1581
1582 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1583 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1584 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1585 if (err)
1586 goto err_close_tx_cqs;
f62b8bb8
AV		 1587 }
1588
1589 return 0;
1590
1591err_close_tx_cqs:
1592 for (tc--; tc >= 0; tc--)
1593 mlx5e_close_cq(&c->sq[tc].cq);
1594
1595 return err;
1596}
1597
1598static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1599{
1600 int tc;
1601
1602 for (tc = 0; tc < c->num_tc; tc++)
1603 mlx5e_close_cq(&c->sq[tc].cq);
1604}
1605
1606static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1607 struct mlx5e_params *params,
f62b8bb8
AV		 1608 struct mlx5e_channel_param *cparam)
1609{
1610 int err;
1611 int tc;
1612
6a9764ef
SM		 1613 for (tc = 0; tc < params->num_tc; tc++) {
1614 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1615
a43b25da
SM		 1616 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1617 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1618 if (err)
1619 goto err_close_sqs;
1620 }
1621
1622 return 0;
1623
1624err_close_sqs:
1625 for (tc--; tc >= 0; tc--)
31391048 1626 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1627
1628 return err;
1629}
1630
1631static void mlx5e_close_sqs(struct mlx5e_channel *c)
1632{
1633 int tc;
1634
1635 for (tc = 0; tc < c->num_tc; tc++)
31391048 1636 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1637}
1638
507f0c81 1639static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1640 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1641{
1642 struct mlx5e_priv *priv = netdev_priv(dev);
1643 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1644 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1645 u16 rl_index = 0;
1646 int err;
1647
1648 if (rate == sq->rate_limit)
1649 /* nothing to do */
1650 return 0;
1651
1652 if (sq->rate_limit)
1653 /* remove current rl index to free space to next ones */
1654 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1655
1656 sq->rate_limit = 0;
1657
1658 if (rate) {
1659 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1660 if (err) {
1661 netdev_err(dev, "Failed configuring rate %u: %d\n",
1662 rate, err);
1663 return err;
1664 }
1665 }
1666
33ad9711
SM		 1667 msp.curr_state = MLX5_SQC_STATE_RDY;
1668 msp.next_state = MLX5_SQC_STATE_RDY;
1669 msp.rl_index = rl_index;
1670 msp.rl_update = true;
a43b25da 1671 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1672 if (err) {
1673 netdev_err(dev, "Failed configuring rate %u: %d\n",
1674 rate, err);
1675 /* remove the rate from the table */
1676 if (rate)
1677 mlx5_rl_remove_rate(mdev, rate);
1678 return err;
1679 }
1680
1681 sq->rate_limit = rate;
1682 return 0;
1683}
1684
1685static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1686{
1687 struct mlx5e_priv *priv = netdev_priv(dev);
1688 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1689 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1690 int err = 0;
1691
1692 if (!mlx5_rl_is_supported(mdev)) {
1693 netdev_err(dev, "Rate limiting is not supported on this device\n");
1694 return -EINVAL;
1695 }
1696
1697 /* rate is given in Mb/sec, HW config is in Kb/sec */
1698 rate = rate << 10;
1699
1700 /* Check whether rate in valid range, 0 is always valid */
1701 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1702 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1703 return -ERANGE;
1704 }
1705
1706 mutex_lock(&priv->state_lock);
1707 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1708 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1709 if (!err)
1710 priv->tx_rates[index] = rate;
1711 mutex_unlock(&priv->state_lock);
1712
1713 return err;
1714}
1715
f62b8bb8 1716static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1717 struct mlx5e_params *params,
f62b8bb8
AV		 1718 struct mlx5e_channel_param *cparam,
1719 struct mlx5e_channel **cp)
1720{
6a9764ef 1721 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8
AV		 1722 struct net_device *netdev = priv->netdev;
1723 int cpu = mlx5e_get_cpu(priv, ix);
1724 struct mlx5e_channel *c;
1725 int err;
1726
1727 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1728 if (!c)
1729 return -ENOMEM;
1730
1731 c->priv = priv;
a43b25da
SM		 1732 c->mdev = priv->mdev;
1733 c->tstamp = &priv->tstamp;
f62b8bb8
AV		 1734 c->ix = ix;
1735 c->cpu = cpu;
1736 c->pdev = &priv->mdev->pdev->dev;
1737 c->netdev = priv->netdev;
b50d292b 1738 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1739 c->num_tc = params->num_tc;
1740 c->xdp = !!params->xdp_prog;
cb3c7fd4 1741
f62b8bb8
AV		 1742 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1743
6a9764ef 1744 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1745 if (err)
1746 goto err_napi_del;
1747
6a9764ef 1748 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1749 if (err)
1750 goto err_close_icosq_cq;
1751
6a9764ef 1752 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1753 if (err)
1754 goto err_close_tx_cqs;
f62b8bb8 1755
d7a0ecab 1756 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1757 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1758 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1759 if (err)
1760 goto err_close_rx_cq;
1761
f62b8bb8
AV		 1762 napi_enable(&c->napi);
1763
6a9764ef 1764 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1765 if (err)
1766 goto err_disable_napi;
1767
6a9764ef 1768 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1769 if (err)
1770 goto err_close_icosq;
1771
6a9764ef 1772 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1773 if (err)
1774 goto err_close_sqs;
b5503b99 1775
6a9764ef 1776 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1777 if (err)
b5503b99 1778 goto err_close_xdp_sq;
f62b8bb8 1779
f62b8bb8
AV		 1780 *cp = c;
1781
1782 return 0;
b5503b99 1783err_close_xdp_sq:
d7a0ecab 1784 if (c->xdp)
31391048 1785 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1786
1787err_close_sqs:
1788 mlx5e_close_sqs(c);
1789
d3c9bc27 1790err_close_icosq:
31391048 1791 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1792
f62b8bb8
AV		 1793err_disable_napi:
1794 napi_disable(&c->napi);
d7a0ecab 1795 if (c->xdp)
31871f87 1796 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1797
1798err_close_rx_cq:
f62b8bb8
AV		 1799 mlx5e_close_cq(&c->rq.cq);
1800
1801err_close_tx_cqs:
1802 mlx5e_close_tx_cqs(c);
1803
d3c9bc27
TT		 1804err_close_icosq_cq:
1805 mlx5e_close_cq(&c->icosq.cq);
1806
f62b8bb8
AV		 1807err_napi_del:
1808 netif_napi_del(&c->napi);
1809 kfree(c);
1810
1811 return err;
1812}
1813
acc6c595
SM		 1814static void mlx5e_activate_channel(struct mlx5e_channel *c)
1815{
1816 int tc;
1817
1818 for (tc = 0; tc < c->num_tc; tc++)
1819 mlx5e_activate_txqsq(&c->sq[tc]);
1820 mlx5e_activate_rq(&c->rq);
a43b25da 1821 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1822}
1823
1824static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1825{
1826 int tc;
1827
1828 mlx5e_deactivate_rq(&c->rq);
1829 for (tc = 0; tc < c->num_tc; tc++)
1830 mlx5e_deactivate_txqsq(&c->sq[tc]);
1831}
1832
f62b8bb8
AV		 1833static void mlx5e_close_channel(struct mlx5e_channel *c)
1834{
1835 mlx5e_close_rq(&c->rq);
b5503b99 1836 if (c->xdp)
31391048 1837 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1838 mlx5e_close_sqs(c);
31391048 1839 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1840 napi_disable(&c->napi);
b5503b99 1841 if (c->xdp)
31871f87 1842 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1843 mlx5e_close_cq(&c->rq.cq);
1844 mlx5e_close_tx_cqs(c);
d3c9bc27 1845 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1846 netif_napi_del(&c->napi);
7ae92ae5 1847
f62b8bb8
AV		 1848 kfree(c);
1849}
1850
1851static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1852 struct mlx5e_params *params,
f62b8bb8
AV		 1853 struct mlx5e_rq_param *param)
1854{
1855 void *rqc = param->rqc;
1856 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1857
6a9764ef 1858 switch (params->rq_wq_type) {
461017cb 1859 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1860 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1861 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1862 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1863 break;
1864 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1865 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1866 }
1867
f62b8bb8
AV		 1868 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1869 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1870 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1871 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1872 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1873 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1874 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1875
311c7c71 1876 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1877 param->wq.linear = 1;
1878}
1879
556dd1b9
TT		 1880static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1881{
1882 void *rqc = param->rqc;
1883 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1884
1885 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1886 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1887}
1888
d3c9bc27
TT		 1889static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1890 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1891{
1892 void *sqc = param->sqc;
1893 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1894
f62b8bb8 1895 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1896 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1897
311c7c71 1898 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1899}
1900
1901static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1902 struct mlx5e_params *params,
d3c9bc27
TT		 1903 struct mlx5e_sq_param *param)
1904{
1905 void *sqc = param->sqc;
1906 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1907
1908 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1909 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
f62b8bb8
AV		 1910}
1911
1912static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1913 struct mlx5e_cq_param *param)
1914{
1915 void *cqc = param->cqc;
1916
30aa60b3 1917 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1918}
1919
1920static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1921 struct mlx5e_params *params,
f62b8bb8
AV		 1922 struct mlx5e_cq_param *param)
1923{
1924 void *cqc = param->cqc;
461017cb 1925 u8 log_cq_size;
f62b8bb8 1926
6a9764ef 1927 switch (params->rq_wq_type) {
461017cb 1928 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1929 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1930 break;
1931 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1932 log_cq_size = params->log_rq_size;
461017cb
TT		 1933 }
1934
1935 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1936 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1937 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1938 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1939 }
f62b8bb8
AV		 1940
1941 mlx5e_build_common_cq_param(priv, param);
1942}
1943
1944static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1945 struct mlx5e_params *params,
f62b8bb8
AV		 1946 struct mlx5e_cq_param *param)
1947{
1948 void *cqc = param->cqc;
1949
6a9764ef 1950 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1951
1952 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1953
1954 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1955}
1956
d3c9bc27 1957static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1958 u8 log_wq_size,
1959 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1960{
1961 void *cqc = param->cqc;
1962
1963 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1964
1965 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1966
1967 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1968}
1969
1970static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1971 u8 log_wq_size,
1972 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1973{
1974 void *sqc = param->sqc;
1975 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1976
1977 mlx5e_build_sq_param_common(priv, param);
1978
1979 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1980 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1981}
1982
b5503b99 1983static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1984 struct mlx5e_params *params,
b5503b99
SM		 1985 struct mlx5e_sq_param *param)
1986{
1987 void *sqc = param->sqc;
1988 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1989
1990 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1991 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1992}
1993
6a9764ef
SM		 1994static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1995 struct mlx5e_params *params,
1996 struct mlx5e_channel_param *cparam)
f62b8bb8 1997{
bc77b240 1998 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1999
6a9764ef
SM		 2000 mlx5e_build_rq_param(priv, params, &cparam->rq);
2001 mlx5e_build_sq_param(priv, params, &cparam->sq);
2002 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2003 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2004 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2005 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2006 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2007}
2008
55c2503d
SM		 2009int mlx5e_open_channels(struct mlx5e_priv *priv,
2010 struct mlx5e_channels *chs)
f62b8bb8 2011{
6b87663f 2012 struct mlx5e_channel_param *cparam;
03289b88 2013 int err = -ENOMEM;
f62b8bb8 2014 int i;
f62b8bb8 2015
6a9764ef 2016 chs->num = chs->params.num_channels;
03289b88 2017
ff9c852f 2018 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2019 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2020 if (!chs->c || !cparam)
2021 goto err_free;
f62b8bb8 2022
6a9764ef 2023 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2024 for (i = 0; i < chs->num; i++) {
6a9764ef 2025 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2026 if (err)
2027 goto err_close_channels;
2028 }
2029
6b87663f 2030 kfree(cparam);
f62b8bb8
AV		 2031 return 0;
2032
2033err_close_channels:
2034 for (i--; i >= 0; i--)
ff9c852f 2035 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2036
acc6c595 2037err_free:
ff9c852f 2038 kfree(chs->c);
6b87663f 2039 kfree(cparam);
ff9c852f 2040 chs->num = 0;
f62b8bb8
AV		 2041 return err;
2042}
2043
acc6c595 2044static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2045{
2046 int i;
2047
acc6c595
SM		 2048 for (i = 0; i < chs->num; i++)
2049 mlx5e_activate_channel(chs->c[i]);
2050}
2051
2052static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2053{
2054 int err = 0;
2055 int i;
2056
2057 for (i = 0; i < chs->num; i++) {
2058 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2059 if (err)
2060 break;
2061 }
2062
2063 return err;
2064}
2065
2066static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2067{
2068 int i;
2069
2070 for (i = 0; i < chs->num; i++)
2071 mlx5e_deactivate_channel(chs->c[i]);
2072}
2073
55c2503d 2074void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2075{
2076 int i;
c3b7c5c9 2077
ff9c852f
SM		 2078 for (i = 0; i < chs->num; i++)
2079 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2080
ff9c852f
SM		 2081 kfree(chs->c);
2082 chs->num = 0;
f62b8bb8
AV		 2083}
2084
a5f97fee
SM		 2085static int
2086mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2087{
2088 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2089 void *rqtc;
2090 int inlen;
2091 int err;
1da36696 2092 u32 *in;
a5f97fee 2093 int i;
f62b8bb8 2094
f62b8bb8 2095 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2096 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2097 if (!in)
2098 return -ENOMEM;
2099
2100 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2101
2102 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2103 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2104
a5f97fee
SM		 2105 for (i = 0; i < sz; i++)
2106 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2107
398f3351
HHZ		 2108 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2109 if (!err)
2110 rqt->enabled = true;
f62b8bb8
AV		 2111
2112 kvfree(in);
1da36696
TT		 2113 return err;
2114}
2115
cb67b832 2116void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2117{
398f3351
HHZ		 2118 rqt->enabled = false;
2119 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2120}
2121
8f493ffd 2122int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2123{
2124 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2125 int err;
6bfd390b 2126
8f493ffd
SM		 2127 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2128 if (err)
2129 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2130 return err;
6bfd390b
HHZ		 2131}
2132
cb67b832 2133int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2134{
398f3351 2135 struct mlx5e_rqt *rqt;
1da36696
TT		 2136 int err;
2137 int ix;
2138
6bfd390b 2139 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2140 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2141 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2142 if (err)
2143 goto err_destroy_rqts;
2144 }
2145
2146 return 0;
2147
2148err_destroy_rqts:
8f493ffd 2149 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2150 for (ix--; ix >= 0; ix--)
398f3351 2151 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2152
f62b8bb8
AV		 2153 return err;
2154}
2155
8f493ffd
SM		 2156void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2157{
2158 int i;
2159
2160 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2161 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2162}
2163
a5f97fee
SM		 2164static int mlx5e_rx_hash_fn(int hfunc)
2165{
2166 return (hfunc == ETH_RSS_HASH_TOP) ?
2167 MLX5_RX_HASH_FN_TOEPLITZ :
2168 MLX5_RX_HASH_FN_INVERTED_XOR8;
2169}
2170
2171static int mlx5e_bits_invert(unsigned long a, int size)
2172{
2173 int inv = 0;
2174 int i;
2175
2176 for (i = 0; i < size; i++)
2177 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2178
2179 return inv;
2180}
2181
2182static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2183 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2184{
2185 int i;
2186
2187 for (i = 0; i < sz; i++) {
2188 u32 rqn;
2189
2190 if (rrp.is_rss) {
2191 int ix = i;
2192
2193 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2194 ix = mlx5e_bits_invert(i, ilog2(sz));
2195
6a9764ef 2196 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2197 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2198 } else {
2199 rqn = rrp.rqn;
2200 }
2201 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2202 }
2203}
2204
2205int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2206 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2207{
2208 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2209 void *rqtc;
2210 int inlen;
1da36696 2211 u32 *in;
5c50368f
AS		 2212 int err;
2213
5c50368f 2214 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2215 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2216 if (!in)
2217 return -ENOMEM;
2218
2219 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2220
2221 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2222 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2223 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2224 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2225
2226 kvfree(in);
5c50368f
AS		 2227 return err;
2228}
2229
a5f97fee
SM		 2230static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2231 struct mlx5e_redirect_rqt_param rrp)
2232{
2233 if (!rrp.is_rss)
2234 return rrp.rqn;
2235
2236 if (ix >= rrp.rss.channels->num)
2237 return priv->drop_rq.rqn;
2238
2239 return rrp.rss.channels->c[ix]->rq.rqn;
2240}
2241
2242static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2243 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2244{
1da36696
TT		 2245 u32 rqtn;
2246 int ix;
2247
398f3351 2248 if (priv->indir_rqt.enabled) {
a5f97fee 2249 /* RSS RQ table */
398f3351 2250 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2251 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2252 }
2253
a5f97fee
SM		 2254 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2255 struct mlx5e_redirect_rqt_param direct_rrp = {
2256 .is_rss = false,
95632791
AM		 2257 {
2258 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2259 },
a5f97fee
SM		 2260 };
2261
2262 /* Direct RQ Tables */
398f3351
HHZ		 2263 if (!priv->direct_tir[ix].rqt.enabled)
2264 continue;
a5f97fee 2265
398f3351 2266 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2267 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2268 }
40ab6a6e
AS		 2269}
2270
a5f97fee
SM		 2271static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2272 struct mlx5e_channels *chs)
2273{
2274 struct mlx5e_redirect_rqt_param rrp = {
2275 .is_rss = true,
95632791
AM		 2276 {
2277 .rss = {
2278 .channels = chs,
2279 .hfunc = chs->params.rss_hfunc,
2280 }
2281 },
a5f97fee
SM		 2282 };
2283
2284 mlx5e_redirect_rqts(priv, rrp);
2285}
2286
2287static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2288{
2289 struct mlx5e_redirect_rqt_param drop_rrp = {
2290 .is_rss = false,
95632791
AM		 2291 {
2292 .rqn = priv->drop_rq.rqn,
2293 },
a5f97fee
SM		 2294 };
2295
2296 mlx5e_redirect_rqts(priv, drop_rrp);
2297}
2298
6a9764ef 2299static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2300{
6a9764ef 2301 if (!params->lro_en)
5c50368f
AS		 2302 return;
2303
2304#define ROUGH_MAX_L2_L3_HDR_SZ 256
2305
2306 MLX5_SET(tirc, tirc, lro_enable_mask,
2307 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2308 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2309 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2310 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2311 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2312}
2313
6a9764ef
SM		 2314void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2315 enum mlx5e_traffic_types tt,
2316 void *tirc)
bdfc028d 2317{
a100ff3e
GP		 2318 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2319
2320#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2321 MLX5_HASH_FIELD_SEL_DST_IP)
2322
2323#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2324 MLX5_HASH_FIELD_SEL_DST_IP |\
2325 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2326 MLX5_HASH_FIELD_SEL_L4_DPORT)
2327
2328#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2329 MLX5_HASH_FIELD_SEL_DST_IP |\
2330 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2331
6a9764ef
SM		 2332 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2333 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2334 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2335 rx_hash_toeplitz_key);
2336 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2337 rx_hash_toeplitz_key);
2338
2339 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2340 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2341 }
a100ff3e
GP		 2342
2343 switch (tt) {
2344 case MLX5E_TT_IPV4_TCP:
2345 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2346 MLX5_L3_PROT_TYPE_IPV4);
2347 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2348 MLX5_L4_PROT_TYPE_TCP);
2349 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2350 MLX5_HASH_IP_L4PORTS);
2351 break;
2352
2353 case MLX5E_TT_IPV6_TCP:
2354 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2355 MLX5_L3_PROT_TYPE_IPV6);
2356 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2357 MLX5_L4_PROT_TYPE_TCP);
2358 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2359 MLX5_HASH_IP_L4PORTS);
2360 break;
2361
2362 case MLX5E_TT_IPV4_UDP:
2363 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2364 MLX5_L3_PROT_TYPE_IPV4);
2365 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2366 MLX5_L4_PROT_TYPE_UDP);
2367 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2368 MLX5_HASH_IP_L4PORTS);
2369 break;
2370
2371 case MLX5E_TT_IPV6_UDP:
2372 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2373 MLX5_L3_PROT_TYPE_IPV6);
2374 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2375 MLX5_L4_PROT_TYPE_UDP);
2376 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2377 MLX5_HASH_IP_L4PORTS);
2378 break;
2379
2380 case MLX5E_TT_IPV4_IPSEC_AH:
2381 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2382 MLX5_L3_PROT_TYPE_IPV4);
2383 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2384 MLX5_HASH_IP_IPSEC_SPI);
2385 break;
2386
2387 case MLX5E_TT_IPV6_IPSEC_AH:
2388 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2389 MLX5_L3_PROT_TYPE_IPV6);
2390 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2391 MLX5_HASH_IP_IPSEC_SPI);
2392 break;
2393
2394 case MLX5E_TT_IPV4_IPSEC_ESP:
2395 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2396 MLX5_L3_PROT_TYPE_IPV4);
2397 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2398 MLX5_HASH_IP_IPSEC_SPI);
2399 break;
2400
2401 case MLX5E_TT_IPV6_IPSEC_ESP:
2402 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2403 MLX5_L3_PROT_TYPE_IPV6);
2404 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2405 MLX5_HASH_IP_IPSEC_SPI);
2406 break;
2407
2408 case MLX5E_TT_IPV4:
2409 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2410 MLX5_L3_PROT_TYPE_IPV4);
2411 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2412 MLX5_HASH_IP);
2413 break;
2414
2415 case MLX5E_TT_IPV6:
2416 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2417 MLX5_L3_PROT_TYPE_IPV6);
2418 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2419 MLX5_HASH_IP);
2420 break;
2421 default:
2422 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2423 }
bdfc028d
TT		 2424}
2425
ab0394fe 2426static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2427{
2428 struct mlx5_core_dev *mdev = priv->mdev;
2429
2430 void *in;
2431 void *tirc;
2432 int inlen;
2433 int err;
ab0394fe 2434 int tt;
1da36696 2435 int ix;
5c50368f
AS		 2436
2437 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2438 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2439 if (!in)
2440 return -ENOMEM;
2441
2442 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2443 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2444
6a9764ef 2445 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2446
1da36696 2447 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2448 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2449 inlen);
ab0394fe 2450 if (err)
1da36696 2451 goto free_in;
ab0394fe 2452 }
5c50368f 2453
6bfd390b 2454 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2455 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2456 in, inlen);
2457 if (err)
2458 goto free_in;
2459 }
2460
2461free_in:
5c50368f
AS		 2462 kvfree(in);
2463
2464 return err;
2465}
2466
cd255eff 2467static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2468{
40ab6a6e 2469 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2470 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2471 int err;
2472
cd255eff 2473 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2474 if (err)
2475 return err;
2476
cd255eff
SM		 2477 /* Update vport context MTU */
2478 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2479 return 0;
2480}
40ab6a6e 2481
cd255eff
SM		 2482static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2483{
2484 struct mlx5_core_dev *mdev = priv->mdev;
2485 u16 hw_mtu = 0;
2486 int err;
40ab6a6e 2487
cd255eff
SM		 2488 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2489 if (err || !hw_mtu) /* fallback to port oper mtu */
2490 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2491
2492 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2493}
2494
2e20a151 2495static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2496{
2e20a151 2497 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2498 u16 mtu;
2499 int err;
2500
2501 err = mlx5e_set_mtu(priv, netdev->mtu);
2502 if (err)
2503 return err;
40ab6a6e 2504
cd255eff
SM		 2505 mlx5e_query_mtu(priv, &mtu);
2506 if (mtu != netdev->mtu)
2507 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2508 __func__, mtu, netdev->mtu);
40ab6a6e 2509
cd255eff 2510 netdev->mtu = mtu;
40ab6a6e
AS		 2511 return 0;
2512}
2513
08fb1dac
SM		 2514static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2515{
2516 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2517 int nch = priv->channels.params.num_channels;
2518 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2519 int tc;
2520
2521 netdev_reset_tc(netdev);
2522
2523 if (ntc == 1)
2524 return;
2525
2526 netdev_set_num_tc(netdev, ntc);
2527
7ccdd084
RS		 2528 /* Map netdev TCs to offset 0
2529 * We have our own UP to TXQ mapping for QoS
2530 */
08fb1dac 2531 for (tc = 0; tc < ntc; tc++)
7ccdd084 2532 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2533}
2534
acc6c595
SM		 2535static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2536{
2537 struct mlx5e_channel *c;
2538 struct mlx5e_txqsq *sq;
2539 int i, tc;
2540
2541 for (i = 0; i < priv->channels.num; i++)
2542 for (tc = 0; tc < priv->profile->max_tc; tc++)
2543 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2544
2545 for (i = 0; i < priv->channels.num; i++) {
2546 c = priv->channels.c[i];
2547 for (tc = 0; tc < c->num_tc; tc++) {
2548 sq = &c->sq[tc];
2549 priv->txq2sq[sq->txq_ix] = sq;
2550 }
2551 }
2552}
2553
955bc480
SM		 2554static bool mlx5e_is_eswitch_vport_mngr(struct mlx5_core_dev *mdev)
2555{
2556 return (MLX5_CAP_GEN(mdev, vport_group_manager) &&
2557 MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH);
2558}
2559
603f4a45 2560void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2561{
9008ae07
SM		 2562 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2563 struct net_device *netdev = priv->netdev;
2564
2565 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2566 netif_set_real_num_tx_queues(netdev, num_txqs);
2567 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2568
acc6c595
SM		 2569 mlx5e_build_channels_tx_maps(priv);
2570 mlx5e_activate_channels(&priv->channels);
2571 netif_tx_start_all_queues(priv->netdev);
9008ae07 2572
955bc480 2573 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
9008ae07
SM		 2574 mlx5e_add_sqs_fwd_rules(priv);
2575
acc6c595 2576 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2577 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2578}
2579
603f4a45 2580void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2581{
9008ae07
SM		 2582 mlx5e_redirect_rqts_to_drop(priv);
2583
955bc480 2584 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
9008ae07
SM		 2585 mlx5e_remove_sqs_fwd_rules(priv);
2586
acc6c595
SM		 2587 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2588 * polling for inactive tx queues.
2589 */
2590 netif_tx_stop_all_queues(priv->netdev);
2591 netif_tx_disable(priv->netdev);
2592 mlx5e_deactivate_channels(&priv->channels);
2593}
2594
55c2503d 2595void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2596 struct mlx5e_channels *new_chs,
2597 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2598{
2599 struct net_device *netdev = priv->netdev;
2600 int new_num_txqs;
2601
2602 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2603
2604 netif_carrier_off(netdev);
2605
2606 if (new_num_txqs < netdev->real_num_tx_queues)
2607 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2608
2609 mlx5e_deactivate_priv_channels(priv);
2610 mlx5e_close_channels(&priv->channels);
2611
2612 priv->channels = *new_chs;
2613
2e20a151
SM		 2614 /* New channels are ready to roll, modify HW settings if needed */
2615 if (hw_modify)
2616 hw_modify(priv);
2617
55c2503d
SM		 2618 mlx5e_refresh_tirs(priv, false);
2619 mlx5e_activate_priv_channels(priv);
2620
2621 mlx5e_update_carrier(priv);
2622}
2623
40ab6a6e
AS		 2624int mlx5e_open_locked(struct net_device *netdev)
2625{
2626 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2627 int err;
2628
2629 set_bit(MLX5E_STATE_OPENED, &priv->state);
2630
ff9c852f 2631 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2632 if (err)
343b29f3 2633 goto err_clear_state_opened_flag;
40ab6a6e 2634
b676f653 2635 mlx5e_refresh_tirs(priv, false);
acc6c595 2636 mlx5e_activate_priv_channels(priv);
ce89ef36 2637 mlx5e_update_carrier(priv);
ef9814de 2638 mlx5e_timestamp_init(priv);
be4891af 2639
cb67b832
HHZ		 2640 if (priv->profile->update_stats)
2641 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2642
9b37b07f 2643 return 0;
343b29f3
AS		 2644
2645err_clear_state_opened_flag:
2646 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2647 return err;
40ab6a6e
AS		 2648}
2649
cb67b832 2650int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2651{
2652 struct mlx5e_priv *priv = netdev_priv(netdev);
2653 int err;
2654
2655 mutex_lock(&priv->state_lock);
2656 err = mlx5e_open_locked(netdev);
2657 mutex_unlock(&priv->state_lock);
2658
2659 return err;
2660}
2661
2662int mlx5e_close_locked(struct net_device *netdev)
2663{
2664 struct mlx5e_priv *priv = netdev_priv(netdev);
2665
a1985740
AS		 2666 /* May already be CLOSED in case a previous configuration operation
2667 * (e.g RX/TX queue size change) that involves close&open failed.
2668 */
2669 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2670 return 0;
2671
40ab6a6e
AS		 2672 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2673
ef9814de 2674 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2675 netif_carrier_off(priv->netdev);
acc6c595
SM		 2676 mlx5e_deactivate_priv_channels(priv);
2677 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2678
2679 return 0;
2680}
2681
cb67b832 2682int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2683{
2684 struct mlx5e_priv *priv = netdev_priv(netdev);
2685 int err;
2686
26e59d80
MHY		 2687 if (!netif_device_present(netdev))
2688 return -ENODEV;
2689
40ab6a6e
AS		 2690 mutex_lock(&priv->state_lock);
2691 err = mlx5e_close_locked(netdev);
2692 mutex_unlock(&priv->state_lock);
2693
2694 return err;
2695}
2696
a43b25da 2697static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2698 struct mlx5e_rq *rq,
2699 struct mlx5e_rq_param *param)
40ab6a6e 2700{
40ab6a6e
AS		 2701 void *rqc = param->rqc;
2702 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2703 int err;
2704
2705 param->wq.db_numa_node = param->wq.buf_numa_node;
2706
2707 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2708 &rq->wq_ctrl);
2709 if (err)
2710 return err;
2711
a43b25da 2712 rq->mdev = mdev;
40ab6a6e
AS		 2713
2714 return 0;
2715}
2716
a43b25da 2717static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2718 struct mlx5e_cq *cq,
2719 struct mlx5e_cq_param *param)
40ab6a6e 2720{
95b6c6a5 2721 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2722}
2723
a43b25da
SM		 2724static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2725 struct mlx5e_rq *drop_rq)
40ab6a6e 2726{
a43b25da
SM		 2727 struct mlx5e_cq_param cq_param = {};
2728 struct mlx5e_rq_param rq_param = {};
2729 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2730 int err;
2731
556dd1b9 2732 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2733
a43b25da 2734 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2735 if (err)
2736 return err;
2737
3b77235b 2738 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2739 if (err)
3b77235b 2740 goto err_free_cq;
40ab6a6e 2741
a43b25da 2742 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2743 if (err)
3b77235b 2744 goto err_destroy_cq;
40ab6a6e 2745
a43b25da 2746 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2747 if (err)
3b77235b 2748 goto err_free_rq;
40ab6a6e
AS		 2749
2750 return 0;
2751
3b77235b 2752err_free_rq:
a43b25da 2753 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2754
2755err_destroy_cq:
a43b25da 2756 mlx5e_destroy_cq(cq);
40ab6a6e 2757
3b77235b 2758err_free_cq:
a43b25da 2759 mlx5e_free_cq(cq);
3b77235b 2760
40ab6a6e
AS		 2761 return err;
2762}
2763
a43b25da 2764static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2765{
a43b25da
SM		 2766 mlx5e_destroy_rq(drop_rq);
2767 mlx5e_free_rq(drop_rq);
2768 mlx5e_destroy_cq(&drop_rq->cq);
2769 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2770}
2771
5426a0b2
SM		 2772int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2773 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2774{
c4f287c4 2775 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2776 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2777
08fb1dac 2778 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2779 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2780 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2781
2782 if (mlx5_lag_is_lacp_owner(mdev))
2783 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2784
5426a0b2 2785 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2786}
2787
5426a0b2 2788void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2789{
5426a0b2 2790 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2791}
2792
cb67b832 2793int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2794{
2795 int err;
2796 int tc;
2797
6bfd390b 2798 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2799 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2800 if (err)
2801 goto err_close_tises;
2802 }
2803
2804 return 0;
2805
2806err_close_tises:
2807 for (tc--; tc >= 0; tc--)
5426a0b2 2808 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2809
2810 return err;
2811}
2812
cb67b832 2813void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2814{
2815 int tc;
2816
6bfd390b 2817 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2818 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2819}
2820
6a9764ef
SM		 2821static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2822 enum mlx5e_traffic_types tt,
2823 u32 *tirc)
f62b8bb8 2824{
b50d292b 2825 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2826
6a9764ef 2827 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2828
4cbeaff5 2829 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2830 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
6a9764ef 2831 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
f62b8bb8
AV		 2832}
2833
6a9764ef 2834static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2835{
b50d292b 2836 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2837
6a9764ef 2838 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2839
2840 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2841 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2842 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2843}
2844
8f493ffd 2845int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2846{
724b2aa1 2847 struct mlx5e_tir *tir;
f62b8bb8
AV		 2848 void *tirc;
2849 int inlen;
2850 int err;
1da36696 2851 u32 *in;
1da36696 2852 int tt;
f62b8bb8
AV		 2853
2854 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2855 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2856 if (!in)
2857 return -ENOMEM;
2858
1da36696
TT		 2859 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2860 memset(in, 0, inlen);
724b2aa1 2861 tir = &priv->indir_tir[tt];
1da36696 2862 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2863 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2864 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2865 if (err)
40ab6a6e 2866 goto err_destroy_tirs;
f62b8bb8
AV		 2867 }
2868
6bfd390b
HHZ		 2869 kvfree(in);
2870
2871 return 0;
2872
2873err_destroy_tirs:
8f493ffd 2874 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
6bfd390b
HHZ		 2875 for (tt--; tt >= 0; tt--)
2876 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2877
2878 kvfree(in);
2879
2880 return err;
2881}
2882
cb67b832 2883int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2884{
2885 int nch = priv->profile->max_nch(priv->mdev);
2886 struct mlx5e_tir *tir;
2887 void *tirc;
2888 int inlen;
2889 int err;
2890 u32 *in;
2891 int ix;
2892
2893 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2894 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2895 if (!in)
2896 return -ENOMEM;
2897
1da36696
TT		 2898 for (ix = 0; ix < nch; ix++) {
2899 memset(in, 0, inlen);
724b2aa1 2900 tir = &priv->direct_tir[ix];
1da36696 2901 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2902 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2903 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2904 if (err)
2905 goto err_destroy_ch_tirs;
2906 }
2907
2908 kvfree(in);
2909
f62b8bb8
AV		 2910 return 0;
2911
1da36696 2912err_destroy_ch_tirs:
8f493ffd 2913 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 2914 for (ix--; ix >= 0; ix--)
724b2aa1 2915 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2916
1da36696 2917 kvfree(in);
f62b8bb8
AV		 2918
2919 return err;
2920}
2921
8f493ffd 2922void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2923{
2924 int i;
2925
1da36696 2926 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2927 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2928}
2929
cb67b832 2930void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2931{
2932 int nch = priv->profile->max_nch(priv->mdev);
2933 int i;
2934
2935 for (i = 0; i < nch; i++)
2936 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2937}
2938
102722fc
GE		 2939static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2940{
2941 int err = 0;
2942 int i;
2943
2944 for (i = 0; i < chs->num; i++) {
2945 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2946 if (err)
2947 return err;
2948 }
2949
2950 return 0;
2951}
2952
f6d96a20 2953static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2954{
2955 int err = 0;
2956 int i;
2957
ff9c852f
SM		 2958 for (i = 0; i < chs->num; i++) {
2959 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2960 if (err)
2961 return err;
2962 }
2963
2964 return 0;
2965}
2966
08fb1dac
SM		 2967static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2968{
2969 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 2970 struct mlx5e_channels new_channels = {};
08fb1dac
SM		 2971 int err = 0;
2972
2973 if (tc && tc != MLX5E_MAX_NUM_TC)
2974 return -EINVAL;
2975
2976 mutex_lock(&priv->state_lock);
2977
6f9485af
SM		 2978 new_channels.params = priv->channels.params;
2979 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 2980
20b6a1c7 2981 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 2982 priv->channels.params = new_channels.params;
2983 goto out;
2984 }
08fb1dac 2985
6f9485af
SM		 2986 err = mlx5e_open_channels(priv, &new_channels);
2987 if (err)
2988 goto out;
08fb1dac 2989
2e20a151 2990 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 2991out:
08fb1dac 2992 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 2993 return err;
2994}
2995
2996static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
a5fcf8a6
JP		 2997 u32 chain_index, __be16 proto,
2998 struct tc_to_netdev *tc)
08fb1dac 2999{
e8f887ac
AV		 3000 struct mlx5e_priv *priv = netdev_priv(dev);
3001
3002 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
3003 goto mqprio;
3004
a5fcf8a6
JP		 3005 if (chain_index)
3006 return -EOPNOTSUPP;
3007
e8f887ac 3008 switch (tc->type) {
e3a2b7ed
AV		 3009 case TC_SETUP_CLSFLOWER:
3010 switch (tc->cls_flower->command) {
3011 case TC_CLSFLOWER_REPLACE:
3012 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
3013 case TC_CLSFLOWER_DESTROY:
3014 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 3015 case TC_CLSFLOWER_STATS:
3016 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 3017 }
e8f887ac
AV		 3018 default:
3019 return -EOPNOTSUPP;
3020 }
3021
3022mqprio:
67ba422e 3023 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 3024 return -EINVAL;
3025
56f36acd
AN		 3026 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3027
3028 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
08fb1dac
SM		 3029}
3030
bc1f4470 3031static void
f62b8bb8
AV		 3032mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3033{
3034 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3035 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3036 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3037 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3038
370bad0f
OG		 3039 if (mlx5e_is_uplink_rep(priv)) {
3040 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3041 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3042 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3043 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3044 } else {
3045 stats->rx_packets = sstats->rx_packets;
3046 stats->rx_bytes = sstats->rx_bytes;
3047 stats->tx_packets = sstats->tx_packets;
3048 stats->tx_bytes = sstats->tx_bytes;
3049 stats->tx_dropped = sstats->tx_queue_dropped;
3050 }
269e6b3a
GP		 3051
3052 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3053
3054 stats->rx_length_errors =
9218b44d
GP		 3055 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3056 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3057 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3058 stats->rx_crc_errors =
9218b44d
GP		 3059 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3060 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3061 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 3062 stats->tx_carrier_errors =
9218b44d 3063 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 3064 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3065 stats->rx_frame_errors;
3066 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3067
3068 /* vport multicast also counts packets that are dropped due to steering
3069 * or rx out of buffer
3070 */
9218b44d
GP		 3071 stats->multicast =
3072 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3073}
3074
3075static void mlx5e_set_rx_mode(struct net_device *dev)
3076{
3077 struct mlx5e_priv *priv = netdev_priv(dev);
3078
7bb29755 3079 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3080}
3081
3082static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3083{
3084 struct mlx5e_priv *priv = netdev_priv(netdev);
3085 struct sockaddr *saddr = addr;
3086
3087 if (!is_valid_ether_addr(saddr->sa_data))
3088 return -EADDRNOTAVAIL;
3089
3090 netif_addr_lock_bh(netdev);
3091 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3092 netif_addr_unlock_bh(netdev);
3093
7bb29755 3094 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3095
3096 return 0;
3097}
3098
0e405443
GP		 3099#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3100 do { \
3101 if (enable) \
3102 netdev->features |= feature; \
3103 else \
3104 netdev->features &= ~feature; \
3105 } while (0)
3106
3107typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3108
3109static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3110{
3111 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3112 struct mlx5e_channels new_channels = {};
3113 int err = 0;
3114 bool reset;
f62b8bb8
AV		 3115
3116 mutex_lock(&priv->state_lock);
f62b8bb8 3117
2e20a151
SM		 3118 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3119 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3120
2e20a151
SM		 3121 new_channels.params = priv->channels.params;
3122 new_channels.params.lro_en = enable;
3123
3124 if (!reset) {
3125 priv->channels.params = new_channels.params;
3126 err = mlx5e_modify_tirs_lro(priv);
3127 goto out;
98e81b0a 3128 }
f62b8bb8 3129
2e20a151
SM		 3130 err = mlx5e_open_channels(priv, &new_channels);
3131 if (err)
3132 goto out;
0e405443 3133
2e20a151
SM		 3134 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3135out:
9b37b07f 3136 mutex_unlock(&priv->state_lock);
0e405443
GP		 3137 return err;
3138}
3139
3140static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3141{
3142 struct mlx5e_priv *priv = netdev_priv(netdev);
3143
3144 if (enable)
3145 mlx5e_enable_vlan_filter(priv);
3146 else
3147 mlx5e_disable_vlan_filter(priv);
3148
3149 return 0;
3150}
3151
3152static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3153{
3154 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3155
0e405443 3156 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3157 netdev_err(netdev,
3158 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3159 return -EINVAL;
3160 }
3161
0e405443
GP		 3162 return 0;
3163}
3164
94cb1ebb
EBE		 3165static int set_feature_rx_all(struct net_device *netdev, bool enable)
3166{
3167 struct mlx5e_priv *priv = netdev_priv(netdev);
3168 struct mlx5_core_dev *mdev = priv->mdev;
3169
3170 return mlx5_set_port_fcs(mdev, !enable);
3171}
3172
102722fc
GE		 3173static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3174{
3175 struct mlx5e_priv *priv = netdev_priv(netdev);
3176 int err;
3177
3178 mutex_lock(&priv->state_lock);
3179
3180 priv->channels.params.scatter_fcs_en = enable;
3181 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3182 if (err)
3183 priv->channels.params.scatter_fcs_en = !enable;
3184
3185 mutex_unlock(&priv->state_lock);
3186
3187 return err;
3188}
3189
36350114
GP		 3190static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3191{
3192 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3193 int err = 0;
36350114
GP		 3194
3195 mutex_lock(&priv->state_lock);
3196
6a9764ef 3197 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3198 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3199 goto unlock;
3200
3201 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3202 if (err)
6a9764ef 3203 priv->channels.params.vlan_strip_disable = enable;
36350114 3204
ff9c852f 3205unlock:
36350114
GP		 3206 mutex_unlock(&priv->state_lock);
3207
3208 return err;
3209}
3210
45bf454a
MG		 3211#ifdef CONFIG_RFS_ACCEL
3212static int set_feature_arfs(struct net_device *netdev, bool enable)
3213{
3214 struct mlx5e_priv *priv = netdev_priv(netdev);
3215 int err;
3216
3217 if (enable)
3218 err = mlx5e_arfs_enable(priv);
3219 else
3220 err = mlx5e_arfs_disable(priv);
3221
3222 return err;
3223}
3224#endif
3225
0e405443
GP		 3226static int mlx5e_handle_feature(struct net_device *netdev,
3227 netdev_features_t wanted_features,
3228 netdev_features_t feature,
3229 mlx5e_feature_handler feature_handler)
3230{
3231 netdev_features_t changes = wanted_features ^ netdev->features;
3232 bool enable = !!(wanted_features & feature);
3233 int err;
3234
3235 if (!(changes & feature))
3236 return 0;
3237
3238 err = feature_handler(netdev, enable);
3239 if (err) {
3240 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3241 enable ? "Enable" : "Disable", feature, err);
3242 return err;
3243 }
3244
3245 MLX5E_SET_FEATURE(netdev, feature, enable);
3246 return 0;
3247}
3248
3249static int mlx5e_set_features(struct net_device *netdev,
3250 netdev_features_t features)
3251{
3252 int err;
3253
3254 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3255 set_feature_lro);
3256 err |= mlx5e_handle_feature(netdev, features,
3257 NETIF_F_HW_VLAN_CTAG_FILTER,
3258 set_feature_vlan_filter);
3259 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3260 set_feature_tc_num_filters);
94cb1ebb
EBE		 3261 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3262 set_feature_rx_all);
102722fc
GE		 3263 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3264 set_feature_rx_fcs);
36350114
GP		 3265 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3266 set_feature_rx_vlan);
45bf454a
MG		 3267#ifdef CONFIG_RFS_ACCEL
3268 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3269 set_feature_arfs);
3270#endif
0e405443
GP		 3271
3272 return err ? -EINVAL : 0;
f62b8bb8
AV		 3273}
3274
3275static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3276{
3277 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3278 struct mlx5e_channels new_channels = {};
3279 int curr_mtu;
98e81b0a 3280 int err = 0;
506753b0 3281 bool reset;
f62b8bb8 3282
f62b8bb8 3283 mutex_lock(&priv->state_lock);
98e81b0a 3284
6a9764ef
SM		 3285 reset = !priv->channels.params.lro_en &&
3286 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3287 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3288
2e20a151 3289 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3290
2e20a151 3291 curr_mtu = netdev->mtu;
f62b8bb8 3292 netdev->mtu = new_mtu;
98e81b0a 3293
2e20a151
SM		 3294 if (!reset) {
3295 mlx5e_set_dev_port_mtu(priv);
3296 goto out;
3297 }
98e81b0a 3298
2e20a151
SM		 3299 new_channels.params = priv->channels.params;
3300 err = mlx5e_open_channels(priv, &new_channels);
3301 if (err) {
3302 netdev->mtu = curr_mtu;
3303 goto out;
3304 }
3305
3306 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3307
2e20a151
SM		 3308out:
3309 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3310 return err;
3311}
3312
ef9814de
EBE		 3313static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3314{
3315 switch (cmd) {
3316 case SIOCSHWTSTAMP:
3317 return mlx5e_hwstamp_set(dev, ifr);
3318 case SIOCGHWTSTAMP:
3319 return mlx5e_hwstamp_get(dev, ifr);
3320 default:
3321 return -EOPNOTSUPP;
3322 }
3323}
3324
66e49ded
SM		 3325static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3326{
3327 struct mlx5e_priv *priv = netdev_priv(dev);
3328 struct mlx5_core_dev *mdev = priv->mdev;
3329
3330 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3331}
3332
79aab093
MS		 3333static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3334 __be16 vlan_proto)
66e49ded
SM		 3335{
3336 struct mlx5e_priv *priv = netdev_priv(dev);
3337 struct mlx5_core_dev *mdev = priv->mdev;
3338
79aab093
MS		 3339 if (vlan_proto != htons(ETH_P_8021Q))
3340 return -EPROTONOSUPPORT;
3341
66e49ded
SM		 3342 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3343 vlan, qos);
3344}
3345
f942380c
MHY		 3346static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3347{
3348 struct mlx5e_priv *priv = netdev_priv(dev);
3349 struct mlx5_core_dev *mdev = priv->mdev;
3350
3351 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3352}
3353
1edc57e2
MHY		 3354static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3355{
3356 struct mlx5e_priv *priv = netdev_priv(dev);
3357 struct mlx5_core_dev *mdev = priv->mdev;
3358
3359 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3360}
bd77bf1c
MHY		 3361
3362static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3363 int max_tx_rate)
3364{
3365 struct mlx5e_priv *priv = netdev_priv(dev);
3366 struct mlx5_core_dev *mdev = priv->mdev;
3367
bd77bf1c 3368 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3369 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3370}
3371
66e49ded
SM		 3372static int mlx5_vport_link2ifla(u8 esw_link)
3373{
3374 switch (esw_link) {
3375 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3376 return IFLA_VF_LINK_STATE_DISABLE;
3377 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3378 return IFLA_VF_LINK_STATE_ENABLE;
3379 }
3380 return IFLA_VF_LINK_STATE_AUTO;
3381}
3382
3383static int mlx5_ifla_link2vport(u8 ifla_link)
3384{
3385 switch (ifla_link) {
3386 case IFLA_VF_LINK_STATE_DISABLE:
3387 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3388 case IFLA_VF_LINK_STATE_ENABLE:
3389 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3390 }
3391 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3392}
3393
3394static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3395 int link_state)
3396{
3397 struct mlx5e_priv *priv = netdev_priv(dev);
3398 struct mlx5_core_dev *mdev = priv->mdev;
3399
3400 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3401 mlx5_ifla_link2vport(link_state));
3402}
3403
3404static int mlx5e_get_vf_config(struct net_device *dev,
3405 int vf, struct ifla_vf_info *ivi)
3406{
3407 struct mlx5e_priv *priv = netdev_priv(dev);
3408 struct mlx5_core_dev *mdev = priv->mdev;
3409 int err;
3410
3411 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3412 if (err)
3413 return err;
3414 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3415 return 0;
3416}
3417
3418static int mlx5e_get_vf_stats(struct net_device *dev,
3419 int vf, struct ifla_vf_stats *vf_stats)
3420{
3421 struct mlx5e_priv *priv = netdev_priv(dev);
3422 struct mlx5_core_dev *mdev = priv->mdev;
3423
3424 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3425 vf_stats);
3426}
3427
1ad9a00a
PB		 3428static void mlx5e_add_vxlan_port(struct net_device *netdev,
3429 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3430{
3431 struct mlx5e_priv *priv = netdev_priv(netdev);
3432
974c3f30
AD		 3433 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3434 return;
3435
b3f63c3d
MF		 3436 if (!mlx5e_vxlan_allowed(priv->mdev))
3437 return;
3438
974c3f30 3439 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3440}
3441
1ad9a00a
PB		 3442static void mlx5e_del_vxlan_port(struct net_device *netdev,
3443 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3444{
3445 struct mlx5e_priv *priv = netdev_priv(netdev);
3446
974c3f30
AD		 3447 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3448 return;
3449
b3f63c3d
MF		 3450 if (!mlx5e_vxlan_allowed(priv->mdev))
3451 return;
3452
974c3f30 3453 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3454}
3455
3456static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3457 struct sk_buff *skb,
3458 netdev_features_t features)
3459{
3460 struct udphdr *udph;
3461 u16 proto;
3462 u16 port = 0;
3463
3464 switch (vlan_get_protocol(skb)) {
3465 case htons(ETH_P_IP):
3466 proto = ip_hdr(skb)->protocol;
3467 break;
3468 case htons(ETH_P_IPV6):
3469 proto = ipv6_hdr(skb)->nexthdr;
3470 break;
3471 default:
3472 goto out;
3473 }
3474
3475 if (proto == IPPROTO_UDP) {
3476 udph = udp_hdr(skb);
3477 port = be16_to_cpu(udph->dest);
3478 }
3479
3480 /* Verify if UDP port is being offloaded by HW */
3481 if (port && mlx5e_vxlan_lookup_port(priv, port))
3482 return features;
3483
3484out:
3485 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3486 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3487}
3488
3489static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3490 struct net_device *netdev,
3491 netdev_features_t features)
3492{
3493 struct mlx5e_priv *priv = netdev_priv(netdev);
3494
3495 features = vlan_features_check(skb, features);
3496 features = vxlan_features_check(skb, features);
3497
3498 /* Validate if the tunneled packet is being offloaded by HW */
3499 if (skb->encapsulation &&
3500 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3501 return mlx5e_vxlan_features_check(priv, skb, features);
3502
3503 return features;
3504}
3505
3947ca18
DJ		 3506static void mlx5e_tx_timeout(struct net_device *dev)
3507{
3508 struct mlx5e_priv *priv = netdev_priv(dev);
3509 bool sched_work = false;
3510 int i;
3511
3512 netdev_err(dev, "TX timeout detected\n");
3513
6a9764ef 3514 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3515 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3516
2c1ccc99 3517 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3518 continue;
3519 sched_work = true;
c0f1147d 3520 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3521 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3522 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3523 }
3524
3525 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3526 schedule_work(&priv->tx_timeout_work);
3527}
3528
86994156
RS		 3529static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3530{
3531 struct mlx5e_priv *priv = netdev_priv(netdev);
3532 struct bpf_prog *old_prog;
3533 int err = 0;
3534 bool reset, was_opened;
3535 int i;
3536
3537 mutex_lock(&priv->state_lock);
3538
3539 if ((netdev->features & NETIF_F_LRO) && prog) {
3540 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3541 err = -EINVAL;
3542 goto unlock;
3543 }
3544
3545 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3546 /* no need for full reset when exchanging programs */
6a9764ef 3547 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3548
3549 if (was_opened && reset)
3550 mlx5e_close_locked(netdev);
c54c0629
DB		 3551 if (was_opened && !reset) {
3552 /* num_channels is invariant here, so we can take the
3553 * batched reference right upfront.
3554 */
6a9764ef 3555 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3556 if (IS_ERR(prog)) {
3557 err = PTR_ERR(prog);
3558 goto unlock;
3559 }
3560 }
86994156 3561
c54c0629
DB		 3562 /* exchange programs, extra prog reference we got from caller
3563 * as long as we don't fail from this point onwards.
3564 */
6a9764ef 3565 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3566 if (old_prog)
3567 bpf_prog_put(old_prog);
3568
3569 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3570 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3571
3572 if (was_opened && reset)
3573 mlx5e_open_locked(netdev);
3574
3575 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3576 goto unlock;
3577
3578 /* exchanging programs w/o reset, we update ref counts on behalf
3579 * of the channels RQs here.
3580 */
ff9c852f
SM		 3581 for (i = 0; i < priv->channels.num; i++) {
3582 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3583
c0f1147d 3584 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3585 napi_synchronize(&c->napi);
3586 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3587
3588 old_prog = xchg(&c->rq.xdp_prog, prog);
3589
c0f1147d 3590 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3591 /* napi_schedule in case we have missed anything */
3592 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3593 napi_schedule(&c->napi);
3594
3595 if (old_prog)
3596 bpf_prog_put(old_prog);
3597 }
3598
3599unlock:
3600 mutex_unlock(&priv->state_lock);
3601 return err;
3602}
3603
821b2e29 3604static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 3605{
3606 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 3607 const struct bpf_prog *xdp_prog;
3608 u32 prog_id = 0;
86994156 3609
821b2e29
MKL		 3610 mutex_lock(&priv->state_lock);
3611 xdp_prog = priv->channels.params.xdp_prog;
3612 if (xdp_prog)
3613 prog_id = xdp_prog->aux->id;
3614 mutex_unlock(&priv->state_lock);
3615
3616 return prog_id;
86994156
RS		 3617}
3618
3619static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3620{
3621 switch (xdp->command) {
3622 case XDP_SETUP_PROG:
3623 return mlx5e_xdp_set(dev, xdp->prog);
3624 case XDP_QUERY_PROG:
821b2e29
MKL		 3625 xdp->prog_id = mlx5e_xdp_query(dev);
3626 xdp->prog_attached = !!xdp->prog_id;
86994156
RS		 3627 return 0;
3628 default:
3629 return -EINVAL;
3630 }
3631}
3632
80378384
CO		 3633#ifdef CONFIG_NET_POLL_CONTROLLER
3634/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3635 * reenabling interrupts.
3636 */
3637static void mlx5e_netpoll(struct net_device *dev)
3638{
3639 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3640 struct mlx5e_channels *chs = &priv->channels;
3641
80378384
CO		 3642 int i;
3643
ff9c852f
SM		 3644 for (i = 0; i < chs->num; i++)
3645 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3646}
3647#endif
3648
b0eed40e 3649static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3650 .ndo_open = mlx5e_open,
3651 .ndo_stop = mlx5e_close,
3652 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3653 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3654 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3655 .ndo_get_stats64 = mlx5e_get_stats,
3656 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3657 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3658 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3659 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3660 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3661 .ndo_change_mtu = mlx5e_change_mtu,
3662 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3663 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3664#ifdef CONFIG_RFS_ACCEL
3665 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3666#endif
3947ca18 3667 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3668 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3669#ifdef CONFIG_NET_POLL_CONTROLLER
3670 .ndo_poll_controller = mlx5e_netpoll,
3671#endif
b0eed40e
SM		 3672};
3673
3674static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3675 .ndo_open = mlx5e_open,
3676 .ndo_stop = mlx5e_close,
3677 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3678 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3679 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3680 .ndo_get_stats64 = mlx5e_get_stats,
3681 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3682 .ndo_set_mac_address = mlx5e_set_mac,
3683 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3684 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3685 .ndo_set_features = mlx5e_set_features,
3686 .ndo_change_mtu = mlx5e_change_mtu,
3687 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3688 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3689 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3690 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3691 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3692#ifdef CONFIG_RFS_ACCEL
3693 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3694#endif
b0eed40e
SM		 3695 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3696 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3697 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3698 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3699 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3700 .ndo_get_vf_config = mlx5e_get_vf_config,
3701 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3702 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3703 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3704 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3705#ifdef CONFIG_NET_POLL_CONTROLLER
3706 .ndo_poll_controller = mlx5e_netpoll,
3707#endif
370bad0f
OG		 3708 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3709 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3710};
3711
3712static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3713{
3714 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3715 return -EOPNOTSUPP;
f62b8bb8
AV		 3716 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3717 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3718 !MLX5_CAP_ETH(mdev, csum_cap) ||
3719 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3720 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3721 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3722 MLX5_CAP_FLOWTABLE(mdev,
3723 flow_table_properties_nic_receive.max_ft_level)
3724 < 3) {
f62b8bb8
AV		 3725 mlx5_core_warn(mdev,
3726 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3727 return -EOPNOTSUPP;
f62b8bb8 3728 }
66189961
TT		 3729 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3730 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 3731 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 3732 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 3733
f62b8bb8
AV		 3734 return 0;
3735}
3736
58d52291
AS		 3737u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3738{
3739 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3740
3741 return bf_buf_size -
3742 sizeof(struct mlx5e_tx_wqe) +
3743 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3744}
3745
d8c9660d
TT		 3746void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3747 u32 *indirection_rqt, int len,
85082dba
TT		 3748 int num_channels)
3749{
d8c9660d
TT		 3750 int node = mdev->priv.numa_node;
3751 int node_num_of_cores;
85082dba
TT		 3752 int i;
3753
d8c9660d
TT		 3754 if (node == -1)
3755 node = first_online_node;
3756
3757 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3758
3759 if (node_num_of_cores)
3760 num_channels = min_t(int, num_channels, node_num_of_cores);
3761
85082dba
TT		 3762 for (i = 0; i < len; i++)
3763 indirection_rqt[i] = i % num_channels;
3764}
3765
b797a684
SM		 3766static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3767{
3768 enum pcie_link_width width;
3769 enum pci_bus_speed speed;
3770 int err = 0;
3771
3772 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3773 if (err)
3774 return err;
3775
3776 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3777 return -EINVAL;
3778
3779 switch (speed) {
3780 case PCIE_SPEED_2_5GT:
3781 *pci_bw = 2500 * width;
3782 break;
3783 case PCIE_SPEED_5_0GT:
3784 *pci_bw = 5000 * width;
3785 break;
3786 case PCIE_SPEED_8_0GT:
3787 *pci_bw = 8000 * width;
3788 break;
3789 default:
3790 return -EINVAL;
3791 }
3792
3793 return 0;
3794}
3795
3796static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3797{
3798 return (link_speed && pci_bw &&
3799 (pci_bw < 40000) && (pci_bw < link_speed));
3800}
3801
0f6e4cf6
EBE		 3802static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3803{
3804 return !(link_speed && pci_bw &&
3805 (pci_bw <= 16000) && (pci_bw < link_speed));
3806}
3807
9908aa29
TT		 3808void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3809{
3810 params->rx_cq_period_mode = cq_period_mode;
3811
3812 params->rx_cq_moderation.pkts =
3813 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3814 params->rx_cq_moderation.usec =
3815 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3816
3817 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3818 params->rx_cq_moderation.usec =
3819 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 3820
457fcd8a
SM		 3821 if (params->rx_am_enabled)
3822 params->rx_cq_moderation =
3823 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3824
6a9764ef
SM		 3825 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3826 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3827}
3828
2b029556
SM		 3829u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3830{
3831 int i;
3832
3833 /* The supported periods are organized in ascending order */
3834 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3835 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3836 break;
3837
3838 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3839}
3840
8f493ffd
SM		 3841void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3842 struct mlx5e_params *params,
3843 u16 max_channels)
f62b8bb8 3844{
6a9764ef 3845 u8 cq_period_mode = 0;
b797a684
SM		 3846 u32 link_speed = 0;
3847 u32 pci_bw = 0;
2fc4bfb7 3848
6a9764ef
SM		 3849 params->num_channels = max_channels;
3850 params->num_tc = 1;
2b029556 3851
0f6e4cf6
EBE		 3852 mlx5e_get_max_linkspeed(mdev, &link_speed);
3853 mlx5e_get_pci_bw(mdev, &pci_bw);
3854 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3855 link_speed, pci_bw);
3856
6a9764ef
SM		 3857 /* SQ */
3858 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3859 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3860 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3861
b797a684 3862 /* set CQE compression */
6a9764ef 3863 params->rx_cqe_compress_def = false;
b797a684 3864 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 3865 MLX5_CAP_GEN(mdev, vport_group_manager))
6a9764ef 3866 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
0f6e4cf6 3867
6a9764ef
SM		 3868 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3869
3870 /* RQ */
3871 mlx5e_set_rq_params(mdev, params);
b797a684 3872
6a9764ef 3873 /* HW LRO */
5426a0b2 3874 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 3875 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0f6e4cf6 3876 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
6a9764ef 3877 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 3878
6a9764ef
SM		 3879 /* CQ moderation params */
3880 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3881 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3882 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3883 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3884 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
9908aa29 3885
6a9764ef
SM		 3886 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3887 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
9908aa29 3888
6a9764ef
SM		 3889 /* TX inline */
3890 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3891 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3892 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
a6f402e4 3893 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
6a9764ef 3894 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
a6f402e4 3895
6a9764ef
SM		 3896 /* RSS */
3897 params->rss_hfunc = ETH_RSS_HASH_XOR;
3898 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3899 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3900 MLX5E_INDIR_RQT_SIZE, max_channels);
3901}
f62b8bb8 3902
6a9764ef
SM		 3903static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3904 struct net_device *netdev,
3905 const struct mlx5e_profile *profile,
3906 void *ppriv)
3907{
3908 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 3909
6a9764ef
SM		 3910 priv->mdev = mdev;
3911 priv->netdev = netdev;
3912 priv->profile = profile;
3913 priv->ppriv = ppriv;
2d75b2bc 3914
6a9764ef 3915 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 3916
f62b8bb8
AV		 3917 mutex_init(&priv->state_lock);
3918
3919 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3920 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3921 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3922 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3923}
3924
3925static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3926{
3927 struct mlx5e_priv *priv = netdev_priv(netdev);
3928
e1d7d349 3929 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3930 if (is_zero_ether_addr(netdev->dev_addr) &&
3931 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3932 eth_hw_addr_random(netdev);
3933 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3934 }
f62b8bb8
AV		 3935}
3936
cb67b832
HHZ		 3937static const struct switchdev_ops mlx5e_switchdev_ops = {
3938 .switchdev_port_attr_get = mlx5e_attr_get,
3939};
3940
6bfd390b 3941static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3942{
3943 struct mlx5e_priv *priv = netdev_priv(netdev);
3944 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3945 bool fcs_supported;
3946 bool fcs_enabled;
f62b8bb8
AV		 3947
3948 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3949
08fb1dac 3950 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3951 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3952#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3953 if (MLX5_CAP_GEN(mdev, qos))
3954 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3955#endif
3956 } else {
b0eed40e 3957 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3958 }
66e49ded 3959
f62b8bb8
AV		 3960 netdev->watchdog_timeo = 15 * HZ;
3961
3962 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3963
12be4b21 3964 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3965 netdev->vlan_features |= NETIF_F_IP_CSUM;
3966 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3967 netdev->vlan_features |= NETIF_F_GRO;
3968 netdev->vlan_features |= NETIF_F_TSO;
3969 netdev->vlan_features |= NETIF_F_TSO6;
3970 netdev->vlan_features |= NETIF_F_RXCSUM;
3971 netdev->vlan_features |= NETIF_F_RXHASH;
3972
3973 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3974 netdev->vlan_features |= NETIF_F_LRO;
3975
3976 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3977 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3978 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3979 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3980
b3f63c3d 3981 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3982 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3983 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3984 NETIF_F_GSO_PARTIAL;
b3f63c3d 3985 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3986 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3987 netdev->hw_enc_features |= NETIF_F_TSO;
3988 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3989 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3990 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3991 NETIF_F_GSO_PARTIAL;
3992 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3993 }
3994
94cb1ebb
EBE		 3995 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3996
3997 if (fcs_supported)
3998 netdev->hw_features |= NETIF_F_RXALL;
3999
102722fc
GE		 4000 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4001 netdev->hw_features |= NETIF_F_RXFCS;
4002
f62b8bb8 4003 netdev->features = netdev->hw_features;
6a9764ef 4004 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4005 netdev->features &= ~NETIF_F_LRO;
4006
94cb1ebb
EBE		 4007 if (fcs_enabled)
4008 netdev->features &= ~NETIF_F_RXALL;
4009
102722fc
GE		 4010 if (!priv->channels.params.scatter_fcs_en)
4011 netdev->features &= ~NETIF_F_RXFCS;
4012
e8f887ac
AV		 4013#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4014 if (FT_CAP(flow_modify_en) &&
4015 FT_CAP(modify_root) &&
4016 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4017 FT_CAP(flow_table_modify)) {
4018 netdev->hw_features |= NETIF_F_HW_TC;
4019#ifdef CONFIG_RFS_ACCEL
4020 netdev->hw_features |= NETIF_F_NTUPLE;
4021#endif
4022 }
e8f887ac 4023
f62b8bb8
AV		 4024 netdev->features |= NETIF_F_HIGHDMA;
4025
4026 netdev->priv_flags |= IFF_UNICAST_FLT;
4027
4028 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 4029
4030#ifdef CONFIG_NET_SWITCHDEV
4031 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4032 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4033#endif
f62b8bb8
AV		 4034}
4035
593cf338
RS		 4036static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4037{
4038 struct mlx5_core_dev *mdev = priv->mdev;
4039 int err;
4040
4041 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4042 if (err) {
4043 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4044 priv->q_counter = 0;
4045 }
4046}
4047
4048static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4049{
4050 if (!priv->q_counter)
4051 return;
4052
4053 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4054}
4055
6bfd390b
HHZ		 4056static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4057 struct net_device *netdev,
127ea380
HHZ		 4058 const struct mlx5e_profile *profile,
4059 void *ppriv)
6bfd390b
HHZ		 4060{
4061 struct mlx5e_priv *priv = netdev_priv(netdev);
4062
127ea380 4063 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 4064 mlx5e_build_nic_netdev(netdev);
4065 mlx5e_vxlan_init(priv);
4066}
4067
4068static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4069{
4070 mlx5e_vxlan_cleanup(priv);
127ea380 4071
6a9764ef
SM		 4072 if (priv->channels.params.xdp_prog)
4073 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 4074}
4075
4076static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4077{
4078 struct mlx5_core_dev *mdev = priv->mdev;
4079 int err;
6bfd390b 4080
8f493ffd
SM		 4081 err = mlx5e_create_indirect_rqt(priv);
4082 if (err)
6bfd390b 4083 return err;
6bfd390b
HHZ		 4084
4085 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4086 if (err)
6bfd390b 4087 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4088
4089 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4090 if (err)
6bfd390b 4091 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4092
4093 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4094 if (err)
6bfd390b 4095 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4096
4097 err = mlx5e_create_flow_steering(priv);
4098 if (err) {
4099 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4100 goto err_destroy_direct_tirs;
4101 }
4102
4103 err = mlx5e_tc_init(priv);
4104 if (err)
4105 goto err_destroy_flow_steering;
4106
4107 return 0;
4108
4109err_destroy_flow_steering:
4110 mlx5e_destroy_flow_steering(priv);
4111err_destroy_direct_tirs:
4112 mlx5e_destroy_direct_tirs(priv);
4113err_destroy_indirect_tirs:
4114 mlx5e_destroy_indirect_tirs(priv);
4115err_destroy_direct_rqts:
8f493ffd 4116 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4117err_destroy_indirect_rqts:
4118 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4119 return err;
4120}
4121
4122static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4123{
6bfd390b
HHZ		 4124 mlx5e_tc_cleanup(priv);
4125 mlx5e_destroy_flow_steering(priv);
4126 mlx5e_destroy_direct_tirs(priv);
4127 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4128 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4129 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4130}
4131
4132static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4133{
4134 int err;
4135
4136 err = mlx5e_create_tises(priv);
4137 if (err) {
4138 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4139 return err;
4140 }
4141
4142#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4143 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4144#endif
4145 return 0;
4146}
4147
4148static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4149{
4150 struct net_device *netdev = priv->netdev;
4151 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4152 u16 max_mtu;
4153
4154 mlx5e_init_l2_addr(priv);
4155
4156 /* MTU range: 68 - hw-specific max */
4157 netdev->min_mtu = ETH_MIN_MTU;
4158 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4159 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4160 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4161
7907f23a
AH		 4162 mlx5_lag_add(mdev, netdev);
4163
6bfd390b 4164 mlx5e_enable_async_events(priv);
127ea380 4165
1d447a39
SM		 4166 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4167 mlx5e_register_vport_reps(priv);
2c3b5bee 4168
610e89e0
SM		 4169 if (netdev->reg_state != NETREG_REGISTERED)
4170 return;
4171
4172 /* Device already registered: sync netdev system state */
4173 if (mlx5e_vxlan_allowed(mdev)) {
4174 rtnl_lock();
4175 udp_tunnel_get_rx_info(netdev);
4176 rtnl_unlock();
4177 }
4178
4179 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4180
4181 rtnl_lock();
4182 if (netif_running(netdev))
4183 mlx5e_open(netdev);
4184 netif_device_attach(netdev);
4185 rtnl_unlock();
6bfd390b
HHZ		 4186}
4187
4188static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4189{
3deef8ce 4190 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4191
2c3b5bee
SM		 4192 rtnl_lock();
4193 if (netif_running(priv->netdev))
4194 mlx5e_close(priv->netdev);
4195 netif_device_detach(priv->netdev);
4196 rtnl_unlock();
4197
6bfd390b 4198 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4199
3deef8ce 4200 if (MLX5_CAP_GEN(mdev, vport_group_manager))
1d447a39
SM		 4201 mlx5e_unregister_vport_reps(priv);
4202
6bfd390b 4203 mlx5e_disable_async_events(priv);
3deef8ce 4204 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4205}
4206
4207static const struct mlx5e_profile mlx5e_nic_profile = {
4208 .init = mlx5e_nic_init,
4209 .cleanup = mlx5e_nic_cleanup,
4210 .init_rx = mlx5e_init_nic_rx,
4211 .cleanup_rx = mlx5e_cleanup_nic_rx,
4212 .init_tx = mlx5e_init_nic_tx,
4213 .cleanup_tx = mlx5e_cleanup_nic_tx,
4214 .enable = mlx5e_nic_enable,
4215 .disable = mlx5e_nic_disable,
3834a5e6 4216 .update_stats = mlx5e_update_ndo_stats,
6bfd390b 4217 .max_nch = mlx5e_get_max_num_channels,
20fd0c19
SM		 4218 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4219 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4220 .max_tc = MLX5E_MAX_NUM_TC,
4221};
4222
2c3b5bee
SM		 4223/* mlx5e generic netdev management API (move to en_common.c) */
4224
26e59d80
MHY		 4225struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4226 const struct mlx5e_profile *profile,
4227 void *ppriv)
f62b8bb8 4228{
26e59d80 4229 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4230 struct net_device *netdev;
4231 struct mlx5e_priv *priv;
f62b8bb8 4232
08fb1dac 4233 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4234 nch * profile->max_tc,
08fb1dac 4235 nch);
f62b8bb8
AV		 4236 if (!netdev) {
4237 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4238 return NULL;
4239 }
4240
be4891af
SM		 4241#ifdef CONFIG_RFS_ACCEL
4242 netdev->rx_cpu_rmap = mdev->rmap;
4243#endif
4244
127ea380 4245 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4246
4247 netif_carrier_off(netdev);
4248
4249 priv = netdev_priv(netdev);
4250
7bb29755
MF		 4251 priv->wq = create_singlethread_workqueue("mlx5e");
4252 if (!priv->wq)
26e59d80
MHY		 4253 goto err_cleanup_nic;
4254
4255 return netdev;
4256
4257err_cleanup_nic:
4258 profile->cleanup(priv);
4259 free_netdev(netdev);
4260
4261 return NULL;
4262}
4263
2c3b5bee 4264int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4265{
2c3b5bee 4266 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4267 const struct mlx5e_profile *profile;
26e59d80
MHY		 4268 int err;
4269
26e59d80
MHY		 4270 profile = priv->profile;
4271 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4272
6bfd390b
HHZ		 4273 err = profile->init_tx(priv);
4274 if (err)
ec8b9981 4275 goto out;
5c50368f 4276
a43b25da 4277 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4278 if (err) {
4279 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4280 goto err_cleanup_tx;
5c50368f
AS		 4281 }
4282
6bfd390b
HHZ		 4283 err = profile->init_rx(priv);
4284 if (err)
5c50368f 4285 goto err_close_drop_rq;
5c50368f 4286
593cf338
RS		 4287 mlx5e_create_q_counter(priv);
4288
6bfd390b
HHZ		 4289 if (profile->enable)
4290 profile->enable(priv);
f62b8bb8 4291
26e59d80 4292 return 0;
5c50368f
AS		 4293
4294err_close_drop_rq:
a43b25da 4295 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4296
6bfd390b
HHZ		 4297err_cleanup_tx:
4298 profile->cleanup_tx(priv);
5c50368f 4299
26e59d80
MHY		 4300out:
4301 return err;
f62b8bb8
AV		 4302}
4303
2c3b5bee 4304void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4305{
26e59d80
MHY		 4306 const struct mlx5e_profile *profile = priv->profile;
4307
4308 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4309
37f304d1
SM		 4310 if (profile->disable)
4311 profile->disable(priv);
4312 flush_workqueue(priv->wq);
4313
26e59d80
MHY		 4314 mlx5e_destroy_q_counter(priv);
4315 profile->cleanup_rx(priv);
a43b25da 4316 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4317 profile->cleanup_tx(priv);
26e59d80
MHY		 4318 cancel_delayed_work_sync(&priv->update_stats_work);
4319}
4320
2c3b5bee
SM		 4321void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4322{
4323 const struct mlx5e_profile *profile = priv->profile;
4324 struct net_device *netdev = priv->netdev;
4325
4326 destroy_workqueue(priv->wq);
4327 if (profile->cleanup)
4328 profile->cleanup(priv);
4329 free_netdev(netdev);
4330}
4331
26e59d80
MHY		 4332/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4333 * hardware contexts and to connect it to the current netdev.
4334 */
4335static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4336{
4337 struct mlx5e_priv *priv = vpriv;
4338 struct net_device *netdev = priv->netdev;
4339 int err;
4340
4341 if (netif_device_present(netdev))
4342 return 0;
4343
4344 err = mlx5e_create_mdev_resources(mdev);
4345 if (err)
4346 return err;
4347
2c3b5bee 4348 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4349 if (err) {
4350 mlx5e_destroy_mdev_resources(mdev);
4351 return err;
4352 }
4353
4354 return 0;
4355}
4356
4357static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4358{
4359 struct mlx5e_priv *priv = vpriv;
4360 struct net_device *netdev = priv->netdev;
4361
4362 if (!netif_device_present(netdev))
4363 return;
4364
2c3b5bee 4365 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4366 mlx5e_destroy_mdev_resources(mdev);
4367}
4368
b50d292b
HHZ		 4369static void *mlx5e_add(struct mlx5_core_dev *mdev)
4370{
127ea380 4371 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4372 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
1d447a39 4373 struct mlx5e_rep_priv *rpriv = NULL;
26e59d80
MHY		 4374 void *priv;
4375 int vport;
4376 int err;
4377 struct net_device *netdev;
b50d292b 4378
26e59d80
MHY		 4379 err = mlx5e_check_required_hca_cap(mdev);
4380 if (err)
b50d292b
HHZ		 4381 return NULL;
4382
1d447a39
SM		 4383 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
4384 rpriv = kzalloc(sizeof(*rpriv), GFP_KERNEL);
4385 if (!rpriv) {
4386 mlx5_core_warn(mdev,
4387 "Not creating net device, Failed to alloc rep priv data\n");
4388 return NULL;
4389 }
4390 rpriv->rep = &esw->offloads.vport_reps[0];
4391 }
127ea380 4392
1d447a39 4393 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4394 if (!netdev) {
4395 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4396 goto err_unregister_reps;
4397 }
4398
4399 priv = netdev_priv(netdev);
4400
4401 err = mlx5e_attach(mdev, priv);
4402 if (err) {
4403 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4404 goto err_destroy_netdev;
4405 }
4406
4407 err = register_netdev(netdev);
4408 if (err) {
4409 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4410 goto err_detach;
b50d292b 4411 }
26e59d80
MHY		 4412
4413 return priv;
4414
4415err_detach:
4416 mlx5e_detach(mdev, priv);
4417
4418err_destroy_netdev:
2c3b5bee 4419 mlx5e_destroy_netdev(priv);
26e59d80
MHY		 4420
4421err_unregister_reps:
4422 for (vport = 1; vport < total_vfs; vport++)
4423 mlx5_eswitch_unregister_vport_rep(esw, vport);
4424
1d447a39 4425 kfree(rpriv);
26e59d80 4426 return NULL;
b50d292b
HHZ		 4427}
4428
b50d292b
HHZ		 4429static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4430{
4431 struct mlx5e_priv *priv = vpriv;
1d447a39 4432 void *ppriv = priv->ppriv;
127ea380 4433
5e1e93c7 4434 unregister_netdev(priv->netdev);
26e59d80 4435 mlx5e_detach(mdev, vpriv);
2c3b5bee 4436 mlx5e_destroy_netdev(priv);
1d447a39 4437 kfree(ppriv);
b50d292b
HHZ		 4438}
4439
f62b8bb8
AV		 4440static void *mlx5e_get_netdev(void *vpriv)
4441{
4442 struct mlx5e_priv *priv = vpriv;
4443
4444 return priv->netdev;
4445}
4446
4447static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4448 .add = mlx5e_add,
4449 .remove = mlx5e_remove,
26e59d80
MHY		 4450 .attach = mlx5e_attach,
4451 .detach = mlx5e_detach,
f62b8bb8
AV		 4452 .event = mlx5e_async_event,
4453 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4454 .get_dev = mlx5e_get_netdev,
4455};
4456
4457void mlx5e_init(void)
4458{
665bc539 4459 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4460 mlx5_register_interface(&mlx5e_interface);
4461}
4462
4463void mlx5e_cleanup(void)
4464{
4465 mlx5_unregister_interface(&mlx5e_interface);
4466}
ubuntu-bionic-kernel mirror