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net/mlx5e: Add link down events counter
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
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f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8
AV		 41
42struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45};
46
47struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
58d52291 50 u16 max_inline;
d3c9bc27 51 bool icosq;
f62b8bb8
AV		 52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
58};
59
60struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
d3c9bc27 63 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
d3c9bc27 66 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 67};
68
69static void mlx5e_update_carrier(struct mlx5e_priv *priv)
70{
71 struct mlx5_core_dev *mdev = priv->mdev;
72 u8 port_state;
73
74 port_state = mlx5_query_vport_state(mdev,
e7546514 75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 76
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
79 else
80 netif_carrier_off(priv->netdev);
81}
82
83static void mlx5e_update_carrier_work(struct work_struct *work)
84{
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
86 update_carrier_work);
87
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
92}
93
9218b44d 94static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 95{
9218b44d 96 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
9218b44d 99 u64 tx_offload_none = 0;
f62b8bb8
AV		 100 int i, j;
101
9218b44d 102 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
105
faf4478b
GP		 106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
f62b8bb8
AV		 108 s->lro_packets += rq_stats->lro_packets;
109 s->lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
bbceefce 111 s->rx_csum_sw += rq_stats->csum_sw;
f62b8bb8 112 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 113 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 114 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 115 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
f62b8bb8 116
a4418a6c 117 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 118 sq_stats = &priv->channel[i]->sq[j].stats;
119
faf4478b
GP		 120 s->tx_packets += sq_stats->packets;
121 s->tx_bytes += sq_stats->bytes;
f62b8bb8
AV		 122 s->tso_packets += sq_stats->tso_packets;
123 s->tso_bytes += sq_stats->tso_bytes;
89db09eb
MF		 124 s->tso_inner_packets += sq_stats->tso_inner_packets;
125 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 126 s->tx_queue_stopped += sq_stats->stopped;
127 s->tx_queue_wake += sq_stats->wake;
128 s->tx_queue_dropped += sq_stats->dropped;
89db09eb 129 s->tx_csum_inner += sq_stats->csum_offload_inner;
f62b8bb8
AV		 130 tx_offload_none += sq_stats->csum_offload_none;
131 }
132 }
133
9218b44d
GP		 134 /* Update calculated offload counters */
135 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
136 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
137 s->rx_csum_sw;
121fcdc8
GP		 138
139 s->link_down_events = MLX5_GET(ppcnt_reg,
140 priv->stats.pport.phy_counters,
141 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 142}
143
144static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
145{
146 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
147 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
148 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
149 struct mlx5_core_dev *mdev = priv->mdev;
150
f62b8bb8
AV		 151 memset(in, 0, sizeof(in));
152
153 MLX5_SET(query_vport_counter_in, in, opcode,
154 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
155 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
156 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
157
158 memset(out, 0, outlen);
159
9218b44d
GP		 160 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
161}
162
163static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
164{
165 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
166 struct mlx5_core_dev *mdev = priv->mdev;
167 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 168 int prio;
9218b44d
GP		 169 void *out;
170 u32 *in;
171
172 in = mlx5_vzalloc(sz);
173 if (!in)
f62b8bb8
AV		 174 goto free_out;
175
9218b44d 176 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 177
9218b44d
GP		 178 out = pstats->IEEE_802_3_counters;
179 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
180 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 181
9218b44d
GP		 182 out = pstats->RFC_2863_counters;
183 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
184 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
185
186 out = pstats->RFC_2819_counters;
187 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
188 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 189
121fcdc8
GP		 190 out = pstats->phy_counters;
191 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
192 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
193
cf678570
GP		 194 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
195 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
196 out = pstats->per_prio_counters[prio];
197 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
198 mlx5_core_access_reg(mdev, in, sz, out, sz,
199 MLX5_REG_PPCNT, 0, 0);
200 }
201
f62b8bb8 202free_out:
9218b44d
GP		 203 kvfree(in);
204}
205
206static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
207{
208 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
209
210 if (!priv->q_counter)
211 return;
212
213 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
214 &qcnt->rx_out_of_buffer);
215}
216
217void mlx5e_update_stats(struct mlx5e_priv *priv)
218{
9218b44d
GP		 219 mlx5e_update_q_counter(priv);
220 mlx5e_update_vport_counters(priv);
221 mlx5e_update_pport_counters(priv);
121fcdc8 222 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 223}
224
225static void mlx5e_update_stats_work(struct work_struct *work)
226{
227 struct delayed_work *dwork = to_delayed_work(work);
228 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
229 update_stats_work);
230 mutex_lock(&priv->state_lock);
231 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
232 mlx5e_update_stats(priv);
233 schedule_delayed_work(dwork,
234 msecs_to_jiffies(
235 MLX5E_UPDATE_STATS_INTERVAL));
236 }
237 mutex_unlock(&priv->state_lock);
238}
239
daa21560
TT		 240static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
241 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 242{
daa21560
TT		 243 struct mlx5e_priv *priv = vpriv;
244
245 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
246 return;
247
f62b8bb8
AV		 248 switch (event) {
249 case MLX5_DEV_EVENT_PORT_UP:
250 case MLX5_DEV_EVENT_PORT_DOWN:
251 schedule_work(&priv->update_carrier_work);
252 break;
253
254 default:
255 break;
256 }
257}
258
f62b8bb8
AV		 259static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
260{
261 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
262}
263
264static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
265{
f62b8bb8 266 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
daa21560 267 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 268}
269
facc9699
SM		 270#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
271#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
272
f62b8bb8
AV		 273static int mlx5e_create_rq(struct mlx5e_channel *c,
274 struct mlx5e_rq_param *param,
275 struct mlx5e_rq *rq)
276{
277 struct mlx5e_priv *priv = c->priv;
278 struct mlx5_core_dev *mdev = priv->mdev;
279 void *rqc = param->rqc;
280 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 281 u32 byte_count;
f62b8bb8
AV		 282 int wq_sz;
283 int err;
284 int i;
285
311c7c71
SM		 286 param->wq.db_numa_node = cpu_to_node(c->cpu);
287
f62b8bb8
AV		 288 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
289 &rq->wq_ctrl);
290 if (err)
291 return err;
292
293 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
294
295 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 296
461017cb
TT		 297 switch (priv->params.rq_wq_type) {
298 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
299 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
300 GFP_KERNEL, cpu_to_node(c->cpu));
301 if (!rq->wqe_info) {
302 err = -ENOMEM;
303 goto err_rq_wq_destroy;
304 }
305 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
306 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
307
308 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
309 byte_count = rq->wqe_sz;
310 break;
311 default: /* MLX5_WQ_TYPE_LINKED_LIST */
312 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
313 cpu_to_node(c->cpu));
314 if (!rq->skb) {
315 err = -ENOMEM;
316 goto err_rq_wq_destroy;
317 }
318 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
319 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
320
321 rq->wqe_sz = (priv->params.lro_en) ?
322 priv->params.lro_wqe_sz :
323 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 324 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
325 byte_count = rq->wqe_sz;
461017cb
TT		 326 byte_count |= MLX5_HW_START_PADDING;
327 }
f62b8bb8
AV		 328
329 for (i = 0; i < wq_sz; i++) {
330 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
331
461017cb 332 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 333 }
334
461017cb 335 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 336 rq->pdev = c->pdev;
337 rq->netdev = c->netdev;
ef9814de 338 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 339 rq->channel = c;
340 rq->ix = c->ix;
50cfa25a 341 rq->priv = c->priv;
bc77b240
TT		 342 rq->mkey_be = c->mkey_be;
343 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 344
345 return 0;
346
347err_rq_wq_destroy:
348 mlx5_wq_destroy(&rq->wq_ctrl);
349
350 return err;
351}
352
353static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
354{
461017cb
TT		 355 switch (rq->wq_type) {
356 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
357 kfree(rq->wqe_info);
358 break;
359 default: /* MLX5_WQ_TYPE_LINKED_LIST */
360 kfree(rq->skb);
361 }
362
f62b8bb8
AV		 363 mlx5_wq_destroy(&rq->wq_ctrl);
364}
365
366static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
367{
50cfa25a 368 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 369 struct mlx5_core_dev *mdev = priv->mdev;
370
371 void *in;
372 void *rqc;
373 void *wq;
374 int inlen;
375 int err;
376
377 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
378 sizeof(u64) * rq->wq_ctrl.buf.npages;
379 in = mlx5_vzalloc(inlen);
380 if (!in)
381 return -ENOMEM;
382
383 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
384 wq = MLX5_ADDR_OF(rqc, rqc, wq);
385
386 memcpy(rqc, param->rqc, sizeof(param->rqc));
387
97de9f31 388 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 389 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
390 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
f62b8bb8 391 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 392 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 393 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
394
395 mlx5_fill_page_array(&rq->wq_ctrl.buf,
396 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
397
7db22ffb 398 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 399
400 kvfree(in);
401
402 return err;
403}
404
405static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
406{
407 struct mlx5e_channel *c = rq->channel;
408 struct mlx5e_priv *priv = c->priv;
409 struct mlx5_core_dev *mdev = priv->mdev;
410
411 void *in;
412 void *rqc;
413 int inlen;
414 int err;
415
416 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
417 in = mlx5_vzalloc(inlen);
418 if (!in)
419 return -ENOMEM;
420
421 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
422
423 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
424 MLX5_SET(rqc, rqc, state, next_state);
425
7db22ffb 426 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 427
428 kvfree(in);
429
430 return err;
431}
432
433static void mlx5e_disable_rq(struct mlx5e_rq *rq)
434{
50cfa25a 435 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 436}
437
438static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
439{
01c196a2 440 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 441 struct mlx5e_channel *c = rq->channel;
442 struct mlx5e_priv *priv = c->priv;
443 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 444
01c196a2 445 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 446 if (wq->cur_sz >= priv->params.min_rx_wqes)
447 return 0;
448
449 msleep(20);
450 }
451
452 return -ETIMEDOUT;
453}
454
455static int mlx5e_open_rq(struct mlx5e_channel *c,
456 struct mlx5e_rq_param *param,
457 struct mlx5e_rq *rq)
458{
d3c9bc27
TT		 459 struct mlx5e_sq *sq = &c->icosq;
460 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 461 int err;
462
463 err = mlx5e_create_rq(c, param, rq);
464 if (err)
465 return err;
466
467 err = mlx5e_enable_rq(rq, param);
468 if (err)
469 goto err_destroy_rq;
470
471 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
472 if (err)
473 goto err_disable_rq;
474
475 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
d3c9bc27
TT		 476
477 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
478 sq->ico_wqe_info[pi].num_wqebbs = 1;
479 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 480
481 return 0;
482
483err_disable_rq:
484 mlx5e_disable_rq(rq);
485err_destroy_rq:
486 mlx5e_destroy_rq(rq);
487
488 return err;
489}
490
491static void mlx5e_close_rq(struct mlx5e_rq *rq)
492{
493 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
494 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
495
496 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
497 while (!mlx5_wq_ll_is_empty(&rq->wq))
498 msleep(20);
499
500 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
501 napi_synchronize(&rq->channel->napi);
502
503 mlx5e_disable_rq(rq);
504 mlx5e_destroy_rq(rq);
505}
506
507static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
508{
34802a42 509 kfree(sq->wqe_info);
f62b8bb8
AV		 510 kfree(sq->dma_fifo);
511 kfree(sq->skb);
512}
513
514static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
515{
516 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
517 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
518
519 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
520 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
521 numa);
34802a42
AS		 522 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
523 numa);
f62b8bb8 524
34802a42 525 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 526 mlx5e_free_sq_db(sq);
527 return -ENOMEM;
528 }
529
530 sq->dma_fifo_mask = df_sz - 1;
531
532 return 0;
533}
534
535static int mlx5e_create_sq(struct mlx5e_channel *c,
536 int tc,
537 struct mlx5e_sq_param *param,
538 struct mlx5e_sq *sq)
539{
540 struct mlx5e_priv *priv = c->priv;
541 struct mlx5_core_dev *mdev = priv->mdev;
542
543 void *sqc = param->sqc;
544 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
545 int err;
546
0ba42241 547 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
f62b8bb8
AV		 548 if (err)
549 return err;
550
311c7c71
SM		 551 param->wq.db_numa_node = cpu_to_node(c->cpu);
552
f62b8bb8
AV		 553 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
554 &sq->wq_ctrl);
555 if (err)
556 goto err_unmap_free_uar;
557
558 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 559 if (sq->uar.bf_map) {
560 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
561 sq->uar_map = sq->uar.bf_map;
562 } else {
563 sq->uar_map = sq->uar.map;
564 }
f62b8bb8 565 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 566 sq->max_inline = param->max_inline;
f62b8bb8 567
7ec0bb22
DC		 568 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
569 if (err)
f62b8bb8
AV		 570 goto err_sq_wq_destroy;
571
d3c9bc27
TT		 572 if (param->icosq) {
573 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
574
575 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
576 wq_sz,
577 GFP_KERNEL,
578 cpu_to_node(c->cpu));
579 if (!sq->ico_wqe_info) {
580 err = -ENOMEM;
581 goto err_free_sq_db;
582 }
583 } else {
584 int txq_ix;
585
586 txq_ix = c->ix + tc * priv->params.num_channels;
587 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
588 priv->txq_to_sq_map[txq_ix] = sq;
589 }
f62b8bb8 590
88a85f99 591 sq->pdev = c->pdev;
ef9814de 592 sq->tstamp = &priv->tstamp;
88a85f99
AS		 593 sq->mkey_be = c->mkey_be;
594 sq->channel = c;
595 sq->tc = tc;
596 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
597 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 598
599 return 0;
600
d3c9bc27
TT		 601err_free_sq_db:
602 mlx5e_free_sq_db(sq);
603
f62b8bb8
AV		 604err_sq_wq_destroy:
605 mlx5_wq_destroy(&sq->wq_ctrl);
606
607err_unmap_free_uar:
608 mlx5_unmap_free_uar(mdev, &sq->uar);
609
610 return err;
611}
612
613static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
614{
615 struct mlx5e_channel *c = sq->channel;
616 struct mlx5e_priv *priv = c->priv;
617
d3c9bc27 618 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 619 mlx5e_free_sq_db(sq);
620 mlx5_wq_destroy(&sq->wq_ctrl);
621 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
622}
623
624static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
625{
626 struct mlx5e_channel *c = sq->channel;
627 struct mlx5e_priv *priv = c->priv;
628 struct mlx5_core_dev *mdev = priv->mdev;
629
630 void *in;
631 void *sqc;
632 void *wq;
633 int inlen;
634 int err;
635
636 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
637 sizeof(u64) * sq->wq_ctrl.buf.npages;
638 in = mlx5_vzalloc(inlen);
639 if (!in)
640 return -ENOMEM;
641
642 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
643 wq = MLX5_ADDR_OF(sqc, sqc, wq);
644
645 memcpy(sqc, param->sqc, sizeof(param->sqc));
646
d3c9bc27
TT		 647 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
648 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
f62b8bb8 649 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 650 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 651 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
652
653 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
654 MLX5_SET(wq, wq, uar_page, sq->uar.index);
655 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 656 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 657 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
658
659 mlx5_fill_page_array(&sq->wq_ctrl.buf,
660 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
661
7db22ffb 662 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 663
664 kvfree(in);
665
666 return err;
667}
668
669static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
670{
671 struct mlx5e_channel *c = sq->channel;
672 struct mlx5e_priv *priv = c->priv;
673 struct mlx5_core_dev *mdev = priv->mdev;
674
675 void *in;
676 void *sqc;
677 int inlen;
678 int err;
679
680 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
681 in = mlx5_vzalloc(inlen);
682 if (!in)
683 return -ENOMEM;
684
685 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
686
687 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
688 MLX5_SET(sqc, sqc, state, next_state);
689
7db22ffb 690 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 691
692 kvfree(in);
693
694 return err;
695}
696
697static void mlx5e_disable_sq(struct mlx5e_sq *sq)
698{
699 struct mlx5e_channel *c = sq->channel;
700 struct mlx5e_priv *priv = c->priv;
701 struct mlx5_core_dev *mdev = priv->mdev;
702
7db22ffb 703 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 704}
705
706static int mlx5e_open_sq(struct mlx5e_channel *c,
707 int tc,
708 struct mlx5e_sq_param *param,
709 struct mlx5e_sq *sq)
710{
711 int err;
712
713 err = mlx5e_create_sq(c, tc, param, sq);
714 if (err)
715 return err;
716
717 err = mlx5e_enable_sq(sq, param);
718 if (err)
719 goto err_destroy_sq;
720
721 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
722 if (err)
723 goto err_disable_sq;
724
d3c9bc27
TT		 725 if (sq->txq) {
726 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
727 netdev_tx_reset_queue(sq->txq);
728 netif_tx_start_queue(sq->txq);
729 }
f62b8bb8
AV		 730
731 return 0;
732
733err_disable_sq:
734 mlx5e_disable_sq(sq);
735err_destroy_sq:
736 mlx5e_destroy_sq(sq);
737
738 return err;
739}
740
741static inline void netif_tx_disable_queue(struct netdev_queue *txq)
742{
743 __netif_tx_lock_bh(txq);
744 netif_tx_stop_queue(txq);
745 __netif_tx_unlock_bh(txq);
746}
747
748static void mlx5e_close_sq(struct mlx5e_sq *sq)
749{
d3c9bc27
TT		 750 if (sq->txq) {
751 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
752 /* prevent netif_tx_wake_queue */
753 napi_synchronize(&sq->channel->napi);
754 netif_tx_disable_queue(sq->txq);
f62b8bb8 755
d3c9bc27
TT		 756 /* ensure hw is notified of all pending wqes */
757 if (mlx5e_sq_has_room_for(sq, 1))
758 mlx5e_send_nop(sq, true);
759
760 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
761 }
f62b8bb8 762
f62b8bb8
AV		 763 while (sq->cc != sq->pc) /* wait till sq is empty */
764 msleep(20);
765
766 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
767 napi_synchronize(&sq->channel->napi);
768
769 mlx5e_disable_sq(sq);
770 mlx5e_destroy_sq(sq);
771}
772
773static int mlx5e_create_cq(struct mlx5e_channel *c,
774 struct mlx5e_cq_param *param,
775 struct mlx5e_cq *cq)
776{
777 struct mlx5e_priv *priv = c->priv;
778 struct mlx5_core_dev *mdev = priv->mdev;
779 struct mlx5_core_cq *mcq = &cq->mcq;
780 int eqn_not_used;
0b6e26ce 781 unsigned int irqn;
f62b8bb8
AV		 782 int err;
783 u32 i;
784
311c7c71
SM		 785 param->wq.buf_numa_node = cpu_to_node(c->cpu);
786 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 787 param->eq_ix = c->ix;
788
789 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
790 &cq->wq_ctrl);
791 if (err)
792 return err;
793
794 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
795
796 cq->napi = &c->napi;
797
798 mcq->cqe_sz = 64;
799 mcq->set_ci_db = cq->wq_ctrl.db.db;
800 mcq->arm_db = cq->wq_ctrl.db.db + 1;
801 *mcq->set_ci_db = 0;
802 *mcq->arm_db = 0;
803 mcq->vector = param->eq_ix;
804 mcq->comp = mlx5e_completion_event;
805 mcq->event = mlx5e_cq_error_event;
806 mcq->irqn = irqn;
807 mcq->uar = &priv->cq_uar;
808
809 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
810 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
811
812 cqe->op_own = 0xf1;
813 }
814
815 cq->channel = c;
50cfa25a 816 cq->priv = priv;
f62b8bb8
AV		 817
818 return 0;
819}
820
821static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
822{
823 mlx5_wq_destroy(&cq->wq_ctrl);
824}
825
826static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
827{
50cfa25a 828 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 829 struct mlx5_core_dev *mdev = priv->mdev;
830 struct mlx5_core_cq *mcq = &cq->mcq;
831
832 void *in;
833 void *cqc;
834 int inlen;
0b6e26ce 835 unsigned int irqn_not_used;
f62b8bb8
AV		 836 int eqn;
837 int err;
838
839 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
840 sizeof(u64) * cq->wq_ctrl.buf.npages;
841 in = mlx5_vzalloc(inlen);
842 if (!in)
843 return -ENOMEM;
844
845 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
846
847 memcpy(cqc, param->cqc, sizeof(param->cqc));
848
849 mlx5_fill_page_array(&cq->wq_ctrl.buf,
850 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
851
852 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
853
854 MLX5_SET(cqc, cqc, c_eqn, eqn);
855 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
856 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 857 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 858 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
859
860 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
861
862 kvfree(in);
863
864 if (err)
865 return err;
866
867 mlx5e_cq_arm(cq);
868
869 return 0;
870}
871
872static void mlx5e_disable_cq(struct mlx5e_cq *cq)
873{
50cfa25a 874 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 875 struct mlx5_core_dev *mdev = priv->mdev;
876
877 mlx5_core_destroy_cq(mdev, &cq->mcq);
878}
879
880static int mlx5e_open_cq(struct mlx5e_channel *c,
881 struct mlx5e_cq_param *param,
882 struct mlx5e_cq *cq,
883 u16 moderation_usecs,
884 u16 moderation_frames)
885{
886 int err;
887 struct mlx5e_priv *priv = c->priv;
888 struct mlx5_core_dev *mdev = priv->mdev;
889
890 err = mlx5e_create_cq(c, param, cq);
891 if (err)
892 return err;
893
894 err = mlx5e_enable_cq(cq, param);
895 if (err)
896 goto err_destroy_cq;
897
7524a5d8
GP		 898 if (MLX5_CAP_GEN(mdev, cq_moderation))
899 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
900 moderation_usecs,
901 moderation_frames);
f62b8bb8
AV		 902 return 0;
903
904err_destroy_cq:
905 mlx5e_destroy_cq(cq);
906
907 return err;
908}
909
910static void mlx5e_close_cq(struct mlx5e_cq *cq)
911{
912 mlx5e_disable_cq(cq);
913 mlx5e_destroy_cq(cq);
914}
915
916static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
917{
918 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
919}
920
921static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
922 struct mlx5e_channel_param *cparam)
923{
924 struct mlx5e_priv *priv = c->priv;
925 int err;
926 int tc;
927
928 for (tc = 0; tc < c->num_tc; tc++) {
929 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
930 priv->params.tx_cq_moderation_usec,
931 priv->params.tx_cq_moderation_pkts);
932 if (err)
933 goto err_close_tx_cqs;
f62b8bb8
AV		 934 }
935
936 return 0;
937
938err_close_tx_cqs:
939 for (tc--; tc >= 0; tc--)
940 mlx5e_close_cq(&c->sq[tc].cq);
941
942 return err;
943}
944
945static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
946{
947 int tc;
948
949 for (tc = 0; tc < c->num_tc; tc++)
950 mlx5e_close_cq(&c->sq[tc].cq);
951}
952
953static int mlx5e_open_sqs(struct mlx5e_channel *c,
954 struct mlx5e_channel_param *cparam)
955{
956 int err;
957 int tc;
958
959 for (tc = 0; tc < c->num_tc; tc++) {
960 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
961 if (err)
962 goto err_close_sqs;
963 }
964
965 return 0;
966
967err_close_sqs:
968 for (tc--; tc >= 0; tc--)
969 mlx5e_close_sq(&c->sq[tc]);
970
971 return err;
972}
973
974static void mlx5e_close_sqs(struct mlx5e_channel *c)
975{
976 int tc;
977
978 for (tc = 0; tc < c->num_tc; tc++)
979 mlx5e_close_sq(&c->sq[tc]);
980}
981
5283af89 982static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 983{
984 int i;
985
986 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 987 priv->channeltc_to_txq_map[ix][i] =
988 ix + i * priv->params.num_channels;
03289b88
SM		 989}
990
f62b8bb8
AV		 991static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
992 struct mlx5e_channel_param *cparam,
993 struct mlx5e_channel **cp)
994{
995 struct net_device *netdev = priv->netdev;
996 int cpu = mlx5e_get_cpu(priv, ix);
997 struct mlx5e_channel *c;
998 int err;
999
1000 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1001 if (!c)
1002 return -ENOMEM;
1003
1004 c->priv = priv;
1005 c->ix = ix;
1006 c->cpu = cpu;
1007 c->pdev = &priv->mdev->pdev->dev;
1008 c->netdev = priv->netdev;
a606b0f6 1009 c->mkey_be = cpu_to_be32(priv->mkey.key);
a4418a6c 1010 c->num_tc = priv->params.num_tc;
f62b8bb8 1011
5283af89 1012 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1013
f62b8bb8
AV		 1014 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1015
d3c9bc27 1016 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
f62b8bb8
AV		 1017 if (err)
1018 goto err_napi_del;
1019
d3c9bc27
TT		 1020 err = mlx5e_open_tx_cqs(c, cparam);
1021 if (err)
1022 goto err_close_icosq_cq;
1023
f62b8bb8
AV		 1024 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1025 priv->params.rx_cq_moderation_usec,
1026 priv->params.rx_cq_moderation_pkts);
1027 if (err)
1028 goto err_close_tx_cqs;
f62b8bb8
AV		 1029
1030 napi_enable(&c->napi);
1031
d3c9bc27 1032 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1033 if (err)
1034 goto err_disable_napi;
1035
d3c9bc27
TT		 1036 err = mlx5e_open_sqs(c, cparam);
1037 if (err)
1038 goto err_close_icosq;
1039
f62b8bb8
AV		 1040 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1041 if (err)
1042 goto err_close_sqs;
1043
1044 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1045 *cp = c;
1046
1047 return 0;
1048
1049err_close_sqs:
1050 mlx5e_close_sqs(c);
1051
d3c9bc27
TT		 1052err_close_icosq:
1053 mlx5e_close_sq(&c->icosq);
1054
f62b8bb8
AV		 1055err_disable_napi:
1056 napi_disable(&c->napi);
1057 mlx5e_close_cq(&c->rq.cq);
1058
1059err_close_tx_cqs:
1060 mlx5e_close_tx_cqs(c);
1061
d3c9bc27
TT		 1062err_close_icosq_cq:
1063 mlx5e_close_cq(&c->icosq.cq);
1064
f62b8bb8
AV		 1065err_napi_del:
1066 netif_napi_del(&c->napi);
7ae92ae5 1067 napi_hash_del(&c->napi);
f62b8bb8
AV		 1068 kfree(c);
1069
1070 return err;
1071}
1072
1073static void mlx5e_close_channel(struct mlx5e_channel *c)
1074{
1075 mlx5e_close_rq(&c->rq);
1076 mlx5e_close_sqs(c);
d3c9bc27 1077 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1078 napi_disable(&c->napi);
1079 mlx5e_close_cq(&c->rq.cq);
1080 mlx5e_close_tx_cqs(c);
d3c9bc27 1081 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1082 netif_napi_del(&c->napi);
7ae92ae5
ED		 1083
1084 napi_hash_del(&c->napi);
1085 synchronize_rcu();
1086
f62b8bb8
AV		 1087 kfree(c);
1088}
1089
1090static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1091 struct mlx5e_rq_param *param)
1092{
1093 void *rqc = param->rqc;
1094 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1095
461017cb
TT		 1096 switch (priv->params.rq_wq_type) {
1097 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1098 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1099 MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1100 MLX5_SET(wq, wq, log_wqe_stride_size,
1101 MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1102 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1103 break;
1104 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1105 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1106 }
1107
f62b8bb8
AV		 1108 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1109 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1110 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1111 MLX5_SET(wq, wq, pd, priv->pdn);
593cf338 1112 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1113
311c7c71 1114 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1115 param->wq.linear = 1;
1116}
1117
556dd1b9
TT		 1118static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1119{
1120 void *rqc = param->rqc;
1121 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1122
1123 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1124 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1125}
1126
d3c9bc27
TT		 1127static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1128 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1129{
1130 void *sqc = param->sqc;
1131 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1132
f62b8bb8
AV		 1133 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1134 MLX5_SET(wq, wq, pd, priv->pdn);
1135
311c7c71 1136 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1137}
1138
1139static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1140 struct mlx5e_sq_param *param)
1141{
1142 void *sqc = param->sqc;
1143 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1144
1145 mlx5e_build_sq_param_common(priv, param);
1146 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1147
58d52291 1148 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1149}
1150
1151static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1152 struct mlx5e_cq_param *param)
1153{
1154 void *cqc = param->cqc;
1155
1156 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1157}
1158
1159static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1160 struct mlx5e_cq_param *param)
1161{
1162 void *cqc = param->cqc;
461017cb 1163 u8 log_cq_size;
f62b8bb8 1164
461017cb
TT		 1165 switch (priv->params.rq_wq_type) {
1166 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1167 log_cq_size = priv->params.log_rq_size +
1168 MLX5_MPWRQ_LOG_NUM_STRIDES;
1169 break;
1170 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1171 log_cq_size = priv->params.log_rq_size;
1172 }
1173
1174 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
f62b8bb8
AV		 1175
1176 mlx5e_build_common_cq_param(priv, param);
1177}
1178
1179static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1180 struct mlx5e_cq_param *param)
1181{
1182 void *cqc = param->cqc;
1183
d3c9bc27 1184 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1185
1186 mlx5e_build_common_cq_param(priv, param);
1187}
1188
d3c9bc27
TT		 1189static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1190 struct mlx5e_cq_param *param,
1191 u8 log_wq_size)
1192{
1193 void *cqc = param->cqc;
1194
1195 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1196
1197 mlx5e_build_common_cq_param(priv, param);
1198}
1199
1200static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1201 struct mlx5e_sq_param *param,
1202 u8 log_wq_size)
1203{
1204 void *sqc = param->sqc;
1205 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1206
1207 mlx5e_build_sq_param_common(priv, param);
1208
1209 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1210 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1211
1212 param->icosq = true;
1213}
1214
f62b8bb8
AV		 1215static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1216 struct mlx5e_channel_param *cparam)
1217{
bc77b240 1218 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1219
f62b8bb8
AV		 1220 memset(cparam, 0, sizeof(*cparam));
1221
1222 mlx5e_build_rq_param(priv, &cparam->rq);
1223 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1224 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1225 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1226 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1227 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1228}
1229
1230static int mlx5e_open_channels(struct mlx5e_priv *priv)
1231{
1232 struct mlx5e_channel_param cparam;
a4418a6c 1233 int nch = priv->params.num_channels;
03289b88 1234 int err = -ENOMEM;
f62b8bb8
AV		 1235 int i;
1236 int j;
1237
a4418a6c
AS		 1238 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1239 GFP_KERNEL);
03289b88 1240
a4418a6c 1241 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1242 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1243
1244 if (!priv->channel || !priv->txq_to_sq_map)
1245 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1246
1247 mlx5e_build_channel_param(priv, &cparam);
a4418a6c 1248 for (i = 0; i < nch; i++) {
f62b8bb8
AV		 1249 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1250 if (err)
1251 goto err_close_channels;
1252 }
1253
a4418a6c 1254 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1255 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1256 if (err)
1257 goto err_close_channels;
1258 }
1259
1260 return 0;
1261
1262err_close_channels:
1263 for (i--; i >= 0; i--)
1264 mlx5e_close_channel(priv->channel[i]);
1265
03289b88
SM		 1266err_free_txq_to_sq_map:
1267 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1268 kfree(priv->channel);
1269
1270 return err;
1271}
1272
1273static void mlx5e_close_channels(struct mlx5e_priv *priv)
1274{
1275 int i;
1276
1277 for (i = 0; i < priv->params.num_channels; i++)
1278 mlx5e_close_channel(priv->channel[i]);
1279
03289b88 1280 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1281 kfree(priv->channel);
1282}
1283
2be6967c
SM		 1284static int mlx5e_rx_hash_fn(int hfunc)
1285{
1286 return (hfunc == ETH_RSS_HASH_TOP) ?
1287 MLX5_RX_HASH_FN_TOEPLITZ :
1288 MLX5_RX_HASH_FN_INVERTED_XOR8;
1289}
1290
1291static int mlx5e_bits_invert(unsigned long a, int size)
1292{
1293 int inv = 0;
1294 int i;
1295
1296 for (i = 0; i < size; i++)
1297 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1298
1299 return inv;
1300}
1301
936896e9
AS		 1302static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1303{
1304 int i;
1305
1306 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1307 int ix = i;
1308
1309 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1310 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1311
2d75b2bc 1312 ix = priv->params.indirection_rqt[ix];
936896e9
AS		 1313 MLX5_SET(rqtc, rqtc, rq_num[i],
1314 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1315 priv->channel[ix]->rq.rqn :
1316 priv->drop_rq.rqn);
1317 }
1318}
1319
4cbeaff5
AS		 1320static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1321 enum mlx5e_rqt_ix rqt_ix)
1322{
4cbeaff5
AS		 1323
1324 switch (rqt_ix) {
1325 case MLX5E_INDIRECTION_RQT:
936896e9 1326 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
4cbeaff5
AS		 1327
1328 break;
1329
1330 default: /* MLX5E_SINGLE_RQ_RQT */
1331 MLX5_SET(rqtc, rqtc, rq_num[0],
5c50368f
AS		 1332 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1333 priv->channel[0]->rq.rqn :
1334 priv->drop_rq.rqn);
4cbeaff5
AS		 1335
1336 break;
1337 }
1338}
1339
40ab6a6e 1340static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8
AV		 1341{
1342 struct mlx5_core_dev *mdev = priv->mdev;
1343 u32 *in;
f62b8bb8
AV		 1344 void *rqtc;
1345 int inlen;
4cbeaff5 1346 int sz;
f62b8bb8 1347 int err;
4cbeaff5 1348
936896e9 1349 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
f62b8bb8 1350
f62b8bb8
AV		 1351 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1352 in = mlx5_vzalloc(inlen);
1353 if (!in)
1354 return -ENOMEM;
1355
1356 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1357
1358 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1359 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1360
4cbeaff5 1361 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
2be6967c 1362
4cbeaff5 1363 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1364
1365 kvfree(in);
1366
1367 return err;
1368}
1369
2d75b2bc 1370int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
5c50368f
AS		 1371{
1372 struct mlx5_core_dev *mdev = priv->mdev;
1373 u32 *in;
1374 void *rqtc;
1375 int inlen;
5c50368f
AS		 1376 int sz;
1377 int err;
1378
936896e9 1379 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
5c50368f
AS		 1380
1381 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1382 in = mlx5_vzalloc(inlen);
1383 if (!in)
1384 return -ENOMEM;
1385
1386 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1387
1388 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1389
1390 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1391
1392 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1393
1394 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1395
1396 kvfree(in);
1397
1398 return err;
1399}
1400
40ab6a6e 1401static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8 1402{
4cbeaff5 1403 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1404}
1405
40ab6a6e
AS		 1406static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1407{
1408 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1409 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1410}
1411
5c50368f
AS		 1412static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1413{
1414 if (!priv->params.lro_en)
1415 return;
1416
1417#define ROUGH_MAX_L2_L3_HDR_SZ 256
1418
1419 MLX5_SET(tirc, tirc, lro_enable_mask,
1420 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1421 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1422 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1423 (priv->params.lro_wqe_sz -
1424 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1425 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1426 MLX5_CAP_ETH(priv->mdev,
d9a40271 1427 lro_timer_supported_periods[2]));
5c50368f
AS		 1428}
1429
bdfc028d
TT		 1430void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1431{
1432 MLX5_SET(tirc, tirc, rx_hash_fn,
1433 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1434 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1435 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1436 rx_hash_toeplitz_key);
1437 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1438 rx_hash_toeplitz_key);
1439
1440 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1441 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1442 }
1443}
1444
ab0394fe 1445static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1446{
1447 struct mlx5_core_dev *mdev = priv->mdev;
1448
1449 void *in;
1450 void *tirc;
1451 int inlen;
1452 int err;
ab0394fe 1453 int tt;
5c50368f
AS		 1454
1455 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1456 in = mlx5_vzalloc(inlen);
1457 if (!in)
1458 return -ENOMEM;
1459
1460 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1461 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1462
1463 mlx5e_build_tir_ctx_lro(tirc, priv);
1464
ab0394fe
TT		 1465 for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1466 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1467 if (err)
1468 break;
1469 }
5c50368f
AS		 1470
1471 kvfree(in);
1472
1473 return err;
1474}
1475
66189961
TT		 1476static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1477 u32 tirn)
1478{
1479 void *in;
1480 int inlen;
1481 int err;
1482
1483 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1484 in = mlx5_vzalloc(inlen);
1485 if (!in)
1486 return -ENOMEM;
1487
1488 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1489
1490 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1491
1492 kvfree(in);
1493
1494 return err;
1495}
1496
1497static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1498{
1499 int err;
1500 int i;
1501
1502 for (i = 0; i < MLX5E_NUM_TT; i++) {
1503 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1504 priv->tirn[i]);
1505 if (err)
1506 return err;
1507 }
1508
1509 return 0;
1510}
1511
40ab6a6e
AS		 1512static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1513{
1514 struct mlx5e_priv *priv = netdev_priv(netdev);
1515 struct mlx5_core_dev *mdev = priv->mdev;
1516 int hw_mtu;
1517 int err;
1518
1519 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1520 if (err)
1521 return err;
1522
1523 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1524
1525 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1526 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1527 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1528
1529 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1530 return 0;
1531}
1532
08fb1dac
SM		 1533static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1534{
1535 struct mlx5e_priv *priv = netdev_priv(netdev);
1536 int nch = priv->params.num_channels;
1537 int ntc = priv->params.num_tc;
1538 int tc;
1539
1540 netdev_reset_tc(netdev);
1541
1542 if (ntc == 1)
1543 return;
1544
1545 netdev_set_num_tc(netdev, ntc);
1546
1547 for (tc = 0; tc < ntc; tc++)
1548 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1549}
1550
40ab6a6e
AS		 1551int mlx5e_open_locked(struct net_device *netdev)
1552{
1553 struct mlx5e_priv *priv = netdev_priv(netdev);
1554 int num_txqs;
1555 int err;
1556
1557 set_bit(MLX5E_STATE_OPENED, &priv->state);
1558
08fb1dac
SM		 1559 mlx5e_netdev_set_tcs(netdev);
1560
40ab6a6e
AS		 1561 num_txqs = priv->params.num_channels * priv->params.num_tc;
1562 netif_set_real_num_tx_queues(netdev, num_txqs);
1563 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1564
1565 err = mlx5e_set_dev_port_mtu(netdev);
1566 if (err)
343b29f3 1567 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1568
1569 err = mlx5e_open_channels(priv);
1570 if (err) {
1571 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1572 __func__, err);
343b29f3 1573 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1574 }
1575
66189961
TT		 1576 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1577 if (err) {
1578 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1579 __func__, err);
1580 goto err_close_channels;
1581 }
1582
40ab6a6e 1583 mlx5e_redirect_rqts(priv);
ce89ef36 1584 mlx5e_update_carrier(priv);
ef9814de 1585 mlx5e_timestamp_init(priv);
40ab6a6e
AS		 1586
1587 schedule_delayed_work(&priv->update_stats_work, 0);
40ab6a6e 1588
9b37b07f 1589 return 0;
343b29f3 1590
66189961
TT		 1591err_close_channels:
1592 mlx5e_close_channels(priv);
343b29f3
AS		 1593err_clear_state_opened_flag:
1594 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1595 return err;
40ab6a6e
AS		 1596}
1597
1598static int mlx5e_open(struct net_device *netdev)
1599{
1600 struct mlx5e_priv *priv = netdev_priv(netdev);
1601 int err;
1602
1603 mutex_lock(&priv->state_lock);
1604 err = mlx5e_open_locked(netdev);
1605 mutex_unlock(&priv->state_lock);
1606
1607 return err;
1608}
1609
1610int mlx5e_close_locked(struct net_device *netdev)
1611{
1612 struct mlx5e_priv *priv = netdev_priv(netdev);
1613
a1985740
AS		 1614 /* May already be CLOSED in case a previous configuration operation
1615 * (e.g RX/TX queue size change) that involves close&open failed.
1616 */
1617 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1618 return 0;
1619
40ab6a6e
AS		 1620 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1621
ef9814de 1622 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1623 netif_carrier_off(priv->netdev);
ce89ef36 1624 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1625 mlx5e_close_channels(priv);
1626
1627 return 0;
1628}
1629
1630static int mlx5e_close(struct net_device *netdev)
1631{
1632 struct mlx5e_priv *priv = netdev_priv(netdev);
1633 int err;
1634
1635 mutex_lock(&priv->state_lock);
1636 err = mlx5e_close_locked(netdev);
1637 mutex_unlock(&priv->state_lock);
1638
1639 return err;
1640}
1641
1642static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1643 struct mlx5e_rq *rq,
1644 struct mlx5e_rq_param *param)
1645{
1646 struct mlx5_core_dev *mdev = priv->mdev;
1647 void *rqc = param->rqc;
1648 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1649 int err;
1650
1651 param->wq.db_numa_node = param->wq.buf_numa_node;
1652
1653 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1654 &rq->wq_ctrl);
1655 if (err)
1656 return err;
1657
1658 rq->priv = priv;
1659
1660 return 0;
1661}
1662
1663static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1664 struct mlx5e_cq *cq,
1665 struct mlx5e_cq_param *param)
1666{
1667 struct mlx5_core_dev *mdev = priv->mdev;
1668 struct mlx5_core_cq *mcq = &cq->mcq;
1669 int eqn_not_used;
0b6e26ce 1670 unsigned int irqn;
40ab6a6e
AS		 1671 int err;
1672
1673 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1674 &cq->wq_ctrl);
1675 if (err)
1676 return err;
1677
1678 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1679
1680 mcq->cqe_sz = 64;
1681 mcq->set_ci_db = cq->wq_ctrl.db.db;
1682 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1683 *mcq->set_ci_db = 0;
1684 *mcq->arm_db = 0;
1685 mcq->vector = param->eq_ix;
1686 mcq->comp = mlx5e_completion_event;
1687 mcq->event = mlx5e_cq_error_event;
1688 mcq->irqn = irqn;
1689 mcq->uar = &priv->cq_uar;
1690
1691 cq->priv = priv;
1692
1693 return 0;
1694}
1695
1696static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1697{
1698 struct mlx5e_cq_param cq_param;
1699 struct mlx5e_rq_param rq_param;
1700 struct mlx5e_rq *rq = &priv->drop_rq;
1701 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1702 int err;
1703
1704 memset(&cq_param, 0, sizeof(cq_param));
1705 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1706 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1707
1708 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1709 if (err)
1710 return err;
1711
1712 err = mlx5e_enable_cq(cq, &cq_param);
1713 if (err)
1714 goto err_destroy_cq;
1715
1716 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1717 if (err)
1718 goto err_disable_cq;
1719
1720 err = mlx5e_enable_rq(rq, &rq_param);
1721 if (err)
1722 goto err_destroy_rq;
1723
1724 return 0;
1725
1726err_destroy_rq:
1727 mlx5e_destroy_rq(&priv->drop_rq);
1728
1729err_disable_cq:
1730 mlx5e_disable_cq(&priv->drop_rq.cq);
1731
1732err_destroy_cq:
1733 mlx5e_destroy_cq(&priv->drop_rq.cq);
1734
1735 return err;
1736}
1737
1738static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1739{
1740 mlx5e_disable_rq(&priv->drop_rq);
1741 mlx5e_destroy_rq(&priv->drop_rq);
1742 mlx5e_disable_cq(&priv->drop_rq.cq);
1743 mlx5e_destroy_cq(&priv->drop_rq.cq);
1744}
1745
1746static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1747{
1748 struct mlx5_core_dev *mdev = priv->mdev;
1749 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1750 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1751
1752 memset(in, 0, sizeof(in));
1753
08fb1dac 1754 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1755 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1756
1757 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1758}
1759
1760static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1761{
1762 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1763}
1764
1765static int mlx5e_create_tises(struct mlx5e_priv *priv)
1766{
1767 int err;
1768 int tc;
1769
08fb1dac 1770 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1771 err = mlx5e_create_tis(priv, tc);
1772 if (err)
1773 goto err_close_tises;
1774 }
1775
1776 return 0;
1777
1778err_close_tises:
1779 for (tc--; tc >= 0; tc--)
1780 mlx5e_destroy_tis(priv, tc);
1781
1782 return err;
1783}
1784
1785static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1786{
1787 int tc;
1788
08fb1dac 1789 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 1790 mlx5e_destroy_tis(priv, tc);
1791}
1792
f62b8bb8
AV		 1793static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1794{
1795 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1796
3191e05f
AS		 1797 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1798
5a6f8aef
AS		 1799#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1800 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1801
5a6f8aef
AS		 1802#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1803 MLX5_HASH_FIELD_SEL_DST_IP |\
1804 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1805 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1806
a741749f
AS		 1807#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1808 MLX5_HASH_FIELD_SEL_DST_IP |\
1809 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1810
5c50368f 1811 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1812
4cbeaff5
AS		 1813 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1814
f62b8bb8
AV		 1815 switch (tt) {
1816 case MLX5E_TT_ANY:
4cbeaff5
AS		 1817 MLX5_SET(tirc, tirc, indirect_table,
1818 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1819 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
f62b8bb8
AV		 1820 break;
1821 default:
f62b8bb8 1822 MLX5_SET(tirc, tirc, indirect_table,
4cbeaff5 1823 priv->rqtn[MLX5E_INDIRECTION_RQT]);
bdfc028d 1824 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 1825 break;
1826 }
1827
1828 switch (tt) {
1829 case MLX5E_TT_IPV4_TCP:
1830 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1831 MLX5_L3_PROT_TYPE_IPV4);
1832 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1833 MLX5_L4_PROT_TYPE_TCP);
1834 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1835 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1836 break;
1837
1838 case MLX5E_TT_IPV6_TCP:
1839 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1840 MLX5_L3_PROT_TYPE_IPV6);
1841 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1842 MLX5_L4_PROT_TYPE_TCP);
1843 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1844 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1845 break;
1846
1847 case MLX5E_TT_IPV4_UDP:
1848 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1849 MLX5_L3_PROT_TYPE_IPV4);
1850 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1851 MLX5_L4_PROT_TYPE_UDP);
1852 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1853 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1854 break;
1855
1856 case MLX5E_TT_IPV6_UDP:
1857 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1858 MLX5_L3_PROT_TYPE_IPV6);
1859 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1860 MLX5_L4_PROT_TYPE_UDP);
1861 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1862 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1863 break;
1864
a741749f
AS		 1865 case MLX5E_TT_IPV4_IPSEC_AH:
1866 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1867 MLX5_L3_PROT_TYPE_IPV4);
1868 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1869 MLX5_HASH_IP_IPSEC_SPI);
1870 break;
1871
1872 case MLX5E_TT_IPV6_IPSEC_AH:
1873 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1874 MLX5_L3_PROT_TYPE_IPV6);
1875 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1876 MLX5_HASH_IP_IPSEC_SPI);
1877 break;
1878
1879 case MLX5E_TT_IPV4_IPSEC_ESP:
1880 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1881 MLX5_L3_PROT_TYPE_IPV4);
1882 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1883 MLX5_HASH_IP_IPSEC_SPI);
1884 break;
1885
1886 case MLX5E_TT_IPV6_IPSEC_ESP:
1887 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1888 MLX5_L3_PROT_TYPE_IPV6);
1889 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1890 MLX5_HASH_IP_IPSEC_SPI);
1891 break;
1892
f62b8bb8
AV		 1893 case MLX5E_TT_IPV4:
1894 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1895 MLX5_L3_PROT_TYPE_IPV4);
1896 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1897 MLX5_HASH_IP);
1898 break;
1899
1900 case MLX5E_TT_IPV6:
1901 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1902 MLX5_L3_PROT_TYPE_IPV6);
1903 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1904 MLX5_HASH_IP);
1905 break;
1906 }
1907}
1908
40ab6a6e 1909static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8
AV		 1910{
1911 struct mlx5_core_dev *mdev = priv->mdev;
1912 u32 *in;
1913 void *tirc;
1914 int inlen;
1915 int err;
1916
1917 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1918 in = mlx5_vzalloc(inlen);
1919 if (!in)
1920 return -ENOMEM;
1921
1922 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1923
1924 mlx5e_build_tir_ctx(priv, tirc, tt);
1925
7db22ffb 1926 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1927
1928 kvfree(in);
1929
1930 return err;
1931}
1932
40ab6a6e 1933static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8 1934{
7db22ffb 1935 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1936}
1937
40ab6a6e 1938static int mlx5e_create_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1939{
1940 int err;
1941 int i;
1942
1943 for (i = 0; i < MLX5E_NUM_TT; i++) {
40ab6a6e 1944 err = mlx5e_create_tir(priv, i);
f62b8bb8 1945 if (err)
40ab6a6e 1946 goto err_destroy_tirs;
f62b8bb8
AV		 1947 }
1948
1949 return 0;
1950
40ab6a6e 1951err_destroy_tirs:
f62b8bb8 1952 for (i--; i >= 0; i--)
40ab6a6e 1953 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1954
1955 return err;
1956}
1957
40ab6a6e 1958static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1959{
1960 int i;
1961
1962 for (i = 0; i < MLX5E_NUM_TT; i++)
40ab6a6e 1963 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1964}
1965
08fb1dac
SM		 1966static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1967{
1968 struct mlx5e_priv *priv = netdev_priv(netdev);
1969 bool was_opened;
1970 int err = 0;
1971
1972 if (tc && tc != MLX5E_MAX_NUM_TC)
1973 return -EINVAL;
1974
1975 mutex_lock(&priv->state_lock);
1976
1977 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1978 if (was_opened)
1979 mlx5e_close_locked(priv->netdev);
1980
1981 priv->params.num_tc = tc ? tc : 1;
1982
1983 if (was_opened)
1984 err = mlx5e_open_locked(priv->netdev);
1985
1986 mutex_unlock(&priv->state_lock);
1987
1988 return err;
1989}
1990
1991static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1992 __be16 proto, struct tc_to_netdev *tc)
1993{
e8f887ac
AV		 1994 struct mlx5e_priv *priv = netdev_priv(dev);
1995
1996 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
1997 goto mqprio;
1998
1999 switch (tc->type) {
e3a2b7ed
AV		 2000 case TC_SETUP_CLSFLOWER:
2001 switch (tc->cls_flower->command) {
2002 case TC_CLSFLOWER_REPLACE:
2003 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2004 case TC_CLSFLOWER_DESTROY:
2005 return mlx5e_delete_flower(priv, tc->cls_flower);
2006 }
e8f887ac
AV		 2007 default:
2008 return -EOPNOTSUPP;
2009 }
2010
2011mqprio:
67ba422e 2012 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2013 return -EINVAL;
2014
2015 return mlx5e_setup_tc(dev, tc->tc);
2016}
2017
f62b8bb8
AV		 2018static struct rtnl_link_stats64 *
2019mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2020{
2021 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2022 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2023 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2024 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2025
9218b44d
GP		 2026 stats->rx_packets = sstats->rx_packets;
2027 stats->rx_bytes = sstats->rx_bytes;
2028 stats->tx_packets = sstats->tx_packets;
2029 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2030
2031 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2032 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2033
2034 stats->rx_length_errors =
9218b44d
GP		 2035 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2036 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2037 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2038 stats->rx_crc_errors =
9218b44d
GP		 2039 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2040 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2041 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2042 stats->tx_carrier_errors =
9218b44d 2043 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2044 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2045 stats->rx_frame_errors;
2046 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2047
2048 /* vport multicast also counts packets that are dropped due to steering
2049 * or rx out of buffer
2050 */
9218b44d
GP		 2051 stats->multicast =
2052 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2053
2054 return stats;
2055}
2056
2057static void mlx5e_set_rx_mode(struct net_device *dev)
2058{
2059 struct mlx5e_priv *priv = netdev_priv(dev);
2060
2061 schedule_work(&priv->set_rx_mode_work);
2062}
2063
2064static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2065{
2066 struct mlx5e_priv *priv = netdev_priv(netdev);
2067 struct sockaddr *saddr = addr;
2068
2069 if (!is_valid_ether_addr(saddr->sa_data))
2070 return -EADDRNOTAVAIL;
2071
2072 netif_addr_lock_bh(netdev);
2073 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2074 netif_addr_unlock_bh(netdev);
2075
2076 schedule_work(&priv->set_rx_mode_work);
2077
2078 return 0;
2079}
2080
2081static int mlx5e_set_features(struct net_device *netdev,
2082 netdev_features_t features)
2083{
2084 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 2085 int err = 0;
f62b8bb8 2086 netdev_features_t changes = features ^ netdev->features;
f62b8bb8
AV		 2087
2088 mutex_lock(&priv->state_lock);
f62b8bb8
AV		 2089
2090 if (changes & NETIF_F_LRO) {
98e81b0a
AS		 2091 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2092
461017cb
TT		 2093 if (was_opened && (priv->params.rq_wq_type ==
2094 MLX5_WQ_TYPE_LINKED_LIST))
98e81b0a 2095 mlx5e_close_locked(priv->netdev);
f62b8bb8 2096
98e81b0a 2097 priv->params.lro_en = !!(features & NETIF_F_LRO);
ab0394fe
TT		 2098 err = mlx5e_modify_tirs_lro(priv);
2099 if (err)
2100 mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
2101 err);
98e81b0a 2102
461017cb
TT		 2103 if (was_opened && (priv->params.rq_wq_type ==
2104 MLX5_WQ_TYPE_LINKED_LIST))
98e81b0a
AS		 2105 err = mlx5e_open_locked(priv->netdev);
2106 }
f62b8bb8 2107
9b37b07f
AS		 2108 mutex_unlock(&priv->state_lock);
2109
f62b8bb8
AV		 2110 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
2111 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
2112 mlx5e_enable_vlan_filter(priv);
2113 else
2114 mlx5e_disable_vlan_filter(priv);
2115 }
2116
e8f887ac
AV		 2117 if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
2118 mlx5e_tc_num_filters(priv)) {
2119 netdev_err(netdev,
2120 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2121 return -EINVAL;
2122 }
2123
fe9f4fe5 2124 return err;
f62b8bb8
AV		 2125}
2126
2127static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2128{
2129 struct mlx5e_priv *priv = netdev_priv(netdev);
2130 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2131 bool was_opened;
f62b8bb8 2132 int max_mtu;
98e81b0a 2133 int err = 0;
f62b8bb8 2134
facc9699 2135 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2136
50a9eea6
DT		 2137 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2138
facc9699
SM		 2139 if (new_mtu > max_mtu) {
2140 netdev_err(netdev,
2141 "%s: Bad MTU (%d) > (%d) Max\n",
2142 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 2143 return -EINVAL;
2144 }
2145
2146 mutex_lock(&priv->state_lock);
98e81b0a
AS		 2147
2148 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2149 if (was_opened)
2150 mlx5e_close_locked(netdev);
2151
f62b8bb8 2152 netdev->mtu = new_mtu;
98e81b0a
AS		 2153
2154 if (was_opened)
2155 err = mlx5e_open_locked(netdev);
2156
f62b8bb8
AV		 2157 mutex_unlock(&priv->state_lock);
2158
2159 return err;
2160}
2161
ef9814de
EBE		 2162static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2163{
2164 switch (cmd) {
2165 case SIOCSHWTSTAMP:
2166 return mlx5e_hwstamp_set(dev, ifr);
2167 case SIOCGHWTSTAMP:
2168 return mlx5e_hwstamp_get(dev, ifr);
2169 default:
2170 return -EOPNOTSUPP;
2171 }
2172}
2173
66e49ded
SM		 2174static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2175{
2176 struct mlx5e_priv *priv = netdev_priv(dev);
2177 struct mlx5_core_dev *mdev = priv->mdev;
2178
2179 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2180}
2181
2182static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2183{
2184 struct mlx5e_priv *priv = netdev_priv(dev);
2185 struct mlx5_core_dev *mdev = priv->mdev;
2186
2187 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2188 vlan, qos);
2189}
2190
2191static int mlx5_vport_link2ifla(u8 esw_link)
2192{
2193 switch (esw_link) {
2194 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2195 return IFLA_VF_LINK_STATE_DISABLE;
2196 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2197 return IFLA_VF_LINK_STATE_ENABLE;
2198 }
2199 return IFLA_VF_LINK_STATE_AUTO;
2200}
2201
2202static int mlx5_ifla_link2vport(u8 ifla_link)
2203{
2204 switch (ifla_link) {
2205 case IFLA_VF_LINK_STATE_DISABLE:
2206 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2207 case IFLA_VF_LINK_STATE_ENABLE:
2208 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2209 }
2210 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2211}
2212
2213static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2214 int link_state)
2215{
2216 struct mlx5e_priv *priv = netdev_priv(dev);
2217 struct mlx5_core_dev *mdev = priv->mdev;
2218
2219 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2220 mlx5_ifla_link2vport(link_state));
2221}
2222
2223static int mlx5e_get_vf_config(struct net_device *dev,
2224 int vf, struct ifla_vf_info *ivi)
2225{
2226 struct mlx5e_priv *priv = netdev_priv(dev);
2227 struct mlx5_core_dev *mdev = priv->mdev;
2228 int err;
2229
2230 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2231 if (err)
2232 return err;
2233 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2234 return 0;
2235}
2236
2237static int mlx5e_get_vf_stats(struct net_device *dev,
2238 int vf, struct ifla_vf_stats *vf_stats)
2239{
2240 struct mlx5e_priv *priv = netdev_priv(dev);
2241 struct mlx5_core_dev *mdev = priv->mdev;
2242
2243 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2244 vf_stats);
2245}
2246
b3f63c3d
MF		 2247static void mlx5e_add_vxlan_port(struct net_device *netdev,
2248 sa_family_t sa_family, __be16 port)
2249{
2250 struct mlx5e_priv *priv = netdev_priv(netdev);
2251
2252 if (!mlx5e_vxlan_allowed(priv->mdev))
2253 return;
2254
2255 mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2256}
2257
2258static void mlx5e_del_vxlan_port(struct net_device *netdev,
2259 sa_family_t sa_family, __be16 port)
2260{
2261 struct mlx5e_priv *priv = netdev_priv(netdev);
2262
2263 if (!mlx5e_vxlan_allowed(priv->mdev))
2264 return;
2265
2266 mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2267}
2268
2269static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2270 struct sk_buff *skb,
2271 netdev_features_t features)
2272{
2273 struct udphdr *udph;
2274 u16 proto;
2275 u16 port = 0;
2276
2277 switch (vlan_get_protocol(skb)) {
2278 case htons(ETH_P_IP):
2279 proto = ip_hdr(skb)->protocol;
2280 break;
2281 case htons(ETH_P_IPV6):
2282 proto = ipv6_hdr(skb)->nexthdr;
2283 break;
2284 default:
2285 goto out;
2286 }
2287
2288 if (proto == IPPROTO_UDP) {
2289 udph = udp_hdr(skb);
2290 port = be16_to_cpu(udph->dest);
2291 }
2292
2293 /* Verify if UDP port is being offloaded by HW */
2294 if (port && mlx5e_vxlan_lookup_port(priv, port))
2295 return features;
2296
2297out:
2298 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2299 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2300}
2301
2302static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2303 struct net_device *netdev,
2304 netdev_features_t features)
2305{
2306 struct mlx5e_priv *priv = netdev_priv(netdev);
2307
2308 features = vlan_features_check(skb, features);
2309 features = vxlan_features_check(skb, features);
2310
2311 /* Validate if the tunneled packet is being offloaded by HW */
2312 if (skb->encapsulation &&
2313 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2314 return mlx5e_vxlan_features_check(priv, skb, features);
2315
2316 return features;
2317}
2318
b0eed40e 2319static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2320 .ndo_open = mlx5e_open,
2321 .ndo_stop = mlx5e_close,
2322 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2323 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2324 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2325 .ndo_get_stats64 = mlx5e_get_stats,
2326 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2327 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2328 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2329 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2330 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2331 .ndo_change_mtu = mlx5e_change_mtu,
2332 .ndo_do_ioctl = mlx5e_ioctl,
2333};
2334
2335static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2336 .ndo_open = mlx5e_open,
2337 .ndo_stop = mlx5e_close,
2338 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2339 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2340 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2341 .ndo_get_stats64 = mlx5e_get_stats,
2342 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2343 .ndo_set_mac_address = mlx5e_set_mac,
2344 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2345 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2346 .ndo_set_features = mlx5e_set_features,
2347 .ndo_change_mtu = mlx5e_change_mtu,
2348 .ndo_do_ioctl = mlx5e_ioctl,
b3f63c3d
MF		 2349 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2350 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2351 .ndo_features_check = mlx5e_features_check,
b0eed40e
SM		 2352 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2353 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2354 .ndo_get_vf_config = mlx5e_get_vf_config,
2355 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2356 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2357};
2358
2359static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2360{
2361 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2362 return -ENOTSUPP;
2363 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2364 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2365 !MLX5_CAP_ETH(mdev, csum_cap) ||
2366 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2367 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2368 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2369 MLX5_CAP_FLOWTABLE(mdev,
2370 flow_table_properties_nic_receive.max_ft_level)
2371 < 3) {
f62b8bb8
AV		 2372 mlx5_core_warn(mdev,
2373 "Not creating net device, some required device capabilities are missing\n");
2374 return -ENOTSUPP;
2375 }
66189961
TT		 2376 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2377 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2378 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2379 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2380
f62b8bb8
AV		 2381 return 0;
2382}
2383
58d52291
AS		 2384u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2385{
2386 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2387
2388 return bf_buf_size -
2389 sizeof(struct mlx5e_tx_wqe) +
2390 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2391}
2392
08fb1dac
SM		 2393#ifdef CONFIG_MLX5_CORE_EN_DCB
2394static void mlx5e_ets_init(struct mlx5e_priv *priv)
2395{
2396 int i;
2397
2398 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2399 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2400 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2401 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2402 priv->params.ets.prio_tc[i] = i;
2403 }
2404
2405 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2406 priv->params.ets.prio_tc[0] = 1;
2407 priv->params.ets.prio_tc[1] = 0;
2408}
2409#endif
2410
d8c9660d
TT		 2411void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2412 u32 *indirection_rqt, int len,
85082dba
TT		 2413 int num_channels)
2414{
d8c9660d
TT		 2415 int node = mdev->priv.numa_node;
2416 int node_num_of_cores;
85082dba
TT		 2417 int i;
2418
d8c9660d
TT		 2419 if (node == -1)
2420 node = first_online_node;
2421
2422 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2423
2424 if (node_num_of_cores)
2425 num_channels = min_t(int, num_channels, node_num_of_cores);
2426
85082dba
TT		 2427 for (i = 0; i < len; i++)
2428 indirection_rqt[i] = i % num_channels;
2429}
2430
bc77b240
TT		 2431static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2432{
2433 return MLX5_CAP_GEN(mdev, striding_rq) &&
2434 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2435 MLX5_CAP_ETH(mdev, reg_umr_sq);
2436}
2437
f62b8bb8
AV		 2438static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2439 struct net_device *netdev,
936896e9 2440 int num_channels)
f62b8bb8
AV		 2441{
2442 struct mlx5e_priv *priv = netdev_priv(netdev);
2443
2444 priv->params.log_sq_size =
2445 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 2446 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 2447 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2448 MLX5_WQ_TYPE_LINKED_LIST;
2449
2450 switch (priv->params.rq_wq_type) {
2451 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2452 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2453 priv->params.lro_en = true;
2454 break;
2455 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2456 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2457 }
2458
2459 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2460 BIT(priv->params.log_rq_size));
f62b8bb8
AV		 2461 priv->params.rx_cq_moderation_usec =
2462 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2463 priv->params.rx_cq_moderation_pkts =
2464 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2465 priv->params.tx_cq_moderation_usec =
2466 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2467 priv->params.tx_cq_moderation_pkts =
2468 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2469 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8 2470 priv->params.num_tc = 1;
2be6967c 2471 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2472
57afead5
AS		 2473 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2474 sizeof(priv->params.toeplitz_hash_key));
2475
d8c9660d 2476 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
85082dba 2477 MLX5E_INDIR_RQT_SIZE, num_channels);
2d75b2bc 2478
f62b8bb8
AV		 2479 priv->params.lro_wqe_sz =
2480 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2481
2482 priv->mdev = mdev;
2483 priv->netdev = netdev;
936896e9 2484 priv->params.num_channels = num_channels;
f62b8bb8 2485
08fb1dac
SM		 2486#ifdef CONFIG_MLX5_CORE_EN_DCB
2487 mlx5e_ets_init(priv);
2488#endif
f62b8bb8 2489
f62b8bb8
AV		 2490 mutex_init(&priv->state_lock);
2491
2492 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2493 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2494 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2495}
2496
2497static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2498{
2499 struct mlx5e_priv *priv = netdev_priv(netdev);
2500
e1d7d349 2501 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2502 if (is_zero_ether_addr(netdev->dev_addr) &&
2503 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2504 eth_hw_addr_random(netdev);
2505 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2506 }
f62b8bb8
AV		 2507}
2508
2509static void mlx5e_build_netdev(struct net_device *netdev)
2510{
2511 struct mlx5e_priv *priv = netdev_priv(netdev);
2512 struct mlx5_core_dev *mdev = priv->mdev;
2513
2514 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2515
08fb1dac 2516 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2517 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2518#ifdef CONFIG_MLX5_CORE_EN_DCB
2519 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2520#endif
2521 } else {
b0eed40e 2522 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2523 }
66e49ded 2524
f62b8bb8
AV		 2525 netdev->watchdog_timeo = 15 * HZ;
2526
2527 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2528
12be4b21 2529 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2530 netdev->vlan_features |= NETIF_F_IP_CSUM;
2531 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2532 netdev->vlan_features |= NETIF_F_GRO;
2533 netdev->vlan_features |= NETIF_F_TSO;
2534 netdev->vlan_features |= NETIF_F_TSO6;
2535 netdev->vlan_features |= NETIF_F_RXCSUM;
2536 netdev->vlan_features |= NETIF_F_RXHASH;
2537
2538 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2539 netdev->vlan_features |= NETIF_F_LRO;
2540
2541 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2542 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2543 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2544 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2545
b3f63c3d
MF		 2546 if (mlx5e_vxlan_allowed(mdev)) {
2547 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2548 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2549 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2550 netdev->hw_enc_features |= NETIF_F_TSO;
2551 netdev->hw_enc_features |= NETIF_F_TSO6;
2552 netdev->hw_enc_features |= NETIF_F_RXHASH;
2553 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2554 }
2555
f62b8bb8
AV		 2556 netdev->features = netdev->hw_features;
2557 if (!priv->params.lro_en)
2558 netdev->features &= ~NETIF_F_LRO;
2559
e8f887ac
AV		 2560#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2561 if (FT_CAP(flow_modify_en) &&
2562 FT_CAP(modify_root) &&
2563 FT_CAP(identified_miss_table_mode) &&
2564 FT_CAP(flow_table_modify))
2565 priv->netdev->hw_features |= NETIF_F_HW_TC;
2566
f62b8bb8
AV		 2567 netdev->features |= NETIF_F_HIGHDMA;
2568
2569 netdev->priv_flags |= IFF_UNICAST_FLT;
2570
2571 mlx5e_set_netdev_dev_addr(netdev);
2572}
2573
2574static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
a606b0f6 2575 struct mlx5_core_mkey *mkey)
f62b8bb8
AV		 2576{
2577 struct mlx5_core_dev *mdev = priv->mdev;
2578 struct mlx5_create_mkey_mbox_in *in;
2579 int err;
2580
2581 in = mlx5_vzalloc(sizeof(*in));
2582 if (!in)
2583 return -ENOMEM;
2584
2585 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2586 MLX5_PERM_LOCAL_READ |
2587 MLX5_ACCESS_MODE_PA;
2588 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2589 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2590
a606b0f6 2591 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
f62b8bb8
AV		 2592 NULL);
2593
2594 kvfree(in);
2595
2596 return err;
2597}
2598
593cf338
RS		 2599static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2600{
2601 struct mlx5_core_dev *mdev = priv->mdev;
2602 int err;
2603
2604 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2605 if (err) {
2606 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2607 priv->q_counter = 0;
2608 }
2609}
2610
2611static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2612{
2613 if (!priv->q_counter)
2614 return;
2615
2616 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2617}
2618
bc77b240
TT		 2619static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2620{
2621 struct mlx5_core_dev *mdev = priv->mdev;
2622 struct mlx5_create_mkey_mbox_in *in;
2623 struct mlx5_mkey_seg *mkc;
2624 int inlen = sizeof(*in);
2625 u64 npages =
2626 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2627 int err;
2628
2629 in = mlx5_vzalloc(inlen);
2630 if (!in)
2631 return -ENOMEM;
2632
2633 mkc = &in->seg;
2634 mkc->status = MLX5_MKEY_STATUS_FREE;
2635 mkc->flags = MLX5_PERM_UMR_EN |
2636 MLX5_PERM_LOCAL_READ |
2637 MLX5_PERM_LOCAL_WRITE |
2638 MLX5_ACCESS_MODE_MTT;
2639
2640 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2641 mkc->flags_pd = cpu_to_be32(priv->pdn);
2642 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2643 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2644 mkc->log2_page_size = PAGE_SHIFT;
2645
2646 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2647 NULL, NULL);
2648
2649 kvfree(in);
2650
2651 return err;
2652}
2653
f62b8bb8
AV		 2654static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2655{
2656 struct net_device *netdev;
2657 struct mlx5e_priv *priv;
3435ab59 2658 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 2659 int err;
2660
2661 if (mlx5e_check_required_hca_cap(mdev))
2662 return NULL;
2663
08fb1dac
SM		 2664 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2665 nch * MLX5E_MAX_NUM_TC,
2666 nch);
f62b8bb8
AV		 2667 if (!netdev) {
2668 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2669 return NULL;
2670 }
2671
936896e9 2672 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 2673 mlx5e_build_netdev(netdev);
2674
2675 netif_carrier_off(netdev);
2676
2677 priv = netdev_priv(netdev);
2678
0ba42241 2679 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
f62b8bb8 2680 if (err) {
1f2a3003 2681 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2682 goto err_free_netdev;
2683 }
2684
2685 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2686 if (err) {
1f2a3003 2687 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2688 goto err_unmap_free_uar;
2689 }
2690
8d7f9ecb 2691 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 2692 if (err) {
1f2a3003 2693 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2694 goto err_dealloc_pd;
2695 }
2696
a606b0f6 2697 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
f62b8bb8 2698 if (err) {
1f2a3003 2699 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2700 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2701 }
2702
bc77b240
TT		 2703 err = mlx5e_create_umr_mkey(priv);
2704 if (err) {
2705 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2706 goto err_destroy_mkey;
2707 }
2708
40ab6a6e 2709 err = mlx5e_create_tises(priv);
5c50368f 2710 if (err) {
40ab6a6e 2711 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
bc77b240 2712 goto err_destroy_umr_mkey;
5c50368f
AS		 2713 }
2714
2715 err = mlx5e_open_drop_rq(priv);
2716 if (err) {
2717 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 2718 goto err_destroy_tises;
5c50368f
AS		 2719 }
2720
40ab6a6e 2721 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2722 if (err) {
40ab6a6e 2723 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
5c50368f
AS		 2724 goto err_close_drop_rq;
2725 }
2726
40ab6a6e 2727 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2728 if (err) {
40ab6a6e
AS		 2729 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2730 goto err_destroy_rqt_indir;
5c50368f
AS		 2731 }
2732
40ab6a6e 2733 err = mlx5e_create_tirs(priv);
5c50368f 2734 if (err) {
40ab6a6e
AS		 2735 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2736 goto err_destroy_rqt_single;
5c50368f
AS		 2737 }
2738
40ab6a6e 2739 err = mlx5e_create_flow_tables(priv);
5c50368f 2740 if (err) {
40ab6a6e
AS		 2741 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2742 goto err_destroy_tirs;
5c50368f
AS		 2743 }
2744
593cf338
RS		 2745 mlx5e_create_q_counter(priv);
2746
5c50368f
AS		 2747 mlx5e_init_eth_addr(priv);
2748
b3f63c3d
MF		 2749 mlx5e_vxlan_init(priv);
2750
e8f887ac
AV		 2751 err = mlx5e_tc_init(priv);
2752 if (err)
593cf338 2753 goto err_dealloc_q_counters;
e8f887ac 2754
08fb1dac
SM		 2755#ifdef CONFIG_MLX5_CORE_EN_DCB
2756 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2757#endif
2758
f62b8bb8
AV		 2759 err = register_netdev(netdev);
2760 if (err) {
1f2a3003 2761 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
e8f887ac 2762 goto err_tc_cleanup;
f62b8bb8
AV		 2763 }
2764
b3f63c3d
MF		 2765 if (mlx5e_vxlan_allowed(mdev))
2766 vxlan_get_rx_port(netdev);
2767
f62b8bb8 2768 mlx5e_enable_async_events(priv);
9b37b07f 2769 schedule_work(&priv->set_rx_mode_work);
f62b8bb8
AV		 2770
2771 return priv;
2772
e8f887ac
AV		 2773err_tc_cleanup:
2774 mlx5e_tc_cleanup(priv);
2775
593cf338
RS		 2776err_dealloc_q_counters:
2777 mlx5e_destroy_q_counter(priv);
40ab6a6e 2778 mlx5e_destroy_flow_tables(priv);
5c50368f 2779
40ab6a6e
AS		 2780err_destroy_tirs:
2781 mlx5e_destroy_tirs(priv);
5c50368f 2782
40ab6a6e
AS		 2783err_destroy_rqt_single:
2784 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2785
40ab6a6e
AS		 2786err_destroy_rqt_indir:
2787 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f
AS		 2788
2789err_close_drop_rq:
2790 mlx5e_close_drop_rq(priv);
2791
40ab6a6e
AS		 2792err_destroy_tises:
2793 mlx5e_destroy_tises(priv);
5c50368f 2794
bc77b240
TT		 2795err_destroy_umr_mkey:
2796 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
2797
f62b8bb8 2798err_destroy_mkey:
a606b0f6 2799 mlx5_core_destroy_mkey(mdev, &priv->mkey);
f62b8bb8 2800
3191e05f 2801err_dealloc_transport_domain:
8d7f9ecb 2802 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 2803
f62b8bb8
AV		 2804err_dealloc_pd:
2805 mlx5_core_dealloc_pd(mdev, priv->pdn);
2806
2807err_unmap_free_uar:
2808 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2809
2810err_free_netdev:
2811 free_netdev(netdev);
2812
2813 return NULL;
2814}
2815
2816static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2817{
2818 struct mlx5e_priv *priv = vpriv;
2819 struct net_device *netdev = priv->netdev;
2820
9b37b07f
AS		 2821 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2822
2823 schedule_work(&priv->set_rx_mode_work);
1cefa326
AS		 2824 mlx5e_disable_async_events(priv);
2825 flush_scheduled_work();
f62b8bb8 2826 unregister_netdev(netdev);
e8f887ac 2827 mlx5e_tc_cleanup(priv);
b3f63c3d 2828 mlx5e_vxlan_cleanup(priv);
593cf338 2829 mlx5e_destroy_q_counter(priv);
40ab6a6e
AS		 2830 mlx5e_destroy_flow_tables(priv);
2831 mlx5e_destroy_tirs(priv);
2832 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2833 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2834 mlx5e_close_drop_rq(priv);
40ab6a6e 2835 mlx5e_destroy_tises(priv);
bc77b240 2836 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
a606b0f6 2837 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
8d7f9ecb 2838 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 2839 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2840 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
f62b8bb8
AV		 2841 free_netdev(netdev);
2842}
2843
2844static void *mlx5e_get_netdev(void *vpriv)
2845{
2846 struct mlx5e_priv *priv = vpriv;
2847
2848 return priv->netdev;
2849}
2850
2851static struct mlx5_interface mlx5e_interface = {
2852 .add = mlx5e_create_netdev,
2853 .remove = mlx5e_destroy_netdev,
2854 .event = mlx5e_async_event,
2855 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2856 .get_dev = mlx5e_get_netdev,
2857};
2858
2859void mlx5e_init(void)
2860{
2861 mlx5_register_interface(&mlx5e_interface);
2862}
2863
2864void mlx5e_cleanup(void)
2865{
2866 mlx5_unregister_interface(&mlx5e_interface);
2867}
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