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taskstats: fix the length of cgroupstats_cmd_get_policy
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
f62b8bb8 38#include "en.h"
e8f887ac 39#include "en_tc.h"
66e49ded 40#include "eswitch.h"
b3f63c3d 41#include "vxlan.h"
f62b8bb8
AV		 42
43struct mlx5e_rq_param {
cb3c7fd4
GR		 44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
46 bool am_enabled;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
58d52291 52 u16 max_inline;
cff92d7c 53 u8 min_inline_mode;
f10b7cc7 54 enum mlx5e_sq_type type;
f62b8bb8
AV		 55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
81static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
82{
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
87 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
88 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
89 MLX5_MPWRQ_LOG_STRIDE_SIZE;
90 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
91 priv->params.mpwqe_log_stride_sz;
92 break;
93 default: /* MLX5_WQ_TYPE_LINKED_LIST */
94 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
95 }
96 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
97 BIT(priv->params.log_rq_size));
98
99 mlx5_core_info(priv->mdev,
100 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
101 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
102 BIT(priv->params.log_rq_size),
103 BIT(priv->params.mpwqe_log_stride_sz),
104 priv->params.rx_cqe_compress_admin);
105}
106
107static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
108{
86994156
RS		 109 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
110 !priv->xdp_prog ?
2fc4bfb7
SM		 111 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
112 MLX5_WQ_TYPE_LINKED_LIST;
113 mlx5e_set_rq_type_params(priv, rq_type);
114}
115
f62b8bb8
AV		 116static void mlx5e_update_carrier(struct mlx5e_priv *priv)
117{
118 struct mlx5_core_dev *mdev = priv->mdev;
119 u8 port_state;
120
121 port_state = mlx5_query_vport_state(mdev,
e7546514 122 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 123
87424ad5
SD		 124 if (port_state == VPORT_STATE_UP) {
125 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 126 netif_carrier_on(priv->netdev);
87424ad5
SD		 127 } else {
128 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 129 netif_carrier_off(priv->netdev);
87424ad5 130 }
f62b8bb8
AV		 131}
132
133static void mlx5e_update_carrier_work(struct work_struct *work)
134{
135 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
136 update_carrier_work);
137
138 mutex_lock(&priv->state_lock);
139 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
140 mlx5e_update_carrier(priv);
141 mutex_unlock(&priv->state_lock);
142}
143
3947ca18
DJ		 144static void mlx5e_tx_timeout_work(struct work_struct *work)
145{
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147 tx_timeout_work);
148 int err;
149
150 rtnl_lock();
151 mutex_lock(&priv->state_lock);
152 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
153 goto unlock;
154 mlx5e_close_locked(priv->netdev);
155 err = mlx5e_open_locked(priv->netdev);
156 if (err)
157 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
158 err);
159unlock:
160 mutex_unlock(&priv->state_lock);
161 rtnl_unlock();
162}
163
9218b44d 164static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 165{
9218b44d 166 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 167 struct mlx5e_rq_stats *rq_stats;
168 struct mlx5e_sq_stats *sq_stats;
9218b44d 169 u64 tx_offload_none = 0;
f62b8bb8
AV		 170 int i, j;
171
9218b44d 172 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 173 for (i = 0; i < priv->params.num_channels; i++) {
174 rq_stats = &priv->channel[i]->rq.stats;
175
faf4478b
GP		 176 s->rx_packets += rq_stats->packets;
177 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 178 s->rx_lro_packets += rq_stats->lro_packets;
179 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 180 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 181 s->rx_csum_complete += rq_stats->csum_complete;
182 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 183 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 184 s->rx_xdp_tx += rq_stats->xdp_tx;
185 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 186 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 187 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 188 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 189 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
190 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 191 s->rx_cache_reuse += rq_stats->cache_reuse;
192 s->rx_cache_full += rq_stats->cache_full;
193 s->rx_cache_empty += rq_stats->cache_empty;
194 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 195
a4418a6c 196 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 197 sq_stats = &priv->channel[i]->sq[j].stats;
198
faf4478b
GP		 199 s->tx_packets += sq_stats->packets;
200 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 201 s->tx_tso_packets += sq_stats->tso_packets;
202 s->tx_tso_bytes += sq_stats->tso_bytes;
203 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
204 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 205 s->tx_queue_stopped += sq_stats->stopped;
206 s->tx_queue_wake += sq_stats->wake;
207 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 208 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 209 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
210 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 211 }
212 }
213
9218b44d 214 /* Update calculated offload counters */
bfe6d8d1
GP		 215 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
216 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 217
bfe6d8d1 218 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 219 priv->stats.pport.phy_counters,
220 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 221}
222
223static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
224{
225 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
226 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 227 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 228 struct mlx5_core_dev *mdev = priv->mdev;
229
f62b8bb8
AV		 230 MLX5_SET(query_vport_counter_in, in, opcode,
231 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
232 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
233 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
234
235 memset(out, 0, outlen);
9218b44d
GP		 236 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
237}
238
239static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
240{
241 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
242 struct mlx5_core_dev *mdev = priv->mdev;
243 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 244 int prio;
9218b44d
GP		 245 void *out;
246 u32 *in;
247
248 in = mlx5_vzalloc(sz);
249 if (!in)
f62b8bb8
AV		 250 goto free_out;
251
9218b44d 252 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 253
9218b44d
GP		 254 out = pstats->IEEE_802_3_counters;
255 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
256 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 257
9218b44d
GP		 258 out = pstats->RFC_2863_counters;
259 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
260 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
261
262 out = pstats->RFC_2819_counters;
263 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
264 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 265
121fcdc8
GP		 266 out = pstats->phy_counters;
267 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
268 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
269
cf678570
GP		 270 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
271 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
272 out = pstats->per_prio_counters[prio];
273 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
274 mlx5_core_access_reg(mdev, in, sz, out, sz,
275 MLX5_REG_PPCNT, 0, 0);
276 }
277
f62b8bb8 278free_out:
9218b44d
GP		 279 kvfree(in);
280}
281
282static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
283{
284 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
285
286 if (!priv->q_counter)
287 return;
288
289 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
290 &qcnt->rx_out_of_buffer);
291}
292
293void mlx5e_update_stats(struct mlx5e_priv *priv)
294{
9218b44d
GP		 295 mlx5e_update_q_counter(priv);
296 mlx5e_update_vport_counters(priv);
297 mlx5e_update_pport_counters(priv);
121fcdc8 298 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 299}
300
cb67b832 301void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 302{
303 struct delayed_work *dwork = to_delayed_work(work);
304 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
305 update_stats_work);
306 mutex_lock(&priv->state_lock);
307 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 308 priv->profile->update_stats(priv);
7bb29755
MF		 309 queue_delayed_work(priv->wq, dwork,
310 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 311 }
312 mutex_unlock(&priv->state_lock);
313}
314
daa21560
TT		 315static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
316 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 317{
daa21560
TT		 318 struct mlx5e_priv *priv = vpriv;
319
e0f46eb9 320 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 321 return;
322
f62b8bb8
AV		 323 switch (event) {
324 case MLX5_DEV_EVENT_PORT_UP:
325 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 326 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 327 break;
328
329 default:
330 break;
331 }
332}
333
f62b8bb8
AV		 334static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
335{
e0f46eb9 336 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 337}
338
339static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
340{
e0f46eb9 341 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 342 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 343}
344
facc9699
SM		 345#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
346#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
347
7e426671
TT		 348static inline int mlx5e_get_wqe_mtt_sz(void)
349{
350 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
351 * To avoid copying garbage after the mtt array, we allocate
352 * a little more.
353 */
354 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
355 MLX5_UMR_MTT_ALIGNMENT);
356}
357
358static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
359 struct mlx5e_umr_wqe *wqe, u16 ix)
360{
361 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
362 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
363 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 364 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 365 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
366 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
367
368 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
369 ds_cnt);
370 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
371 cseg->imm = rq->mkey_be;
372
373 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
374 ucseg->klm_octowords =
375 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
376 ucseg->bsf_octowords =
377 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
378 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
379
380 dseg->lkey = sq->mkey_be;
381 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
382}
383
384static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
385 struct mlx5e_channel *c)
386{
387 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
388 int mtt_sz = mlx5e_get_wqe_mtt_sz();
389 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
390 int i;
391
21c59685
SM		 392 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
393 GFP_KERNEL, cpu_to_node(c->cpu));
394 if (!rq->mpwqe.info)
7e426671
TT		 395 goto err_out;
396
397 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 398 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 399 cpu_to_node(c->cpu));
21c59685 400 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 401 goto err_free_wqe_info;
402
403 for (i = 0; i < wq_sz; i++) {
21c59685 404 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 405
21c59685 406 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 407 MLX5_UMR_ALIGN);
408 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
409 PCI_DMA_TODEVICE);
410 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
411 goto err_unmap_mtts;
412
413 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
414 }
415
416 return 0;
417
418err_unmap_mtts:
419 while (--i >= 0) {
21c59685 420 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 421
422 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
423 PCI_DMA_TODEVICE);
424 }
21c59685 425 kfree(rq->mpwqe.mtt_no_align);
7e426671 426err_free_wqe_info:
21c59685 427 kfree(rq->mpwqe.info);
7e426671
TT		 428
429err_out:
430 return -ENOMEM;
431}
432
433static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
434{
435 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
436 int mtt_sz = mlx5e_get_wqe_mtt_sz();
437 int i;
438
439 for (i = 0; i < wq_sz; i++) {
21c59685 440 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 441
442 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
443 PCI_DMA_TODEVICE);
444 }
21c59685
SM		 445 kfree(rq->mpwqe.mtt_no_align);
446 kfree(rq->mpwqe.info);
7e426671
TT		 447}
448
f5f82476
OG		 449static bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv)
450{
451 struct mlx5_eswitch_rep *rep = (struct mlx5_eswitch_rep *)priv->ppriv;
452
453 if (rep && rep->vport != FDB_UPLINK_VPORT)
454 return true;
455
456 return false;
457}
458
f62b8bb8
AV		 459static int mlx5e_create_rq(struct mlx5e_channel *c,
460 struct mlx5e_rq_param *param,
461 struct mlx5e_rq *rq)
462{
463 struct mlx5e_priv *priv = c->priv;
464 struct mlx5_core_dev *mdev = priv->mdev;
465 void *rqc = param->rqc;
466 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 467 u32 byte_count;
1bfecfca
SM		 468 u32 frag_sz;
469 int npages;
f62b8bb8
AV		 470 int wq_sz;
471 int err;
472 int i;
473
311c7c71
SM		 474 param->wq.db_numa_node = cpu_to_node(c->cpu);
475
f62b8bb8
AV		 476 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
477 &rq->wq_ctrl);
478 if (err)
479 return err;
480
481 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
482
483 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 484
7e426671
TT		 485 rq->wq_type = priv->params.rq_wq_type;
486 rq->pdev = c->pdev;
487 rq->netdev = c->netdev;
488 rq->tstamp = &priv->tstamp;
489 rq->channel = c;
490 rq->ix = c->ix;
491 rq->priv = c->priv;
86994156 492 rq->xdp_prog = priv->xdp_prog;
7e426671 493
b5503b99
SM		 494 rq->buff.map_dir = DMA_FROM_DEVICE;
495 if (rq->xdp_prog)
496 rq->buff.map_dir = DMA_BIDIRECTIONAL;
497
461017cb
TT		 498 switch (priv->params.rq_wq_type) {
499 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476
OG		 500 if (mlx5e_is_vf_vport_rep(priv)) {
501 err = -EINVAL;
502 goto err_rq_wq_destroy;
503 }
504
461017cb
TT		 505 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
506 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 507 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 508
21c59685 509 rq->mpwqe.mtt_offset = c->ix *
fe4c988b
SM		 510 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
511
d9d9f156
TT		 512 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
513 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
1bfecfca
SM		 514
515 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
516 byte_count = rq->buff.wqe_sz;
7e426671
TT		 517 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
518 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
519 if (err)
520 goto err_rq_wq_destroy;
461017cb
TT		 521 break;
522 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 523 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
524 GFP_KERNEL, cpu_to_node(c->cpu));
525 if (!rq->dma_info) {
461017cb
TT		 526 err = -ENOMEM;
527 goto err_rq_wq_destroy;
528 }
1bfecfca 529
f5f82476
OG		 530 if (mlx5e_is_vf_vport_rep(priv))
531 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
532 else
533 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
534
461017cb 535 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 536 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 537
1bfecfca 538 rq->buff.wqe_sz = (priv->params.lro_en) ?
461017cb
TT		 539 priv->params.lro_wqe_sz :
540 MLX5E_SW2HW_MTU(priv->netdev->mtu);
1bfecfca
SM		 541 byte_count = rq->buff.wqe_sz;
542
543 /* calc the required page order */
544 frag_sz = MLX5_RX_HEADROOM +
545 byte_count /* packet data */ +
546 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
547 frag_sz = SKB_DATA_ALIGN(frag_sz);
548
549 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
550 rq->buff.page_order = order_base_2(npages);
551
461017cb 552 byte_count |= MLX5_HW_START_PADDING;
7e426671 553 rq->mkey_be = c->mkey_be;
461017cb 554 }
f62b8bb8
AV		 555
556 for (i = 0; i < wq_sz; i++) {
557 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
558
461017cb 559 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 560 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 561 }
562
cb3c7fd4
GR		 563 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
564 rq->am.mode = priv->params.rx_cq_period_mode;
565
4415a031
TT		 566 rq->page_cache.head = 0;
567 rq->page_cache.tail = 0;
568
86994156
RS		 569 if (rq->xdp_prog)
570 bpf_prog_add(rq->xdp_prog, 1);
571
f62b8bb8
AV		 572 return 0;
573
574err_rq_wq_destroy:
575 mlx5_wq_destroy(&rq->wq_ctrl);
576
577 return err;
578}
579
580static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
581{
4415a031
TT		 582 int i;
583
86994156
RS		 584 if (rq->xdp_prog)
585 bpf_prog_put(rq->xdp_prog);
586
461017cb
TT		 587 switch (rq->wq_type) {
588 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 589 mlx5e_rq_free_mpwqe_info(rq);
461017cb
TT		 590 break;
591 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 592 kfree(rq->dma_info);
461017cb
TT		 593 }
594
4415a031
TT		 595 for (i = rq->page_cache.head; i != rq->page_cache.tail;
596 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
597 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
598
599 mlx5e_page_release(rq, dma_info, false);
600 }
f62b8bb8
AV		 601 mlx5_wq_destroy(&rq->wq_ctrl);
602}
603
604static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
605{
50cfa25a 606 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 607 struct mlx5_core_dev *mdev = priv->mdev;
608
609 void *in;
610 void *rqc;
611 void *wq;
612 int inlen;
613 int err;
614
615 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
616 sizeof(u64) * rq->wq_ctrl.buf.npages;
617 in = mlx5_vzalloc(inlen);
618 if (!in)
619 return -ENOMEM;
620
621 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
622 wq = MLX5_ADDR_OF(rqc, rqc, wq);
623
624 memcpy(rqc, param->rqc, sizeof(param->rqc));
625
97de9f31 626 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 627 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 628 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 629 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 630 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 631 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
632
633 mlx5_fill_page_array(&rq->wq_ctrl.buf,
634 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
635
7db22ffb 636 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 637
638 kvfree(in);
639
640 return err;
641}
642
36350114
GP		 643static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
644 int next_state)
f62b8bb8
AV		 645{
646 struct mlx5e_channel *c = rq->channel;
647 struct mlx5e_priv *priv = c->priv;
648 struct mlx5_core_dev *mdev = priv->mdev;
649
650 void *in;
651 void *rqc;
652 int inlen;
653 int err;
654
655 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
656 in = mlx5_vzalloc(inlen);
657 if (!in)
658 return -ENOMEM;
659
660 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
661
662 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
663 MLX5_SET(rqc, rqc, state, next_state);
664
7db22ffb 665 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 666
667 kvfree(in);
668
669 return err;
670}
671
36350114
GP		 672static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
673{
674 struct mlx5e_channel *c = rq->channel;
675 struct mlx5e_priv *priv = c->priv;
676 struct mlx5_core_dev *mdev = priv->mdev;
677
678 void *in;
679 void *rqc;
680 int inlen;
681 int err;
682
683 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
684 in = mlx5_vzalloc(inlen);
685 if (!in)
686 return -ENOMEM;
687
688 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
689
690 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 691 MLX5_SET64(modify_rq_in, in, modify_bitmask,
692 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 693 MLX5_SET(rqc, rqc, vsd, vsd);
694 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
695
696 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
697
698 kvfree(in);
699
700 return err;
701}
702
f62b8bb8
AV		 703static void mlx5e_disable_rq(struct mlx5e_rq *rq)
704{
50cfa25a 705 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 706}
707
708static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
709{
01c196a2 710 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 711 struct mlx5e_channel *c = rq->channel;
712 struct mlx5e_priv *priv = c->priv;
713 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 714
01c196a2 715 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 716 if (wq->cur_sz >= priv->params.min_rx_wqes)
717 return 0;
718
719 msleep(20);
720 }
721
722 return -ETIMEDOUT;
723}
724
f2fde18c
SM		 725static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
726{
727 struct mlx5_wq_ll *wq = &rq->wq;
728 struct mlx5e_rx_wqe *wqe;
729 __be16 wqe_ix_be;
730 u16 wqe_ix;
731
8484f9ed
SM		 732 /* UMR WQE (if in progress) is always at wq->head */
733 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 734 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 735
f2fde18c
SM		 736 while (!mlx5_wq_ll_is_empty(wq)) {
737 wqe_ix_be = *wq->tail_next;
738 wqe_ix = be16_to_cpu(wqe_ix_be);
739 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
740 rq->dealloc_wqe(rq, wqe_ix);
741 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
742 &wqe->next.next_wqe_index);
743 }
744}
745
f62b8bb8
AV		 746static int mlx5e_open_rq(struct mlx5e_channel *c,
747 struct mlx5e_rq_param *param,
748 struct mlx5e_rq *rq)
749{
d3c9bc27
TT		 750 struct mlx5e_sq *sq = &c->icosq;
751 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 752 int err;
753
754 err = mlx5e_create_rq(c, param, rq);
755 if (err)
756 return err;
757
758 err = mlx5e_enable_rq(rq, param);
759 if (err)
760 goto err_destroy_rq;
761
36350114 762 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 763 if (err)
764 goto err_disable_rq;
765
cb3c7fd4
GR		 766 if (param->am_enabled)
767 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
768
f10b7cc7
SM		 769 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
770 sq->db.ico_wqe[pi].num_wqebbs = 1;
d3c9bc27 771 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 772
773 return 0;
774
775err_disable_rq:
776 mlx5e_disable_rq(rq);
777err_destroy_rq:
778 mlx5e_destroy_rq(rq);
779
780 return err;
781}
782
783static void mlx5e_close_rq(struct mlx5e_rq *rq)
784{
f2fde18c 785 set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
f62b8bb8 786 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 787 cancel_work_sync(&rq->am.work);
788
f62b8bb8 789 mlx5e_disable_rq(rq);
6cd392a0 790 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 791 mlx5e_destroy_rq(rq);
792}
793
b5503b99
SM		 794static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
795{
796 kfree(sq->db.xdp.di);
797 kfree(sq->db.xdp.wqe_info);
798}
799
800static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
801{
802 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
803
804 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
805 GFP_KERNEL, numa);
806 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
807 GFP_KERNEL, numa);
808 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
809 mlx5e_free_sq_xdp_db(sq);
810 return -ENOMEM;
811 }
812
813 return 0;
814}
815
f10b7cc7 816static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
f62b8bb8 817{
f10b7cc7 818 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 819}
820
f10b7cc7
SM		 821static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
822{
823 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
824
825 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
826 GFP_KERNEL, numa);
827 if (!sq->db.ico_wqe)
828 return -ENOMEM;
829
830 return 0;
831}
832
833static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
834{
835 kfree(sq->db.txq.wqe_info);
836 kfree(sq->db.txq.dma_fifo);
837 kfree(sq->db.txq.skb);
838}
839
840static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
f62b8bb8
AV		 841{
842 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
843 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
844
f10b7cc7
SM		 845 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
846 GFP_KERNEL, numa);
847 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
848 GFP_KERNEL, numa);
849 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
850 GFP_KERNEL, numa);
851 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
852 mlx5e_free_sq_txq_db(sq);
f62b8bb8
AV		 853 return -ENOMEM;
854 }
855
856 sq->dma_fifo_mask = df_sz - 1;
857
858 return 0;
859}
860
f10b7cc7
SM		 861static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
862{
863 switch (sq->type) {
864 case MLX5E_SQ_TXQ:
865 mlx5e_free_sq_txq_db(sq);
866 break;
867 case MLX5E_SQ_ICO:
868 mlx5e_free_sq_ico_db(sq);
869 break;
b5503b99
SM		 870 case MLX5E_SQ_XDP:
871 mlx5e_free_sq_xdp_db(sq);
872 break;
f10b7cc7
SM		 873 }
874}
875
876static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
877{
878 switch (sq->type) {
879 case MLX5E_SQ_TXQ:
880 return mlx5e_alloc_sq_txq_db(sq, numa);
881 case MLX5E_SQ_ICO:
882 return mlx5e_alloc_sq_ico_db(sq, numa);
b5503b99
SM		 883 case MLX5E_SQ_XDP:
884 return mlx5e_alloc_sq_xdp_db(sq, numa);
f10b7cc7
SM		 885 }
886
887 return 0;
888}
889
b5503b99
SM		 890static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
891{
892 switch (sq_type) {
893 case MLX5E_SQ_ICO:
894 return MLX5E_ICOSQ_MAX_WQEBBS;
895 case MLX5E_SQ_XDP:
896 return MLX5E_XDP_TX_WQEBBS;
897 }
898 return MLX5_SEND_WQE_MAX_WQEBBS;
899}
900
f62b8bb8
AV		 901static int mlx5e_create_sq(struct mlx5e_channel *c,
902 int tc,
903 struct mlx5e_sq_param *param,
904 struct mlx5e_sq *sq)
905{
906 struct mlx5e_priv *priv = c->priv;
907 struct mlx5_core_dev *mdev = priv->mdev;
908
909 void *sqc = param->sqc;
910 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
911 int err;
912
f10b7cc7
SM		 913 sq->type = param->type;
914 sq->pdev = c->pdev;
915 sq->tstamp = &priv->tstamp;
916 sq->mkey_be = c->mkey_be;
917 sq->channel = c;
918 sq->tc = tc;
919
fd4782c2 920 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 921 if (err)
922 return err;
923
311c7c71
SM		 924 param->wq.db_numa_node = cpu_to_node(c->cpu);
925
f62b8bb8
AV		 926 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
927 &sq->wq_ctrl);
928 if (err)
929 goto err_unmap_free_uar;
930
931 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 932 if (sq->uar.bf_map) {
933 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
934 sq->uar_map = sq->uar.bf_map;
935 } else {
936 sq->uar_map = sq->uar.map;
937 }
f62b8bb8 938 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 939 sq->max_inline = param->max_inline;
cff92d7c
HHZ		 940 sq->min_inline_mode =
941 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
942 param->min_inline_mode : 0;
f62b8bb8 943
7ec0bb22
DC		 944 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
945 if (err)
f62b8bb8
AV		 946 goto err_sq_wq_destroy;
947
f10b7cc7 948 if (sq->type == MLX5E_SQ_TXQ) {
d3c9bc27
TT		 949 int txq_ix;
950
951 txq_ix = c->ix + tc * priv->params.num_channels;
952 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
953 priv->txq_to_sq_map[txq_ix] = sq;
954 }
f62b8bb8 955
b5503b99 956 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
88a85f99 957 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 958
959 return 0;
960
961err_sq_wq_destroy:
962 mlx5_wq_destroy(&sq->wq_ctrl);
963
964err_unmap_free_uar:
965 mlx5_unmap_free_uar(mdev, &sq->uar);
966
967 return err;
968}
969
970static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
971{
972 struct mlx5e_channel *c = sq->channel;
973 struct mlx5e_priv *priv = c->priv;
974
975 mlx5e_free_sq_db(sq);
976 mlx5_wq_destroy(&sq->wq_ctrl);
977 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
978}
979
980static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
981{
982 struct mlx5e_channel *c = sq->channel;
983 struct mlx5e_priv *priv = c->priv;
984 struct mlx5_core_dev *mdev = priv->mdev;
985
986 void *in;
987 void *sqc;
988 void *wq;
989 int inlen;
990 int err;
991
992 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
993 sizeof(u64) * sq->wq_ctrl.buf.npages;
994 in = mlx5_vzalloc(inlen);
995 if (!in)
996 return -ENOMEM;
997
998 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
999 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1000
1001 memcpy(sqc, param->sqc, sizeof(param->sqc));
1002
f10b7cc7
SM		 1003 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1004 0 : priv->tisn[sq->tc]);
d3c9bc27 1005 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 1006 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 1007 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f10b7cc7 1008 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
f62b8bb8
AV		 1009 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1010
1011 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1012 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1013 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 1014 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1015 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1016
1017 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1018 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1019
7db22ffb 1020 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 1021
1022 kvfree(in);
1023
1024 return err;
1025}
1026
507f0c81
YP		 1027static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1028 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 1029{
1030 struct mlx5e_channel *c = sq->channel;
1031 struct mlx5e_priv *priv = c->priv;
1032 struct mlx5_core_dev *mdev = priv->mdev;
1033
1034 void *in;
1035 void *sqc;
1036 int inlen;
1037 int err;
1038
1039 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1040 in = mlx5_vzalloc(inlen);
1041 if (!in)
1042 return -ENOMEM;
1043
1044 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1045
1046 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1047 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 1048 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1049 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1050 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1051 }
f62b8bb8 1052
7db22ffb 1053 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 1054
1055 kvfree(in);
1056
1057 return err;
1058}
1059
1060static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1061{
1062 struct mlx5e_channel *c = sq->channel;
1063 struct mlx5e_priv *priv = c->priv;
1064 struct mlx5_core_dev *mdev = priv->mdev;
1065
7db22ffb 1066 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 1067 if (sq->rate_limit)
1068 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 1069}
1070
1071static int mlx5e_open_sq(struct mlx5e_channel *c,
1072 int tc,
1073 struct mlx5e_sq_param *param,
1074 struct mlx5e_sq *sq)
1075{
1076 int err;
1077
1078 err = mlx5e_create_sq(c, tc, param, sq);
1079 if (err)
1080 return err;
1081
1082 err = mlx5e_enable_sq(sq, param);
1083 if (err)
1084 goto err_destroy_sq;
1085
507f0c81
YP		 1086 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1087 false, 0);
f62b8bb8
AV		 1088 if (err)
1089 goto err_disable_sq;
1090
d3c9bc27 1091 if (sq->txq) {
d3c9bc27
TT		 1092 netdev_tx_reset_queue(sq->txq);
1093 netif_tx_start_queue(sq->txq);
1094 }
f62b8bb8
AV		 1095
1096 return 0;
1097
1098err_disable_sq:
1099 mlx5e_disable_sq(sq);
1100err_destroy_sq:
1101 mlx5e_destroy_sq(sq);
1102
1103 return err;
1104}
1105
1106static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1107{
1108 __netif_tx_lock_bh(txq);
1109 netif_tx_stop_queue(txq);
1110 __netif_tx_unlock_bh(txq);
1111}
1112
1113static void mlx5e_close_sq(struct mlx5e_sq *sq)
1114{
6e8dd6d6
SM		 1115 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1116 /* prevent netif_tx_wake_queue */
1117 napi_synchronize(&sq->channel->napi);
29429f33 1118
d3c9bc27 1119 if (sq->txq) {
d3c9bc27 1120 netif_tx_disable_queue(sq->txq);
f62b8bb8 1121
6e8dd6d6 1122 /* last doorbell out, godspeed .. */
f10b7cc7
SM		 1123 if (mlx5e_sq_has_room_for(sq, 1)) {
1124 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
d3c9bc27 1125 mlx5e_send_nop(sq, true);
f10b7cc7 1126 }
29429f33 1127 }
f62b8bb8 1128
f62b8bb8 1129 mlx5e_disable_sq(sq);
b5503b99 1130 mlx5e_free_sq_descs(sq);
f62b8bb8
AV		 1131 mlx5e_destroy_sq(sq);
1132}
1133
1134static int mlx5e_create_cq(struct mlx5e_channel *c,
1135 struct mlx5e_cq_param *param,
1136 struct mlx5e_cq *cq)
1137{
1138 struct mlx5e_priv *priv = c->priv;
1139 struct mlx5_core_dev *mdev = priv->mdev;
1140 struct mlx5_core_cq *mcq = &cq->mcq;
1141 int eqn_not_used;
0b6e26ce 1142 unsigned int irqn;
f62b8bb8
AV		 1143 int err;
1144 u32 i;
1145
311c7c71
SM		 1146 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1147 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1148 param->eq_ix = c->ix;
1149
1150 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1151 &cq->wq_ctrl);
1152 if (err)
1153 return err;
1154
1155 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1156
1157 cq->napi = &c->napi;
1158
1159 mcq->cqe_sz = 64;
1160 mcq->set_ci_db = cq->wq_ctrl.db.db;
1161 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1162 *mcq->set_ci_db = 0;
1163 *mcq->arm_db = 0;
1164 mcq->vector = param->eq_ix;
1165 mcq->comp = mlx5e_completion_event;
1166 mcq->event = mlx5e_cq_error_event;
1167 mcq->irqn = irqn;
b50d292b 1168 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 1169
1170 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1171 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1172
1173 cqe->op_own = 0xf1;
1174 }
1175
1176 cq->channel = c;
50cfa25a 1177 cq->priv = priv;
f62b8bb8
AV		 1178
1179 return 0;
1180}
1181
1182static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1183{
1184 mlx5_wq_destroy(&cq->wq_ctrl);
1185}
1186
1187static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1188{
50cfa25a 1189 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1190 struct mlx5_core_dev *mdev = priv->mdev;
1191 struct mlx5_core_cq *mcq = &cq->mcq;
1192
1193 void *in;
1194 void *cqc;
1195 int inlen;
0b6e26ce 1196 unsigned int irqn_not_used;
f62b8bb8
AV		 1197 int eqn;
1198 int err;
1199
1200 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1201 sizeof(u64) * cq->wq_ctrl.buf.npages;
1202 in = mlx5_vzalloc(inlen);
1203 if (!in)
1204 return -ENOMEM;
1205
1206 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1207
1208 memcpy(cqc, param->cqc, sizeof(param->cqc));
1209
1210 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1211 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1212
1213 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1214
9908aa29 1215 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 1216 MLX5_SET(cqc, cqc, c_eqn, eqn);
1217 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1218 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 1219 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1220 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1221
1222 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1223
1224 kvfree(in);
1225
1226 if (err)
1227 return err;
1228
1229 mlx5e_cq_arm(cq);
1230
1231 return 0;
1232}
1233
1234static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1235{
50cfa25a 1236 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1237 struct mlx5_core_dev *mdev = priv->mdev;
1238
1239 mlx5_core_destroy_cq(mdev, &cq->mcq);
1240}
1241
1242static int mlx5e_open_cq(struct mlx5e_channel *c,
1243 struct mlx5e_cq_param *param,
1244 struct mlx5e_cq *cq,
9908aa29 1245 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 1246{
1247 int err;
1248 struct mlx5e_priv *priv = c->priv;
1249 struct mlx5_core_dev *mdev = priv->mdev;
1250
1251 err = mlx5e_create_cq(c, param, cq);
1252 if (err)
1253 return err;
1254
1255 err = mlx5e_enable_cq(cq, param);
1256 if (err)
1257 goto err_destroy_cq;
1258
7524a5d8
GP		 1259 if (MLX5_CAP_GEN(mdev, cq_moderation))
1260 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1261 moderation.usec,
1262 moderation.pkts);
f62b8bb8
AV		 1263 return 0;
1264
1265err_destroy_cq:
1266 mlx5e_destroy_cq(cq);
1267
1268 return err;
1269}
1270
1271static void mlx5e_close_cq(struct mlx5e_cq *cq)
1272{
1273 mlx5e_disable_cq(cq);
1274 mlx5e_destroy_cq(cq);
1275}
1276
1277static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1278{
1279 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1280}
1281
1282static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1283 struct mlx5e_channel_param *cparam)
1284{
1285 struct mlx5e_priv *priv = c->priv;
1286 int err;
1287 int tc;
1288
1289 for (tc = 0; tc < c->num_tc; tc++) {
1290 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1291 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1292 if (err)
1293 goto err_close_tx_cqs;
f62b8bb8
AV		 1294 }
1295
1296 return 0;
1297
1298err_close_tx_cqs:
1299 for (tc--; tc >= 0; tc--)
1300 mlx5e_close_cq(&c->sq[tc].cq);
1301
1302 return err;
1303}
1304
1305static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1306{
1307 int tc;
1308
1309 for (tc = 0; tc < c->num_tc; tc++)
1310 mlx5e_close_cq(&c->sq[tc].cq);
1311}
1312
1313static int mlx5e_open_sqs(struct mlx5e_channel *c,
1314 struct mlx5e_channel_param *cparam)
1315{
1316 int err;
1317 int tc;
1318
1319 for (tc = 0; tc < c->num_tc; tc++) {
1320 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1321 if (err)
1322 goto err_close_sqs;
1323 }
1324
1325 return 0;
1326
1327err_close_sqs:
1328 for (tc--; tc >= 0; tc--)
1329 mlx5e_close_sq(&c->sq[tc]);
1330
1331 return err;
1332}
1333
1334static void mlx5e_close_sqs(struct mlx5e_channel *c)
1335{
1336 int tc;
1337
1338 for (tc = 0; tc < c->num_tc; tc++)
1339 mlx5e_close_sq(&c->sq[tc]);
1340}
1341
5283af89 1342static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1343{
1344 int i;
1345
6bfd390b 1346 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1347 priv->channeltc_to_txq_map[ix][i] =
1348 ix + i * priv->params.num_channels;
03289b88
SM		 1349}
1350
507f0c81
YP		 1351static int mlx5e_set_sq_maxrate(struct net_device *dev,
1352 struct mlx5e_sq *sq, u32 rate)
1353{
1354 struct mlx5e_priv *priv = netdev_priv(dev);
1355 struct mlx5_core_dev *mdev = priv->mdev;
1356 u16 rl_index = 0;
1357 int err;
1358
1359 if (rate == sq->rate_limit)
1360 /* nothing to do */
1361 return 0;
1362
1363 if (sq->rate_limit)
1364 /* remove current rl index to free space to next ones */
1365 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1366
1367 sq->rate_limit = 0;
1368
1369 if (rate) {
1370 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1371 if (err) {
1372 netdev_err(dev, "Failed configuring rate %u: %d\n",
1373 rate, err);
1374 return err;
1375 }
1376 }
1377
1378 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1379 MLX5_SQC_STATE_RDY, true, rl_index);
1380 if (err) {
1381 netdev_err(dev, "Failed configuring rate %u: %d\n",
1382 rate, err);
1383 /* remove the rate from the table */
1384 if (rate)
1385 mlx5_rl_remove_rate(mdev, rate);
1386 return err;
1387 }
1388
1389 sq->rate_limit = rate;
1390 return 0;
1391}
1392
1393static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1394{
1395 struct mlx5e_priv *priv = netdev_priv(dev);
1396 struct mlx5_core_dev *mdev = priv->mdev;
1397 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1398 int err = 0;
1399
1400 if (!mlx5_rl_is_supported(mdev)) {
1401 netdev_err(dev, "Rate limiting is not supported on this device\n");
1402 return -EINVAL;
1403 }
1404
1405 /* rate is given in Mb/sec, HW config is in Kb/sec */
1406 rate = rate << 10;
1407
1408 /* Check whether rate in valid range, 0 is always valid */
1409 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1410 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1411 return -ERANGE;
1412 }
1413
1414 mutex_lock(&priv->state_lock);
1415 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1416 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1417 if (!err)
1418 priv->tx_rates[index] = rate;
1419 mutex_unlock(&priv->state_lock);
1420
1421 return err;
1422}
1423
f62b8bb8
AV		 1424static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1425 struct mlx5e_channel_param *cparam,
1426 struct mlx5e_channel **cp)
1427{
9908aa29 1428 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1429 struct net_device *netdev = priv->netdev;
cb3c7fd4 1430 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1431 int cpu = mlx5e_get_cpu(priv, ix);
1432 struct mlx5e_channel *c;
507f0c81 1433 struct mlx5e_sq *sq;
f62b8bb8 1434 int err;
507f0c81 1435 int i;
f62b8bb8
AV		 1436
1437 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1438 if (!c)
1439 return -ENOMEM;
1440
1441 c->priv = priv;
1442 c->ix = ix;
1443 c->cpu = cpu;
1444 c->pdev = &priv->mdev->pdev->dev;
1445 c->netdev = priv->netdev;
b50d292b 1446 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1447 c->num_tc = priv->params.num_tc;
f62b8bb8 1448
cb3c7fd4
GR		 1449 if (priv->params.rx_am_enabled)
1450 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1451 else
1452 rx_cq_profile = priv->params.rx_cq_moderation;
1453
5283af89 1454 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1455
f62b8bb8
AV		 1456 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1457
9908aa29 1458 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1459 if (err)
1460 goto err_napi_del;
1461
d3c9bc27
TT		 1462 err = mlx5e_open_tx_cqs(c, cparam);
1463 if (err)
1464 goto err_close_icosq_cq;
1465
f62b8bb8 1466 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1467 rx_cq_profile);
f62b8bb8
AV		 1468 if (err)
1469 goto err_close_tx_cqs;
f62b8bb8
AV		 1470
1471 napi_enable(&c->napi);
1472
d3c9bc27 1473 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1474 if (err)
1475 goto err_disable_napi;
1476
d3c9bc27
TT		 1477 err = mlx5e_open_sqs(c, cparam);
1478 if (err)
1479 goto err_close_icosq;
1480
507f0c81
YP		 1481 for (i = 0; i < priv->params.num_tc; i++) {
1482 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1483
1484 if (priv->tx_rates[txq_ix]) {
1485 sq = priv->txq_to_sq_map[txq_ix];
1486 mlx5e_set_sq_maxrate(priv->netdev, sq,
1487 priv->tx_rates[txq_ix]);
1488 }
1489 }
1490
b5503b99
SM		 1491 if (priv->xdp_prog) {
1492 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1493 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1494 priv->params.tx_cq_moderation);
1495 if (err)
1496 goto err_close_sqs;
1497
1498 err = mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq);
1499 if (err) {
1500 mlx5e_close_cq(&c->xdp_sq.cq);
1501 goto err_close_sqs;
1502 }
1503 }
1504
1505 c->xdp = !!priv->xdp_prog;
f62b8bb8
AV		 1506 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1507 if (err)
b5503b99 1508 goto err_close_xdp_sq;
f62b8bb8
AV		 1509
1510 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1511 *cp = c;
1512
1513 return 0;
b5503b99
SM		 1514err_close_xdp_sq:
1515 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8
AV		 1516
1517err_close_sqs:
1518 mlx5e_close_sqs(c);
1519
d3c9bc27
TT		 1520err_close_icosq:
1521 mlx5e_close_sq(&c->icosq);
1522
f62b8bb8
AV		 1523err_disable_napi:
1524 napi_disable(&c->napi);
1525 mlx5e_close_cq(&c->rq.cq);
1526
1527err_close_tx_cqs:
1528 mlx5e_close_tx_cqs(c);
1529
d3c9bc27
TT		 1530err_close_icosq_cq:
1531 mlx5e_close_cq(&c->icosq.cq);
1532
f62b8bb8
AV		 1533err_napi_del:
1534 netif_napi_del(&c->napi);
7ae92ae5 1535 napi_hash_del(&c->napi);
f62b8bb8
AV		 1536 kfree(c);
1537
1538 return err;
1539}
1540
1541static void mlx5e_close_channel(struct mlx5e_channel *c)
1542{
1543 mlx5e_close_rq(&c->rq);
b5503b99
SM		 1544 if (c->xdp)
1545 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8 1546 mlx5e_close_sqs(c);
d3c9bc27 1547 mlx5e_close_sq(&c->icosq);
f62b8bb8 1548 napi_disable(&c->napi);
b5503b99
SM		 1549 if (c->xdp)
1550 mlx5e_close_cq(&c->xdp_sq.cq);
f62b8bb8
AV		 1551 mlx5e_close_cq(&c->rq.cq);
1552 mlx5e_close_tx_cqs(c);
d3c9bc27 1553 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1554 netif_napi_del(&c->napi);
7ae92ae5
ED		 1555
1556 napi_hash_del(&c->napi);
1557 synchronize_rcu();
1558
f62b8bb8
AV		 1559 kfree(c);
1560}
1561
1562static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1563 struct mlx5e_rq_param *param)
1564{
1565 void *rqc = param->rqc;
1566 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1567
461017cb
TT		 1568 switch (priv->params.rq_wq_type) {
1569 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1570 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1571 priv->params.mpwqe_log_num_strides - 9);
461017cb 1572 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1573 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1574 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1575 break;
1576 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1577 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1578 }
1579
f62b8bb8
AV		 1580 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1581 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1582 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1583 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1584 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1585
311c7c71 1586 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1587 param->wq.linear = 1;
cb3c7fd4
GR		 1588
1589 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1590}
1591
556dd1b9
TT		 1592static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1593{
1594 void *rqc = param->rqc;
1595 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1596
1597 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1598 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1599}
1600
d3c9bc27
TT		 1601static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1602 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1603{
1604 void *sqc = param->sqc;
1605 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1606
f62b8bb8 1607 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1608 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1609
311c7c71 1610 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1611}
1612
1613static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1614 struct mlx5e_sq_param *param)
1615{
1616 void *sqc = param->sqc;
1617 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1618
1619 mlx5e_build_sq_param_common(priv, param);
1620 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1621
58d52291 1622 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1623 param->min_inline_mode = priv->params.tx_min_inline_mode;
f10b7cc7 1624 param->type = MLX5E_SQ_TXQ;
f62b8bb8
AV		 1625}
1626
1627static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1628 struct mlx5e_cq_param *param)
1629{
1630 void *cqc = param->cqc;
1631
b50d292b 1632 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1633}
1634
1635static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1636 struct mlx5e_cq_param *param)
1637{
1638 void *cqc = param->cqc;
461017cb 1639 u8 log_cq_size;
f62b8bb8 1640
461017cb
TT		 1641 switch (priv->params.rq_wq_type) {
1642 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1643 log_cq_size = priv->params.log_rq_size +
d9d9f156 1644 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1645 break;
1646 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1647 log_cq_size = priv->params.log_rq_size;
1648 }
1649
1650 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1651 if (priv->params.rx_cqe_compress) {
1652 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1653 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1654 }
f62b8bb8
AV		 1655
1656 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1657
1658 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1659}
1660
1661static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1662 struct mlx5e_cq_param *param)
1663{
1664 void *cqc = param->cqc;
1665
d3c9bc27 1666 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1667
1668 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1669
1670 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1671}
1672
d3c9bc27
TT		 1673static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1674 struct mlx5e_cq_param *param,
1675 u8 log_wq_size)
1676{
1677 void *cqc = param->cqc;
1678
1679 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1680
1681 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1682
1683 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1684}
1685
1686static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1687 struct mlx5e_sq_param *param,
1688 u8 log_wq_size)
1689{
1690 void *sqc = param->sqc;
1691 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1692
1693 mlx5e_build_sq_param_common(priv, param);
1694
1695 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1696 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27 1697
f10b7cc7 1698 param->type = MLX5E_SQ_ICO;
d3c9bc27
TT		 1699}
1700
b5503b99
SM		 1701static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1702 struct mlx5e_sq_param *param)
1703{
1704 void *sqc = param->sqc;
1705 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1706
1707 mlx5e_build_sq_param_common(priv, param);
1708 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1709
1710 param->max_inline = priv->params.tx_max_inline;
1711 /* FOR XDP SQs will support only L2 inline mode */
1712 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1713 param->type = MLX5E_SQ_XDP;
1714}
1715
6b87663f 1716static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1717{
bc77b240 1718 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1719
f62b8bb8
AV		 1720 mlx5e_build_rq_param(priv, &cparam->rq);
1721 mlx5e_build_sq_param(priv, &cparam->sq);
b5503b99 1722 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
d3c9bc27 1723 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1724 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1725 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1726 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1727}
1728
1729static int mlx5e_open_channels(struct mlx5e_priv *priv)
1730{
6b87663f 1731 struct mlx5e_channel_param *cparam;
a4418a6c 1732 int nch = priv->params.num_channels;
03289b88 1733 int err = -ENOMEM;
f62b8bb8
AV		 1734 int i;
1735 int j;
1736
a4418a6c
AS		 1737 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1738 GFP_KERNEL);
03289b88 1739
a4418a6c 1740 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1741 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1742
6b87663f
AB		 1743 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1744
1745 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1746 goto err_free_txq_to_sq_map;
f62b8bb8 1747
6b87663f
AB		 1748 mlx5e_build_channel_param(priv, cparam);
1749
a4418a6c 1750 for (i = 0; i < nch; i++) {
6b87663f 1751 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1752 if (err)
1753 goto err_close_channels;
1754 }
1755
a4418a6c 1756 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1757 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1758 if (err)
1759 goto err_close_channels;
1760 }
1761
c3b7c5c9
MHY		 1762 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1763 * polling for inactive tx queues.
1764 */
1765 netif_tx_start_all_queues(priv->netdev);
1766
6b87663f 1767 kfree(cparam);
f62b8bb8
AV		 1768 return 0;
1769
1770err_close_channels:
1771 for (i--; i >= 0; i--)
1772 mlx5e_close_channel(priv->channel[i]);
1773
03289b88
SM		 1774err_free_txq_to_sq_map:
1775 kfree(priv->txq_to_sq_map);
f62b8bb8 1776 kfree(priv->channel);
6b87663f 1777 kfree(cparam);
f62b8bb8
AV		 1778
1779 return err;
1780}
1781
1782static void mlx5e_close_channels(struct mlx5e_priv *priv)
1783{
1784 int i;
1785
c3b7c5c9
MHY		 1786 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1787 * polling for inactive tx queues.
1788 */
1789 netif_tx_stop_all_queues(priv->netdev);
1790 netif_tx_disable(priv->netdev);
1791
f62b8bb8
AV		 1792 for (i = 0; i < priv->params.num_channels; i++)
1793 mlx5e_close_channel(priv->channel[i]);
1794
03289b88 1795 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1796 kfree(priv->channel);
1797}
1798
2be6967c
SM		 1799static int mlx5e_rx_hash_fn(int hfunc)
1800{
1801 return (hfunc == ETH_RSS_HASH_TOP) ?
1802 MLX5_RX_HASH_FN_TOEPLITZ :
1803 MLX5_RX_HASH_FN_INVERTED_XOR8;
1804}
1805
1806static int mlx5e_bits_invert(unsigned long a, int size)
1807{
1808 int inv = 0;
1809 int i;
1810
1811 for (i = 0; i < size; i++)
1812 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1813
1814 return inv;
1815}
1816
936896e9
AS		 1817static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1818{
1819 int i;
1820
1821 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1822 int ix = i;
1da36696 1823 u32 rqn;
936896e9
AS		 1824
1825 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1826 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1827
2d75b2bc 1828 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1829 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1830 priv->channel[ix]->rq.rqn :
1831 priv->drop_rq.rqn;
1832 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1833 }
1834}
1835
1da36696
TT		 1836static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1837 int ix)
4cbeaff5 1838{
1da36696
TT		 1839 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1840 priv->channel[ix]->rq.rqn :
1841 priv->drop_rq.rqn;
4cbeaff5 1842
1da36696 1843 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1844}
1845
398f3351
HHZ		 1846static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1847 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1848{
1849 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1850 void *rqtc;
1851 int inlen;
1852 int err;
1da36696 1853 u32 *in;
f62b8bb8 1854
f62b8bb8
AV		 1855 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1856 in = mlx5_vzalloc(inlen);
1857 if (!in)
1858 return -ENOMEM;
1859
1860 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1861
1862 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1863 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1864
1da36696
TT		 1865 if (sz > 1) /* RSS */
1866 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1867 else
1868 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1869
398f3351
HHZ		 1870 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1871 if (!err)
1872 rqt->enabled = true;
f62b8bb8
AV		 1873
1874 kvfree(in);
1da36696
TT		 1875 return err;
1876}
1877
cb67b832 1878void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1879{
398f3351
HHZ		 1880 rqt->enabled = false;
1881 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1882}
1883
6bfd390b
HHZ		 1884static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1885{
1886 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1887
1888 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1889}
1890
cb67b832 1891int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1892{
398f3351 1893 struct mlx5e_rqt *rqt;
1da36696
TT		 1894 int err;
1895 int ix;
1896
6bfd390b 1897 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1898 rqt = &priv->direct_tir[ix].rqt;
1899 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1900 if (err)
1901 goto err_destroy_rqts;
1902 }
1903
1904 return 0;
1905
1906err_destroy_rqts:
1907 for (ix--; ix >= 0; ix--)
398f3351 1908 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1909
f62b8bb8
AV		 1910 return err;
1911}
1912
1da36696 1913int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1914{
1915 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1916 void *rqtc;
1917 int inlen;
1da36696 1918 u32 *in;
5c50368f
AS		 1919 int err;
1920
5c50368f
AS		 1921 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1922 in = mlx5_vzalloc(inlen);
1923 if (!in)
1924 return -ENOMEM;
1925
1926 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1927
1928 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1929 if (sz > 1) /* RSS */
1930 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1931 else
1932 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1933
1934 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1935
1da36696 1936 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1937
1938 kvfree(in);
1939
1940 return err;
1941}
1942
40ab6a6e
AS		 1943static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1944{
1da36696
TT		 1945 u32 rqtn;
1946 int ix;
1947
398f3351
HHZ		 1948 if (priv->indir_rqt.enabled) {
1949 rqtn = priv->indir_rqt.rqtn;
1950 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1951 }
1952
1da36696 1953 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 1954 if (!priv->direct_tir[ix].rqt.enabled)
1955 continue;
1956 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 1957 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1958 }
40ab6a6e
AS		 1959}
1960
5c50368f
AS		 1961static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1962{
1963 if (!priv->params.lro_en)
1964 return;
1965
1966#define ROUGH_MAX_L2_L3_HDR_SZ 256
1967
1968 MLX5_SET(tirc, tirc, lro_enable_mask,
1969 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1970 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1971 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1972 (priv->params.lro_wqe_sz -
1973 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2b029556 1974 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
5c50368f
AS		 1975}
1976
bdfc028d
TT		 1977void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1978{
1979 MLX5_SET(tirc, tirc, rx_hash_fn,
1980 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1981 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1982 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1983 rx_hash_toeplitz_key);
1984 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1985 rx_hash_toeplitz_key);
1986
1987 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1988 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1989 }
1990}
1991
ab0394fe 1992static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1993{
1994 struct mlx5_core_dev *mdev = priv->mdev;
1995
1996 void *in;
1997 void *tirc;
1998 int inlen;
1999 int err;
ab0394fe 2000 int tt;
1da36696 2001 int ix;
5c50368f
AS		 2002
2003 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2004 in = mlx5_vzalloc(inlen);
2005 if (!in)
2006 return -ENOMEM;
2007
2008 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2009 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2010
2011 mlx5e_build_tir_ctx_lro(tirc, priv);
2012
1da36696 2013 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2014 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2015 inlen);
ab0394fe 2016 if (err)
1da36696 2017 goto free_in;
ab0394fe 2018 }
5c50368f 2019
6bfd390b 2020 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2021 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2022 in, inlen);
2023 if (err)
2024 goto free_in;
2025 }
2026
2027free_in:
5c50368f
AS		 2028 kvfree(in);
2029
2030 return err;
2031}
2032
cd255eff 2033static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2034{
40ab6a6e 2035 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2036 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2037 int err;
2038
cd255eff 2039 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2040 if (err)
2041 return err;
2042
cd255eff
SM		 2043 /* Update vport context MTU */
2044 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2045 return 0;
2046}
40ab6a6e 2047
cd255eff
SM		 2048static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2049{
2050 struct mlx5_core_dev *mdev = priv->mdev;
2051 u16 hw_mtu = 0;
2052 int err;
40ab6a6e 2053
cd255eff
SM		 2054 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2055 if (err || !hw_mtu) /* fallback to port oper mtu */
2056 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2057
2058 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2059}
2060
2061static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2062{
2063 struct mlx5e_priv *priv = netdev_priv(netdev);
2064 u16 mtu;
2065 int err;
2066
2067 err = mlx5e_set_mtu(priv, netdev->mtu);
2068 if (err)
2069 return err;
40ab6a6e 2070
cd255eff
SM		 2071 mlx5e_query_mtu(priv, &mtu);
2072 if (mtu != netdev->mtu)
2073 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2074 __func__, mtu, netdev->mtu);
40ab6a6e 2075
cd255eff 2076 netdev->mtu = mtu;
40ab6a6e
AS		 2077 return 0;
2078}
2079
08fb1dac
SM		 2080static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2081{
2082 struct mlx5e_priv *priv = netdev_priv(netdev);
2083 int nch = priv->params.num_channels;
2084 int ntc = priv->params.num_tc;
2085 int tc;
2086
2087 netdev_reset_tc(netdev);
2088
2089 if (ntc == 1)
2090 return;
2091
2092 netdev_set_num_tc(netdev, ntc);
2093
7ccdd084
RS		 2094 /* Map netdev TCs to offset 0
2095 * We have our own UP to TXQ mapping for QoS
2096 */
08fb1dac 2097 for (tc = 0; tc < ntc; tc++)
7ccdd084 2098 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2099}
2100
40ab6a6e
AS		 2101int mlx5e_open_locked(struct net_device *netdev)
2102{
2103 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2104 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 2105 int num_txqs;
2106 int err;
2107
2108 set_bit(MLX5E_STATE_OPENED, &priv->state);
2109
08fb1dac
SM		 2110 mlx5e_netdev_set_tcs(netdev);
2111
40ab6a6e
AS		 2112 num_txqs = priv->params.num_channels * priv->params.num_tc;
2113 netif_set_real_num_tx_queues(netdev, num_txqs);
2114 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2115
40ab6a6e
AS		 2116 err = mlx5e_open_channels(priv);
2117 if (err) {
2118 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2119 __func__, err);
343b29f3 2120 goto err_clear_state_opened_flag;
40ab6a6e
AS		 2121 }
2122
724b2aa1 2123 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
66189961
TT		 2124 if (err) {
2125 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2126 __func__, err);
2127 goto err_close_channels;
2128 }
2129
40ab6a6e 2130 mlx5e_redirect_rqts(priv);
ce89ef36 2131 mlx5e_update_carrier(priv);
ef9814de 2132 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 2133#ifdef CONFIG_RFS_ACCEL
2134 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2135#endif
cb67b832
HHZ		 2136 if (priv->profile->update_stats)
2137 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2138
cb67b832
HHZ		 2139 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2140 err = mlx5e_add_sqs_fwd_rules(priv);
2141 if (err)
2142 goto err_close_channels;
2143 }
9b37b07f 2144 return 0;
343b29f3 2145
66189961
TT		 2146err_close_channels:
2147 mlx5e_close_channels(priv);
343b29f3
AS		 2148err_clear_state_opened_flag:
2149 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2150 return err;
40ab6a6e
AS		 2151}
2152
cb67b832 2153int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2154{
2155 struct mlx5e_priv *priv = netdev_priv(netdev);
2156 int err;
2157
2158 mutex_lock(&priv->state_lock);
2159 err = mlx5e_open_locked(netdev);
2160 mutex_unlock(&priv->state_lock);
2161
2162 return err;
2163}
2164
2165int mlx5e_close_locked(struct net_device *netdev)
2166{
2167 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2168 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 2169
a1985740
AS		 2170 /* May already be CLOSED in case a previous configuration operation
2171 * (e.g RX/TX queue size change) that involves close&open failed.
2172 */
2173 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2174 return 0;
2175
40ab6a6e
AS		 2176 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2177
cb67b832
HHZ		 2178 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2179 mlx5e_remove_sqs_fwd_rules(priv);
2180
ef9814de 2181 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2182 netif_carrier_off(priv->netdev);
ce89ef36 2183 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 2184 mlx5e_close_channels(priv);
2185
2186 return 0;
2187}
2188
cb67b832 2189int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2190{
2191 struct mlx5e_priv *priv = netdev_priv(netdev);
2192 int err;
2193
26e59d80
MHY		 2194 if (!netif_device_present(netdev))
2195 return -ENODEV;
2196
40ab6a6e
AS		 2197 mutex_lock(&priv->state_lock);
2198 err = mlx5e_close_locked(netdev);
2199 mutex_unlock(&priv->state_lock);
2200
2201 return err;
2202}
2203
2204static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2205 struct mlx5e_rq *rq,
2206 struct mlx5e_rq_param *param)
2207{
2208 struct mlx5_core_dev *mdev = priv->mdev;
2209 void *rqc = param->rqc;
2210 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2211 int err;
2212
2213 param->wq.db_numa_node = param->wq.buf_numa_node;
2214
2215 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2216 &rq->wq_ctrl);
2217 if (err)
2218 return err;
2219
2220 rq->priv = priv;
2221
2222 return 0;
2223}
2224
2225static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2226 struct mlx5e_cq *cq,
2227 struct mlx5e_cq_param *param)
2228{
2229 struct mlx5_core_dev *mdev = priv->mdev;
2230 struct mlx5_core_cq *mcq = &cq->mcq;
2231 int eqn_not_used;
0b6e26ce 2232 unsigned int irqn;
40ab6a6e
AS		 2233 int err;
2234
2235 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2236 &cq->wq_ctrl);
2237 if (err)
2238 return err;
2239
2240 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2241
2242 mcq->cqe_sz = 64;
2243 mcq->set_ci_db = cq->wq_ctrl.db.db;
2244 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2245 *mcq->set_ci_db = 0;
2246 *mcq->arm_db = 0;
2247 mcq->vector = param->eq_ix;
2248 mcq->comp = mlx5e_completion_event;
2249 mcq->event = mlx5e_cq_error_event;
2250 mcq->irqn = irqn;
b50d292b 2251 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 2252
2253 cq->priv = priv;
2254
2255 return 0;
2256}
2257
2258static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2259{
2260 struct mlx5e_cq_param cq_param;
2261 struct mlx5e_rq_param rq_param;
2262 struct mlx5e_rq *rq = &priv->drop_rq;
2263 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2264 int err;
2265
2266 memset(&cq_param, 0, sizeof(cq_param));
2267 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 2268 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 2269
2270 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2271 if (err)
2272 return err;
2273
2274 err = mlx5e_enable_cq(cq, &cq_param);
2275 if (err)
2276 goto err_destroy_cq;
2277
2278 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2279 if (err)
2280 goto err_disable_cq;
2281
2282 err = mlx5e_enable_rq(rq, &rq_param);
2283 if (err)
2284 goto err_destroy_rq;
2285
2286 return 0;
2287
2288err_destroy_rq:
2289 mlx5e_destroy_rq(&priv->drop_rq);
2290
2291err_disable_cq:
2292 mlx5e_disable_cq(&priv->drop_rq.cq);
2293
2294err_destroy_cq:
2295 mlx5e_destroy_cq(&priv->drop_rq.cq);
2296
2297 return err;
2298}
2299
2300static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2301{
2302 mlx5e_disable_rq(&priv->drop_rq);
2303 mlx5e_destroy_rq(&priv->drop_rq);
2304 mlx5e_disable_cq(&priv->drop_rq.cq);
2305 mlx5e_destroy_cq(&priv->drop_rq.cq);
2306}
2307
2308static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2309{
2310 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2311 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2312 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2313
08fb1dac 2314 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2315 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2316
2317 if (mlx5_lag_is_lacp_owner(mdev))
2318 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2319
40ab6a6e
AS		 2320 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2321}
2322
2323static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2324{
2325 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2326}
2327
cb67b832 2328int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2329{
2330 int err;
2331 int tc;
2332
6bfd390b 2333 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2334 err = mlx5e_create_tis(priv, tc);
2335 if (err)
2336 goto err_close_tises;
2337 }
2338
2339 return 0;
2340
2341err_close_tises:
2342 for (tc--; tc >= 0; tc--)
2343 mlx5e_destroy_tis(priv, tc);
2344
2345 return err;
2346}
2347
cb67b832 2348void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2349{
2350 int tc;
2351
6bfd390b 2352 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2353 mlx5e_destroy_tis(priv, tc);
2354}
2355
1da36696
TT		 2356static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2357 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2358{
2359 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2360
b50d292b 2361 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2362
5a6f8aef
AS		 2363#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2364 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2365
5a6f8aef
AS		 2366#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2367 MLX5_HASH_FIELD_SEL_DST_IP |\
2368 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2369 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2370
a741749f
AS		 2371#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2372 MLX5_HASH_FIELD_SEL_DST_IP |\
2373 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2374
5c50368f 2375 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2376
4cbeaff5 2377 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2378 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2379 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2380
2381 switch (tt) {
2382 case MLX5E_TT_IPV4_TCP:
2383 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2384 MLX5_L3_PROT_TYPE_IPV4);
2385 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2386 MLX5_L4_PROT_TYPE_TCP);
2387 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2388 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2389 break;
2390
2391 case MLX5E_TT_IPV6_TCP:
2392 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2393 MLX5_L3_PROT_TYPE_IPV6);
2394 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2395 MLX5_L4_PROT_TYPE_TCP);
2396 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2397 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2398 break;
2399
2400 case MLX5E_TT_IPV4_UDP:
2401 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2402 MLX5_L3_PROT_TYPE_IPV4);
2403 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2404 MLX5_L4_PROT_TYPE_UDP);
2405 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2406 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2407 break;
2408
2409 case MLX5E_TT_IPV6_UDP:
2410 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2411 MLX5_L3_PROT_TYPE_IPV6);
2412 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2413 MLX5_L4_PROT_TYPE_UDP);
2414 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2415 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2416 break;
2417
a741749f
AS		 2418 case MLX5E_TT_IPV4_IPSEC_AH:
2419 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2420 MLX5_L3_PROT_TYPE_IPV4);
2421 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2422 MLX5_HASH_IP_IPSEC_SPI);
2423 break;
2424
2425 case MLX5E_TT_IPV6_IPSEC_AH:
2426 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2427 MLX5_L3_PROT_TYPE_IPV6);
2428 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2429 MLX5_HASH_IP_IPSEC_SPI);
2430 break;
2431
2432 case MLX5E_TT_IPV4_IPSEC_ESP:
2433 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2434 MLX5_L3_PROT_TYPE_IPV4);
2435 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436 MLX5_HASH_IP_IPSEC_SPI);
2437 break;
2438
2439 case MLX5E_TT_IPV6_IPSEC_ESP:
2440 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441 MLX5_L3_PROT_TYPE_IPV6);
2442 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443 MLX5_HASH_IP_IPSEC_SPI);
2444 break;
2445
f62b8bb8
AV		 2446 case MLX5E_TT_IPV4:
2447 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448 MLX5_L3_PROT_TYPE_IPV4);
2449 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450 MLX5_HASH_IP);
2451 break;
2452
2453 case MLX5E_TT_IPV6:
2454 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2455 MLX5_L3_PROT_TYPE_IPV6);
2456 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2457 MLX5_HASH_IP);
2458 break;
1da36696
TT		 2459 default:
2460 WARN_ONCE(true,
2461 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2462 }
2463}
2464
1da36696
TT		 2465static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2466 u32 rqtn)
f62b8bb8 2467{
b50d292b 2468 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2469
2470 mlx5e_build_tir_ctx_lro(tirc, priv);
2471
2472 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2473 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2474 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2475}
2476
6bfd390b 2477static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2478{
724b2aa1 2479 struct mlx5e_tir *tir;
f62b8bb8
AV		 2480 void *tirc;
2481 int inlen;
2482 int err;
1da36696 2483 u32 *in;
1da36696 2484 int tt;
f62b8bb8
AV		 2485
2486 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2487 in = mlx5_vzalloc(inlen);
2488 if (!in)
2489 return -ENOMEM;
2490
1da36696
TT		 2491 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2492 memset(in, 0, inlen);
724b2aa1 2493 tir = &priv->indir_tir[tt];
1da36696
TT		 2494 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2495 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2496 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2497 if (err)
40ab6a6e 2498 goto err_destroy_tirs;
f62b8bb8
AV		 2499 }
2500
6bfd390b
HHZ		 2501 kvfree(in);
2502
2503 return 0;
2504
2505err_destroy_tirs:
2506 for (tt--; tt >= 0; tt--)
2507 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2508
2509 kvfree(in);
2510
2511 return err;
2512}
2513
cb67b832 2514int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2515{
2516 int nch = priv->profile->max_nch(priv->mdev);
2517 struct mlx5e_tir *tir;
2518 void *tirc;
2519 int inlen;
2520 int err;
2521 u32 *in;
2522 int ix;
2523
2524 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2525 in = mlx5_vzalloc(inlen);
2526 if (!in)
2527 return -ENOMEM;
2528
1da36696
TT		 2529 for (ix = 0; ix < nch; ix++) {
2530 memset(in, 0, inlen);
724b2aa1 2531 tir = &priv->direct_tir[ix];
1da36696
TT		 2532 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2533 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2534 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2535 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2536 if (err)
2537 goto err_destroy_ch_tirs;
2538 }
2539
2540 kvfree(in);
2541
f62b8bb8
AV		 2542 return 0;
2543
1da36696
TT		 2544err_destroy_ch_tirs:
2545 for (ix--; ix >= 0; ix--)
724b2aa1 2546 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2547
1da36696 2548 kvfree(in);
f62b8bb8
AV		 2549
2550 return err;
2551}
2552
6bfd390b 2553static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2554{
2555 int i;
2556
1da36696 2557 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2558 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2559}
2560
cb67b832 2561void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2562{
2563 int nch = priv->profile->max_nch(priv->mdev);
2564 int i;
2565
2566 for (i = 0; i < nch; i++)
2567 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2568}
2569
36350114
GP		 2570int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2571{
2572 int err = 0;
2573 int i;
2574
2575 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2576 return 0;
2577
2578 for (i = 0; i < priv->params.num_channels; i++) {
2579 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2580 if (err)
2581 return err;
2582 }
2583
2584 return 0;
2585}
2586
08fb1dac
SM		 2587static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2588{
2589 struct mlx5e_priv *priv = netdev_priv(netdev);
2590 bool was_opened;
2591 int err = 0;
2592
2593 if (tc && tc != MLX5E_MAX_NUM_TC)
2594 return -EINVAL;
2595
2596 mutex_lock(&priv->state_lock);
2597
2598 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2599 if (was_opened)
2600 mlx5e_close_locked(priv->netdev);
2601
2602 priv->params.num_tc = tc ? tc : 1;
2603
2604 if (was_opened)
2605 err = mlx5e_open_locked(priv->netdev);
2606
2607 mutex_unlock(&priv->state_lock);
2608
2609 return err;
2610}
2611
2612static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2613 __be16 proto, struct tc_to_netdev *tc)
2614{
e8f887ac
AV		 2615 struct mlx5e_priv *priv = netdev_priv(dev);
2616
2617 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2618 goto mqprio;
2619
2620 switch (tc->type) {
e3a2b7ed
AV		 2621 case TC_SETUP_CLSFLOWER:
2622 switch (tc->cls_flower->command) {
2623 case TC_CLSFLOWER_REPLACE:
2624 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2625 case TC_CLSFLOWER_DESTROY:
2626 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2627 case TC_CLSFLOWER_STATS:
2628 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2629 }
e8f887ac
AV		 2630 default:
2631 return -EOPNOTSUPP;
2632 }
2633
2634mqprio:
67ba422e 2635 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2636 return -EINVAL;
2637
2638 return mlx5e_setup_tc(dev, tc->tc);
2639}
2640
cb67b832 2641struct rtnl_link_stats64 *
f62b8bb8
AV		 2642mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2643{
2644 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2645 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2646 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2647 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2648
9218b44d
GP		 2649 stats->rx_packets = sstats->rx_packets;
2650 stats->rx_bytes = sstats->rx_bytes;
2651 stats->tx_packets = sstats->tx_packets;
2652 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2653
2654 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2655 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2656
2657 stats->rx_length_errors =
9218b44d
GP		 2658 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2659 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2660 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2661 stats->rx_crc_errors =
9218b44d
GP		 2662 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2663 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2664 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2665 stats->tx_carrier_errors =
9218b44d 2666 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2667 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2668 stats->rx_frame_errors;
2669 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2670
2671 /* vport multicast also counts packets that are dropped due to steering
2672 * or rx out of buffer
2673 */
9218b44d
GP		 2674 stats->multicast =
2675 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2676
2677 return stats;
2678}
2679
2680static void mlx5e_set_rx_mode(struct net_device *dev)
2681{
2682 struct mlx5e_priv *priv = netdev_priv(dev);
2683
7bb29755 2684 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2685}
2686
2687static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2688{
2689 struct mlx5e_priv *priv = netdev_priv(netdev);
2690 struct sockaddr *saddr = addr;
2691
2692 if (!is_valid_ether_addr(saddr->sa_data))
2693 return -EADDRNOTAVAIL;
2694
2695 netif_addr_lock_bh(netdev);
2696 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2697 netif_addr_unlock_bh(netdev);
2698
7bb29755 2699 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2700
2701 return 0;
2702}
2703
0e405443
GP		 2704#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2705 do { \
2706 if (enable) \
2707 netdev->features |= feature; \
2708 else \
2709 netdev->features &= ~feature; \
2710 } while (0)
2711
2712typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2713
2714static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2715{
2716 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2717 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2718 int err;
f62b8bb8
AV		 2719
2720 mutex_lock(&priv->state_lock);
f62b8bb8 2721
0e405443
GP		 2722 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2723 mlx5e_close_locked(priv->netdev);
98e81b0a 2724
0e405443
GP		 2725 priv->params.lro_en = enable;
2726 err = mlx5e_modify_tirs_lro(priv);
2727 if (err) {
2728 netdev_err(netdev, "lro modify failed, %d\n", err);
2729 priv->params.lro_en = !enable;
98e81b0a 2730 }
f62b8bb8 2731
0e405443
GP		 2732 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2733 mlx5e_open_locked(priv->netdev);
2734
9b37b07f
AS		 2735 mutex_unlock(&priv->state_lock);
2736
0e405443
GP		 2737 return err;
2738}
2739
2740static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2741{
2742 struct mlx5e_priv *priv = netdev_priv(netdev);
2743
2744 if (enable)
2745 mlx5e_enable_vlan_filter(priv);
2746 else
2747 mlx5e_disable_vlan_filter(priv);
2748
2749 return 0;
2750}
2751
2752static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2753{
2754 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2755
0e405443 2756 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2757 netdev_err(netdev,
2758 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2759 return -EINVAL;
2760 }
2761
0e405443
GP		 2762 return 0;
2763}
2764
94cb1ebb
EBE		 2765static int set_feature_rx_all(struct net_device *netdev, bool enable)
2766{
2767 struct mlx5e_priv *priv = netdev_priv(netdev);
2768 struct mlx5_core_dev *mdev = priv->mdev;
2769
2770 return mlx5_set_port_fcs(mdev, !enable);
2771}
2772
36350114
GP		 2773static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2774{
2775 struct mlx5e_priv *priv = netdev_priv(netdev);
2776 int err;
2777
2778 mutex_lock(&priv->state_lock);
2779
2780 priv->params.vlan_strip_disable = !enable;
2781 err = mlx5e_modify_rqs_vsd(priv, !enable);
2782 if (err)
2783 priv->params.vlan_strip_disable = enable;
2784
2785 mutex_unlock(&priv->state_lock);
2786
2787 return err;
2788}
2789
45bf454a
MG		 2790#ifdef CONFIG_RFS_ACCEL
2791static int set_feature_arfs(struct net_device *netdev, bool enable)
2792{
2793 struct mlx5e_priv *priv = netdev_priv(netdev);
2794 int err;
2795
2796 if (enable)
2797 err = mlx5e_arfs_enable(priv);
2798 else
2799 err = mlx5e_arfs_disable(priv);
2800
2801 return err;
2802}
2803#endif
2804
0e405443
GP		 2805static int mlx5e_handle_feature(struct net_device *netdev,
2806 netdev_features_t wanted_features,
2807 netdev_features_t feature,
2808 mlx5e_feature_handler feature_handler)
2809{
2810 netdev_features_t changes = wanted_features ^ netdev->features;
2811 bool enable = !!(wanted_features & feature);
2812 int err;
2813
2814 if (!(changes & feature))
2815 return 0;
2816
2817 err = feature_handler(netdev, enable);
2818 if (err) {
2819 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2820 enable ? "Enable" : "Disable", feature, err);
2821 return err;
2822 }
2823
2824 MLX5E_SET_FEATURE(netdev, feature, enable);
2825 return 0;
2826}
2827
2828static int mlx5e_set_features(struct net_device *netdev,
2829 netdev_features_t features)
2830{
2831 int err;
2832
2833 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2834 set_feature_lro);
2835 err |= mlx5e_handle_feature(netdev, features,
2836 NETIF_F_HW_VLAN_CTAG_FILTER,
2837 set_feature_vlan_filter);
2838 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2839 set_feature_tc_num_filters);
94cb1ebb
EBE		 2840 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2841 set_feature_rx_all);
36350114
GP		 2842 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2843 set_feature_rx_vlan);
45bf454a
MG		 2844#ifdef CONFIG_RFS_ACCEL
2845 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2846 set_feature_arfs);
2847#endif
0e405443
GP		 2848
2849 return err ? -EINVAL : 0;
f62b8bb8
AV		 2850}
2851
d8edd246
SM		 2852#define MXL5_HW_MIN_MTU 64
2853#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2854
f62b8bb8
AV		 2855static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2856{
2857 struct mlx5e_priv *priv = netdev_priv(netdev);
2858 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2859 bool was_opened;
046339ea 2860 u16 max_mtu;
d8edd246 2861 u16 min_mtu;
98e81b0a 2862 int err = 0;
506753b0 2863 bool reset;
f62b8bb8 2864
facc9699 2865 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2866
50a9eea6 2867 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2868 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2869
d8edd246 2870 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2871 netdev_err(netdev,
d8edd246
SM		 2872 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2873 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2874 return -EINVAL;
2875 }
2876
2877 mutex_lock(&priv->state_lock);
98e81b0a 2878
506753b0
TT		 2879 reset = !priv->params.lro_en &&
2880 (priv->params.rq_wq_type !=
2881 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2882
98e81b0a 2883 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2884 if (was_opened && reset)
98e81b0a
AS		 2885 mlx5e_close_locked(netdev);
2886
f62b8bb8 2887 netdev->mtu = new_mtu;
13f9bba7 2888 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 2889
506753b0 2890 if (was_opened && reset)
98e81b0a
AS		 2891 err = mlx5e_open_locked(netdev);
2892
f62b8bb8
AV		 2893 mutex_unlock(&priv->state_lock);
2894
2895 return err;
2896}
2897
ef9814de
EBE		 2898static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2899{
2900 switch (cmd) {
2901 case SIOCSHWTSTAMP:
2902 return mlx5e_hwstamp_set(dev, ifr);
2903 case SIOCGHWTSTAMP:
2904 return mlx5e_hwstamp_get(dev, ifr);
2905 default:
2906 return -EOPNOTSUPP;
2907 }
2908}
2909
66e49ded
SM		 2910static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2911{
2912 struct mlx5e_priv *priv = netdev_priv(dev);
2913 struct mlx5_core_dev *mdev = priv->mdev;
2914
2915 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2916}
2917
79aab093
MS		 2918static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2919 __be16 vlan_proto)
66e49ded
SM		 2920{
2921 struct mlx5e_priv *priv = netdev_priv(dev);
2922 struct mlx5_core_dev *mdev = priv->mdev;
2923
79aab093
MS		 2924 if (vlan_proto != htons(ETH_P_8021Q))
2925 return -EPROTONOSUPPORT;
2926
66e49ded
SM		 2927 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2928 vlan, qos);
2929}
2930
f942380c
MHY		 2931static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2932{
2933 struct mlx5e_priv *priv = netdev_priv(dev);
2934 struct mlx5_core_dev *mdev = priv->mdev;
2935
2936 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2937}
2938
1edc57e2
MHY		 2939static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2940{
2941 struct mlx5e_priv *priv = netdev_priv(dev);
2942 struct mlx5_core_dev *mdev = priv->mdev;
2943
2944 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2945}
66e49ded
SM		 2946static int mlx5_vport_link2ifla(u8 esw_link)
2947{
2948 switch (esw_link) {
2949 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2950 return IFLA_VF_LINK_STATE_DISABLE;
2951 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2952 return IFLA_VF_LINK_STATE_ENABLE;
2953 }
2954 return IFLA_VF_LINK_STATE_AUTO;
2955}
2956
2957static int mlx5_ifla_link2vport(u8 ifla_link)
2958{
2959 switch (ifla_link) {
2960 case IFLA_VF_LINK_STATE_DISABLE:
2961 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2962 case IFLA_VF_LINK_STATE_ENABLE:
2963 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2964 }
2965 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2966}
2967
2968static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2969 int link_state)
2970{
2971 struct mlx5e_priv *priv = netdev_priv(dev);
2972 struct mlx5_core_dev *mdev = priv->mdev;
2973
2974 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2975 mlx5_ifla_link2vport(link_state));
2976}
2977
2978static int mlx5e_get_vf_config(struct net_device *dev,
2979 int vf, struct ifla_vf_info *ivi)
2980{
2981 struct mlx5e_priv *priv = netdev_priv(dev);
2982 struct mlx5_core_dev *mdev = priv->mdev;
2983 int err;
2984
2985 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2986 if (err)
2987 return err;
2988 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2989 return 0;
2990}
2991
2992static int mlx5e_get_vf_stats(struct net_device *dev,
2993 int vf, struct ifla_vf_stats *vf_stats)
2994{
2995 struct mlx5e_priv *priv = netdev_priv(dev);
2996 struct mlx5_core_dev *mdev = priv->mdev;
2997
2998 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2999 vf_stats);
3000}
3001
b3f63c3d 3002static void mlx5e_add_vxlan_port(struct net_device *netdev,
974c3f30 3003 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3004{
3005 struct mlx5e_priv *priv = netdev_priv(netdev);
3006
974c3f30
AD		 3007 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3008 return;
3009
b3f63c3d
MF		 3010 if (!mlx5e_vxlan_allowed(priv->mdev))
3011 return;
3012
974c3f30 3013 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3014}
3015
3016static void mlx5e_del_vxlan_port(struct net_device *netdev,
974c3f30 3017 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3018{
3019 struct mlx5e_priv *priv = netdev_priv(netdev);
3020
974c3f30
AD		 3021 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3022 return;
3023
b3f63c3d
MF		 3024 if (!mlx5e_vxlan_allowed(priv->mdev))
3025 return;
3026
974c3f30 3027 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3028}
3029
3030static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3031 struct sk_buff *skb,
3032 netdev_features_t features)
3033{
3034 struct udphdr *udph;
3035 u16 proto;
3036 u16 port = 0;
3037
3038 switch (vlan_get_protocol(skb)) {
3039 case htons(ETH_P_IP):
3040 proto = ip_hdr(skb)->protocol;
3041 break;
3042 case htons(ETH_P_IPV6):
3043 proto = ipv6_hdr(skb)->nexthdr;
3044 break;
3045 default:
3046 goto out;
3047 }
3048
3049 if (proto == IPPROTO_UDP) {
3050 udph = udp_hdr(skb);
3051 port = be16_to_cpu(udph->dest);
3052 }
3053
3054 /* Verify if UDP port is being offloaded by HW */
3055 if (port && mlx5e_vxlan_lookup_port(priv, port))
3056 return features;
3057
3058out:
3059 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3060 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3061}
3062
3063static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3064 struct net_device *netdev,
3065 netdev_features_t features)
3066{
3067 struct mlx5e_priv *priv = netdev_priv(netdev);
3068
3069 features = vlan_features_check(skb, features);
3070 features = vxlan_features_check(skb, features);
3071
3072 /* Validate if the tunneled packet is being offloaded by HW */
3073 if (skb->encapsulation &&
3074 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3075 return mlx5e_vxlan_features_check(priv, skb, features);
3076
3077 return features;
3078}
3079
3947ca18
DJ		 3080static void mlx5e_tx_timeout(struct net_device *dev)
3081{
3082 struct mlx5e_priv *priv = netdev_priv(dev);
3083 bool sched_work = false;
3084 int i;
3085
3086 netdev_err(dev, "TX timeout detected\n");
3087
3088 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3089 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3090
2c1ccc99 3091 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3092 continue;
3093 sched_work = true;
6e8dd6d6 3094 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3947ca18
DJ		 3095 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3096 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3097 }
3098
3099 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3100 schedule_work(&priv->tx_timeout_work);
3101}
3102
86994156
RS		 3103static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3104{
3105 struct mlx5e_priv *priv = netdev_priv(netdev);
3106 struct bpf_prog *old_prog;
3107 int err = 0;
3108 bool reset, was_opened;
3109 int i;
3110
3111 mutex_lock(&priv->state_lock);
3112
3113 if ((netdev->features & NETIF_F_LRO) && prog) {
3114 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3115 err = -EINVAL;
3116 goto unlock;
3117 }
3118
3119 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3120 /* no need for full reset when exchanging programs */
3121 reset = (!priv->xdp_prog || !prog);
3122
3123 if (was_opened && reset)
3124 mlx5e_close_locked(netdev);
3125
3126 /* exchange programs */
3127 old_prog = xchg(&priv->xdp_prog, prog);
3128 if (prog)
3129 bpf_prog_add(prog, 1);
3130 if (old_prog)
3131 bpf_prog_put(old_prog);
3132
3133 if (reset) /* change RQ type according to priv->xdp_prog */
3134 mlx5e_set_rq_priv_params(priv);
3135
3136 if (was_opened && reset)
3137 mlx5e_open_locked(netdev);
3138
3139 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3140 goto unlock;
3141
3142 /* exchanging programs w/o reset, we update ref counts on behalf
3143 * of the channels RQs here.
3144 */
3145 bpf_prog_add(prog, priv->params.num_channels);
3146 for (i = 0; i < priv->params.num_channels; i++) {
3147 struct mlx5e_channel *c = priv->channel[i];
3148
3149 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3150 napi_synchronize(&c->napi);
3151 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3152
3153 old_prog = xchg(&c->rq.xdp_prog, prog);
3154
3155 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3156 /* napi_schedule in case we have missed anything */
3157 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3158 napi_schedule(&c->napi);
3159
3160 if (old_prog)
3161 bpf_prog_put(old_prog);
3162 }
3163
3164unlock:
3165 mutex_unlock(&priv->state_lock);
3166 return err;
3167}
3168
3169static bool mlx5e_xdp_attached(struct net_device *dev)
3170{
3171 struct mlx5e_priv *priv = netdev_priv(dev);
3172
3173 return !!priv->xdp_prog;
3174}
3175
3176static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3177{
3178 switch (xdp->command) {
3179 case XDP_SETUP_PROG:
3180 return mlx5e_xdp_set(dev, xdp->prog);
3181 case XDP_QUERY_PROG:
3182 xdp->prog_attached = mlx5e_xdp_attached(dev);
3183 return 0;
3184 default:
3185 return -EINVAL;
3186 }
3187}
3188
80378384
CO		 3189#ifdef CONFIG_NET_POLL_CONTROLLER
3190/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3191 * reenabling interrupts.
3192 */
3193static void mlx5e_netpoll(struct net_device *dev)
3194{
3195 struct mlx5e_priv *priv = netdev_priv(dev);
3196 int i;
3197
3198 for (i = 0; i < priv->params.num_channels; i++)
3199 napi_schedule(&priv->channel[i]->napi);
3200}
3201#endif
3202
b0eed40e 3203static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3204 .ndo_open = mlx5e_open,
3205 .ndo_stop = mlx5e_close,
3206 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3207 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3208 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3209 .ndo_get_stats64 = mlx5e_get_stats,
3210 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3211 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3212 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3213 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3214 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3215 .ndo_change_mtu = mlx5e_change_mtu,
3216 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3217 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3218#ifdef CONFIG_RFS_ACCEL
3219 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3220#endif
3947ca18 3221 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3222 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3223#ifdef CONFIG_NET_POLL_CONTROLLER
3224 .ndo_poll_controller = mlx5e_netpoll,
3225#endif
b0eed40e
SM		 3226};
3227
3228static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3229 .ndo_open = mlx5e_open,
3230 .ndo_stop = mlx5e_close,
3231 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3232 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3233 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3234 .ndo_get_stats64 = mlx5e_get_stats,
3235 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3236 .ndo_set_mac_address = mlx5e_set_mac,
3237 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3238 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3239 .ndo_set_features = mlx5e_set_features,
3240 .ndo_change_mtu = mlx5e_change_mtu,
3241 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3242 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3243 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3244 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3245 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3246#ifdef CONFIG_RFS_ACCEL
3247 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3248#endif
b0eed40e
SM		 3249 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3250 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3251 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3252 .ndo_set_vf_trust = mlx5e_set_vf_trust,
b0eed40e
SM		 3253 .ndo_get_vf_config = mlx5e_get_vf_config,
3254 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3255 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3256 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3257 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3258#ifdef CONFIG_NET_POLL_CONTROLLER
3259 .ndo_poll_controller = mlx5e_netpoll,
3260#endif
f62b8bb8
AV		 3261};
3262
3263static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3264{
3265 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3266 return -ENOTSUPP;
3267 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3268 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3269 !MLX5_CAP_ETH(mdev, csum_cap) ||
3270 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3271 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3272 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3273 MLX5_CAP_FLOWTABLE(mdev,
3274 flow_table_properties_nic_receive.max_ft_level)
3275 < 3) {
f62b8bb8
AV		 3276 mlx5_core_warn(mdev,
3277 "Not creating net device, some required device capabilities are missing\n");
3278 return -ENOTSUPP;
3279 }
66189961
TT		 3280 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3281 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3282 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3283 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3284
f62b8bb8
AV		 3285 return 0;
3286}
3287
58d52291
AS		 3288u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3289{
3290 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3291
3292 return bf_buf_size -
3293 sizeof(struct mlx5e_tx_wqe) +
3294 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3295}
3296
08fb1dac
SM		 3297#ifdef CONFIG_MLX5_CORE_EN_DCB
3298static void mlx5e_ets_init(struct mlx5e_priv *priv)
3299{
3300 int i;
3301
3302 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3303 for (i = 0; i < priv->params.ets.ets_cap; i++) {
3304 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3305 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3306 priv->params.ets.prio_tc[i] = i;
3307 }
3308
3309 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3310 priv->params.ets.prio_tc[0] = 1;
3311 priv->params.ets.prio_tc[1] = 0;
3312}
3313#endif
3314
d8c9660d
TT		 3315void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3316 u32 *indirection_rqt, int len,
85082dba
TT		 3317 int num_channels)
3318{
d8c9660d
TT		 3319 int node = mdev->priv.numa_node;
3320 int node_num_of_cores;
85082dba
TT		 3321 int i;
3322
d8c9660d
TT		 3323 if (node == -1)
3324 node = first_online_node;
3325
3326 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3327
3328 if (node_num_of_cores)
3329 num_channels = min_t(int, num_channels, node_num_of_cores);
3330
85082dba
TT		 3331 for (i = 0; i < len; i++)
3332 indirection_rqt[i] = i % num_channels;
3333}
3334
b797a684
SM		 3335static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3336{
3337 enum pcie_link_width width;
3338 enum pci_bus_speed speed;
3339 int err = 0;
3340
3341 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3342 if (err)
3343 return err;
3344
3345 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3346 return -EINVAL;
3347
3348 switch (speed) {
3349 case PCIE_SPEED_2_5GT:
3350 *pci_bw = 2500 * width;
3351 break;
3352 case PCIE_SPEED_5_0GT:
3353 *pci_bw = 5000 * width;
3354 break;
3355 case PCIE_SPEED_8_0GT:
3356 *pci_bw = 8000 * width;
3357 break;
3358 default:
3359 return -EINVAL;
3360 }
3361
3362 return 0;
3363}
3364
3365static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3366{
3367 return (link_speed && pci_bw &&
3368 (pci_bw < 40000) && (pci_bw < link_speed));
3369}
3370
9908aa29
TT		 3371void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3372{
3373 params->rx_cq_period_mode = cq_period_mode;
3374
3375 params->rx_cq_moderation.pkts =
3376 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3377 params->rx_cq_moderation.usec =
3378 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3379
3380 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3381 params->rx_cq_moderation.usec =
3382 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3383}
3384
cff92d7c
HHZ		 3385static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3386 u8 *min_inline_mode)
3387{
3388 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3389 case MLX5E_INLINE_MODE_L2:
3390 *min_inline_mode = MLX5_INLINE_MODE_L2;
3391 break;
3392 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3393 mlx5_query_nic_vport_min_inline(mdev,
3394 min_inline_mode);
3395 break;
3396 case MLX5_INLINE_MODE_NOT_REQUIRED:
3397 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3398 break;
3399 }
3400}
3401
2b029556
SM		 3402u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3403{
3404 int i;
3405
3406 /* The supported periods are organized in ascending order */
3407 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3408 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3409 break;
3410
3411 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3412}
3413
6bfd390b
HHZ		 3414static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3415 struct net_device *netdev,
127ea380
HHZ		 3416 const struct mlx5e_profile *profile,
3417 void *ppriv)
f62b8bb8
AV		 3418{
3419 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3420 u32 link_speed = 0;
3421 u32 pci_bw = 0;
cb3c7fd4
GR		 3422 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3423 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3424 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8 3425
2fc4bfb7
SM		 3426 priv->mdev = mdev;
3427 priv->netdev = netdev;
3428 priv->params.num_channels = profile->max_nch(mdev);
3429 priv->profile = profile;
3430 priv->ppriv = ppriv;
3431
2b029556
SM		 3432 priv->params.lro_timeout =
3433 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3434
2fc4bfb7 3435 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3436
b797a684
SM		 3437 /* set CQE compression */
3438 priv->params.rx_cqe_compress_admin = false;
3439 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3440 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3441 mlx5e_get_max_linkspeed(mdev, &link_speed);
3442 mlx5e_get_pci_bw(mdev, &pci_bw);
3443 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3444 link_speed, pci_bw);
3445 priv->params.rx_cqe_compress_admin =
3446 cqe_compress_heuristic(link_speed, pci_bw);
3447 }
b797a684
SM		 3448 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3449
2fc4bfb7
SM		 3450 mlx5e_set_rq_priv_params(priv);
3451 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
461017cb 3452 priv->params.lro_en = true;
9908aa29 3453
cb3c7fd4
GR		 3454 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3455 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3456
3457 priv->params.tx_cq_moderation.usec =
f62b8bb8 3458 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3459 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3460 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3461 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
cff92d7c 3462 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3463 priv->params.num_tc = 1;
2be6967c 3464 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3465
57afead5
AS		 3466 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3467 sizeof(priv->params.toeplitz_hash_key));
3468
d8c9660d 3469 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3470 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3471
e4b85508
SM		 3472 priv->params.lro_wqe_sz =
3473 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3474 /* Extra room needed for build_skb */
3475 MLX5_RX_HEADROOM -
3476 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
f62b8bb8 3477
9908aa29
TT		 3478 /* Initialize pflags */
3479 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3480 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3481
08fb1dac
SM		 3482#ifdef CONFIG_MLX5_CORE_EN_DCB
3483 mlx5e_ets_init(priv);
3484#endif
f62b8bb8 3485
f62b8bb8
AV		 3486 mutex_init(&priv->state_lock);
3487
3488 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3489 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3490 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3491 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3492}
3493
3494static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3495{
3496 struct mlx5e_priv *priv = netdev_priv(netdev);
3497
e1d7d349 3498 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3499 if (is_zero_ether_addr(netdev->dev_addr) &&
3500 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3501 eth_hw_addr_random(netdev);
3502 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3503 }
f62b8bb8
AV		 3504}
3505
cb67b832
HHZ		 3506static const struct switchdev_ops mlx5e_switchdev_ops = {
3507 .switchdev_port_attr_get = mlx5e_attr_get,
3508};
3509
6bfd390b 3510static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3511{
3512 struct mlx5e_priv *priv = netdev_priv(netdev);
3513 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3514 bool fcs_supported;
3515 bool fcs_enabled;
f62b8bb8
AV		 3516
3517 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3518
08fb1dac 3519 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3520 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 3521#ifdef CONFIG_MLX5_CORE_EN_DCB
3522 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3523#endif
3524 } else {
b0eed40e 3525 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3526 }
66e49ded 3527
f62b8bb8
AV		 3528 netdev->watchdog_timeo = 15 * HZ;
3529
3530 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3531
12be4b21 3532 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3533 netdev->vlan_features |= NETIF_F_IP_CSUM;
3534 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3535 netdev->vlan_features |= NETIF_F_GRO;
3536 netdev->vlan_features |= NETIF_F_TSO;
3537 netdev->vlan_features |= NETIF_F_TSO6;
3538 netdev->vlan_features |= NETIF_F_RXCSUM;
3539 netdev->vlan_features |= NETIF_F_RXHASH;
3540
3541 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3542 netdev->vlan_features |= NETIF_F_LRO;
3543
3544 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3545 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3546 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3547 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3548
b3f63c3d 3549 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3550 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3551 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3552 NETIF_F_GSO_PARTIAL;
b3f63c3d 3553 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3554 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3555 netdev->hw_enc_features |= NETIF_F_TSO;
3556 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3557 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3558 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3559 NETIF_F_GSO_PARTIAL;
3560 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3561 }
3562
94cb1ebb
EBE		 3563 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3564
3565 if (fcs_supported)
3566 netdev->hw_features |= NETIF_F_RXALL;
3567
f62b8bb8
AV		 3568 netdev->features = netdev->hw_features;
3569 if (!priv->params.lro_en)
3570 netdev->features &= ~NETIF_F_LRO;
3571
94cb1ebb
EBE		 3572 if (fcs_enabled)
3573 netdev->features &= ~NETIF_F_RXALL;
3574
e8f887ac
AV		 3575#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3576 if (FT_CAP(flow_modify_en) &&
3577 FT_CAP(modify_root) &&
3578 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3579 FT_CAP(flow_table_modify)) {
3580 netdev->hw_features |= NETIF_F_HW_TC;
3581#ifdef CONFIG_RFS_ACCEL
3582 netdev->hw_features |= NETIF_F_NTUPLE;
3583#endif
3584 }
e8f887ac 3585
f62b8bb8
AV		 3586 netdev->features |= NETIF_F_HIGHDMA;
3587
3588 netdev->priv_flags |= IFF_UNICAST_FLT;
3589
3590 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3591
3592#ifdef CONFIG_NET_SWITCHDEV
3593 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3594 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3595#endif
f62b8bb8
AV		 3596}
3597
593cf338
RS		 3598static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3599{
3600 struct mlx5_core_dev *mdev = priv->mdev;
3601 int err;
3602
3603 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3604 if (err) {
3605 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3606 priv->q_counter = 0;
3607 }
3608}
3609
3610static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3611{
3612 if (!priv->q_counter)
3613 return;
3614
3615 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3616}
3617
bc77b240
TT		 3618static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3619{
3620 struct mlx5_core_dev *mdev = priv->mdev;
fe4c988b
SM		 3621 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3622 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
ec22eb53
SM		 3623 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3624 void *mkc;
3625 u32 *in;
bc77b240
TT		 3626 int err;
3627
3628 in = mlx5_vzalloc(inlen);
3629 if (!in)
3630 return -ENOMEM;
3631
ec22eb53 3632 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
bc77b240 3633
fe4c988b
SM		 3634 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3635
ec22eb53
SM		 3636 MLX5_SET(mkc, mkc, free, 1);
3637 MLX5_SET(mkc, mkc, umr_en, 1);
3638 MLX5_SET(mkc, mkc, lw, 1);
3639 MLX5_SET(mkc, mkc, lr, 1);
3640 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
bc77b240 3641
ec22eb53
SM		 3642 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3643 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3644 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3645 MLX5_SET(mkc, mkc, translations_octword_size,
6abdd5f5 3646 MLX5_MTT_OCTW(npages));
ec22eb53 3647 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
bc77b240 3648
ec22eb53 3649 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
bc77b240 3650
ec22eb53 3651 kvfree(in);
bc77b240
TT		 3652 return err;
3653}
3654
6bfd390b
HHZ		 3655static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3656 struct net_device *netdev,
127ea380
HHZ		 3657 const struct mlx5e_profile *profile,
3658 void *ppriv)
6bfd390b
HHZ		 3659{
3660 struct mlx5e_priv *priv = netdev_priv(netdev);
3661
127ea380 3662 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3663 mlx5e_build_nic_netdev(netdev);
3664 mlx5e_vxlan_init(priv);
3665}
3666
3667static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3668{
127ea380
HHZ		 3669 struct mlx5_core_dev *mdev = priv->mdev;
3670 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3671
6bfd390b 3672 mlx5e_vxlan_cleanup(priv);
127ea380
HHZ		 3673
3674 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3675 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b
HHZ		 3676}
3677
3678static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3679{
3680 struct mlx5_core_dev *mdev = priv->mdev;
3681 int err;
3682 int i;
3683
3684 err = mlx5e_create_indirect_rqts(priv);
3685 if (err) {
3686 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3687 return err;
3688 }
3689
3690 err = mlx5e_create_direct_rqts(priv);
3691 if (err) {
3692 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3693 goto err_destroy_indirect_rqts;
3694 }
3695
3696 err = mlx5e_create_indirect_tirs(priv);
3697 if (err) {
3698 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3699 goto err_destroy_direct_rqts;
3700 }
3701
3702 err = mlx5e_create_direct_tirs(priv);
3703 if (err) {
3704 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3705 goto err_destroy_indirect_tirs;
3706 }
3707
3708 err = mlx5e_create_flow_steering(priv);
3709 if (err) {
3710 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3711 goto err_destroy_direct_tirs;
3712 }
3713
3714 err = mlx5e_tc_init(priv);
3715 if (err)
3716 goto err_destroy_flow_steering;
3717
3718 return 0;
3719
3720err_destroy_flow_steering:
3721 mlx5e_destroy_flow_steering(priv);
3722err_destroy_direct_tirs:
3723 mlx5e_destroy_direct_tirs(priv);
3724err_destroy_indirect_tirs:
3725 mlx5e_destroy_indirect_tirs(priv);
3726err_destroy_direct_rqts:
3727 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3728 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3729err_destroy_indirect_rqts:
3730 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3731 return err;
3732}
3733
3734static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3735{
3736 int i;
3737
3738 mlx5e_tc_cleanup(priv);
3739 mlx5e_destroy_flow_steering(priv);
3740 mlx5e_destroy_direct_tirs(priv);
3741 mlx5e_destroy_indirect_tirs(priv);
3742 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3743 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3744 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3745}
3746
3747static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3748{
3749 int err;
3750
3751 err = mlx5e_create_tises(priv);
3752 if (err) {
3753 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3754 return err;
3755 }
3756
3757#ifdef CONFIG_MLX5_CORE_EN_DCB
3758 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3759#endif
3760 return 0;
3761}
3762
3763static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3764{
3765 struct net_device *netdev = priv->netdev;
3766 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3767 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3768 struct mlx5_eswitch_rep rep;
6bfd390b 3769
7907f23a
AH		 3770 mlx5_lag_add(mdev, netdev);
3771
6bfd390b
HHZ		 3772 if (mlx5e_vxlan_allowed(mdev)) {
3773 rtnl_lock();
3774 udp_tunnel_get_rx_info(netdev);
3775 rtnl_unlock();
3776 }
3777
3778 mlx5e_enable_async_events(priv);
3779 queue_work(priv->wq, &priv->set_rx_mode_work);
127ea380
HHZ		 3780
3781 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3782 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3783 rep.load = mlx5e_nic_rep_load;
3784 rep.unload = mlx5e_nic_rep_unload;
9deb2241 3785 rep.vport = FDB_UPLINK_VPORT;
127ea380 3786 rep.priv_data = priv;
9deb2241 3787 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 3788 }
6bfd390b
HHZ		 3789}
3790
3791static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3792{
3793 queue_work(priv->wq, &priv->set_rx_mode_work);
3794 mlx5e_disable_async_events(priv);
7907f23a 3795 mlx5_lag_remove(priv->mdev);
6bfd390b
HHZ		 3796}
3797
3798static const struct mlx5e_profile mlx5e_nic_profile = {
3799 .init = mlx5e_nic_init,
3800 .cleanup = mlx5e_nic_cleanup,
3801 .init_rx = mlx5e_init_nic_rx,
3802 .cleanup_rx = mlx5e_cleanup_nic_rx,
3803 .init_tx = mlx5e_init_nic_tx,
3804 .cleanup_tx = mlx5e_cleanup_nic_tx,
3805 .enable = mlx5e_nic_enable,
3806 .disable = mlx5e_nic_disable,
3807 .update_stats = mlx5e_update_stats,
3808 .max_nch = mlx5e_get_max_num_channels,
3809 .max_tc = MLX5E_MAX_NUM_TC,
3810};
3811
26e59d80
MHY		 3812struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3813 const struct mlx5e_profile *profile,
3814 void *ppriv)
f62b8bb8 3815{
26e59d80 3816 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3817 struct net_device *netdev;
3818 struct mlx5e_priv *priv;
f62b8bb8 3819
08fb1dac 3820 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3821 nch * profile->max_tc,
08fb1dac 3822 nch);
f62b8bb8
AV		 3823 if (!netdev) {
3824 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3825 return NULL;
3826 }
3827
127ea380 3828 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3829
3830 netif_carrier_off(netdev);
3831
3832 priv = netdev_priv(netdev);
3833
7bb29755
MF		 3834 priv->wq = create_singlethread_workqueue("mlx5e");
3835 if (!priv->wq)
26e59d80
MHY		 3836 goto err_cleanup_nic;
3837
3838 return netdev;
3839
3840err_cleanup_nic:
3841 profile->cleanup(priv);
3842 free_netdev(netdev);
3843
3844 return NULL;
3845}
3846
3847int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3848{
3849 const struct mlx5e_profile *profile;
3850 struct mlx5e_priv *priv;
3851 int err;
3852
3853 priv = netdev_priv(netdev);
3854 profile = priv->profile;
3855 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3856
bc77b240
TT		 3857 err = mlx5e_create_umr_mkey(priv);
3858 if (err) {
3859 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
26e59d80 3860 goto out;
bc77b240
TT		 3861 }
3862
6bfd390b
HHZ		 3863 err = profile->init_tx(priv);
3864 if (err)
bc77b240 3865 goto err_destroy_umr_mkey;
5c50368f
AS		 3866
3867 err = mlx5e_open_drop_rq(priv);
3868 if (err) {
3869 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3870 goto err_cleanup_tx;
5c50368f
AS		 3871 }
3872
6bfd390b
HHZ		 3873 err = profile->init_rx(priv);
3874 if (err)
5c50368f 3875 goto err_close_drop_rq;
5c50368f 3876
593cf338
RS		 3877 mlx5e_create_q_counter(priv);
3878
33cfaaa8 3879 mlx5e_init_l2_addr(priv);
5c50368f 3880
13f9bba7
SM		 3881 mlx5e_set_dev_port_mtu(netdev);
3882
6bfd390b
HHZ		 3883 if (profile->enable)
3884 profile->enable(priv);
f62b8bb8 3885
26e59d80
MHY		 3886 rtnl_lock();
3887 if (netif_running(netdev))
3888 mlx5e_open(netdev);
3889 netif_device_attach(netdev);
3890 rtnl_unlock();
f62b8bb8 3891
26e59d80 3892 return 0;
5c50368f
AS		 3893
3894err_close_drop_rq:
3895 mlx5e_close_drop_rq(priv);
3896
6bfd390b
HHZ		 3897err_cleanup_tx:
3898 profile->cleanup_tx(priv);
5c50368f 3899
bc77b240
TT		 3900err_destroy_umr_mkey:
3901 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3902
26e59d80
MHY		 3903out:
3904 return err;
f62b8bb8
AV		 3905}
3906
127ea380
HHZ		 3907static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3908{
3909 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3910 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3911 int vport;
dbe413e3 3912 u8 mac[ETH_ALEN];
127ea380
HHZ		 3913
3914 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3915 return;
3916
dbe413e3
HHZ		 3917 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3918
127ea380
HHZ		 3919 for (vport = 1; vport < total_vfs; vport++) {
3920 struct mlx5_eswitch_rep rep;
3921
cb67b832
HHZ		 3922 rep.load = mlx5e_vport_rep_load;
3923 rep.unload = mlx5e_vport_rep_unload;
127ea380 3924 rep.vport = vport;
dbe413e3 3925 ether_addr_copy(rep.hw_id, mac);
9deb2241 3926 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 3927 }
3928}
3929
26e59d80
MHY		 3930void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3931{
3932 struct mlx5e_priv *priv = netdev_priv(netdev);
3933 const struct mlx5e_profile *profile = priv->profile;
3934
3935 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3936 if (profile->disable)
3937 profile->disable(priv);
3938
3939 flush_workqueue(priv->wq);
3940
3941 rtnl_lock();
3942 if (netif_running(netdev))
3943 mlx5e_close(netdev);
3944 netif_device_detach(netdev);
3945 rtnl_unlock();
3946
3947 mlx5e_destroy_q_counter(priv);
3948 profile->cleanup_rx(priv);
3949 mlx5e_close_drop_rq(priv);
3950 profile->cleanup_tx(priv);
3951 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3952 cancel_delayed_work_sync(&priv->update_stats_work);
3953}
3954
3955/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3956 * hardware contexts and to connect it to the current netdev.
3957 */
3958static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3959{
3960 struct mlx5e_priv *priv = vpriv;
3961 struct net_device *netdev = priv->netdev;
3962 int err;
3963
3964 if (netif_device_present(netdev))
3965 return 0;
3966
3967 err = mlx5e_create_mdev_resources(mdev);
3968 if (err)
3969 return err;
3970
3971 err = mlx5e_attach_netdev(mdev, netdev);
3972 if (err) {
3973 mlx5e_destroy_mdev_resources(mdev);
3974 return err;
3975 }
3976
3977 return 0;
3978}
3979
3980static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3981{
3982 struct mlx5e_priv *priv = vpriv;
3983 struct net_device *netdev = priv->netdev;
3984
3985 if (!netif_device_present(netdev))
3986 return;
3987
3988 mlx5e_detach_netdev(mdev, netdev);
3989 mlx5e_destroy_mdev_resources(mdev);
3990}
3991
b50d292b
HHZ		 3992static void *mlx5e_add(struct mlx5_core_dev *mdev)
3993{
127ea380 3994 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 3995 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 3996 void *ppriv = NULL;
26e59d80
MHY		 3997 void *priv;
3998 int vport;
3999 int err;
4000 struct net_device *netdev;
b50d292b 4001
26e59d80
MHY		 4002 err = mlx5e_check_required_hca_cap(mdev);
4003 if (err)
b50d292b
HHZ		 4004 return NULL;
4005
127ea380
HHZ		 4006 mlx5e_register_vport_rep(mdev);
4007
4008 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4009 ppriv = &esw->offloads.vport_reps[0];
4010
26e59d80
MHY		 4011 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4012 if (!netdev) {
4013 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4014 goto err_unregister_reps;
4015 }
4016
4017 priv = netdev_priv(netdev);
4018
4019 err = mlx5e_attach(mdev, priv);
4020 if (err) {
4021 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4022 goto err_destroy_netdev;
4023 }
4024
4025 err = register_netdev(netdev);
4026 if (err) {
4027 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4028 goto err_detach;
b50d292b 4029 }
26e59d80
MHY		 4030
4031 return priv;
4032
4033err_detach:
4034 mlx5e_detach(mdev, priv);
4035
4036err_destroy_netdev:
4037 mlx5e_destroy_netdev(mdev, priv);
4038
4039err_unregister_reps:
4040 for (vport = 1; vport < total_vfs; vport++)
4041 mlx5_eswitch_unregister_vport_rep(esw, vport);
4042
4043 return NULL;
b50d292b
HHZ		 4044}
4045
cb67b832 4046void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4047{
6bfd390b 4048 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4049 struct net_device *netdev = priv->netdev;
4050
7bb29755 4051 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4052 if (profile->cleanup)
4053 profile->cleanup(priv);
26e59d80 4054 free_netdev(netdev);
f62b8bb8
AV		 4055}
4056
b50d292b
HHZ		 4057static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4058{
127ea380
HHZ		 4059 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4060 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 4061 struct mlx5e_priv *priv = vpriv;
127ea380 4062 int vport;
b50d292b 4063
127ea380
HHZ		 4064 for (vport = 1; vport < total_vfs; vport++)
4065 mlx5_eswitch_unregister_vport_rep(esw, vport);
4066
5e1e93c7 4067 unregister_netdev(priv->netdev);
26e59d80
MHY		 4068 mlx5e_detach(mdev, vpriv);
4069 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4070}
4071
f62b8bb8
AV		 4072static void *mlx5e_get_netdev(void *vpriv)
4073{
4074 struct mlx5e_priv *priv = vpriv;
4075
4076 return priv->netdev;
4077}
4078
4079static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4080 .add = mlx5e_add,
4081 .remove = mlx5e_remove,
26e59d80
MHY		 4082 .attach = mlx5e_attach,
4083 .detach = mlx5e_detach,
f62b8bb8
AV		 4084 .event = mlx5e_async_event,
4085 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4086 .get_dev = mlx5e_get_netdev,
4087};
4088
4089void mlx5e_init(void)
4090{
665bc539 4091 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4092 mlx5_register_interface(&mlx5e_interface);
4093}
4094
4095void mlx5e_cleanup(void)
4096{
4097 mlx5_unregister_interface(&mlx5e_interface);
4098}
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